Datasheet M27V320 Datasheet (SGS Thomson Microelectronics)

32 Mbit (4Mb x8 or 2Mb x16) OTP EPROM

■ 3.3V ± 10% SUPPLY VOLTAGE in READ

OPERATION

■ ACCESS TIME: 100ns

■ BYTE-WIDE or WORD-WIDE

CONFIGURABLE

■ 32 Mbit MASK ROM REPLACEMENT

■ LOW POWER CONSUMPTION

– Active Current 30mA at 5MHz
– Standby Current 60µA

■ PROGRAMMI NG VOLT AGE: 12V ± 0.2 5 V

■ PROGRAMMING TIME: 50µs/word

■ ELECTRONIC SIGNATURE:

– Manufacturer Code 20h
– Device Code: 32h

M27V320

SO44 (M) TSOP48 (N)

12 x 20 mm

Figure 1. Logic Diagram

DESCRIPTION

The M27V320 is a low voltage 32 Mbit EPROM of­fered in the OTP range (one time programmable).
It is ideally suited for microprocessor systems re­quiring large data or program st orage. It is organ­ised as either 4 MWords of 8 bit or 2 MWords of 16
bit. The pin-out is compatible with the 32 Mbit
Mask ROM.

The M27V320 is offered in SO44 and TSOP48
(12 x 20 mm) packages.

A0-A20

GV

PP

V

CC

21

E

M27V320

V

SS

Q15A–1

15

Q0-Q14

BYTE

AI05852

1/15August 2002

M27V320

Figure 2. SO Connections

NC A20

A17 A8

A7
A6
A5
A4
A3
A2
A1
A0

V

SS

GV

PP
Q0

Q8

Q9

Q10

Q3

Q11

1
2
3
4
5
6
7
8
9
10
11

M27V320

12

E

13
14
15
16
17Q1
18
19
20
21

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
2322

AI05853

A19A18

A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V

SS

Q15A–1
Q7
Q14
Q6
Q13
Q5Q2
Q12
Q4
V

CC

Figure 3. TSOP Connections

BYTE

A16
A15
A14
A13
A12

A10

A19

V

SS

A20
A18
A17

1

A9
A8

12
13

A7
A6
A5
A4

A2
A1
A0

24 25

E

M27V320

48

37
36

AI05854

V

SS

V

SS

Q15A–1
Q7
Q14
Q6
Q13A11
Q5
Q12
Q4
V

CC

V

CC

V

SS

Q11
Q3
Q10
Q2
Q9
Q1
Q8A3
Q0
GV

PP

V

SS

V

SS

Table 1. Signal Names

A0-A20 Address Inputs
Q0-Q7 Data Outputs
Q8-Q14 Data Outputs
Q15A–1 Data Output / Address Input
E
G

V

PP

BYTE Byte-Wide Select
V

CC

V

SS

NC Not Connected Internally

2/15

Chip Enable
Output Enable / Program Supply

Supply Voltage
Ground

DEVICE OPERATION

The operating modes of the M27V320 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatib le exc ept for V

and 12V on A9 for the

PP

Electronic Signature.

Read Mode

The M27V32 0 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTE

pin. When BYTE is at V
the Word-wide organisation is selected and the
Q15A–1 pin is used for Q15 Data Output. When
the BY T E

pin is at VIL the Byte-wide organisat ion
is selected and the Q15A–1 pin is used for the Ad­dress Input A–1. When the memory is logically re­garded as 16 bit wide, but read in the Byte-wide
organisation, then with A–1 at V

the lower 8 bits

IL

of the 16 bit data are selected and with A–1 at V
the upper 8 bits of the 16 bit data are selected.

IH

IH

M27V320

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A Ambient Operating Temperature

T

BIAS

T

STG

(2)

V

IO

V

CC

(2)

V

A9

V

PP

Note: 1. Except for the ratin g "Operating Temperat ure Range", stresse s above th ose listed i n t he Table "Absolute M aximum Rat i ngs" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indi cated in t he Operating secti ons of t hi s specifi cation i s not impl i ed. Exposure to Absolute Maximum Rating condi­tions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroe lectronics SURE Program an d other relevan t qual­ity docum en ts .

2. Minimum DC vo ltage on Inpu t or Out put is – 0.5V w ith poss ible un dershoot to –2. 0V fo r a peri od les s than 20ns. Ma ximum DC
voltage on Output is V

3. Depends on range.

Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V

Program Supply Voltage –2 to 14 V

+0.5V with possible overshoot to VCC +2V for a period l ess than 20ns.

CC

(3)

–40 to 125 °C

Table 3. Operating Modes

Mode E

Read Word-wide
Read Byte-wide Upper
Read Byte-wide Lower
Output Disable
Program
Program Inhibit
Standby
Electronic Signature

Note: X = VIH or VIL, VID = 12V ± 0.5V.

V
V
V
V

V

Pulse V

IL

V
V

V

GV

PP

IL

IL

IL

IL

IH

IH

IL

V

IL

V

IL

V

IL

V

IH

PP

V

PP

X X X Hi-Z Hi-Z Hi-Z

V

IL

BYTE A9 Q15A–1 Q14-Q8 Q7-Q0

V

IH

V

IL

V

IL

X Data Out Data Out Data Out
X
X

V

IH

V

IL

Hi-Z Data Out
Hi-Z Data Out

X X Hi-Z Hi-Z Hi-Z

V

IH

V

IH

V

IH

X Data In Data In Data In
X Hi-Z Hi-Z Hi-Z

V

ID

Code Codes Codes

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code
Device Code

Note: Output s Q15-Q8 are s et to '0' .

V
V

IL

IH

00100000 20h
00110010 32h

3/15

M27V320

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 4. AC Testing Input Output Waveform

High Speed

3V

1.5V

0V

Standard

2.4V

0.4V

Table 6. Capacitance

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampled only, not 100% tested.

(1)

(TA = 25 °C, f = 1 MHz)

Input Capacitance
Output Capacitance

2.0V

0.8V

AI01822

Figure 5. AC Testing Load Circuit

1.3V

DEVICE
UNDER

TEST

CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance

V

= 0V

IN

V

= 0V

OUT

1N914

3.3kΩ

CL

10 pF
12 pF

OUT

AI01823B

The M27V320 ha s two control functions, both of
which must be logically ac tive in order to obtain
data at the outputs. In addition the Word-wide or
Byte-wide organisation must be selected.

Chip Enable (E
used for device selection. Output Enable (G

) is the power control and should be

VPP) is
the output control and should be used to gate data
to the output pins independent of device selection.
Assuming that the addresses are s table, the ad­dress access time (t
from E

to output (t

4/15

ELQV

) is equal to the delay

AVQV

). Data is available at the

output after a delay of t
of G

VPP, assuming that E has been low and t he
addresses have been stable for at least t
t

.

GLQV

from the falling e dge

GLQV

AVQV

Standby Mode

The M27V320 has standby mode which reduces
the supply current from 50mA to 100µA. The
M27V320 is placed in the standby mode by apply­ing a CMOS high signal to the E

input. When in the
standby mode, the outputs are in a high imped­ance state, independent of the G

VPP input.

-

M27V320

Table 7. Read Mode DC Characteristics

(1)

(TA = 0 to 70°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)

Symbol Parameter Test Condition Min Max Unit

I

I

I

CC

I

CC

I

CC

I
V

VIH

V
V

Note: 1. VCC must be ap pl i e d simultaneously with or before VPP and removed simultane ously or aft er VPP.

Two Line Outp ut C ontrol

Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con­trol function which accommodates the use of mul­tiple memory connection. The two line control
function allows:

a. the lowest possible memory power dissipation,
b. comple te assuranc e that output bus contention

will not occur.

For the most efficient use of these two control
lines, E
ry device selecting function, while G
made a common connectio n to all devices in the
array and connected to the READ
system control bus. This ensures that all deselect­ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.

Input Leakage Current

LI

Output Leakage Current

LO

Supply Current

1

Supply Current (Standby) TTL

2

Supply Current (Standby) CMOS E
Program Current

PP

Input Low Voltage –0.6

IL

(2)

Input High Voltage
Output Low Voltage

OL

Output High Voltage TTL

OH

2. Maximu m DC voltage on Ou tput is V

CC

+0.5 V .

E

0V ≤ V

0V ≤ V

= VIL, GVPP = VIL, I

f = 5MHz, V

> VCC – 0.2V, VCC ≤ 3.6V 60 µA

I

IN

OUT

E = V

V

= V

PP

I

= 2.1mA

OL

= –400µA

OH

≤ V

≤ V

≤ 3.6V

CC

IH

CC

CC

CC

OUT

System Considerations

The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current I
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E

The magnitude of the transient current peaks is
dependent on the capacitive and inductive loading

should be decoded and used as the prima-

VPP should be
line from the

of the device outputs. The associated transient
voltage peaks can be suppressed by complying
with the two line output control and by properly se­lected decoupling capacitors . It is recommended
that a 0.1µF ceramic capacitor is used o n every
device between V
high frequency type of low inherent inductance
and should be placed as close as possible to the
device. In addition, a 4.7µF electro lytic capacitor
should be used between V

= 0mA,

CC

±1 µA

±10 µA

30 mA

1mA

10 µA

0.2V

CC

0.7V

CCVCC

2.4 V

+ 0.5

0.4 V

.

and VSS. This sho uld be a

and VSS for every

CC

eight devices. This capacitor should be mounted
near the power supply connect ion point. The pur­pose of this capacitor is to overcome the voltage
drop caused by the inductive ef fects of PC B trac­es.

V
V

CC

5/15

M27V320

Table 8. Read Mode AC Characteristics

(1)

(TA = 0 to 70°C or –40 to 85°C; VCC = 3.3V ± 10%)

Symbol Alt Parameter

t

AVQVtACC

t

BHQV

t

ELQV

t

GLQV

(2)

t

BLQZ

(2)

t

EHQZ

(2)

t

GHQZ

t

AXQX

t

BLQX

Note: 1. VCC must be ap pl i e d simultaneously with or before VPP and removed simultane ously or aft er V

2. Sampled only, not 100% tested.

3. Speed obt ai ned with High Speed AC measurement condition s.

Address Valid to Output Valid

t

BYTE High to Output Valid

ST

t

Chip Enable Low to Output Valid

CE

t

Output Enable Low to Output Valid

OE

t

BYTE Low to Output Hi-Z

STD

t

Chip Enable High to Output Hi-Z

DF

Output Enable High to Output

t

DF

Hi-Z
Address Transition to Output

t

OH

Transition

t

BYTE Low to Output Transition

OH

Test

Condition

E

= VIL,

GVPP = V

E

= VIL,

GVPP = V
G

VPP = V

E

= V

IL

E

= VIL,

GVPP = V
G

VPP = V

= V

E

IL

= VIL,

E

GVPP = V

E

= VIL,

GVPP = V

IL

IL

IL

IL

IL

IL

IL

(3)

-100

Min Max Min Max Min Max

100 120 150 ns

100 120 150 ns

100 120 150 ns

45 50 60 ns

45 50 50 ns

045050050ns

045050050ns

555ns

555ns

M27V320

-120 -15 0

PP.

Unit

Figure 6. Word-Wide Read Mode AC Waveforms

A0-A20

E

GV

PP

Q0-Q15

Note: BYTE = VIH.

VALID

tAVQV

tGLQV

tELQV

VALID

tAXQX

tEHQZ

tGHQZ

Hi-Z

AI02207

6/15

Figure 7. Byte-Wide Read Mode AC Waveforms

M27V320

A0-A20

E

GV

Q0-Q7

Note: BYTE = VIL.

PP

VALID

tAVQV

tGLQV

tELQV

Figure 8. BYTE Transition AC Waveforms

A0-A20

VALID

tAXQX

tEHQZ

tGHQZ

Hi-Z

AI02218

VALID

A–1

BYTE

Q0-Q7

Q8-Q15

Note: E = VIL; GVPP = VIL.

tAVQV

tBLQZ

tBLQX

VALID

Hi-Z

tAXQX

tBHQV

DATA OUT

DATA OUT

AI02219

7/15

M27V320

Table 9. Programming Mode DC Characteristics

(1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V)

Symbol Parameter Test Condition Min Max Unit

I

LI

I

CC

I

PP

V

V

V

OL

V

OH

V

Note: 1. VCC must be ap pl i e d simultaneously with or before VPP and removed simultane ously or aft er VPP.

Input Leakage Current
Supply Current 50 mA
Program Current
Input Low Voltage –0.3 0.8 V

IL

Input High Voltage 2.4

IH

Output Low Voltage
Output High Voltage TTL
A9 Voltage 11.5 12 .5 V

ID

Table 10. MARGIN MODE AC Characteristics

V

I

(1)

≤ VIN ≤ V

IL

E

= V

I

= 2.1mA

OL

= –2.5mA

OH

IH

IL

±10 µA

50 mA

V

+ 0.5

CC

0.4 V

3.5 V

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V)

Symbol Alt Parameter Test Condition Min Max Unit

t

A9HVPH

t

VPHEL

t

A10HEH

t

A10LEH

t

EXA10X

t

EXVPX

t

VPXA9X

Note: 1. VCC must be ap pl i e d simultaneously with or before VPP and removed simultane ously or aft er VPP.

t
t

t

AS10VA10

t

AS10VA10

t

AH10

t
t

VA9 High to VPP High

AS9

VPP High to Chip Enable Low

VPS

Chip Enable Transition to V
Chip Enable Transition to VPP Transition

VPH

VPP Transition to V

AH9

High to Chip Enable High (Set)
Low to Chip Enable High (Reset)

Transition

A10

Transition

A9

2µs
2µs
1µs
1µs
1µs
2µs
2µs

V

Programming

When delivered, all bits of the M27V320 are in the
'1' state. Data is introduced by selectively pro­gramming '0's into the desired bit locations. Al­though only '0's will be programmed, both '1's and
'0's can be present in the data word. The M27V320

8/15

is in the programming mode w hen VPP input is at

12.5V, G

VPP is at VIH and E is pulsed to VIL. The
data to be programmed is applied to 16 bits in par­allel to the data output pins. The levels required for
the address and data inputs are TTL. V

is spec-

CC

ified to be 6.25V ± 0.25V.

M27V320

Table 11. Programming Mode AC Characteristics

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V)

(1)

Symbol Alt Parameter Test Condition Min Max Unit

t

AVEL

t

QVEL

t

VCHEL

t

VPHEL

t

VPLVPH

t

ELEH

t

EHQX

t

EHVPX

t

VPLEL

t

ELQV

(2)

t

EHQZ

t

EHAX

Note: 1. VCC must be ap pl i e d simultaneously with or before VPP and removed simultane ously or aft er VPP.

2. Sampled only, not 100% tested.

t

t

t

VCS

t

OES

t

PRT

t

PW

t

DH

t

OEH

t
t

t

DFP

t

AS

DS

VR

DV

AH

Address Valid to Chip Enable Low 1 µs
Input Valid to Chip Enable Low 1 µs
VCC High to Chip Enable Low
VPP High to Chip Enable Low
VPP Rise Time

2µs
1µs

50 ns
Chip Enable Program Pulse Width (Initial) 45 55 µs
Chip Enable High to Input Transition 2 µs
Chip Enable High to VPP Transition
VPP Low to Chip Enable Low

2µs

1µs
Chip Enable Low to Output Valid 1 µs
Chip Enable High to Output Hi-Z 0 130 ns
Chip Enable High to Address Transition 0 ns

Figure 9. MARGIN MODE AC Waveforms

V

CC

A8

A9

tA9HVPH tVPXA9X

GV

PP

E

A10 Set

A10 Reset

tVPHEL

tA10HEH

tA10LEH

tEXVPX

tEXA10X

AI00736B

Note: A8 High lev el = 5V; A9 High level = 12V.

9/15

M27V320

Figure 10. Programming and Verify Modes AC Waveforms

A0-A20

tAVEL

Q0-Q15

tQVEL

V

CC

tVCHEL

GV

PP

tVPHEL

E

Note: BYTE = VIH; GVPP High level = 12V.

Figure 11. Programming Flowchart

VCC = 6.25V, VPP = 12V

SET MARGIN MODE

n = 0

E = 50µs Pulse

NO

NO

VERIFY

YES

Last

NO

Addr

YES

RESET MARGIN MODE

CHECK ALL WORDS

BYTE = V
1st: VCC = 5V
2nd: VCC = 3V

IH

++ Addr

YES

++n

= 25

FAIL

VALID

DATA IN DATA OUT

tEHQX

tEHVPX tELQV

tVPLEL

tELEH

PROGRAM VERIFY

PRESTO III P rog ra m mi ng Algorithm

The PRESTO III Programming Algorithm allows
the whole array to be program ed with a guaran­teed margin in a typical time of 100 seconds. Pro­gramming with PRESTO I II con sists of a pplying a
sequence of 50µs program pulses t o each word
until a correct verify occurs (see Figure 11). During
programing and verify operation a MARGIN
MODE circuit must be activated to guarantee that
each cell is programed with enough margin. No
overprogram pulse is applied since the verify in
MARGIN MODE provides the necessary margin to
each programmed cell.

Program Inhibit

Programming of multiple M27V320s in parallel
with different data is also easily accomplished. Ex­cept for E

, all like inputs including GVPP of the par­allel M27V320 may b e common. A TTL l ow level
pulse applied to a M27V320's E
12V, will program that M27V320. A high level E
put inhibits the ot her M27V320s from b eing pro­grammed.

Program Verify

A verify (read) should be performed on the pro­grammed bits to determine that they were correct­ly programmed. The verify is accomplished with

VPP at VIL. Data should be verified with t

AI05820

G
ter the falling edge of E

.

tEHAX

tEHQZ

AI02205

input and VPP at

ELQV

in-

af-

10/15

M27V320

Electronic Signature

The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufac turer and type. This m ode
is intended for use by program ming equipme nt to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am­bient temperature range that is required when pro­gramming the M27V320. To activate the ES mode,
the programming equipment must force 11.5V to

12.5V on address line A9 of the M27V320, with
V

= V

PP

= 5V. Two identifier bytes may th en be

CC

sequenced from the device outputs by toggling ad­dress line A0 from V
lines must be held at V

to VIH. All other address

IL

during Electronic Signa-

IL

ture mode.
Byte 0 (A0 = V

code and byte 1 (A0 = V

) represents the manufacturer

IL

) the device identifier

IH

code. For the STMicroelectronics M27V320, these
two identifier bytes are given in Table 4 and can be
read-out on outputs Q7 to Q0.

11/15

M27V320

Table 12. Ordering Information Scheme

Example: M27V320 -100 M 1

Device Type

M27

Supply Voltage

V = 3.3V ± 10%

Device Function

320 = 32 Mbit (4Mb x 8 or 2Mb x 16)

Speed

(1)

= 100 ns

-100

-120 = 120 ns

-150 = 150 ns

Package

M = SO44
N = TSOP48: 12 x 20 mm

Temperature Rang e

1 = 0 to 70 °C
6 = –40 to 85 °C

Note: 1. High Speed, see AC Char acterist ics section fo r f urther information .

For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this de­vice, please contact the STMicroelectronics Sales Office nearest to you.

Table 13. Revision History

Date Version Revision Details

December 2001 1.0 First Issue
26-Aug-2002 1.1 Document status moved to Data Sheet

12/15

M27V320

Table 14. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechan ical Data

Symbol

Typ Min Ma x Typ Min Max

A 2.80 0.1102
A1 0.10 0.0039
A2 2.30 2.20 2.4 0 0.0906 0.0866 0.0945

b 0.40 0.35 0.50 0.0157 0.0138 0.0197

C 0.15 0.10 0.20 0.0059 0.0039 0.0079
CP 0.08 0.0030

D 28.20 28.00 28.40 1.1102 1.1024 1.1181

e 1.27 – – 0.0500 – –

E 1 3.30 13.20 13.5 0 0.5236 0.5197 0.5315
EH 16.00 15.75 16.25 0.6299 0.6201 0.6398

L 0.80 0.0315
α 8° 8°
N44 44

millimeters inches

Figure 12. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

A2

A

C

b

e

CP

D

N

E

EH

1

Drawing is not to scale.

LA1 α

SO-d

13/15

M27V320

Table 15. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechani cal Data

Symb

Typ Min Max Typ Min Max

A 1.20 0.047

A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041

B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008

CP 0.10 0.004

D 19.80 20.20 0.780 0.795

D1 18.30 18.50 0.720 0.728

E 11.90 12.10 0.469 0 .476

e 0.50 - - 0.020 - -

L 0.50 0.7 0 0.020 0.028
α 0° 5° 0° 5°
N48 48

mm inc hes

Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline

A2

1 N

e

E

B

N/2

D1

D

DIE

A

CP

C

TSOP-a

Drawing is not to scale.

LA1 α

14/15

M27V320

Information furnished is believed to be ac curate and reliable. However, STMicroelectro ni cs assumes no resp onsibility for the consequ ences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or pat ent righ ts of STMicroe l ectronics . Specificati ons menti oned in thi s publication are subject
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