Page 1
M27V256
256 Kbit (32Kb x 8) Low Voltage UV EPROM and OTP EPROM
■ LOW VOLTAGE READ OPERATION:
3V to 3.6V
■ FAST ACCESS TIME: 90ns
■ LOW POWER CONSUMPTION:
CC
28
V
PP
1
8 x 13.4mm
8
– Active Current 10mA at 5MHz
– Standby Current 10µA
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIME: 100µs/byte (typical)
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 8Dh
DESCRIPTION
The M27V256 is a low voltage 256 Kbit EPROM
offered in the two ranges UV (ultra violet erase)
and OTP (one time programmable). It is ideally
suited for microprocessor systems and is organized as 32,768 by 8 bits.
The M27V256 operates in the read mode with a
supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP28W (window ceramic frit-seal package)
has a transparent lid which allows the user to expose the chiptoultraviolet light to erase the bit pattern. A new pattern can then be written to the
device by following the programming procedure.
28
1
FDIP28W (F) PDIP28 (B)
PLCC32 (K) TSOP28 (N)
Figure 1. Logic Diagram
V
15
A0-A14 Q0-Q7
Table 1. Signal Names
A0-A14 Address Inputs
Q0-Q7 Data Outputs
E Chip Enable
G Output Enable
V
PP
V
CC
V
SS
Program Supply
Supply Voltage
Ground
E
G
M27V256
V
SS
AI01908
1/15May 1998
Page 2
M27V256
Figure 2A. DIP Pin Connections
V
PP
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q2
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
M27V256
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI01909
V
CC
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5Q1
Q4
Q3V
Figure 2B. LCC Pin Connections
PP
CC
A13
DU
32
DU
V
Q3
A14
Q4
25
Q5
A8
A9
A11
NC
G
A10
E
Q7
Q6
AI01910
V
A7
A12
A6
A5
A4
A3
A2
9
A1
A0
NC
Q0
Q1
Warning: NC = Not Connected, DU = Dont’t Use.
1
M27V256
17
Q2
SS
V
Figure 2C. TSOP Pin Connections
G
A11
A13
A14
V
V
A12
A9
A8
CC
PP
A7
A6
A5
A4
A3
22
28
M27V256
1
78
21
15
14
AI01911
A10
E
Q7
Q6
Q5
Q4
Q3
V
SS
Q2
Q1
Q0
A0
A1
A2
For applications where the content is programmed
only one time and erasure is not required, the
M27V256 is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages.
DEVICE OPERATION
The modes of operation of the M27V256are listed
in the Operating Modes. A single power supply is
required in the read mode. All inputs are TTL levels except for VPPand 12V on A9 for Electronic
Signature.
Read Mode
The M27V256 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time
(t
) is equal to the delay from E to output
AVQV
(t
). Data is available at the output after delay
ELQV
of t
from the falling edge of G, assuming that
GLQV
E has been low and the addresses have been stable for at least t
AVQV-tGLQV
.
2/15
Page 3
M27V256
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device.These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program andother relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V
+0.5V with possible overshoot to VCC+2V for a period less than 20ns.
CC
(3)
–40 to 125 °C
Table 3. Operating Modes
Mode E G A9
Read
Output Disable V
Program
V
Verify V
Program Inhibit
Standby
Electronic Signature
Note: X = VIHor VIL,VID= 12V ± 0.5V.
V
IL
IL
Pulse V
IL
IH
V
IH
V
IH
V
IL
V
IL
V
IH
IH
V
IL
V
IH
X
XVCCHi-Z
X
XVPPData Out
X
XX
V
IL
V
ID
V
PP
V
CC
V
PP
V
PP
V
CC
V
CC
Data Out
Q0-Q7
Data In
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code
Device Code
V
IL
V
IH
Standby Mode
The M27V256 hasastandbymodewhich reduces
the supply current from 10mA to 10µA with low
voltage operationVCC≤ 3.6V, seeRead Mode DC
00100000 20h
10001101 8Dh
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
Characteristics table for details. The M27V256 is
3/15
Page 4
M27V256
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: Sampled only, not 100% tested.
Input Capacitance
Output Capacitance V
(1)
(TA=25°C, f = 1 MHz)
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
C
L
CL= 30pF for High Speed
CL= 100pF for Standard
CLincludes JIG capacitance
V
=0V
IN
=0V 12 pF
OUT
6pF
OUT
AI01823B
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E shouldbe decoded and used as theprimary device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
4/15
system control bus. This ensures that all deselected memory devices are intheir lowpower standby
mode and hat the output pins are only active when
data is desired from a particular memory device.
System Considerations
The power switching characteristics of Advance
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three segments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
this transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
Page 5
M27V256
Table 7. Read Mode DC Characteristics
(1)
(TA = 0 to 70°C or –40 to 85°C; VCC= 3.3V ± 10%;VPP=VCC)
Symbol Parameter Test Condition Min Max Unit
I
I
I
CC
I
CC1
I
CC2
I
V
V
IH
V
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Table 8A. Read Mode AC Characteristics
Input Leakage Current
LI
Output Leakage Current
LO
Supply Current
E=V
IL
f = 5MHz, V
0V ≤ V
0V ≤ V
,G=VIL,I
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
PP
Input Low Voltage –0.3 0.8 V
IL
(2)
Input High Voltage 2
Output Low Voltage
OL
Output High Voltage TTL
OH
Output High Voltage CMOS
2. Maximum DC voltage on Output is V
CC
+0.5V.
(1)
E>V
CC
I
I
OH
OH
≤ V
IN
CC
≤ V
OUT
E=V
CC
IH
CC
OUT
≤ 3.6V
= 0mA,
–0.2V,VCC≤ 3.6V
V
PP=VCC
I
= 2.1mA
OL
= –400µA
= –100µA
2.4 V
Vcc – 0.7V V
±10 µA
±10 µA
10 mA
1mA
10 µA
10 µA
V
+1
CC
0.4 V
(TA= 0 to 70 °C or –40 to 85°;VCC= 3.3V ± 10%; VPP=VCC)
M27V256
Symbol Alt Parameter Test Condition
-90
(3)
-100
Min Max Min Max
Unit
V
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between V
and VSS. This should be a high frequency capacitor of low inherent inductance and should be
(2)
(2)
t
Address Valid to Output Valid E = VIL,G=V
ACC
t
Chip Enable Low to Output Valid
CE
t
Output Enable Low to Output Valid
OE
t
Chip Enable High to Output Hi-Z G = V
DF
t
Output Enable High to Output Hi-Z
DF
Address Transition to Output
t
OH
Transition
CC
90 100 ns
90 100 ns
40 45 ns
025030ns
025030ns
00ns
G=V
E=V
E=V
E=V
,G=V
IL
IL
IL
IL
IL
IL
IL
placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be
used between VCCand VSSfor every eight devices. The bulk capacitor should be located near the
power supplyconnection point. The purposeof the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
Page 6
M27V256
Table 8B. Read Mode AC Characteristics
(1)
(TA= 0 to 70°C or –40 to 85 °C; VCC= 3.3V ± 10%;VPP= Vcc)
M27V256
Symbol Alt Parameter Test Condition
-120 -150 -200
Min Max Min Max Min Max
t
AVQVtACC
t
ELQVtCE
t
GLQVtOE
(2)
t
EHQZ
(2)
t
GHQZ
t
AXQXtOH
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
Address Valid to Output Valid
Chip Enable Low to Output
Valid
Output Enable Low to Output
Valid
Chip Enable High to Output
t
DF
Hi-Z
Output Enable High to Output
t
DF
Hi-Z
Address Transition to Output
Transition
E=V
,G=V
IL
G=V
E=V
G=V
E=V
IL
IL
IL
IL
IL
120 150 200 ns
120 150 200 ns
45 50 60 ns
035040050ns
035040050ns
E = VIL, G =VIL 0 0 0 ns
Figure 5. Read Mode AC Waveforms
Unit
A0-A14
E
G
Q0-Q7
VALID
tAVQV
tGLQV
tELQV
Programming
The M27V256 has been designed to befully compatible with the M27C256B and has the same
electronic signature. As a result the M27V256 can
be programmed as the M27C256B on the same
programming equipments applying 12.75V on V
PP
and 6.25V on VCCby the use of the same PRESTO II algorithm. When delivered (and after each
erasure for UV EPROM), all bits of the M27V256
are inthe ’1’ state. Data is introduced by selectively programming ’0’s into the desired bit locations.
VALID
tAXQX
tEHQZ
tGHQZ
Hi-Z
AI00758B
Although only ’0’s will be programmed, both ’1’s
and ’0’scan be present in the data word. The only
way to change a ’0’ to a ’1’ is by die exposition to
ultraviolet light (UV EPROM). The M27V256 is in
the programming mode when VPPinput is at
12.75V, G isat VIHandE is pulsed to VIL. The data
to be programmed is applied to 8 bits inparallel to
the data output pins. The levels required for the
address and data inputs are TTL. VCCis specified
to be 6.25 V ± 0.25 V.
6/15
Page 7
M27V256
Table 9. Programming Mode AC Characteristics
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)
Symbol Parameter Test Condition Min Max Unit
I
LI
I
CC
I
PP
V
IL
V
IH
V
OL
V
OH
V
ID
Note: VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics
Input Leakage Current
≤ VIN≤ V
V
IL
IH
±10 µA
Supply Current 50 mA
Program Current
E=V
IL
50 mA
Input Low Voltage –0.3 0.8 V
V
Input High Voltage 2
CC
+ 0.5
Output Low Voltage IOL= 2.1mA 0.4 V
I
Output High Voltage TTL
OH
= –1mA
3.6 V
A9 Voltage 11.5 12.5 V
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V
Symbol Alt Parameter Test Condition Min Max Unit
t
AVEL
t
QVEL
t
VPHEL
t
VCHEL
t
ELEH
t
EHQX
t
QXGL
t
GLQV
t
GHQZ
t
GHAX
Note: VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
t
t
t
VPS
t
VCS
t
t
t
OES
t
t
DFP
t
Address Validto Chip Enable Low 2 µs
AS
Input Valid to Chip Enable Low 2 µs
DS
VPPHigh to Chip Enable Low
VCCHigh to Chip Enable Low
Chip Enable Program Pulse Width 95 105 µs
PW
Chip Enable High to Input Transition 2 µs
DH
2 µs
2 µs
Input Transition to Output Enable Low 2 µs
Output Enable Low to Output Valid 100 ns
OE
Output Enable High to Output Hi-Z 0 130 ns
Output Enable High to Address
AH
Transition
0ns
V
7/15
Page 8
M27V256
Figure 6. rogramming and Verify Modes AC Waveforms
A0-A14
tAVEL
Q0-Q7
V
PP
V
CC
E
G
DATA IN DATA OUT
tQVEL
tVPHEL
tVCHEL
tELEH
Figure 7. Programming Flowchart
VCC= 6.25V, VPP= 12.75V
n=0
E = 100µs Pulse
NO
NO
VERIFY
YES
Last
NO
Addr
YES
CHECK ALL BYTES
1st: VCC=6V
2nd: VCC= 4.2V
++ Addr
YES
++n
=25
FAIL
VALID
tEHQX
tGLQV
tQXGL
PROGRAM VERIFY
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows to program the whole array with a guaranteed margin, in
a typical time of 3.5 seconds. Programming with
PRESTO II involves the application of a sequence
of 100µs program pulses to each byte until a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE
circuit is automatically activated in order to guarantee that each cell is programmed with enough
margin. Nooverprogram pulse isapplied since the
verify in MARGIN MODE at VCCmuch higher than
3.6V provides necessary margin to each programmed cell.
Program Inhibit
Programming of multiple M27V256s in parallel
with different data is also easily accomplished. Except for E,all like inputs including G of the parallel
M27V256 may be common.A TTL low level pulse
applied to a M27V256’s E input, with VPPat 12.75
V, will program that M27V256. A high level E input
inhibits the other M27V256s from being programmed.
Program Verify
A verify (read) should be performed on the pro-
AI00760B
grammed bits to determine that they were correctly programmed. The verify is accomplished with G
at VIL, E at VIH,VPPat 12.75V and VCCat 6.25V.
tGHQZ
tGHAX
AI00759
8/15
Page 9
M27V256
On-Board Programming
The M27V256 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically matchthe device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C ambient temperaturerange that is required when programming theM27V256. To activatethe ES mode,
the programming equipment must force 11.5V to
12.5V on address line A9 of the M27V256, with
VCC=VPP= 5V. Two identifier bytes may then be
sequenced from the device outputs by toggling address line A0 from VILto VIH. All other address
lines must be held at VILduring Electronic Signature mode. Byte 0 (A0=VIL) represents the manufacturer code and byte 1 (A0=VIH) the device
identifier code. For the STMicroelectronics
M27V256, these two identifier bytes are given in
Table 4 and can be read-out on outputs Q0 to Q7.
Note that the M27V256 and M27C256B have the
same identifier bytes.
ERASURE OPERATION (applies for UV EPROM)
The erasure characteristics of the M27V256 is
such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluorescent lighting could erase a typical M27V256 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27V256 is to be exposed to these
types of lighting conditions for extended periods of
time, itis suggested that opaquelabels beput over
the M27V256 window to prevent unintentional erasure. The recommended erasure procedure for
the M27V256 is exposure to short wave ultraviolet
light which has wavelength 2537Å. The integrated
dose (i.e.UV intensityx exposure time) forerasure
should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to
20 minutes using an ultraviolet lamp with 12000
µW/cm2power rating. The M27V256 should be
placed within 2.5 cm (1 inch) of the lamp tubes
during the erasure. Some lamps have a filter on
their tubes which should be removed before erasure.
9/15
Page 10
M27V256
Table 11. Ordering Information Scheme
Example: M27V256 -90 K 1 TR
Device Type
Speed
(1)
-90
=90ns
-100 = 100 ns
-120 = 120 ns
-150 = 150 ns
-200 = 200 ns
Package
F = FDIP28W
B = PDIP28
K = PLCC32
N = TSOP28: 8 x 13.4mm
Temperature Range
1 = –0 to 70 °C
6 = –40 to 85 °C
Option
TR =Tape & Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
10/15
Page 11
M27V256
Table 12. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
Symb
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 36.50 37.34 1.437 1.470
D2 33.02 – – 1.300 – –
E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 0.125
S 1.52 2.49 0.060 0.098
∅ 7.11 – – 0.280 – –
α 4° 11° 4° 11°
N28 28
Typ Min Max Typ Min Max
mm inches
Figure 8. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline
A2
B1 B e
A3A1A
L
α
C
eA
D2
eB
D
S
N
∅
1
Drawing is not to scale.
E1 E
FDIPW-a
11/15
Page 12
M27V256
Table 13. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 36.83 37.34 1.450 1.470
D2 33.02 – – 1.300 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.08 0.070 0.082
α 0° 10° 0° 10°
mm inches
N28 28
Figure 9. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline
A2A1A
L
B1 B e1
D2
α
C
eA
eB
D
S
N
E1 E
1
PDIP
Drawing is not to scale.
12/15
Page 13
M27V256
Table 14. PLCC32 - 32lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data
Symb
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 – 0.38 – 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004
Typ Min Max Typ Min Max
mm inches
Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline
D
D1
1N
Ne E1 E
F
D2/E2
A2
B
0.51 (.020)
1.14 (.045)
PLCC
Drawing is not to scale.
Nd
R
CP
A
A1
B1
e
13/15
Page 14
M27V256
Table 15. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A 1.00 1.25 0.039 0.049
A1 0.20 0.008
A2 0.95 1.05 0.037 0.041
B 0.30 0.012
C 0.10 0.21 0.004 0.008
D 13.10 13.70 0.516 0.539
D1 11.70 11.90 0.461 0.469
E 7.90 8.25 0.311 0.325
e 0.55 - - 0.022 - -
L 0.30 0.70 0.012 0.028
α 0° 5° 0° 5°
N28 28
CP 0.10 0.004
mm inches
Figure 11. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm, Package Outline
A2
22
21
e
28
1
E
B
78
D1
D
DIE
A
CP
C
TSOP-c
Drawing is not to scale
LA1 α
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