Page 1
2 Mbit (128Kb x16) UV EPROM and OTP EPROM
■ 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■ ACCESS TIME: 45ns
■ LOW POWER CONSUMPTION:
– Active Current 50mA at 5MHz
– Standby Current 100µA
■ PROGRAMMING VOLTAGE: 12.75V± 0.25V
■ PROGRAMMING TIME: 100µs/word
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 1Ch
40
1
FDIP40W (F) PDIP40 (B)
40
M27C202
1
DESCRIPTION
The M27C202 is a 2 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for microprocessor systems requiring large programs, in
the application where the contents is stable and
needs to be programmed only one time,and is organised as 131,072by 16 bits.
The FDIP40W (window ceramic frit-seal package)
has a transparent lids which allow the user to expose the chip to ultraviolet light to erase the bitpattern. A new pattern can then be written to the
device by following the programming procedure.
For applications wherethe content is programmed
only one time and erasure is not required, the
M27C202 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 14mm) packages.
PLCC44 (K)
Figure 1. Logic Diagram
V
CC
17
A0-A16
P
E
G
M27C202
V
SS
V
PP
TSOP40 (N)
10 x 14 mm
16
Q0-Q15
AI01815
1/15April 1999
Page 2
M27C202
Figure 2A. DIP Connections
1
V
PP
2
3
Q15
Q14
4
Q13
5
6
Q12
7
Q11
8
Q10
9
Q9
10
Q8
V
SS
Q7
Q6
Q5
Q4
Q3
Q2
Q0
11
12
13
14
15
16
17
18
19
M27C202
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
2120
AI02784
V
CC
PE
A16
A15
A14
A13
A12
A11
A10
A9
V
SS
A8
A7
A6
A5
A4
A3
A2Q1
A1
A0G
Figure 2B. TSOP Connections
1
A9
A10
A11
A12 A6
A13 A5
A14
A15
A16
P
V
V
DQ15
DQ14
DQ13
DQ12 DQ4
DQ11 DQ5
DQ10
DQ9
DQ8
10
CC
11
PP
E
20 21
M27C202
AI01817B
40
31
30
V
SS
A8
A7
A4
A3
A2
A1
A0
G
DQ0
DQ1
DQ2
DQ3
DQ6
DQ7
V
SS
Figure 2C. LCC Connections
CC
VPPE
Q15
Q13
Q14
Q12
Q11
Q10
Q9 A10
Q8
V
SS
NC
Q6
Q5
Q4
12
Q3
Q2
Q1
Q0
M27C202
23
G
P
V
NC
1
44
NC
A0
A1
A16
A2
A15
A3
A14
34
A4
A13
A12
A11
A9
V
SS
NC
A8Q7
A7
A6
A5
AI01816
Table 1. Signal Names
A0-A16 Address Inputs
Q0-Q15 Data Outputs
E Chip Enable
G Output Enable
P Program
V
PP
V
CC
V
SS
NC Not Connected Internally
Program Supply
Supply Voltage
Ground
2/15
Page 3
M27C202
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or anyother conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extendedperiods may affect device reliability. Referalso to the STMicroelectronics SURE Program andother relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V
+0.5V with possible overshoot to VCC+2V for a period less than 20ns.
CC
(3)
–40 to 125 °C
Table 3. Operating Modes
Mode E G P A9
Read
Output Disable V
Program
Verify V
Program Inhibit
Standby
Electronic Signature
Note: X = VIHor VIL,VID= 12V ± 0.5V.
V
IL
IL
V
IL
IL
V
IH
V
IH
V
IL
V
IL
V
IH
X
V
IL
V
IH
X
XXV
V
IL
Pulse
V
IH
X
XVPPData Output
XXX
XXX
V
IL
V
IH
V
ID
V
PP
V
or V
CC
SS
or V
CC
SS
V
PP
V
PP
V
or V
CC
SS
V
CC
Q15-Q0
Data Output
Hi-Z
Data Input
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code
Device Code
Note: Outputs Q15-Q8 are set to ’0’.
V
IL
V
IH
00100000 20h
00011100 1Ch
3/15
Page 4
M27C202
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: 1. Sampled only, not 100% tested.
Input Capacitance
Output Capacitance
(1)
(TA=25°C, f = 1 MHz)
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
C
L
CL= 30pF for HighSpeed
CL= 100pF for Standard
CLincludes JIG capacitance
V
V
IN
OUT
=0V
=0V
6pF
12 pF
OUT
AI01823B
DEVICE OPERATION
The operatingmodes of the M27C202 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for VPPand 12V on A9 for Electronic
Signature.
Read Mode
The M27C202 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable(G) is the output control and should
be used to gate data to the output pins, indepen-
4/15
dent of device selection. Assuming that the addresses are stable, the address access time
(t
) is equal to the delay from E to output
AVQV
(t
). Data is available atthe outputafter a delay
ELQV
of tOEfrom the falling edge of G, assuming that E
has been low and the addresses have been stable
for at leastt
AVQV-tGLQV
.
Standby Mode
The M27C202 has astandby mode which reduces
the supply current from 50mA to 100µA.
The M27C202 is placed in the standby mode by
applying a TTL high signal to the E input. When in
the standbymode, theoutputs are in a high impedance state, independent of the G input.
Page 5
M27C202
Table 7. Read Mode DC Characteristics
(1)
(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC=5V±10%; VPP=VCC)
Symbol Parameter Test Condition Min Max Unit
I
I
I
CC
I
CC1
I
CC2
I
V
V
IH
V
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Input Leakage Current
LI
Output Leakage Current
LO
Supply Current
Supply Current (Standby) TTL E = V
Supply Current (Standby) CMOS
Program Current
PP
Input Low Voltage –0.3 0.8 V
IL
(2)
Input High Voltage 2
Output Low Voltage
OL
Output High VoltageTTL IOH= –400µA 2.4 V
OH
Output High VoltageCMOS
2. Maximum DC voltage on Output is V
CC
+0.5V.
I
OUT
0V ≤ V
0V ≤ V
E=V
E>V
I
I
OH
≤ V
IN
CC
≤ V
OUT
IL
= 0mA, f = 5MHz
CC
V
PP=VCC
= 2.1mA
OL
= –100µAV
CC
,G=VIL,
IH
– 0.2V
CC
– 0.7V
±10 µA
±10 µA
50 mA
1mA
100 µA
100 µA
V
+1
CC
0.4 V
V
V
Two Line Output Control
Because OTP EPROMs are usually used in larger
memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, Eshould be decoded and used as the primary device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system controlbus. This ensures that alldeselected memory devices are intheir low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three segments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
transient current peaks is dependent on the capacitive and inductive loading of the device at the
output. The associated transient voltage peaks
can be suppressed by complying with the two line
outputcontrol and byproperly selected decoupling
capacitors.It is recommended that a 0.1µF ceramic capacitor be used on every device between V
CC
and VSS. This should be a high frequency capacitor of low inherent inductance and should be
placed as close to the device as possible. Inaddition, a 4.7µF bulk electrolytic capacitor should be
used between VCCand VSSfor every eight devices. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
Page 6
M27C202
Table 8. Read Mode AC Characteristics
(1)
(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC=5V±10%; VPP=VCC)
M27C202
Symbol Alt Parameter Test Condition
-45
(3)
-70
(3)
Min Max Min Max Min Max Min Max
Address Validto
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
t
ACC
Output Valid
Chip Enable Low to
t
CE
Output Valid
Output Enable Low
t
OE
to Output Valid
(2)
(2)
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Chip Enable High to
t
DF
Output Hi-Z
Output Enable High
t
DF
to Output Hi-Z
Address Transitionto
t
OH
Output Transition
E=V
G=V
G=V
E=V
,G=V
IL
E=V
E=V
,G=V
IL
IL
IL
IL
IL
IL
IL
45 70 80 100 ns
45 70 80 100 ns
25 40 40 50 ns
0 25 0 30 0 30 0 30 ns
0 25 0 30 0 30 0 30 ns
0000ns
Figure 5. Read Mode AC Waveforms
-80 -100
Unit
A0-A16
E
G
Q0-Q15
tAVQV
tELQV
VALID
tGLQV
VALID
tAXQX
tEHQZ
tGHQZ
Hi-Z
AI01818B
6/15
Page 7
M27C202
Table 9. Programming Mode DC Characteristics
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)
Symbol Parameter Test Condition Min Max Unit
I
LI
I
CC
I
PP
V
IL
V
IH
V
OL
V
OH
V
ID
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics
Input Leakage Current
0 ≤ V
≤ V
IN
IH
±10 µA
Supply Current 50 mA
Program Current
E=V
IL
50 mA
Input Low Voltage –0.3 0.8 V
V
Input High Voltage 2
CC
+ 0.5
Output Low Voltage IOL= 2.1mA 0.4 V
I
Output High Voltage TTL
= –400µA
OH
2.4 V
A9 Voltage 11.5 12.5 V
(1)
(TA=25°C; VCC= 6.25V ± 0.25V; VPP= 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
t
AVPL
t
QVPL
t
VPHPL
t
VCHPL
t
ELPL
t
PLPH
t
PHQX
t
QXGL
t
GLQV
(2)
t
GHQZ
t
GHAX
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
t
t
t
VPS
t
VCS
t
CES
t
t
t
OES
t
t
DFP
t
Address Valid to Program Low 2 µs
AS
Input Valid to Program Low 2 µs
DS
VPPHigh to Program Low
VCCHigh to Program Low
2 µs
2 µs
Chip Enable Low to Program Low 2 µs
Program Pulse Width 95 105 µs
PW
Program High to Input Transition 2 µs
DH
Input Transition to Output Enable Low 2 µs
Output Enable Low to Output Valid 100 ns
OE
Output Enable High to Output Hi-Z 0 130 ns
Output Enable High to Address
AH
Transition
0ns
V
Programming
When delivered (and after each ‘1’serasure for UV
EPROM), all bits of the M27C202 are in the ’1’
state. Data is introduced by selectively programming ’0’s into the desired bit locations. Although
only ’0’s will beprogrammed,both ’1’sand ’0’s can
be present in the data word. The only way to
change a ‘0’ to a ‘1’is by die exposure to ultraviolet
light (UV EPROM). The M27C202 is in the programming mode when VPPinput is at 12.75V,E is
at VILand P is pulsed to VIL. The data to be programmed is applied to 16 bits in parallel, to the
data output pins. The levels required for the address and data inputs are TTL. VCCis specified to
be 6.25V ± 0.25V.
7/15
Page 8
M27C202
Figure 6. Programming and Verify Modes AC Waveforms
A0-A15
tAVPL
Q0-Q15
tQVPL
V
PP
tVPHPL
V
CC
tVCHPL
E
tELPL
P
tPLPH
G
Figure 7. Programming Flowchart
VCC= 6.25V, VPP= 12.75V
n=0
P = 100µs Pulse
NO
NO
VERIFY
YES
Last
NO
Addr
YES
CHECK ALL WORDS
1st: VCC=6V
2nd: VCC= 4.2V
++ Addr
YES
++n
=25
FAIL
VALID
DATA IN DATA OUT
tPHQX
tGLQV
tQXGL
PROGRAM VERIFY
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows programming of the whole array with a guaranteed
margin, in a typical time of 13 seconds. Programming with PRESTO II consists of applying a sequence of 100µs program pulses to each word
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE provides necessary margin to each programmed cell.
Program Inhibit
Programming of multiple M27C202s in parallel
with different data is also easily accomplished. Except for E, all like inputs including G of the parallel
M27C202 may be common. A TTL low level pulse
applied to a M27C202’s P input, with E low and
VPPat 12.75V, will program that M27C202. A high
level E input inhibits the other M27C202s from being programmed.
Program Verify
AI00707C
A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with E
and G at VIL, P at VIH,VPPat 12.75V and VCCat
6.25V.
tGHQZ
tGHAX
AI00706
8/15
Page 9
M27C202
On-Board Programming
The M27C202 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C ambient temperaturerange that is required when programming the M27C202. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V onaddress lineA9 of the M27C202
with VPP=VCC= 5V. Two identifier bytes may
then be sequenced fromthe deviceoutputs by toggling address line A0 from VILto VIH. All other address lines must be held at VILduring Electronic
Signature mode. Byte 0 (A0 = VIL) represents the
manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the STMicroelectronics
M27C202, these two identifier bytes are given in
Table 4and canbe read-out on outputs Q7 to Q0.
ERASURE OPERATION(applies to UV EPROM)
The erasure characteristics of the M27C202 is
such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluorescent lighting could erase a typical M27C202 in
about 3 years, while it would takeapproximately 1
week to cause erasure when exposed to direct
sunlight. If the M27C202 is to be exposed to these
types of lighting conditions for extended periods of
time, it issuggested that opaquelabels be put over
the M27C202 windowto prevent unintentionalerasure. The recommended erasure procedure for
the M27C202 is exposure to short wave ultraviolet
light which has wavelength 2537 Å. The integrated
dose (i.e.UV intensityx exposure time) for erasure
should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to
20 minutes using an ultraviolet lamp with
12000µW/cm2power rating. The M27C202 should
be placed within 2.5 cm (1 inch) of the lamp tubes
during the erasure. Some lamps have a filter on
their tubes which should be removed before erasure.
9/15
Page 10
M27C202
Table 11. Ordering Information Scheme
Example: M27C202 -80 K 1 TR
Device Type
M27
Supply Voltage
C=5V±10%
Device Function
202 = 2 Mbit (128Kb x16)
Speed
(1)
=45ns
-45
(1)
-70
=70ns
-80 = 80 ns
-100 = 100 ns
Not For New Design
(2)
-120 = 120 ns
-150 = 150 ns
-200 = 200 ns
Package
F = FDIP40W
B = PDIP40
K = PLCC44
N = TSOP40: 10 x 14 mm
Temperature Range
1=0to70°C
3 = –40 to 125 °C
6=–40to85°C
Options
TR = Tape& Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
2. These speeds are replaced by the 100ns.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
10/15
Page 11
M27C202
Table 12. FDIP40W - 40 lead Ceramic Frit-seal DIP with window, Package Mechanical Data
Symb
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 51.79 52.60 2.039 2.071
D2 48.26 – – 1.900 – –
E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 – 0.125 –
S 1.52 2.49 0.060 0.098
∅ 8.13 – – 0.320 – –
α 4° 11° 4° 11°
N40 40
Typ Min Max Typ Min Max
mm inches
Figure 8. FDIP40W - 40 lead Ceramic Frit-seal DIP with window, Package Outline
A2
B1 B e
A3A1A
L
α
C
eA
D2
eB
D
S
N
∅
1
Drawing is notto scale.
E1 E
FDIPW-a
11/15
Page 12
M27C202
Table 13. PDIP40 - 40 pin Plastic DIP, 600 mils width, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A 4.45 – – 0.175 – –
A1 0.64 0.38 – 0.025 0.015 –
A2 3.56 3.91 0.140 0.154
B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.31 0.008 0.012
D 51.78 52.58 2.039 2.070
D2 48.26 – – 1.900 – –
E 14.80 16.26 0.583 0.640
E1 13.46 13.99 0.530 0.551
e1 2.54 – – 0.100 – –
eA 15.24 – – 0.600 –
eB 15.24 17.78 0.600 0.700
L 3.05 3.81 0.120 0.150
S 1.52 2.29 0.060 0.090
α 0° 15° 0° 15°
N40 40
mm inches
Figure 9. PDIP40 - 40 lead Plastic DIP, 600 mils width, Package Outline
A2A1A
L
B1 B e1
D2
α
eA
eB
D
S
N
E1 E
1
Drawing is notto scale.
C
PDIP
12/15
Page 13
M27C202
Table 14. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A 4.20 4.70 0.165 0.185
A1 2.29 3.04 0.090 0.120
A2 – 0.51 – 0.020
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 17.40 17.65 0.685 0.695
D1 16.51 16.66 0.650 0.656
D2 14.99 16.00 0.590 0.630
E 17.40 17.65 0.685 0.695
E1 16.51 16.66 0.650 0.656
E2 14.99 16.00 0.590 0.630
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N44 44
CP 0.10 0.004
mm inches
Figure 10. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline
D
D1
1N
Ne E1 E
F
D2/E2
0.51 (.020)
1.14 (.045)
Nd
R
PLCC
Drawing is notto scale.
A1
A2
B1
e
B
A
CP
13/15
Page 14
M27C202
Table 15. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041
B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 13.80 14.20 0.543 0.559
D1 12.30 12.50 0.484 0.492
E 9.90 10.10 0.390 0.398
e 0.50 – – 0.020 – –
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N40 40
CP 0.10 0.004
mm inches
Figure 11. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Outline
A2
1N
e
E
B
N/2
D1
D
DIE
A
CP
C
TSOP-a
Drawing is notto scale.
LA1 α
14/15
Page 15
M27C202
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
1999 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners.
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom -U.S.A.
STMicroelectronics GROUP OF COMPANIES
http://www.st.com
15/15
Loading...