Datasheet M2732A-20F6, M2732A-20F1, M2732A-F6, M2732A-F1, M2732A-4F1 Datasheet (SGS Thomson Microelectronics)
...
AI00780B
12
A0-A11 Q0-Q7
V
CC
M2732A
GV
PP
E
V
SS
8
Figure 1. Logic Diag ra m
M2732A
NMOS 32K (4K x 8) UV EPROM
FA ST ACCESS TIME: 200ns
EXTENDED TEMPERATURE RANGE
SINGLE 5V SUPPLY VOLTAGE
LOW STANDBY CURRE NT: 35mA max
INPUTS and OUTP UT S TT L CO MPATIB LE
DURING REA D a n d PRO GR AM
COM P LETELY STATIC
DESCRIP TION
The M2732A is a 32,768 bit UV erasable and
electrically programmable memory EPROM. It is
organized as 4,0 96 words by 8 bit s. The M2732A
with its single 5V pow er supply an d with an acc ess
time of 200 ns, is ideal suited for applications wher e
fast turn around and pattern experimentation one
important requirements.
The M2732A is honsed in a 24 pin Window Ceramic
Frit-Seal Dual-in-Line pac kage. The transparent lid
allows the user to expose the chip t o ultraviolet light
to erase the bit patt ern. A new pattern can be then
written to the cleric e by following t he programmi ng
procedure.
A0 - A11 Address Inputs
Q0 - Q7 Data Outputs
E Chip Enable
GV
PP
Output Enable / Program Supply
V
CC
Supply Voltage
V
SS
Ground
T able 1. Signal Names
1
24
FDIP24W (F)
July 1994 1/9
Q2
V
SS
A3
A0
Q0
Q1
A2
A1
GV
PP
Q5
A10
E
Q3
A11
Q7
Q6
Q4
A4
V
CC
A7
AI00781
M2732A
8
1
2
3
4
5
6
7
9
10
11
12
20
19
18
17
16
15
A6
A5
A9
A8
23
22
21
14
13
24
Figure 2. DIP Pin Connecti ons
Symbol Parameter Value Unit
T
A
Ambient Operating Temperature grade 1
grade 6
0 to 70
–40 to 85
°C
T
BIAS
Temperature Under Bias grade 1
grade 6
–10 to 80
–50 to 95
°C
T
STG
Storage Temperature –65 to 125 °C
V
IO
Input or Output Voltages –0.6 to 6 V
V
CC
Supply Voltage –0.6 to 6 V
V
PP
Program Supply Voltage –0.6 to 22 V
Note: Except for the rating "Operating T emperature R ange", stresses above those lis ted in the Table "Absolute Maximum Ratings" may cause
permanent damage to the device. These are stress ratings only and opera tion of the device at these or any other conditions above those
indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rati ng conditions for extended periods
may affect device reliabil ity. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
Tab le 2. Absol ute Maxim u m Ratin gs
DEVICE OPER ATION
The six modes of operation for the M2732A are
listed in the Operating Modes Table. A single 5V
power supply is required in the read mode. All
inputs are TTL level except for V
PP.
Read Mode
The M2732A has two control functions, both of
which must be logically satisfied in order to obtai n
data at the outputs. Chip Enable (
E) is the power
control and should be used for device selection.
Output Enable (
G) is the output control and should
be used to gate data to the output pins, independent of device selection.
Assuming that the addresses are stable, address
access time (t
AVAQ
) is equal to the delay fr om E to
output (t
ELQV
). Data is available at the outputs after
the falling edge of
G, assuming that E has been low
and the addresses have been stable for at least
t
AVQ V-tGLQV
.
Stand by Mod e
The M2732A has a standby mode which reduces
the active power current by 70 %, from 125 mA to
35 mA. The M2732A is placed in the sta ndby mode
by applying a TTL high signal to
E input. When in
standby mode, the outputs are in a high impedance
state, independent of the
GVPP input.
Two Line Output Control
Because M2732A ’s are usually used in larger memory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus content i on
will not occur.
To most efficiently use these two control lines, it is
recommended that
E be decoded and used as the
primary device selecting function, while
G should
be made a common connection to all devices in the
array and connected to the
READ line from the
system control bus.
This ensures that all deselected memory devices
are in their low power standby mode and that the
output pins are only active when data is required
from a particular memory device.
2/9
M2732A
Programmin g
When delivered, and after each erasure, all bits of
the M2732A are in the “1" state. Data is introduce d
by selectively programming ”0’s" into the desired
bit locations. Although only “0’s” will be programmed, both “1’s” a nd “0’s” c an be present ed in
the data word. The only way to change a “0" to a
”1" is by ultraviolet light erasure.
The M2732A is in the programming mode when the
GVPP input is at 21V. A 0.1µF capacitor must be
placed across
GVPP and ground to suppress spurious voltage transients which may damage the
device. The data to be programmed is applied, 8
bits in parallel, to the data output pins. The levels
required for the address and data inputs are TTL.
When the address and data are stable, a 50ms,
active low, TTL program pulse is applied to the
E
input. A program pulse must be applied at each
address location to be programmed. Any location
can be programmed at any time - either individually ,
sequentially, or at random. T he program pulse has
a maximum width of 55ms. The M2732A must not
be programmed with a DC signal applied to the
E
input.
Programming of multiple M2732As in parallel with
the same data can be easily accomplished due to
the simplicity of the programming requirements.
Inputs of the paralleled M2732As may be connected together when they are programmed with
the same data. A low level TTL pulse applied to the
E input programs the paralleled 2732As.
Program Inhibit
Programming of multiple M2732As in parallel with
different data is also easily accomplished. Except
for
E, all like inputs (including GVPP) of the parallel
M2732As may be common. A T TL level program
pulse applied to a M2732A’s
E input with GV
PP
at
21V will program that M2732A. A high level
E input
inhibits the other M2732As from being programmed.
Program Verify
A verify should be performed on the programmed
bits to determine that they were correctly programmed. The verify is carried out with
GVPP and
E at VIL.
ERASURE OPERATION
The erasure characteristics of the M2732A are
such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight
and certain types of fluorescent lamps have wavelengths in the 3000-4000 Å range. Research shows
that constant exposure to room level fluorescent
lighting could erase a typical M2732A in approximately 3 years, while it would take approximately
1 week to cause erasure when exposed to the
direct sunlight. If the M2732A is to be exposed to
these types of lighting conditions for extended periods of time, it is suggested that opaque labels be
put over the M2732A window to prevent unintentional erasure.
The recommended erasure procedure for the
M2732A is exposure to shortwave ultraviolet light
which has a wavelength of 2537 Å. The integrated
dose (i.e. UV intensity x exposure time) for erasure
should be a minimum of 15 W-sec/cm
2
. The erasure time with this dosage is approximately 15 to
20 minutes using an ultraviolet lamp with 12000
µW/cm
2
power rating. The M2732A should be
placed within 2.5 cm of the lamp tubes during
erasure. Some lamps have a filter on their tubes
which should be removed before erasure.
Mode E GV
PP
V
CC
Q0 - Q7
Read V
IL
V
IL
V
CC
Data Out
Program VIL Pulse V
PP
V
CC
Data In
Verify V
IL
V
IL
V
CC
Data Out
Program Inhibit V
IH
V
PP
V
CC
Hi-Z
Standby V
IH
XVCCHi-Z
Note: X = VIH or VIL.
T ab le 3. Operating Modes
3/9
M2732A
AI00827
2.4V
0.45V
2.0V
0.8V
Figure 3. AC Test ing Input Outp ut W avefo rm s
Input Rise and Fall Times ≤ 20ns
Input Pulse Voltages 0.45V to 2.4V
Input and Output Timing Ref. Voltages 0.8V to 2.0V
AC MEASUREMENT CONDITIONS
AI00828
1.3V
OUT
CL = 100pF
CL includes JIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Figure 4. AC T esti ng Load Circui t
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Symbol Parameter Test Condition Min Max Unit
C
IN
Input Capacitance (except GVPP)V
IN
= 0V 6 pF
C
IN1
Input Capacitance (GVPP)V
IN
= 0V 20 pF
C
OUT
Output Capacitance V
OUT
= 0V 12 pF
Note: 1. Sampled only, not 100% tested.
T ab le 4. Capacitance
(1)
(TA = 25 °C, f = 1 MHz )
AI00782
tAXQX
tEHQZ
DATA OUT
A0-A11
E
G
Q0-Q7
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
Figure 5. Read Mode AC Wavefor m s
4/9
M2732A
Symbol Alt Parameter
Test
Condition
M2732A
Unit
-2, -20 blank, -25 -3 -4
Min Max Min Max Min Max Min Max
t
AVQV
t
ACC
Address Valid to
Output Valid
E = VIL,
G = V
IL
200 250 300 450 ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G = V
IL
200 250 300 450 ns
t
GLQV
t
OE
Output Enable Low
to Output Valid
E = V
IL
100 100 150 150 ns
t
EHQZ
(2)
t
DF
Chip Enable High to
Output Hi-Z
G = V
IL
0 60 0 60 0 130 0 130 ns
t
GHQZ
(2)
t
DF
Output Enable High
to Output Hi-Z
E = V
IL
0 60 0 60 0 130 0 130 ns
t
AXQX
t
OH
Address Transition to
Output Transition
E = VIL,
G = V
IL
0000ns
Notes: 1. VCC must be applied simultaneously with or befo re VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
Tab l e 6. Read Mode AC Characterist ics
(1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Parameter Test Condition
Value
Unit
Min Max
I
LI
Input Leakage Current 0 ≤ VIN ≤ V
CC
±10 µA
I
LO
Output Leakage Current V
OUT
= V
CC
±10 µA
I
CC
Supply Current E = VIL, G = V
IL
125 mA
I
CC1
Supply Current (Standby) E = VIH, G = V
IL
35 mA
V
IL
Input Low Voltage –0.1 0.8 V
V
IH
Input High Voltage 2 VCC + 1 V
V
OL
Output Low Voltage IOL = 2.1mA 0.45 V
V
OH
Output High Voltage IOH = –400µA 2.4 V
Note: 1. VCC must be applied simultaneously with or bef o re VPP and removed simultaneously or after VPP.
Tab l e 5. Read Mode DC Characteristics
(1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
5/9
M2732A
Symbol Parameter Test Condition Min Max Units
I
LI
Input Leakage Current VIL ≤ VIN ≤ V
IH
±10 µA
I
CC
Supply Current E = VIL, G = V
IL
125 mA
I
PP
Program Current E = VIL, G = V
PP
30 mA
V
IL
Input Low Voltage –0.1 0.8 V
V
IH
Input High Voltage 2 VCC + 1 V
V
OL
Output Low Voltage IOL = 2.1mA 0.45 V
V
OH
Output High Voltage IOH = –400µA 2.4 V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Tab le 7. Programmin g Mode DC Characteristics
(1)
(TA = 25 °C; VCC = 5V ± 5%; VPP = 21V ± 0.5V)
Symbol Alt Parameter Test Condition Min Max Units
t
AVEL
t
AS
Address Valid to Chip Enable
Low
2 µs
t
QVEL
t
DS
Input Valid to Chip Enable Low 2 µs
t
VPHEL
t
OES
VPP High to Chip Enable Low 2 µs
t
VPL1VPL2
t
PRT
VPP Rise Time 50 ns
t
ELEH
t
PW
Chip Enable Program Pulse
Width
45 55 ms
t
EHQX
t
DH
Chip Enable High to Input
Transition
2 µs
t
EHVPX
t
OEH
Chip Enable High to V
PP
Transition
2 µs
t
VPLEL
t
VR
VPP Low to Chip Enable Low 2 µs
t
ELQV
t
DV
Chip Enable Low to Output
Valid
E = VIL, G = V
IL
1 µs
t
EHQZ
t
DF
Chip Enable High to Output
Hi-Z
0 130 ns
t
EHAX
t
AH
Chip Enable High to Address
Transition
0ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
T ab le 8. Programming Mod e AC Charact eristics
(1)
(TA = 25 °C; VCC = 5V ± 5%; VPP = 21V ± 0.5V)
6/9
M2732A
AI00783
tVPLEL
PROGRAM
DATA IN
A0-A11
E
GV
PP
Q0-Q7
DATA OUT
tAVEL
tQVEL
tVPHEL
tEHQX
tEHVPX
tELEH
tELQV
tEHAX
tEHQZ
VERIFY
VALID
Figure 6. Programming and Verify Modes AC Waveform s
Speed and VCC Tolerance
-2 200 ns, 5V ±5%
blank 250 ns, 5V ±5%
-3 300 ns, 5V ±5%
-4 450 ns, 5V ±5%
-20 200 ns, 5V ±10%
-25 250 ns, 5V ±10%
Package
F FDIP24W
Temperature Range
1 0 to 70 °C
6 –40 to 85 °C
Example: M2732A -2 F 1
ORDERI NG INFO RM ATION SCHEME
For a list of available options (Speed, VCC T olerance, Package, etc ...) refer to the current Memory S hortform
catalogue.
For further information o n any aspect of this device, please contact SGS-THOMSO N Sales Office nearest
to you.
7/9
M2732A
FDIPW-a
A2
A1AL
B1 B e1
D
S
E1 E
N
1
Cα
eA
e3
∅
Symb
mm inches
Typ Min Max Typ Min Max
A 5.71 0.225
A1 0.50 1.78 0.020 0.070
A2 3.90 5.08 0.154 0.200
B 0.40 0.55 0.016 0.022
B1 1.17 1.42 0.046 0.056
C 0.22 0.31 0.009 0.012
D 32.30 1.272
E 15.40 15.80 0.606 0.622
E1 13.05 13.36 0.514 0.526
e1 2.54 – – 0.100 – –
e3 27.94 – – 1.100 – –
eA 16.17 18.32 0.637 0.721
L 3.18 4.10 0.125 0.161
S 1.52 2.49 0.060 0.098
∅ 7.11 – – 0.280 – –
α 4° 15° 4° 15°
N24 24
FDIP24W
Drawing is not to scale
FDIP24W - 24 pin Ceramic Frit-seal DIP, with window
8/9
M2732A
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificat ions mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
© 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocc o - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
9/9
M2732A
Loading...