Datasheet M27256-F6, M27256-F1, M27256-4F6, M27256-3F6, M27256-1F6 Datasheet (SGS Thomson Microelectronics)

FA ST ACCESS TIME: 170ns
EXTENDED TEMPERATURE RANGE
SINGLE 5V SUPPLY VOLTAGE
LOW STANDBY CURRE NT: 40mA max

M27256

NMOS 256K (32K x 8) UV EPROM

TTL COMPATIBLE DURING READ and
PROGRAM

FAST PROGRAMMING ALGORITHM
ELECTRONIC SIGNATURE
PROGRAMMING VOLTAGE: 12V

DESCRIPTION

The M27256 is a 262,144 bit UV erasable and
electrically programmable memory EPROM. It is
organized as 32.768 words by 8 bits.

The M27256 is housed in a 28 pin Window Ceramic
Frit-Seal Dual-in-Line pac kage. The transparent lid
allows the user to expose the chip t o ultraviolet light
to erase the bit patt ern. A new pattern can then be
written to the devic e by following t he programmi ng
procedure.

28

1

FDIP28W (F)

Figure 1. Logic Diag ra m

CC

V

PP

V

15

A0-A14 Q0-Q7

8

E

T able 1. Signal Names

A0 - A14 Address Inputs
Q0 - Q7 Data Outputs
E Chip Enable
G Output Enable
V

PP

V

CC

V

SS

March 1995 1/10

Program Supply
Supply Voltage
Ground

G

M27256

V

SS

AI00767B

M27256

Tab le 2. Absol ute Maxim u m Ratin gs

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

V

IO

V

CC

V

A9

V

PP

Note: Except for the rating "Operating T emperature R ange", stresses above those lis ted in the Table "Absolute Maximum Ratings" may cause
permanent damage to the device. These are stress ratings only and opera tion of the device at these or any other conditions above those
indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rati ng conditions for extended periods
may affect device reliabil ity. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.

Ambient Operating T empera ture grade 1

grade 6

Temperature Under Bias grade 1

grade 6
Storage Temperature –65 to 125 °C
Input or Output Voltages –0.6 to 6.25 V
Supply Voltage –0.6 to 6.25 V
VA9 Voltage –0.6 to 13.5 V
Program Supply –0.6 to 14 V

0 to 70

–40 to 85
–10 to 80

–50 to 95

°C

°C

Figure 2. DIP Pin Connections

V

A12

PP

A7
A6
A5
A4
A3
A2
A1
A0

Q0

Q2
SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14

M27256

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI00768

V

CC

A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5Q1
Q4
Q3V

DEVICE OPERATION

The eight modes of operations of the M27256 are
listed in the Operating Modes Table. A single 5V
power supply is required in the read mode. All
inputs are TTL lev els except for V

and 12V on A9

PP

for Electronic Signature.

Read Mode

The M27256 has two control functions, both of
which must be logically satisfied in order to obtain
data at the outputs. Chip Enable (

E) is the power
control and should be used for device selection.
Output Enable (

G) is the output control and should
be used to gate data to the output pins, inde­pendent of device selection. Assuming that the
addresses are s table, addres s ac ces s time (t
is equal to the delay from

E to output (t

ELQV

AVQV

). Data
is available at the outputs after the falling edge of
G, assuming that E has been low and the ad­dresses have been stable for at least t

AVQV-tGLQV

Stand by Mod e

The M27256 has a standby mode which reduces
the maximum active power current from 100mA to
40mA. The M27256 is placed in the standby mode
by applying a TTL high signal to the

E input. Whe n
in the standby mode, the outputs are in a high
impedance state, independent of the

G input.

Two Line Output Control

Because EPROM s are usually used in larger mem­ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:

a. the lowest possible memory power dissipation,
b. complete ass urance that output bus contention

will not occur .

)

.

2/10

M27256

DEVICE OPER ATION (cont’d)

For the most efficient us e of these two control lines,
E should be decoded and used as the primary
device selecting function, while

G should be made
a common connection to all devices in the array
and connected to the

READ line from the system

control bus.
This ensures that all deselected memory devices

are in their low power standby mode and that the
output pins are only active when data is requi red
from a particular memory device.

System Considerati ons

The power switching characteristics of fast
EPROMs require careful decoupling of the devices.
The supply current, I

, has three segments that

CC

are of interest to t he system designer : the s tandby
current level, the active c urrent level, and transient
current peaks that are produced by the falling and
rising edges of

E. The magnitude of the transient
current peaks is dependent on the capacitive and
inductive loading of the device at the output. The
associated transient voltage peaks can be sup­pressed by complying with the two line output
control and by properly selected decoupling ca­pacitors. It is recommended that a 1µF ceramic
capacitor be used on every device between V

CC

and VSS. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a

4.7µF bulk electrolytic capacitors should be used
between V

and VSS for every eight devices. The

CC

bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB trac es.

Programmain

When delivered, (and after each erasure for UV
EPROM), all bits of the M27256 ar e in the “1" state.
Data is introduced by selectively programming ”0s"
into the desired bit locations. Alth ough only “0s” will
be programmed, both “1s” and “0s” can be present
in the data word. The only way to change a “0" to
a ”1" is by ultraviolet light erasure. The M27256 is
in the programming mode when V

12.5V and

E is at TTL low. The data to be pro-

input is at

PP

grammed is applied 8 bits in parallel to the data
output pins. The levels required for the address and
data inputs are TTL.

Fast Programmi ng Al gor ithm

Fast Programming Algorithm rapidly programs
M27256 EPROMs using an efficient and reliable
method suited to the production programming en­vironment. Programming reliability is also ensured
as the incremental program margin of each byte is
continually monitored to determine when it has
been successfully programmed. A flowchart of the
M27256 Fast Programm ing A lgorithm is shown on
the Flowchart. The Fast Programming Algorithm
utilizes two different pulse types : initial and over­program. The duration of the initial

E pulse(s) is
1ms, which will then be followed by a longer over­program pulse of length 3ms by n (n is equal to the
number of the initial one millisecond pulses applied

Table 3. Operating Modes

Mode E GA9VPPQ0 - Q7

Read V
Output Disable V
Program V
Verify V
Optional Verify V
Program Inhibit V
Standby V
Electronic Signature V

Note: X = VIH or VIL, VID = 12V ± 0.5%.

IL

IL

Pulse V

IL

IH

IL

IH

IH

IL

V

IL

V

IH

IH

V

IL

V

IL

V

IH

XXVCCHi-Z

V

IL

XVCCData Out
XVCCHi-Z
XVPPData In
XVPPData Out
XVPPData Out
XVPPHi-Z

V

ID

V

CC

T ab le 4. Electron ic Sig natu r e

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code V
Device Code V

IL

IH

00100000 20h
00000100 04h

Codes

3/10

M27256

AC MEASUREMENT CONDITIONS

Input Rise and Fall Times ≤ 20ns

Figure 4. AC T esti ng Load Circui t

1.3V

Input Pulse Voltages 0.45V to 2.4V
Input and Output Timing Ref. Voltages 0.8V to 2.0V

1N914

Note that Output Hi-Z is defined as the point where data
is no longer driven.

Figure 3. AC Test ing Input Outp ut W avefo rm s

3.3kΩ

DEVICE
UNDER

2.4V

0.45V

T ab le 5. Capacitance

(1)

(TA = 25 °C, f = 1 MHz )

2.0V

0.8V

AI00827

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampled only, not 100% test ed.

Input Capacitance VIN = 0V 6 pF
Output Capacitance V

OUT

TEST

CL = 100pF

CL includes JIG capacitance

= 0V 12 pF

OUT

AI00828

Figure 5. Read Mode AC W aveforms

A0-A14

tAVQV

E

G

tELQV

Q0-Q7

4/10

tGLQV

VALID

tAXQX

tEHQZ

tGHQZ

Hi-Z

DATA OUT

AI00758

M27256

Tab le 6. Read Mode DC Characteristics

(1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

Symbol Parameter Test Condition Min Max Unit

I

I

I

CC1

I

I

LI
LO
CC

PP

Input Leakage Current 0 ≤ VIN ≤ V
Output Leakage Current V

OUT

= V

CC

CC

Supply Current E = VIL, G = V
Supply Current (Standby) E = V
Program Current VPP = V

IH

CC

IL

±10 µA
±10 µA

100 mA

40 mA

5mA
VILInput Low Voltage –0.1 0.8 V
V

V

OL

V

OH

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

T ab le 7A. Read Mode AC Characteristics

Input High Voltage 2 VCC + 1 V

IH

Output Low Voltage IOL = 2.1mA 0.45 V
Output High Voltage IOH = –400µA 2.4 V

(1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

M27256

Symbol Alt Parameter

t

AVQVtACC

t

ELQV

t

GLQV

(2)

t

EHQZ

(2)

t

GHQZ

t

AXQX

Address Valid to
Output Valid

Chip Enable Low

t

CE

to Output Valid
Output Enable

t

OE

Low to Output Valid
Chip Enable High

t

DF

to Output Hi-Z
Output Enable

t

DF

High to Output Hi-Z
Address Transition

t

OH

to Output Transition

Test

Condition

E = VIL,

G = V

IL

G = V

IL

E = V

IL

G = V

IL

E = V

IL

E = VIL,

G = V

IL

-1 -2, -20 blank, -25

Min Max Min Max Min Max

170 200 250 ns

170 200 250 ns

70 75 100 ns

035055060ns

035055060ns

000ns

Unit

Tab le 7B. Read Mode AC Ch ar acterist ics

(1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

Symbol Alt Parameter

Test

Condition

-3 -4

Min Max Min Max

t

AVQVtACC

t

ELQV

t

GLQV

(2)

t

EHQZ

(2)

t

GHQZ

t

AXQX

Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

Address Valid to
Output Valid

Chip Enable Low

t

CE

to Output Valid
Output Enable

t

OE

Low to Output Valid
Chip Enable High

t

DF

to Output Hi-Z
Output Enable

t

DF

High to Output Hi-Z
Address Transition

t

OH

to Output Transition

E = VIL,

G = V
G = V

IL

IL

300 450 ns

E = VIL, 120 150 ns

G = V

E = V

E = VIL,

G = V

IL

IL

IL

0 105 0 130 ns

0 105 0 130 ns

0 0 ns

M27256

300 450 ns

Unit

5/10

M27256

Tab le 8. Programmin g Mode DC Characteristics

(1)

(TA = 25 °C; VCC = 6V ± 0.25V; VPP = 12.5V ± 0.3V)

Symbol Parameter Test Condition Min Max Unit

I

LI

I

CC

I

PP

V

IL

V

IH

V

OL

V

OH

V

ID

Note. 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

T ab le 9. Programming Mod e AC Charact eristics

Input Leakage Current VIL ≤ VIN ≤ V

IH

±10 µA
Supply Current 100 mA
Program Current E = V

IL

50 mA
Input Low Voltage –0.1 0.8 V
Input High Voltage 2 VCC + 1 V
Output Low Voltage IOL = 2.1mA 0.45 V
Output High Voltage IOH = –400µA 2.4 V
A9 Voltage 11.5 12.5 V

(1)

(TA = 25 °C; VCC = 6V ± 0.25V; VPP = 12.5V ± 0.3V)

Symbol Alt Parameter Test Condition Min Max Unit

t

AVEL

t

Address Valid to Chip Enable

AS

Low

2 µs

t

QVEL

t

VPHEL

t

VCHEL

t

ELEH

t

ELEH

t

EHQX

t

QXGL

t

GLQV

t

GHQZ

t

GHAX

Notes. 1. VCC must be applied simultaneously with or bef o re VPP and removed simultaneously or after VPP.

2. The Initial Program Pulse width tolerance is 1 ms ± 5%.

3. The length of the Over-program Pulse varies from 2.85 ms to 78.95 ms, depending on the multiplication value of the iteration counter.

4. Sampled only , n ot 100% tested.

t

t

VPS

t

VCS

t

t

OPW

t

t

OES

t

(4)

t

DFP

t

Input Valid to Chip Enable Low 2 µs

DS

VPP High to Chip Enable Low 2 µs
VCC High to Chip Enable Low 2 µs
Chip Enable Program Pulse

PW

Width (Initial)
Chip Enable Program Pulse

Width (Overprogram)
Chip Enable High to Input

DH

Transition
Input Transition to Output

Enable Low
Output Enable Low to

OE

Output Valid
Output Enable Low to

Output Hi-Z
Output Enable High to

AH

Address Transition

Note 2 0.95 1.05 ms

Note 3 2.85 78.75 ms

2 µs

2 µs

0 130 ns

0ns

150 ns

6/10

Figure 6. Programming and Verify Modes AC W avefo rm s

M27256

A0-A14

tAVEL

Q0-Q7

V

PP

V

CC

E

G

DATA IN DATA OUT

tQVEL

tVPHEL

tVCHEL

tELEH

Figure 7. Programming Flowchart

VCC = 6V, VPP = 12.5V

n = 1

E = 1ms Pulse

NO

NO

VERIFY

YES

E = 3ms Pulse by n

Last

NO

Addr

YES

CHECK ALL BYTES

VCC = 5V, VPP = 5V

++ Addr

YES

++n

> 25

FAIL

VALID

tEHQX

tGLQV

tQXGL

PROGRAM VERIFY

DEVICE OPERATION (cont’d)
to a particular M27256 location), before a correct

verify occurs. Up to 25 one-millisecond pulses per
byte are provided for before the over program pulse
is applied. The entire sequence of program pulses
and byte verifications is performed at V
V

= 12.5V.

PP

When the Fast Programming cycle has been com­pleted, all bytes should be compared t o the original
data with V

CC

Program Inhibit

Programming of multiple M27256s in parallel with
different data is also easily accomplished. Except
for

E, all like inputs (including G) of the parallel
M27256 may be common. A TTL low pulse applied
to a M27256’s
program that M27256. A high level
the other M27256s from being programmed.

Program Veri fy

A verify should be performed on the programmed
bits to determine that they were correctly pro­grammed. The verify is accomplis hed with
G = VIL and VPP = 12.5V.

AI00774B

Optional Verify

The optional verify may be performed instead of the
verify mode. It is performed with
(as opposed to the standard verify which has E =

tGHQZ

tGHAX

AI00759

= 6V and

CC

= 5V and VPP = 5V.

E input, with VPP = 12.5V, will

E input inhibits

G = VIL, E = V

E = VIH,

IL

7/10

M27256

DEVICE OPER ATION (cont’d)

VIH), and VPP = 12.5V . The outputs will be in a Hi-z
state according to the signal presented to
fore, all devices with V

= 12.5V and G = VIL will

PP

present data on the bus independent of the

G. There-

E state.
When parallel programming several devices which
share the common bus, V

(6V) and the normal read mode used to exe-

V

CC

should be lowered to

PP

cute a program verify.

Electronic Signature

The Electronic Signature mode allows the reading
out of a binary code from an EPROM that will
identify its manufacturer and type. This mode is
intended for use by programming equipment for the
purpose of automatically matching the device to be
programmed with its corresponding programming
algorithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when
programming the M27256. To activate this mode,
the programming equipment must force 11.5V to

12.5V on address line A9 of the M27256. Two
identifier bytes may then be sequenced from the
device outputs by toggling address line A0 f rom V
to VIH. All other address lines must be held at V
during Electronic Signature mode. B yte 0 (A0 = VIL)
represents the manufacturer code and byte 1 (A0
= V

) the device identifier code. For the SGS-

IH

THOMSON M 27256, these two ident ifier byt es are
given below.

ERASURE OPER A TION (ap plies to UV EPRO M)

The erasure characteristic of the M27256 is such
that erasure begins when the cells are exposed to
light with wavelengths shorter than approximately
4000 Å. It should be noted that sunlight and some
type of fluorescent lamps have wavelengt hs in th e
3000-4000 Å range. Research shows that constant
exposure to room level fluorescent lighting could
erase a typical M27256 in about 3 years, while it
would take approximately 1 week to cause erasure
when exposed to direct sunlight. If the M27256 is
to be exposed to these types of lighting conditions
for extended periods of time, it is suggested that
opaque lables be put over the M27256 window to
prevent unintentional erasure. The recommended
erasure procedure for the M27256 is exposure to
short wave ultraviolet light which has wavelength
2537 Å. The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
of 15 W-s ec/cm
is approximately 15 to 20 minutes using an ultra-

IL

violet lamp with 12000 µW/cm

IL

M27256 should be placed within 2.5cm (1 inch) of

2

. The erasure time with this d osage

2

power rating. The

the lamp tubes during the erasure. Some lamps
have a filter on their tubes which should be re­moved before erasure.

ORDERI NG INFO RM ATION SCHEME

Example: M27256 -1 F 1

Speed and V

-1 170 ns, 5V ±5%

-2 200 ns, 5V ±5%

blank 250 ns, 5V ±5%

-3 300 ns, 5V ±5%

-4 400 ns, 5V ±5%

-20 200 ns, 5V ±10%

-25 250 ns, 5V ±10%

For a list of available options (Speed, V

Tolerance

CC

Package

F FDIP28W

T olerance, Package, etc) refer to the current Memory Shortform

CC

Temperature Range

1 0 to 70 °C
6 –40 to 85 °C

catalogue.
For further information o n any aspect of this device, please contact SGS-THOM SON Sales O ffice nearest

to you.

8/10

FDIP28W - 28 pin Ceramic Frit-seal DIP, with window

M27256

Symb

Typ Min Max Typ Min Max

A 5.71 0.225
A1 0.50 1.78 0.020 0.070
A2 3.90 5.08 0.154 0.200

B 0.40 0.55 0.016 0.022
B1 1.17 1.42 0.046 0.056

C 0.22 0.31 0.009 0.012

D 38.10 1.500

E 15.40 15.80 0.606 0.622
E1 13.05 13.36 0.514 0.526

e1 2.54 – – 0.100 – –
e3 33.02 – – 1.300 – –

eA 16.17 18.32 0.637 0.721

L 3.18 4.10 0.125 0.161

S 1.52 2.49 0.060 0.098

∅ 7.11 – – 0.280 – –

α 4° 15° 4° 15°

N28 28

FDIP28W

mm inches

Drawing is not to scale

B1 B e1

e3

D

S

N

∅

1

A2

A1AL

Cα

eA

E1 E

FDIPW-a

9/10

M27256

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificat ions mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.

© 1995 SGS-THOMSON Microelectronics - All Rights Reserved

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Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

10/10