512 Kbit, Low Voltage, Serial Flash Memory
FEATURES SUMMARY
■ 512 Kbit of Flash Memory
■ Page Program (up to 256 Bytes) in 1.5ms
(typical)
■ Sector Erase (256 Kbit) in 2 s (typical)
■ Bulk Erase (512 Kbit) in 3 s (typical)
■ 2.7 V to 3.6 V Single Supply Voltage
■ SPI Bus Compatible Serial Interface
■ 25 MHz Clock Rate (maximum)
■ Deep Power-down Mode 1 µA (typical)
■ Electronic Signature (05h)
■ More than 100,000 Erase/Program Cycles per
Sector
■ More than 20 Year Data Retention
M25P05-A
With 25 MHz SPI Bus Interface
Figure 1. Packages
8
1
SO8 (MN)
150 mil width
ENHANCED VERSION OF THE M25P05
This device is an enhanced version of the
M25P05. The enhanced features include: larger
page size, shorter programming time, higher clock
frequency, specific electronic signature.
VFQFPN8 (MP)
(MLP8)
1/34December 2002
M25P05-A
SUMMARY DESCRIPTION
The M25P05-A is a 512 Kbit (64K x 8) Serial Flash
Memory, with advanced write protection mechanisms, accessed by a high speed SPI -compatible
bus.
The memory can be programmed 1 to 256 bytes at
a time, using the Page Program instruction.
The memory is organized as 2 sec tors, each containing 128 pages . Each page is 25 6 bytes wide.
Thus, the whole memory can be viewed as consisting of 256 pages, or 65,536 bytes.
The whole memory can be eras ed using the B ulk
Erase instruction, or a sector at a time, us ing the
Sector Erase instruction.
Figure 2. Logi c D iagram
V
CC
Figure 3. SO Connect ions
M25P05-A
1
SV
2
3
W
4
SS
AI05758B
8
CC
7
HOLDQ
6
C
5
DV
D
C
S
W
HOLD
M25P05-A
V
SS
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S
W
Write Protect
HOLD
Hold
Chip Select
Q
AI05757
V
V
2/34
CC
SS
Supply Voltage
Ground
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S
). When this input signal is High,
the device is des elected and Serial Data Output
(Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in
progress, the device will b e in the Standby m ode
M25P05-A
(this is not the Deep Power-down mode). Driving
Chip Selec t ( S
in the active power mode.
After Power-up, a falling edge on Chip Select (S
is required prior to the start of any instruction.
Hold (HOLD
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedanc e, and Serial D ata Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, wit h C hip S e lec t (S
Write Protect (W
put signal is to freeze the size of the area of memory that is protected against program or erase
instructions (as specified by the values in the BP1
and BP0 bits of the Status Register).
) Low enables the device, placing it
). The Hold (HOLD) signal is used to
) driven Low.
). The main purpose of this in-
)
3/34
M25P05-A
SPI MODES
These devices can be drive n by a microcont roller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input dat a is latched in on
the rising edge of Serial Clock (C), and output data
Figure 4. Bus Master and Memory Devices on the SPI Bus
is avai lable from the falling edge of Serial Cloc k
(C).
The difference between the two modes, as shown
in Figure 5, is the clock polarity when the bus master is in Stand-by mode and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
Bus Master
(ST6, ST7, ST9,
ST10, Others)
CS3 CS2 CS1
Note: 1. The Write Protect (W) a nd Hold (HOLD) signals should be driven, High or Low as appropriate.
SDO
SDI
SCK
CQD
SPI Memory
Device
S
CQD
SPI Memory
Device
HOLD
W
S
HOLD
W
Figure 5. SPI Modes Sup po r te d
CQD
SPI Memory
Device
S
W
AI03746D
HOLD
4/34
CPOL
0
1
CPHA
0
1
C
C
D
Q
MSB
MSB
AI01438B
OPERATING FEATURES
Page Prog ram m i ng
To program one data byte, two instructions are required: Write Enable (WREN), which is one by te,
and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the
internal Program cycle (of duration t
PP
).
To spread this overhead, the Page P rogram (PP)
instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the
same page of memory.
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to
be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been e rased to a ll
1s (FFh). This can be achieved either a sector at a
time, using the Sector Erase (SE) instruction, or
throughout the entire memory, using the Bulk
Erase (BE) instruction. This starts an internal
Erase cycle (of duration t
or tBE).
SE
The Erase instruction must be preceeded by a
Write Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status
Register (WRSR), Program (PP) or Erase (SE or
BE) can be achieved by n ot waiting for the worst
case delay (t
, tPP, tSE, or tBE). The Write In
W
Progress (WIP) bit is provided in the Status Register so that the application program can monitor its
value, polling it to establish when the previous
Write cycle, Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and De ep
Power-Down Modes
When Chip Select (S) is Low, the device is enabled, and in the Active Power mode.
When Chip Select (S
) is High, the device is dis-
abled, but could remain in the Active Power mode
M25P05-A
until all internal cycles have completed (Pro gram,
Erase, Write Status Register). The device then
goes in to the Stand-by P ower mode. T he device
consumption drops to I
The Deep Power-down mode is entered when the
specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device
consumption drops further to I
mains in this mode until another specific instruction (the Release from Deep Power-down Mode
and Read Electronic S ignature (RES ) instruction)
is executed.
All other instructions are ignored while the device
is in the Deep Power-down mode. This can be
used as an extra software protection mecha nism,
when the device is not in active use, to protect the
device from inadvertant Write, Program or Erase
instructions.
Status Register
The Status Register contains a num ber of status
and control bits, as shown in Table 5, that can be
read or set (as appropriate) by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write Sta tus
Register, Program or Erase cycle.
WEL bit. Th e Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Program and Erase
instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W
) signal. The Status Register
Write Disable (SRWD) bit an d Write Protect (W
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become
read-only bits.
CC1
.
. The device re-
CC2
)
5/34
M25P05-A
Protection Modes
The environments where non-volatile memory devices are used can be v ery noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat t his, t he M 25P 05-A b oas ts
the following data protection mechanisms:
■ Power-On Reset and an internal timer (t
can provide protection against inadvertant
changes while the power supply is outside the
operating specification.
■ Program, Erase and Write Status Register
instructions are checked that they consist of a
number of clock pulses that is a multiple of
eight, before they are accepted for execution.
■ All instructions that modify data must be
preceded by a Write Enable (WREN) instruction
to set the Write Enable Latch (WEL) bit . This bit
is returned to its reset state by the following
events:
– Power-up
– Write Disable (WRDI) instruction completion
PUW
)
– Write Status Register (WRSR) instruction
completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
■ The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only. This
is the Software Protected Mode (SPM).
■ The Write Protect (W) signal, in co-operation
with the Status Register Write Disabl e (SRWD)
bit, allows the Block Protect (BP1, BP0) bits and
Status Register Write Disable (SRWD) bit to be
write-protected. This is the Hardware Protected
Mode (HPM).
■ In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions, as all
instructions are ignored except one particular
instruction (the Release from Deep Powerdown instruction).
Table 2. Protected Area Sizes
Status Register
Content
BP1 Bit BP0 Bit Protected Area Unprotected Area
0 0 none All sectors (Sectors 0 and 1)
0 1
1 0
1 1 All sectors (Sectors 0 and 1) none
Note: 1. The device is ready to accept a Bulk Erase instru ct i on if, and only i f, bo th Block Protec t (BP1, BP0) are 0.
No protection against Page Program (PP) and Sector Erase (SE)
All sectors (Sectors 0 and 1) protected against Bulk Erase (BE)
Memory Content
6/34
Hold Condition
The Hold (HOLD
) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this
signal Low does not terminate any Write Status
Register, Program or Erase cycle that is currently
in progress.
To enter the Hold condition, the device must be
selecte d, w it h C h ip Select ( S
) Low.
The Hold condition starts on the falling edge of the
Hold (HOLD
) signal, provided that this coincides
with Serial Clock (C) being Low (as shown in Figure 6).
The Hold condition ends on the rising edge of the
Hold (HOLD
) signal, provided that this coincides
with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial
Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the
Figure 6. Hold Condition Activation
M25P05-A
rising edge does not coincide with Serial Clock (C)
being Low, the Hold condition ends after Serial
Clock (C) next goes Low. (This is shown in Figure
6).
During the Hold condition, the Serial Data Output
(Q) is high impedanc e, and Serial D ata Input (D)
and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip
Select (S
Hold condition. This is to en sure that the state of
the internal logic remains unchanged from the moment of entering the Hold condition.
If Chip Select (S
the Hold condition, this has the effect of reset ting
the internal logic of the device. To restart communication with the device, it is necessary to drive
Hold (HOLD
(S
to the Hold condition.
) driven Low, for the whole duration of the
) goes High while the d ev ice is in
) High, and then to drive Chip Select
) Low. This prevents the device from going back
HOLD
C
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
AI02029D
7/34
M25P05-A
MEMORY OR GANIZATION
The memory is organized as:
■ 65,536 bytes (8 bits each)
■ 2 sectors (256 Kbits, 32768 bytes each)
■ 256 pages (256 bytes each).
Each page can be individually programmed (bits
are programmed from 1 to 0). The device is Sector
Figure 7. Block D ia gram
or Bulk Erasable (bits are erased from 0 to 1) but
not Page Erasable.
Table 3. Memory Organization
Sector Address Range
1 08000h 0FFFFh
0 00000h 07FFFh
HOLD
W
S
C
D
Q
Control Logic
Address Register
and Counter
08000h
Y Decoder
High Voltage
Generator
I/O Shift Register
256 Byte
Data Buffer
Status
Register
0FFFFh
Size of the
read-only
memory area
8/34
00000h
000FFh
256 Bytes (Page Size)
X Decoder
AI05759
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) a fter Chip Select (S
) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence starts with a one-byte
instruction code. Depending on the instruction,
this might be followed by address bytes, or by data
bytes, or by both or none. Chip Select (S
) must be
driven High after the last bit of the instruction sequence has been shifted in.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Status Register (RDSR) or Release from Deep
Power-down, and Read Electronic Signature
(RES) instruction, the shifted-in instruction sequence is followed by a data-out sequ ence. Chip
Selec t (S
) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase
(SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN), Write Disable
(WRDI) or Deep Power-down (DP) instruction,
Chip Sele ct (S
byte boundary, otherwise the inst ruction is rejected, and is not executed. That is, Chip Select (S
must driven High when the number of clock pulses
after Chip Select (S
multiple of eight.
All attempts to access the memory array during a
Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Register cycle, Program cycle or Erase cycle continues unaffected.
Table 4. Instruction Set
Instruction Description One-byte Instruction Code
M25P05-A
) must be driven High exactly at a
) being driven Low is an exact
Address
Bytes
Dummy
Bytes
Data
Bytes
)
WREN Write Enable 0000 0110 0 0 0
WRDI Write Disable 0000 0100 0 0 0
RDSR Read Status Register 0000 0101 0 0 1 to
WRSR Write Status Register 0000 0001 0 0 1
READ Read Data Bytes 0000 0011 3 0 1 to
FAST_READ Read Data Bytes at Higher Speed 0000 1011 3 1 1 to
PP Page Program 0000 0010 3 0 1 to 256
SE Sector Erase 1101 1000 3 0 0
BE Bulk Erase 1100 0111 0 0 0
DP Deep Power-down 1011 1001 0 0 0
RES
Release from Deep Power-down,
and Read Electronic Signature
Release from Deep Power-down 0 0 0
1010 1011
0 3 1 to
∞
∞
∞
∞
9/34
M25P05-A
Figure 8. Write Enable (WREN) Instruction Sequenc e
S
21 34567
0
C
Instruction
D
High Impedance
Q
(SE), Bulk Erase (BE) and Write Status Register
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8)
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase
(WRSR) instruction.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S
struction code, and then driving Chip Select (S
High.
AI02281E
) Low, sending the in-
)
Figure 9. Write Disable (WRDI) Instruction Sequence
S
21 34567
0
C
Instruction
D
High Impedance
Q
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Ch ip Select (S
tion code, and then driving Chip Select (S
) Low, sending the instruc-
) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions:
AI03750D
– Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction com-
pletion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
10/34
Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
S
21 3456789101112131415
0
C
Instruction
D
M25P05-A
Q
High Impedance
Status Register Out
7 6543210
MSB
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write Status Register cycle is in
progress. When one of these cycl es i s in progress,
it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the
device. It is also possible to read the Status Register continuously, as shown in Figure 10.
Table 5. Status Register Format
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
The status and cont rol bits of t he Stat us Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1,
such a cycle is in progress, when reset to 0 no
such cycle is in progres s.
Status Register Out
7 6543210
MSB
7
AI02031E
WEL bit. Th e Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 t he i nte rnal W rite E nabl e Latch
is reset and no Write S tatus Reg ister, Pr ogram or
Erase instruction is accepted.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Program and Erase
instructions. These bits are written with the Write
Status Register (WRSR) instruction. When one or
both of the Block Protec t (B P 1, B P0 ) bits i s s et t o
1, the relevant memory area (as defined in Table
2) becomes protected against Page Program (PP)
and Sector Erase (SE) instructions. The Block
Protect (BP1, BP0) bits can be written provided
that the Hardware Protect ed mode has not been
set. The Bulk Erase (BE) instruction is executed if,
and only if, both Block Protect (BP1, BP0) bits are
0.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W
) signal. The Status Register
Write Disable (SRWD) bit an d Write Protect (W
signal allow the device to be put in the Hardware
Protected mode (when t he Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W
) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register
(WRSR) instruction is no longer accepted for execution.
)
11/34
M25P05-A
Figure 11. Write Status Register (WRSR) Instruction Sequence
S
21 3456789101112131415
0
C
Instruction Status
D
High Impedance
Q
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded and ex ecuted, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S
) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in Figure 11.
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are always read as 0.
Chip Select (S
) must be driven High after the
eighth bit of the d ata byte has been latched in. If
not, the Write Status Register (WRSR) i nstruction
is not executed. As soon as Chip Select (S
) is driv-
en High, the self-timed Wri te S tatus Regi ster cycl e
Register In
765432 0
MSB
1
AI02282D
(whose duration is tW) is initiated . While the Writ e
Status Register cycle is in progress, the Status
Register may still be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 wh en it is completed. At
some unspecifi ed time befo re the cycle i s completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that is to be trea ted as read-only, as defined
in Table 2. The Write Status Register (WRSR) instruction also allows the user to set or reset the
Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W
) signal. The
Status Register Write Disable (SRWD) bit and
Write Protect (W
) signal allow the device to be put
in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not executed once the Hardware P rotected Mode (HPM) is
entered.
12/34
Table 6. Protection Modes
SRWD
W
Signal
Bit
Mode
Write Protection of the
Status Register
Memory Content
Protected Area
M25P05-A
1
Unprotected Area
1
10
00
11
01
Note: 1. As def i ned by the va lu es in the Block Pr otect (BP1, B P 0) bits of the Status Regist er, as shown i n T able 2.
Software
Protected
(SPM)
Hardware
Protected
(HPM)
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
The values in the SRWD,
BP1 and BP0 bits can be
changed
Status Register is
Hardware write protected
The values in the SRWD
BP1 and BP0 bits cannot
be changed
Protected against Page
Program, Sector Erase
and Bulk Erase
Protected against Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page
Program and Sector
Erase instructions
Ready to accept Page
Program and Sector
Erase instructions
(Attempts to write to the Status Register are reThe protection features of t he de vic e are su mmarized in Table 6.
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) instruction, regardless of th e whether W rite Prote ct
) is driven High or Low.
(W
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered, depending on the st ate of
Write Protect (W
– If Write Protect (W
):
) is driven High, it is possible
to write to the Status Register provided that the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction.
– If Write Protect (W
) is driven Low, it is
sible to write to the Status Register
not
even
pos-
if the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction.
jected, and are not accepted for ex ecution). As
a consequence, all the data bytes in the memory area that are software protected (SPM) by the
Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
– by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W
– or by driving Write Protect (W
the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull W rite Protect (W
High.
If Write Protect (W
) is permanently tied High, t he
Hardware Protected Mode (HPM) can never be
activated, and only t he Software Protec ted Mode
(SPM), using the Block Protect (B P1, BP0) bi ts of
the Status Register, can be used.
) Low
) Low after setting
)
13/34
M25P05-A
Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S
21 345678910 2829303132333435
0
C
Instruction 24-Bit Address
23
D
High Impedance
Q
Note: 1. Address bits A23 to A16 must be set to 00h.
2221 3210
MSB
Read Data Bytes (READ)
The device is f irst s el ected by driving Chip S ele ct
) Low. The instruction code for the Read Data
(S
Bytes (READ) instruction is followed by a 3-byte
address (A23-A0), each bit being latched-in during
the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted o ut, at
a maximum frequency f
, during the falling edge of
R
Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first byte addressed can be at any location.
The address is automatically incremented to the
36 37 38
Data Out 1
76543 1 7
MSB
next higher address after each byte of data is shifted out. The whole memory can, therefore, be read
with a single Read Data Bytes (REA D) i nstruction.
There is no address roll-over; when the highest
address (0FFFFh) is reached, the instruction
should be terminated.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S
(S
) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
the cycle that is in progr es s.
39
2
0
) High. Chip Select
Data Out 2
AI03748D
14/34
M25P05-A
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out
Sequence
S
21 345678910 28293031
0
C
Instruction 24 BIT ADDRESS
23
D
High Impedance
Q
S
2221 3210
32 33 34 36 37 38 39 40 41 42 43 44 45 46
C
D
Q
Note: 1. Address bits A23 to A16 must be set to 00h.
765432 0
35
Dummy Byte
1
765432 0
MSB
Read Data Bytes at Higher Speed
(FAST_READ)
The device is f irst s el ected by driving Chip S ele ct
) Low. The instruction code for the Read Data
(S
Bytes at Higher Speed (FAST_READ) instruction
is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latc hed-in during the
rising edge of Serial Clock (C). Then the memory
contents, at that address, is shifted out on Serial
Data Output (Q), each bit being s hifted out, at a
maximum frequency f
, during the falling edge of
C
Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location.
The address is automatically incremented to the
47
DATA OUT 1
1
DATA OUT 2
7 6543210
MSB MSB
7
next higher address after each byte of data is shifted out. The whole memory can, therefore, be read
with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction.
There is no address roll-over; when the highest
address (0FFFFh) is reached, the instruction
should be terminated.
The Read Data Bytes at Higher Speed
(FAST_READ) instruction is terminated by driving
Chip Select (S
) High. Chip Select (S) can be driven High at any time during data output. Any Read
Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle
is in progress, is rejected without having any effects on the cycle that is in progress.
AI04006
15/34
M25P05-A
Figure 14. Page Program (PP) Instruction Sequence
S
21 345678910 2829303132333435
0
C
36 37 38
39
Instruction 24-Bit Address
23
D
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
Data Byte 2
D
Note: 1. Address bits A23 to A16 must be set to 00h.
765432 0
MSB MSB MSB
1
2221 3210
MSB
765432 0
Page Program (PP)
The Page Program (PP) instruction allows bytes to
be programmed in the memory (changing bits from
1 to 0). Before it can be accept ed, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (S
) Low, followed by the instruction code, three address by tes and at least
one data byte on Serial Data Input (D). If the 8
least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end
of the current page are programmed from the start
address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero).
Chip Selec t (S
) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 14.
If more than 256 bytes are sent to the device, pre-
viously latched data are discarded and the last 256
Data Byte 1
765432 0
MSB
2074
2073
51
Data Byte 3 Data Byte 256
1
2072
765432 0
2075
2076
1
2077
1
2079
2078
AI04082B
data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data
bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same
page.
Chip Select (S
) must be driven High after the
eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed.
As soon as Chip Select (S
) is driv en H i g h, t h e s e lf timed Page Program cycle (whose duration i s t
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the selftimed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset .
A Page Program (PP) instruction applied to a page
which is protected by the Block Protect (BP1, BP0)
bits (see Tables 3 and 2) is not executed.
PP
)
16/34
Figure 15. Sector Erase (SE) Instruction Sequence
S
21 3456789 293031
0
C
M25P05-A
Instruction
D
Note: 1. Address bits A23 to A16 must be set to 00h.
Sector Erase (SE)
The Sector Erase (SE) instruction sets t o 1 (FFh)
all bits inside the chosen sector. Before it ca n be
accepted, a Write Enable (WREN) instruction
must previously have been executed. After the
Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by
driving Chip Select (S
) Low, followed by the instruction code, and three address by tes on Serial
Data Input (D). Any address inside the Sector (see
Table 3) is a valid address for the Sector Erase
(SE) instruction. Chip Select (S
) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
24 Bit Address
23 22 2 0
MSB
Chip Select (S
1
AI03751D
) must be driven High after the
eighth bit of the last address byte has been latched
in, otherwise the S ector Erase (SE) i nstruction is
not executed. As soon as Chip Select (S
High, the self -timed Sector E rase cycle (who se duration is t
) is initiated. While the Sector Erase cy-
SE
cle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the
self-timed Sector Erase cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset .
A Sector Erase (S E) in struction applie d t o a page
which is protected by the Block Protect (BP1, BP0)
bits (see Tables 3 and 2) is not executed.
) is driven
17/34
M25P05-A
Figure 16. Bulk Erase (BE) Instruction Sequence
S
21 345670
C
D
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1
(FFh). Before it can be ac cepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S
code on Serial Data Input (D). Chip Select (S
must be driven Low for the entire duration of the
sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S
eighth bit of the instruction code has been latched
) Low, followed by the instruction
)
) must be driven High after the
Instruction
AI03752D
in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S
) is driven High,
the self-ti med Bu lk Erase cycle (whose durat ion i s
t
) is initiate d. While the Bulk Erase cycle is in
BE
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the selftimed Bulk Erase cycle, a nd is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is
reset.
The Bulk Erase (BE) instruction is executed only if
both Block Protect (BP1, BP0) bits are 0. The Bulk
Erase (BE) instruction is ignored if one, or more,
sectors are protected.
18/34
Figure 17. Deep Power-down (DP) Instruction Sequence
S
21 345670
C
Instruction
D
t
DP
M25P05-A
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction
is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It
can also be used as an extra s oftware protection
mechanism, while the device is not in active use,
since in this mod e, the device ign ores all Write,
Program and Erase instructions.
Driving Chip Select (S
) High deselects the device,
and puts the device in the S tandby m ode (if there
is no internal cycle currently in progress). But this
mode is not the Deep Power-down mode. The
Deep Power-down mode can only b e entered by
executing the Deep Power-down (DP ) instruction,
to reduce the standby current (from I
CC1
to I
CC2
as specified in Table 12).
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down and Read Electronic Signature (RES) instruction. This releases
the device from this mode. The Release from
Deep Power-down and Read Electronic Signature
(RES) instruction also allows the Electronic S igna-
Stand-by Mode
Deep Power-down Mode
ture of the device to be output on Serial Data Output (Q).
The Deep Power-down mode au tomatically stops
at Power-down, and the device always Powers-up
in the Standby mode.
The Deep Power-down (DP) instruction is entered
by driving Chip Select (S
) Low, followed by the in-
struction code on Serial Data Input (D). Chip Se-
) must be driven Low for the entire duration
lect (S
of the sequence.
The instruction sequence is shown in Figure 17.
Chip Select (S
) must be driven High after the
eighth bit of the instruction code has been latched
in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (S
,
driven High, it requires a delay of t
supply current is reduced to I
DP
and the Deep
CC2
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is rejected without havin g any effects on the cycle that
is in progress.
AI03753D
) is
before the
19/34
M25P05-A
Figure 18. Release from Deep Power-d ow n and Read Electronic Sign atur e (RES) Instruction
Sequence a n d D at a- Out Sequ ence
S
21 345678910 2829303132333435
0
C
36 37 38
Instruction 3 Dummy Bytes
23
D
High Impedance
Q
2221 3210
MSB
Release from Deep Power-down and Read
Electronic Signature (RES)
Once the device has entered the Deep Powerdown mode, all instructions are ignored except the
Release from Deep Power-down and Read Electronic Signature (RES) instruction. Executing this
instruction takes the device out of the Deep Power-down mode. The instruction can also be used to
read, on Serial Data Output (Q), the 8-bit Electronic Signature of the device.
Except while an Erase, P rogram or Write Status
Register cycle is in progress, the Release from
Deep Power-down and Read Electronic Signature
(RES) instruction always provides access to the
Electronic Signature of the device, and can be applied even if the Deep Power-down mode has not
been entered.
Any Release from Deep Power-down and Read
Electronic Signature (RES) instruction while an
Erase, Program or Write Status Register cycle is in
progress, is not decoded, and has no effect on the
cycle that is in progress.
This instruction serves a second purpose. The device features an 8-bit Electronic Signature, whose
value for the M25P05-A is 05h. This can be read
using the Release from Deep Power-down and
Read Electronic Signature (RES) instruction.
t
RES2
Electronic Signature Out
765432 0
MSB
Deep Power-down Mode
1
Stand-by Mode
AI04047C
The device is f irst s el ected by driving Chip S el ect
) Low. The instruction code is followed by 3
(S
dummy bytes, each bit being latched-in on Serial
Data Input (D) during the rising edge of Serial
Clock (C). Then, the 8-bit Electronic Signature,
stored in the memory, is shifted out on Serial Data
Output (Q), each bit being shifted out during the
falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 18.
The Release from Deep Power-down and Read
Electronic Signature (RES) instruction is terminated by driving Chip Select (S
) High after the Electronic Signature has been read at least once.
Sending additional clock cycles on Serial Clock
(C), while Chip Select (S
) is driven Low, cause the
Electronic Signature to be output repeatedly.
When Chip Select (S
) is driv en High, the device is
put in the Stand-by Power mode. If the device was
not previously in the Deep Power-down mode, the
transition to the Stand-by Power mode is imm ediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by t
) must remain High for at least t
lect (S
, and Chip Se-
RES2
RES2
(max),
as specified in Table 13. Once in the Stand-by
Power mode, the device waits to be selected, so
that it can receive, decode and execute instructions .
20/34
Figure 19. Release from Deep Power-d ow n (RES) Instruction Seq uen ce
S
t
21 345670
C
Instruction
D
High Impedance
Q
RES1
M25P05-A
Driving Chip Select (S
) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has
been transmitted for the first time (as shown in Figure 19), still insures that the device is put into
Stand-by Power mode. If the d evice was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If
Deep Power-down Mode
Stand-by Mode
AI04078B
the device was previously in the Deep Powerdown mode, though, the transition to the Stand-by
Power mode is delayed by t
) must remain High for at least t
(S
, and Chip Selec t
RES1
RES1
(max), as
specified in Table 13. Once in the Stand-by Power
mode, the device waits to be selected, so that it
can receive, decode and execute instructions.
21/34
M25P05-A
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S
the voltage applied on V
) until VCC reaches the
CC
correct value:
(min) at Power-up, and then for a further de-
–V
CC
lay of t
VSL
–VSS at Power-down
Usually a simple pull-up resistor on Chip Select (S
can be used to insure safe and proper Power-up
and Power-down.
To avoid data corruption and inadvertent write
operations during power up, a Power On Reset
(POR) circuit is included. The logic inside the
device is held reset while V
threshold value, V
– all operations are disabled,
WI
is less than the POR
CC
and the device does not respond to any
instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Program (PP), Sector Erase (SE),
Bulk Erase (BE) and Write Status Register
(WRSR) instructions until a time delay of t
elapsed after the moment that V
V
threshold. However, the correct operation of
WI
the device is not guaranteed if, by this time, V
still below V
(min). No Write Status Register,
CC
Program or Erase instructions should be sent until
the later of:
) must follow
rises above the
CC
PUW
has
CC
is
–t
–t
after VCC passed the VWI threshold
PUW
afterVCC passed the VCC(min) level
VSL
These values are specified in Table 7.
If the delay, t
above V
CC
READ instructions even if the t
, has elapsed, after VCC has risen
VSL
(min), the device can be selected for
delay is not yet
PUW
fully elapsed.
)
At Power-up, the device is in the following state:
– The device is in the Standby mode (not the
Deep Power-down mode).
– The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail
decoupling, to stablise the V
in a system should have the V
feed. Each device
CC
rail decoupled by
CC
a suitable capacitor close to the package pins.
(Generally, this capacitor is of the order of 0.1µF).
At Power-down, when V
drops from the
CC
operating voltage, to below the POR threshold
value, V
, all operations are disabled and the
WI
device does not respon d to any instruction. (The
designer needs to be aware that if a Power-down
occurs while a Write, Program or Erase cycle is in
progress, some data corruption can result.)
Figure 20. Power-up Timing
V
CC
VCC(max)
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
VCC(min)
Reset State
of the
Device
V
WI
tVSL
tPUW
Read Access allowed Device fully
accessible
time
AI04009C
22/34
M25P05-A
Table 7. Power-Up Timing and VWI Threshol d
Symbol Parameter Min. Max. Unit
1
t
VSL
t
PUW
V
Note: 1. These param eters are characteri zed only .
VCC(min) to S low
1
Time delay to Write instruction 1 10 ms
1
Write Inhibit Voltage 1 2 V
WI
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains
FFh). The Status Register contains 00h (all Status
Register bits are 0).
10 µs
23/34
M25P05-A
MAXIMUM RATI N G
Stressing the device above the rating l isted in the
Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress
ratings only and operation of the device at t hese or
any other conditions ab ove those i ndicated in t he
Operating sections of this specificat ion is not im-
Table 8. Absolute Maximum Ratings
Symbol P arameter Min. Max. Unit
T
STG
T
LEAD
V
IO
V
CC
V
ESD
Note: 1. IPC/JEDEC J-STD- 020 A
2. JEDEC Std JESD 22-A114A (C1=100 pF, R1=1500
Storage Temperature –65 150 °C
Lead Temperature during Soldering
(20 seconds max.)
1
Input and Output Voltage (with respect to Ground) –0.6 4.0 V
Supply Voltage –0.6 4.0 V
Electrostatic Discharge Voltage (Human Body model)
Ω, R2=500 Ω)
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents .
SO 235 °C
VFQFPN 235 °C
2
–2000 2000 V
24/34
DC AND AC PARAMETERS
This section summarizes the operat ing and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC Characteristic tables that follow are derived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit matc h the measurem ent
conditions when relying on the quoted parameters.
Table 9. Operating Conditions
Symbol Parameter Min. Max. Unit
M25P05-A
V
CC
T
A
Supply Voltage 2.7 3.6 V
Ambient Operating Temperature –40 85 °C
Table 10. AC Measurement Conditions
Symbol Parameter Min. Max. Unit
C
L
Load Capacitance 30 pF
Input Rise and Fall Times 5 ns
to 0.8V
Input Pulse Voltages
Input and Output Timing Reference Voltages
Note: 1. Output Hi-Z is de fined as the point where da ta out is no longer driven .
0.2V
0.3V
CC
to 0.7V
CC
CC
CC
Figure 21. AC Measurement I/O Waveform
Input Levels
0.8V
CC
0.2V
CC
Input and Output
Timing Reference Levels
0.7V
CC
0.3V
CC
AI00825B
V
V
Table 11. Capacitance
Symbol Parameter Test Condition Min. Max. Unit
C
OUT
C
IN
Note: Sampled only, not 10 0% tested, at TA=25°C an d a frequency of 20 MHz.
Output Capacitance (Q) V
Input Capacitance (other pins) VIN = 0V 6 pF
= 0V 8 pF
OUT
25/34
M25P05-A
Table 12. DC Characteristics
Symbol Parameter
Input Leakage Current ± 2 µA
I
LI
I
I
I
I
Output Leakage Current ± 2 µA
LO
Standby Current
CC1
Deep Power-down Current S = VCC, VIN= VSS or V
CC2
Operating Current (READ)
CC3
Test Condition
(in addition to those in Table 9)
S
= VCC, VIN= VSS or V
C = 0.1V
/ 0.9.VCC at 25 MHz,
CC
CC
CC
Q = open
Min. Max. Unit
50 µA
5µA
4mA
I
CC4
I
CC5
I
CC6
I
CC7
V
IL
V
IH
V
OL
V
OH
Operating Current (PP) S = V
Operating Current (WRSR) S = V
Operating Current (SE) S = V
Operating Current (BE)
S
= V
CC
CC
CC
CC
Input Low Voltage – 0.5
Input High Voltage
0.7V
CCVCC
Output Low Voltage IOL = 1.6 mA 0.4 V
I
Output High Voltage
= –100µAV
OH
CC
–0.2
15 mA
15 mA
15 mA
15 mA
0.3V
CC
+0.4
Table 13. AC Characteristics
Test conditions specified in Table 9 and Table 10
Symbol Alt. Parameter Min. Typ. Max. Unit
f
f
t
CH
t
CL
t
CLCH
t
CHCL
t
SLCH
t
CHSL
t
DVCH
t
CHDX
t
CHSH
t
SHCH
t
SHSL
t
SHQZ
t
CLQV
t
CLH
t
CLL
t
CSS
t
DSU
t
t
CSH
t
DIS
f
C
DH
t
V
C
R
1
1
2
2
2
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES,
D.C. 25 MHz
WREN, WRDI, RDSR, WRSR
Clock Frequency for READ instructions D.C. 20 MHz
Clock High Time 18 ns
Clock Low Time 18 ns
Clock Rise Time3 (peak to peak)
Clock Fall Time3 (peak to peak)
0.1 V/ns
0.1 V/ns
S Active Setup Time (relative to C) 10 ns
S Not Active Hold Time (relative to C) 10 ns
Data In Setup Time 5 ns
Data In Hold Time 5 ns
S Active Hold Time (relative to C) 10 ns
S Not Active Setup Time (relative to C) 10 ns
S Deselect Time 100 ns
Output Disable Time 15 ns
Clock Low to Output Valid 15 ns
V
V
V
26/34
M25P05-A
Test conditions specified in Table 9 and Table 10
Symbol Alt. Parameter Min. Typ. Max. Unit
t
CLQX
t
HLCH
t
CHHH
t
HHCH
t
CHHL
2
t
HHQX
2
t
HLQZ
4
t
WHSL
4
t
SHWL
2
t
DP
2
t
RES1
2
t
RES2
t
W
t
PP
t
SE
t
BE
Note: 1. tCH + tCL must be greater than or equal to 1/ f
2. Value guarant eed by characteriza tion, not 100% tested in production .
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when S RWD is set at 1.
t
HO
Output Hold Time 0 ns
HOLD Setup Time (relative to C) 10 ns
HOLD Hold Time (relative to C) 10 ns
HOLD Setup Time (relative to C) 10 ns
HOLD Hold Time (relative to C) 10 ns
t
LZ
t
HZ
HOLD to Output Low-Z 15 ns
HOLD to Output High-Z 20 ns
Write Protect Setup Time 20 ns
Write Protect Hold Time 100 ns
S High to Deep Power-down Mode 3
S High to Standby Mode without Electronic
Signature Read
S High to Standby Mode with Electronic
Signature Read
Write Status Register Cycle Time 5 15 ms
Page Program Cycle Time 1.5 5 ms
Sector Erase Cycle Time 2 3 s
Bulk Erase Cycle Time 3 6 s
C
3
1.8
s
µ
s
µ
s
µ
27/34
M25P05-A
Figure 22. Serial Input Timing
S
C
tDVCH
tSLCH
tSHSL
tCHSHtCHSL
tSHCH
tCHCL
tCHDX
D
Q
MSB IN
High Impedance
tCLCH
LSB IN
Figure 23. Wri t e Pr otect Setup and Hold Ti m ing during WRSR when SRWD=1
W
tWHSL
S
C
AI01447C
tSHWL
28/34
D
High Impedance
Q
AI07439
Figure 24. Hol d Timing
S
C
Q
D
HOLD
tCHHL
M25P05-A
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
AI02032
Figure 25. Output Timing
S
C
tCLQV
tCLQX
Q
ADDR.LSB IN
D
tCLQX
tCLQV
tCH
tCL
tQLQH
tQHQL
tSHQZ
LSB OUT
AI01449D
29/34
M25P05-A
PACKAGE MECHANICAL
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Ou tline
h x 45˚
Note: Drawing is not to scale.
B
SO-a
A
e
D
N
1
CP
E
H
C
LA1 α
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Symb.
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
mm inches
30/34
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α
0° 8° 0° 8°
N8 8
CP 0.10 0.004
VFQFPN8 – 8-contact Very-thin Fine-pitch QFP No-lead, Package Outline
D
D1
E
E1
M25P05-A
eE2
b
A
Note: Drawing is not to scale.
A1
θ
A2
A3
D2
L
VFQFPN-01
VFQFPN8 – 8-contact Very-thin Fine-pitch QFP No-lead, Package Mecha nical Data
Symb.
Typ. Min. Max. Typ. Min. Max.
A 0.85 1.00 0.0 335 0.0394
A1 0 .00 0.05 0.0000 0.0020
A2 0.65 0.0256
A3 0.20 0.0079
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 6.00 0.2362
mm inches
D1 5 .75 0.2264
D2 3 .40 3.20 3.60 0.1339 0.1260 0.1417
E 5.00 0.1969
E1 4.75 0.1870
E2 4.00 3.80 4.20 0.1575 0.1496 0.1654
e 1.27 0.0500
L 0.60 0.50 0.75 0.0236 0.0197 0.0295
θ
12° 12°
31/34
M25P05-A
PART NUMBERING
Table 14. Ordering Information Scheme
Example: M25P05-A V MN 6 T
Device Type
M25P
Device Function
05-A = 512 Kbit (64K x 8) Enhanced Techology in line with
the M25P10-A, M25P20, M25P40, M25P80
Operating Voltage
V = V
Package
MN = SO8 (150 mil width)
MP = VFQFPN8 (MLP8)
Temperature Range
6 = –40 to 85 °C
= 2.7 to 3.6V
CC
Option
T = Tape & Reel Packing
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales O ffice.
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REVISION HIST ORY
Table 15. Document Revision History
Date Rev. Description of Revision
25-Feb-2001 1.0 Document written
11-Apr-2002 1.1
12-Sep-2002 1.2 VFQFPN8 package (MLP8) added.
Clarification of descriptions of entering Stand-by Power mode from Deep Power-down mode,
and of terminating an instruction sequence or data-out sequence.
M25P05-A
13-Dec-2002 1.3
Typical Page Program time improved. Write Protect setup and hold times specified, for
applications that switch Write Protect to exit the Hardware Protection mode immediately before
a WRSR, and to enter the Hardware Protection mode again immediately after.
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M25P05-A
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