Page 1
Features
SO8 (MN)
■ Compatible with all I
– 1 MHz Fast-mode Plus
– 400 kHz Fast mode
– 100 kHz Standard mode
■ Memory array:
– 2 Mb (256 Kbytes) of EEPROM
– Page size: 256 Bytes
■ Additional Write lockable Page (Identification
page)
■ Write
– Byte Write within 10 ms
– Page Write within 10 ms
■ Random and Sequential Read modes
■ Noise suppression
– Schmitt trigger inputs
– Input noise filter
■ Write protect of the whole memory array
■ Single supply voltage:
– 1.8 V to 5.5 V
■ Enhanced ESD/Latch-Up protection
■ More than 1 million Write cycles
■ More than 40-year data retention
■ Packages
– RoHS compliant and halogen-free
(ECOPACK2
2
C bus modes:
®
)
M24M02-DR
2 Mbit serial I²C bus EEPROM
February 2012 Doc ID 18204 Rev 4 1/30
www.st.com
1
Page 2
Contents M24M02-DR
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Chip Enable (E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Write Control (WC
2.5 V
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SS
2.6 Supply voltage (V
2.6.1 Operating supply voltage V
2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.8 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.9 Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.10 Lock Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.11 ECC (error correction code) and Write cycling . . . . . . . . . . . . . . . . . . . . . 16
3.12 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18
3.13 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.15 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.16 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.17 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/30 Doc ID 18204 Rev 4
Page 3
M24M02-DR Contents
3.18 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.19 Read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Doc ID 18204 Rev 4 3/30
Page 4
List of tables M24M02-DR
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Memory cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. AC characteristics at 400 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. SO8N – 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 27
Table 15. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4/30 Doc ID 18204 Rev 4
Page 5
M24M02-DR List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Maximum R
bus at maximum frequency f
Figure 5. Maximum R
bus at maximum frequency f
Figure 6. I
2
C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Write mode sequences with WC
Figure 8. Write mode sequences with WC
Figure 9. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 27
value versus bus parasitic capacitance (C
bus
value versus bus parasitic capacitance (C
bus
= 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
C
= 1 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
C
= 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 13
= 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15
) for an I2C
bus
) for an I2C
bus
Doc ID 18204 Rev 4 5/30
Page 6
Description M24M02-DR
1 Description
The M24M02-DR is an I2C-compatible electrically erasable programmable memory
(EEPROM) device organized as 256 Kb × 8 bits.
The M24M02-DR offers an additional page, named the Identification Page (256 bytes) which
can be written and (later) permanently locked in Read-only mode. This Identification Page
offers flexibility in the application board production line, as it can be used to store unique
identification parameters and/or parameters specific to the production line.
Figure 1. Logic diagram
6
6
##
##
%
%
3#,
3#,
7#
7#
--$2
--$2
3$!
3$!
6
6
33
33
!)
!)
Table 1. Signal names
Signal name Function Direction
E2 Chip Enable Input
SDA Serial Data I/O
SCL Serial Clock Input
WC
V
CC
V
SS
Write Control Input
Supply voltage
Ground
Figure 2. SO8 connections
$5 6
%
33
1. See Section 7: Package mechanical data for package dimensions, and how to identify pin-1.
2. DU = Don’t Use (the pin must be left floating or connected to Vss).
##
7#$5
3#,
3$!6
!)V
6/30 Doc ID 18204 Rev 4
Page 7
M24M02-DR Signal description
Ai12806
V
CC
M24xxx
V
SS
E
i
V
CC
M24xxx
V
SS
E
i
Ai12806
V
CC
M24xxx
V
SS
E
i
V
CC
M24xxx
V
SS
E
i
2 Signal description
2.1 Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to V
most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2 Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to V
the value of the pull-up resistor can be calculated).
. (Figure 5 indicates how the value of the pull-up resistor can be calculated). In
CC
(Figure 5 indicates how
CC
2.3 Chip Enable (E2)
This input signal is used to set the value that is to be looked for on the bit b3 of the 7-bit
device select code. This input must be tied to V
code as shown in Figure 3. When not connected (left floating), this input is read as low (0).
Figure 3. Device select code
or VSS, to establish the device select
CC
Doc ID 18204 Rev 4 7/30
Page 8
Signal description M24M02-DR
2.4 Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC
Write operations are allowed.
) is driven high. When unconnected, the signal is internally read as VIL, and
When Write Control (WC
acknowledged, Data bytes are not acknowledged.
) is driven high, device select and address bytes are
2.5 VSS ground
VSS is the reference for the VCC supply voltage.
2.6 Supply voltage (VCC)
2.6.1 Operating supply voltage V
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V
secure a stable DC supply voltage, it is recommended to decouple the V
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V
pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (t
2.6.2 Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Ta bl e 7 and the rise time must not vary faster than 1 V/µs.
(min), VCC(max)] range must be applied (see Tab l e 7 ). In order to
CC
CC
line with a
CC
CC/VSS
).
W
package
2.6.3 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until V
reached the internal reset threshold voltage. This threshold is lower than the minimum V
operating voltage defined in Ta bl e 7 ). When VCC passes over the POR threshold, the device
is reset and enters the Standby Power mode. The device must not be accessed until V
reaches a valid and stable V
defined in Ta bl e 7 .
In a similar way, during power-down (continuous decrease in V
below the power-on-reset threshold voltage, the device stops responding to any instruction
sent to it.
voltage within the specified [VCC(min), VCC(max)] range
CC
2.6.4 Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that is there is no internal
write cycle in progress).
8/30 Doc ID 18204 Rev 4
), as soon as VCC drops
CC
CC
has
CC
CC
Page 9
M24M02-DR Signal description
AIB
"USLINECAPACITORP&
"USLINEPULLUPRESISTOR
K
)£#BUS
MASTER
-XXX
2
BUS
6
##
#
BUS
3#,
3$!
2
BUS
§
#
BUS
NS
(ERE2
BUS
§#
BUS
NS
K½
P&
4HE2X#TIMECONSTANT
MUSTBEBELOWTHENS
TIMECONSTANTLINEREPRESENTED
ONTHELEFT
BUS
BUS
Figure 4. Maximum R
bus at maximum frequency f
Figure 5. Maximum R
bus at maximum frequency f
2
BU
§
S
#
BU
NS
S
2
BUS
value versus bus parasitic capacitance (C
bus
value versus bus parasitic capacitance (C
bus
§
(ERE
NS
#
BUS
= 400 kHz
C
= 1 MHz
C
4HE2
§#
BUS
MUSTBEBELOWTHENS
TIMECONSTANTLINEREPRESENTED
ONTHELEFT
TIMECONSTANT
BUS
)£#BUS
MASTER
) for an I2C
bus
) for an I2C
bus
6
##
2
3#,
3$!
BUS
-XXX
#
BUS
"USLINEPULLUPRESISTORK
"USLINECAPACITORP&
Doc ID 18204 Rev 4 9/30
-36
Page 10
Signal description M24M02-DR
SCL
SDA
SCL
SDA
SDA
START
Condition
SDA
Input
SDA
Change
AI00792B
STOP
Condition
1 23 7 89
MSB
ACK
START
Condition
SCL
1 23 7 89
MSB ACK
STOP
Condition
SCL
SDA
SCL
SDA
SDA
START
Condition
SDA
Input
SDA
Change
AI00792B
STOP
Condition
1 23 7 89
MSB
ACK
START
Condition
SCL
1 23 7 89
MSB ACK
STOP
Condition
Figure 6. I2C bus protocol
Table 2. Device select code
Device type identifier
b7 b6 b5 b4 b3 b2 b1 b0
Device select code
1. The most significant bit, b7, is sent first.
2. E2 bit value is compared to the logic level applied on the input pin E2.
Table 3. Most significant address byte
1010E2
A15 A14 A13 A12 A11 A10 A9 A8
Table 4. Least significant address byte
A7 A6 A5 A4 A3 A2 A1 A0
10/30 Doc ID 18204 Rev 4
(1)
Chip
Enable
(2)
MSB address
bits
RW
A17 A16 RW
Page 11
M24M02-DR Device operation
3 Device operation
The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always slave in all
communications.
3.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
3.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode. A Stop condition at the end of a Write
instruction triggers the internal EEPROM Write cycle.
3.3 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9
acknowledge the receipt of the eight data bits.
th
clock pulse period, the receiver pulls Serial Data (SDA) low to
3.4 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
Doc ID 18204 Rev 4 11/30
Page 12
Device operation M24M02-DR
3.5 Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Ta bl e 2 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier and a Chip Enable “Address”
(E2). To address the memory array, the 4-bit device type identifier is 1010b.
Up to two memory devices can be connected on a single I
bit value on its Chip Enable E2 input. When the device select code is received, the device
only responds if the Chip Enable address is the same as the value on its Chip Enable E2
input.
th
The 8
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
2
C bus. Each is given a unique 1-
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9
th
bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 5. Operating modes
Mode RW bit WC
Current Address Read 1 X 1 Start, device select, RW
0X
Random Address Read
1 X reStart, device select, RW
Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0 V
Page Write 0 V
1. X = V
IH
or V
.
IL
(1)
Bytes Initial sequence
Start, device select, RW
1
IL
IL
1 Start, device select, RW = 0
≤ 256 Start, device select, RW = 0
= 1
= 0, Address
= 1
12/30 Doc ID 18204 Rev 4
Page 13
M24M02-DR Device operation
Stop
Start
Byte Write Dev sel Byte addr Byte addr Data in
WC
Start
Page Write Dev sel Byte addr Byte addr Data in 1
WC
Data in 2
AI01120d
Page Write (cont'd)
WC (cont'd)
Stop
Data in N
ACK ACK ACK NO ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK NO ACK
Figure 7. Write mode sequences with WC = 1 (data write inhibited)
Doc ID 18204 Rev 4 13/30
Page 14
Device operation M24M02-DR
3.6 Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Each data byte in the memory has an 18-bit address (the most significant bits A17, A16 are
defined in the device select code and the Least Significant Bits A15 - A0 are defined in two
address bytes). The most significant byte (Ta bl e 3 ) is sent first, followed by the least
significant byte (Tab le 4 ).
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10
memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the
internal Write cycle.
After the Stop condition, the delay t
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 7.
th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal
3.7 Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is write-protected, by Write Control (WC
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 8.
3.8 Page Write
, and the successful completion of a Write operation,
W
) being driven high, the
The Page Write mode allows up to 256 bytes to be written in a single write cycle, provided
that they are all located in the same “row” in the memory: that is, the most significant
memory address bits, A17-A8, are the same. If more bytes are sent than will fit up to the end
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 256 bytes of data, each of which is acknowledged by the
device if Write Control (WC
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (the 8 least significant
address bits only) is incremented. The transfer is terminated by the bus master generating a
Stop condition.
14/30 Doc ID 18204 Rev 4
) is low. If Write Control (WC) is high, the contents of the
Page 15
M24M02-DR Device operation
Stop
Start
Byte Write Dev sel Byte addr
Byte addr Data in
WC
Start
Page Write Dev sel Byte addr Byte addr Data in 1
WC
Data in 2
AI01106d
Page Write (cont'd)
WC (cont'd)
Stop
Data in N
ACK
R/W
ACK ACK ACK
ACK ACK ACK ACK
R/W
ACKACK
Figure 8. Write mode sequences with WC = 0 (data write enabled)
3.9 Write Identification Page
The Identification Page (256 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences:
● Device type identifier = 1011b
● MSB address bits A17/A9 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A7/A0 define the byte address inside the identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
Doc ID 18204 Rev 4 15/30
Page 16
Device operation M24M02-DR
3.10 Lock Identification Page
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
● Device type identifier = 1011b
● Address bit A10 must be ‘1’; all other address bits are don't care
● The data byte must be equal to the binary value xxxx xx1x, where x is don't care
If the Identification Page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
3.11 ECC (error correction code) and Write cycling
The M24M02-DR offers an ECC (Error Correction Code) logic which compares each 4-byte
word with its associated 6 EEPROM bits of ECC. As a result, if a single bit out of 4 bytes of
data happens to be erroneous during a Read operation, the ECC detects it and replaces it
with the correct value. The read reliability is therefore much improved by the use of this
feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes
making up the word. It is therefore recommended to write data by word (4 bytes) at address
4*N (where N is an integer) in order to benefit from the larger amount of Write cycles.
The M24M02-DR devices are qualified as 1 million (1,000,000) Write cycles, using a cycling
routine that writes to the device by multiples of 4-byte words.
16/30 Doc ID 18204 Rev 4
Page 17
M24M02-DR Device operation
Write cycle
in progress
AI01847d
Next
Operation is
addressing the
memory
Start condition
Device select
with RW = 0
ACK
returned
YES
NO
YESNO
ReStart
Stop
Data for the
Write cperation
Ddevice select
with RW = 1
Send Address
and Receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YESNO
StartCondition
Continue the
Write operation
Continue the
Random Read operation
Figure 9. Write cycle polling flowchart using ACK
Doc ID 18204 Rev 4 17/30
Page 18
Device operation M24M02-DR
Start
Dev sel * Byte addr Byte addr
Start
Dev sel Data out 1
AI01105d
Data out N
Stop
Start
Current
Address
Read
Dev sel Data out
Random
Address
Read
Stop
Start
Dev sel * Data out
Sequential
Current
Read
Stop
Data out N
Start
Dev sel * Byte addr Byte addr
Sequention
Random
Read
Start
Dev sel * Data out1
Stop
ACK
R/W
NO ACK
ACK
R/W
ACK ACK ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK
ACK ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK
3.12 Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
shown in Ta bl e 1 2 , but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.
The sequence, as shown in Figure 9, is:
● Initial condition: a Write cycle is in progress.
● Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
● Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 10. Read mode sequences
w
) is
18/30 Doc ID 18204 Rev 4
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must
be identical.
Page 19
M24M02-DR Device operation
3.13 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
3.14 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 10) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
bit set to 1. The device
3.15 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 10, without acknowledging the byte.
bit set to 1. The device acknowledges this, and
3.16 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 10.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
3.17 Acknowledge in Read mode
For all Read instructions, the device waits, after each byte read, for an acknowledgment
during the 9
time, the device terminates the data transfer and switches to its Standby mode.
th
bit time. If the bus master does not drive Serial Data (SDA) low during this
Doc ID 18204 Rev 4 19/30
Page 20
Initial delivery state M24M02-DR
3.18 Read Identification Page
The Identification Page (256 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A17/A8 are don't
care, the LSB address bits A7/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary (e.g.: when
reading the Identification Page from location 100d, the number of bytes should be less than
or equal to 156, as the ID page boundary is 256 bytes).
3.19 Read the lock status
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit if the Identification page is unlocked,
otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
● The truncated command is not executed because the Start condition resets the device
internal logic,
● The device is then set back into Standby mode by the Stop condition.
4 Initial delivery state
The device is delivered with all the memory array bits set to 1 (each byte contains FFh).
20/30 Doc ID 18204 Rev 4
Page 21
M24M02-DR Maximum rating
5 Maximum rating
Stressing the device outside the ratings listed in Ta bl e 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 6. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
Ambient temperature with power applied –40 130 °C
T
STG
T
LEAD
V
IO
I
OL
V
CC
V
ESD
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. Positive and negative pulses applied on pin pairs, in accordance with AEC-Q100-002 (compliant with
JEDEC Std JESD22-A114, C1=100pF, R1=1500Ω, R2=500Ω)
Storage temperature –65 150 °C
Lead temperature during soldering see note
(1)
°C
Input or output range –0.50 6.5 V
DC output current (SDA = 0) - 5 mA
Supply voltage –0.50 6.5 V
Electrostatic pulse (Human Body model)
(2)
3000 V
6 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 7. Operating conditions
Symbol Parameter Min. Max. Unit
V
CC
T
A
Supply voltage 1.8 5.5 V
Ambient operating temperature –40 85 °C
Doc ID 18204 Rev 4 21/30
Page 22
DC and AC parameters M24M02-DR
0.8V
CC
0.2V
CC
0.7V
CC
0.3V
CC
Input and Output
Timing Reference Levels
Input Levels
!)#
Table 8. AC measurement conditions
Symbol Parameter Min. Max. Unit
C
Load capacitance 100 pF
L
SCL input rise/fall time,
SDA input fall time
Input levels 0.2VCC to 0.8V
Input and output timing reference levels 0.3VCC to 0.7V
50 ns
CC
CC
Figure 11. AC measurement I/O waveform
Table 9. Memory cell characteristics
Symbol Parameter Test condition Min. Max. Unit
N
cycle
Endurance TA = 25°C, 1.8V < Vcc < 5.5V 1,000,000 - Write cycle
V
V
Note: This parameter is not tested but established by characterization and qualification. To
estimate endurance in a specific application, please refer to AN2014.
Table 10. Input parameters
Symbol Parameter
Input capacitance (SDA) 8 pF
C
IN
C
Input capacitance (other pins) 6 pF
IN
Input impedance
(2)
Z
L
(E2, WC)
Input impedance
(2)
Z
H
(E2, WC)
1. Characterized value, not tested in production.
2. E2: Input impedance when the memory is selected (after a Start condition).
(1)
Test condition Min. Max. Unit
V
IN
V
IN
< 0.3V
> 0.7V
30 kΩ
CC
500 kΩ
CC
22/30 Doc ID 18204 Rev 4
Page 23
M24M02-DR DC and AC parameters
Table 11. DC characteristics
Symbol Parameter
Input leakage current
I
LI
(E2, SCL, SDA)
I
I
I
CC0
I
CC1
V
V
V
1. Characterized value, not tested in production.
2. The device is not selected after a power-up, a Read instruction (after the Stop condition), or after the
completion of an internal write cycle t
Output leakage current
LO
Supply current (Read)
CC
(1)
Supply current (Write)
Standby supply current
Input low voltage
IL
(SCL, SDA, WC
Input high voltage
IH
(SCL, SDA, WC)
Output low voltage
OL
)
Test conditions specified in
Table 7 and Tabl e 8
= VSS or V
V
IN
CC
device in Standby mode
SDA in Hi-Z, external voltage
applied on SDA: V
= 1.8 V, fc= 400 kHz 1 mA
V
CC
= 2.5 V, fc= 400 kHz 1 mA
V
CC
= 5.5 V, fc= 400 kHz 2 mA
V
CC
1.8 V < V
< 5.5 V, fc= 1 MHz 2.5 mA
CC
SS
or V
CC
Average value during tW,
1.8V ≤ V
Device not selected
= VSS or VCC, VCC = 1.8 V
V
IN
Device not selected
V
= VSS or VCC, VCC = 2.5 V
IN
Device not selected
V
= VSS or VCC, VCC = 5.5 V
IN
CC
≤ 5.5V
(2)
(2)
(2)
,
,
,
Min. Max. Unit
± 2 µA
± 2 µA
2mA
3µA
5µA
5µA
1.8 V ≤ VCC < 2.5 V –0.45 0.25 V
2.5 V ≤ V
1.8 V ≤ V
2.5 V ≤ V
I
= 1.0 mA, VCC = 1.8 V 0.2 V
OL
= 2.1 mA, VCC = 2.5 V 0.4 V
I
OL
= 3.0 mA, VCC = 5.5 V 0.4 V
I
OL
(tW is triggered by the correct decoding of a Write instruction).
W
≤ 5.5 V –0.45 0.3 V
CC
< 2.5 V 0.75V
CC
≤ 5.5 V 0.7V
CC
CCVCC
CC
VCC+1
CC
CC
+1 V
V
Doc ID 18204 Rev 4 23/30
Page 24
DC and AC parameters M24M02-DR
Table 12. AC characteristics at 400 kHz
Test conditions specified in Tab l e 7 and Ta b l e 8
Symbol Alt. Parameter Min.
f
C
t
CHCL
t
CLCH
t
QL1QL2
t
XH1XH2
t
XL1XL2
t
DXCX
t
CLDX
t
CLQX
(5)(6)
t
CLQV
t
CHDL
t
DLCL
t
CHDH
t
DHDL
t
W
(2)
t
NS
1. All values are referred to VIL(max) and VIH(min).
2. Characterized only, not tested in production.
3. With CL = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
< 400 kHz.
C
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
6. t
CLQV
0.7VCC, assuming that the R
(2)
f
t
HIGH
t
LOW
t
SU:DAT
t
HD:DAT
t
SU:STA
t
HD:STA
t
SU:STO
t
t
Clock frequency 400 kHz
SCL
Clock pulse width high 600 ns
Clock pulse width low 1300 ns
t
SDA (out) fall time 20
F
t
Input signal rise time
R
t
Input signal fall time
F
Data in set up time 100 ns
Data in hold time 0 ns
t
Data out hold time 100 ns
DH
t
Clock low to next data valid (access time) 100 900 ns
AA
Start condition setup time 600 ns
Start condition hold time 600 ns
Stop condition set up time 600 ns
Time between Stop condition and next Start
BUF
condition
Write time 10 ms
WR
Pulse width ignored (input filter on SCL and
SDA)
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
bus
× C
time constant is within the values specified in Figure 4.
bus
(1)
(3)
(4)
(4) (4)
1300 ns
(1)
Max.
120 ns
(4)
80 ns
Unit
ns
ns
24/30 Doc ID 18204 Rev 4
Page 25
M24M02-DR DC and AC parameters
Table 13. 1 MHz AC characteristics
Test conditions specified in Tab l e 7 and Table 8
Symbol Alt. Parameter Min. Max. Unit
f
C
t
CHCL
t
CLCH
t
XH1XH2
t
XL1XL2
t
QL1QL2
t
DXCX
t
CLDX
(3)
t
CLQX
(4)
t
CLQV
t
CHDL
t
DLCL
t
CHDH
t
DHDL
t
W
(5)
t
NS
1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
< 400 kHz, or less than 120 ns when fC<1MHz.
C
2. With CL = 10 pF
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4. t
5. Characterized only, not tested in production.
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
CLQV
0.7 V
CC
(5)
f
t
HIGH
t
t
SU:DAT
t
HD:DAT
t
SU:STA
t
HD:STA
t
SU:STO
t
Clock frequency 0 1 MHz
SCL
Clock pulse width high 260 - ns
Clock pulse width low 400 - ns
LOW
t
Input signal rise time
R
t
Input signal fall time
F
t
SDA (out) fall time 20
F
Data in setup time 50 - ns
Data in hold time 0 - ns
t
Data out hold time 100 - ns
DH
t
Clock low to next data valid (access time) - 450 ns
AA
Start condition setup time 250 - ns
Start condition hold time 250 - ns
Stop condition setup time 250 - ns
Time between Stop condition and next
BUF
Start condition
t
Write time - 10 ms
WR
Pulse width ignored (input filter on SCL and
SDA)
, assuming that the R
bus
(1)
(1) (1)
500 - ns
×C
time constant is within the values specified in Figure 4.
bus
(1)
ns
ns
(2)
120 ns
-80ns
Doc ID 18204 Rev 4 25/30
Page 26
DC and AC parameters M24M02-DR
Figure 12. AC waveforms
T8(8(
3#,
3$!)N
3#,
3$!)N
3#,
T8,8,
T$,#,
T#($,
3TART
CONDITION
T#($(
T8(8(
3TOP
CONDITION
T#(#,
T#,16 T#,18
T#(#,
3$!
)NPUT
T#,#(
3$!
#HANGE
T7
7RITECYCLE
T8,8,
T$8#(T#,$8
T1,1,
T#($( T$($,
T#($,
3TART
CONDITION
3TOP
CONDITION
3TART
CONDITION
3$!/UT
$ATAVALID
$ATAVALID
!)F
26/30 Doc ID 18204 Rev 4
Page 27
M24M02-DR Package mechanical data
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Figure 13. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scale.
Table 14. SO8N – 8-lead plastic small outline, 150 mils body width, package data
millimeters inches
Symbol
Typ Min Max Typ Min Max
(1)
A 1.75 0.0689
A1 0.1 0.25 0.0039 0.0098
A2 1.25 0.0492
b 0.28 0.48 0.011 0.0189
c 0.17 0.23 0.0067 0.0091
ccc 0.1 0.0039
D 4.9 4.8 5 0.1929 0.189 0.1969
E 6 5.8 6.2 0.2362 0.2283 0.2441
E1 3.9 3.8 4 0.1535 0.1496 0.1575
e 1.27 - - 0.05 - -
h 0.25 0.5 0.0098 0.0197
k 0°8° 0°8°
L 0.4 1.27 0.0157 0.05
L1 1.04 0.0409
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 18204 Rev 4 27/30
Page 28
Part numbering M24M02-DR
8 Part numbering
Table 15. Ordering information scheme
Example: M24M02–D R MN 6 T P
Device type
M24 = I2C serial access EEPROM
Device function
M02–D = 2 Mbit (256 Kb × 8 bits) EEPROM with additional
identification page
Operating voltage
R = V
Package
MN = SO8 (150 mils width)
= 1.8 V to 5.5 V
CC
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = standard packing
T = tape and reel packing
Plating technology
®
P or G = ECOPACK2
(RoHS compliant and
Halogen-free)
28/30 Doc ID 18204 Rev 4
Page 29
M24M02-DR Revision history
9 Revision history
Table 16. Document revision history
Date Revision Changes
22-Dec-2010 1 Initial release.
Updated:
– Section 3.18: Read Identification Page
– Section 3.19: Read the lock status
– Figure 2: SO8 connections
– Table 6: Absolute maximum ratings
09-Feb-2011 2
09-Aug-2011 3
07-Feb-2012 4
– Table 10: Input parameters
– Table 11: DC characteristics
– Table 12: AC characteristics at 400 kHz
– Table 13: 1 MHz AC characteristics
Deleted:
– Table 15 “Available M24M02-x products (package, voltage range,
frequency, temperature grade)”.
Updated Figure 5: Maximum Rbus value versus bus parasitic
capacitance (Cbus) for an I2C bus at maximum frequency fC = 1 MHz
and Table 11: DC characteristics.
Updated:
– Table 2: Device select code
– Table 3: Most significant address byte
– Table 4: Least significant address byte.
– Section 3.6: Write operations
– Section 3.8: Page Write
Doc ID 18204 Rev 4 29/30
Page 30
M24M02-DR
Please Read Carefully:
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30/30 Doc ID 18204 Rev 4
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