Datasheet M24M01-V, M24M01-S, M24M01 Datasheet (SGS Thomson Microelectronics)

M24M01

1 Mbit Serial I²C Bus EEPROM

FEATURES SUMMARY

■ 400 kHz High Speed Two Wire I

2

C Serial

Interface

■ Single Supply Voltage:

– 2.7V to 3.6V for M24M01-V
– 1.8V to 3.6V for M24M01-S

■ Write Control Input

■ BYTE and PAGE WRITE (up to 128 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Tim e d P rogrammin g Cyc le

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ More than 100000 Erase/Write Cycles

■ More than 40 Year Data Retention

Figure 1. Packages

LGA

LGA8 (LA)

1/19January 2003

M24M01

SUMMARY DESCRIPTION

The M24M01 is a 1 M bit (131, 072 x 8 ) electrically
erasable programmable memory (EEPROM) ac­cessed by an I

Figure 2. Logic Diagram

E1-E2

SCL

WC

2

C-compatible bus .

V

CC

2

M24M01

V

SS

SDA

AI04048B

When writing data to the memory, the device in­serts an acknowledge bit during the 9

th

bit time,

following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.

Figure 3. LGA Connections

M24M01

DU

E1
E2

SS

1
2
3
4

8
7
6
5

AI04051C

V

CC
WC
SCL

SDAV

Table 1. Signal Names

E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC
V

CC

V

SS

These devices are compatible with the I

Write Control
Supply Voltage
Ground

2

C memo­ry protocol. This is a two wire s erial interface that
uses a bi-directional data bus and serial clock. The
devices carry a built-in 4-bit Device Type Identifier
code (1010) in accordance with the I

2

C bus defini-

tion.
The device behaves as a slave in the I

2

C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat­ed by a Start condition, generated by the bus mas­ter. The Start condition is followed by a Device
Select Code and RW

bit (as described in Table 2),

terminated by an acknowledge bit.

Note: 1. DU = Don’t Us e (should be left unc onnected, or tied to

V

)

SS

Power On Reset: VCC Lock-Out Write Protect

In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V

has reached the POR

CC

threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V

drops from the operating

CC

voltage, below the POR threshold value, all oper­ations are disabled and the device will not respond
to any command. A stable and valid V

must be

CC

applied before applying any logic signal.
When the power supply is turned on, V

from V

to VCC(min), passing through a value V

SS

CC

rises

in between. The device ignores all instructions un­til a time delay of t
ment that V

CC

has elapsed after the mo-

PU

rises above the Vth threshold.
However, the correct operation of the device is not
guaranteed if, by this time, V
V

(min).No instructions should be sent until the

CC

is still below

CC

later of:
–t

afte r VCC passed the Vth threshold

PU

passed the VCC(min) lev el

–V

CC

These values are specified in Table 9.

th

2/19

SIGNAL DESCRIPTION
Serial Clock (SCL)

This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be con­nected from Serial Clock (SCL) to V

. (Figure 4

CC

indicates how the value of the pull-up resist or can
be calculated). In most applications, thoug h, this
method of synchronization is no t employed, and
so the pull-up resistor is not necessary, provided
that the bus maste r has a push-pull (rather than
open drain) output.

Serial Data (SDA)

This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that

may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V

CC

. (Fig­ure 4 indicates how the value of the pull-up resistor
can be calculated).

M24M01

Chip Enable (E1, E2)

These input signals are used to set the value that
is to be looked for on bits b3 and b2 of the 7-bit De­vice Select Code. These inputs must be tied to

or VSS, to establish the Device Select Code.

V

CC

When unconnected, the Chip Enable (E1, E2) sig­nals are internally read as V

11).

Write Control (WC

)

This input signal is useful for protecting the entire
contents of the memory from inadvertent write op­erations. Write operations are disabled to the en­tire memory array when Write Control (WC
driven High. When unconnected, the signal is in­ternally read as V

, and Write operations are al-

IL

lowed.
When Write Control (WC

Select and Address bytes are acknowledged,
Data bytes are not acknowledged.

(see Tables 10 and

IL

) is

) is driven High, Device

Figure 4. Maximum R

20

16

12

8

Maximum RP value (kΩ)

4

0

10 1000

Value versus Bus Capacitance (C

L

fc = 100kHz

fc = 400kHz

100

C

(pF)

BUS

) for an I2C Bus

BUS

V

MASTER

CC

SDA

SCL

R

R

C

BUS

L

C

BUS

AI01665

L

3/19

M24M01

DEVICE OPERATION

2

The device supports the I

C protocol. This is sum­marized in Figure 2. Any device that sends data on
to the bus is defined to be a transmitter, a nd any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device.
A data transfer can only be initiated by the bus
master, w h ic h will also provide t h e s e r i a l c loc k for
synchronization. The M24M 01 de vice is always a
slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The devi ce continuously
monitors (except duri ng a Write cycle ) Se ri a l Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is give n.

Stop Condition

Stop is identified by a rising edg e of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv­en High. A Stop condition terminates communica­tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condi tion to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE­PROM Wr ite cycle .

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a success­ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the

th

clock pulse period, the receiver pulls Serial

9
Data (SDA) Low to acknowledge the receipt of the
eight data bits.

Data Input

During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change

only

when Serial Clock (SCL) is driv-

en Low.

Memory Addressing

To start communication betwee n the bus master
and the slave device, the bus mas ter mus t initiate
a Start condition. Following this, t he bus master
sends the Device Select Code, shown in Tabl e 2
(on Serial Data (SDA), most significant bit first).

The Device Select Code consists of a 4-bit Device

Type Identifier, and a 2-bit Chip Enable “Address”
(E1, E2). To address the memory array, the 4-bit
Device Type Identifier is 1010b.

Up to four memory devices can be connected on a
single I

2

C bus. Each one is given a unique 2-bit
code on the Chip Enable (E1, E2) i nputs. When
the Device Select Code is received on Serial Data
(SDA), the device only responds if the Chip Enable
Address is the same as the value on the Chip En­able (E1, E2) inputs.

th

The 8

bit is the Read/Write bit (RW). This bi t is

set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code , the

corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9

th

bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand­by mode.

Table 2. Device Select Code

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 E2 E1 A16 RW

Note: 1. The m ost signific ant bit, b7, is sent first.

4/19

1

Device Type Identifier Chip Enable Address RW

Figure 5. I2C Bus Protocol

SCL

SDA

M24M01

SCL

SDA

SCL

SDA

START

Condition

START

Condition

1 23 789

MSB

1 23 789

MSB ACK

SDA

Input

SDA

Change

STOP

Condition

ACK

STOP

Condition

AI00792B

Table 3. Operating Modes

Mode RW bit

Current Address Read 1 X 1 START, Device Select, RW

0X

Random Address Read

1 X reSTART, Device Select, RW
Sequential Read 1 X
Byte Write 0 V
Page Write 0 V

Note: 1. X = V

IH

or V

.

IL

WC

1

Bytes Initial Sequence

START, Device Select, RW

1

1 Similar to Current or Random Address Read

≥

IL

IL

1 START, Device Select, RW = 0

128 START, Device Select, RW

≤

= 1
= 0, Address

= 1

= 0

5/19

M24M01

Figure 6. Wri te M ode Sequence s w ith W C =1 (data write inhib i ted)

WC

ACK ACK ACK NO ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

R/W

START

WC

ACK ACK ACK NO ACK

PAGE WRITE DEV SEL BYTE ADDR

R/W

START

WC (cont'd)

NO ACK NO ACK

PAGE WRITE
(cont'd)

DATA IN N

STOP

BYTE ADDR DATA IN 1

STOP

DATA IN 2

AI01120C

Write Operations

Following a Start condition the bus master sends
a Device Select Code with the RW

bit rese t to 0 .
The device acknowledges this, as shown in Figure
7, and waits for two address bytes. The device re­sponds to each address byte with an acknowledge
bit, and then waits for the data byte.

Writing to the memory may be inhibited if Write
Control (WC
with Write Control (WC

) is driven High. Any Write instruction

) driven High (during a pe­riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are

not

acknowledged, as shown in Figure 6.

Each data byte in the memory has a 17-bit ad­dress. The most significant bit, A16, is sent with
the Device Select Code, and the remaining bits,
A15-A0, in the two a ddress bytes. The Mos t Sig­nificant Byte is sent first, followed by the Least Sig-

6/19

nificant Byte. Bits A16 to A0 form t he address of
the byte in memory.

When the bus mast er generates a Stop con dition

immediately after the Ack bi t (in t he “10

th

bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.

During the internal Write cycle, Serial Da ta (SDA)
is disabled internally, and the devi ce does not re­spond to any requests.

Byte Write

After the Device Select code and the address
bytes, the bus master sends one dat a byte. If the
addressed location is Write-protected, by Write
Control (WC

) being driven High, the device replies
with NoAck, and the location is not modified. If, in­stead, the addressed location is not Write-protect­ed, the device replies with Ack. The bus master

M24M01

terminates the transfer by generating a S top con­dition, as shown in Figure 7.

Page Write

The Page Write mode allows up to 128 bytes to be
written in a single Write cycle, provided that they

are all located in the same ’row’ in the memory:
that is, the most significant m emory address bits
(b16-b7) are the same. If more bytes are sent than
will fit up to t he en d of t he row, a condition known
as ‘roll-over’ occurs. This should be avoided, as
data starts to become overwritten in an implemen­tation dependent way.

Figure 7. Wri te M ode Sequence s w ith W C

WC

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

=0 (data write enabled)

ACK

R/W

The bus master sends from 1 to 128 bytes of data,
each of which is acknowledged by the device if
Write Control (WC

) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca­tion are not modified, and each dat a byte is fol­lowed by a NoAck. After each byt e is transferred,
the internal byte address counte r (the 7 least s ig­nificant address bits only) is incremented. The
transfer is terminated by the bus master generat­ing a Stop condition.

ACK ACK ACK

STOP

WC

ACK ACK ACK ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

R/W

START

WC (cont'd)

ACKACK

PAGE WRITE
(cont'd)

DATA IN N

STOP

DATA IN 2

AI01106C

7/19

M24M01

Figure 8. Wri te Cy cle Pol l in g Fl owchart usin g A CK

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

ACK

NO

Returned

First byte of instruction
with RW = 0 already
decoded by the device

ReSTART

STOP

YES

Next

Operation is

Addressing the

Memory

DATA for the

WRITE Operation

Continue the

WRITE Operation

Minimizing System Delays by Polling On ACK

During the internal Write cycle, the device discon­nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (t

) is shown in Table

w

12, but the typical time is short er. To m ak e use of
this, a polling sequence can be used by the bus
master.

The sequence, as shown in Figure 8, is:

– Initial condition: a Write cycle is in progress.

YESNO

Send Address

and Receive ACK

START

Condition

YESNO

DEVICE SELECT

with RW = 1

Continue the

Random READ Operation

AI01847C

– Step 1: the bus master issues a Start condition

followed by a Device Select Code (the first byte
of the new instruction).

– Step 2: if the device is busy with the internal

Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).

8/19

Figure 9. Read Mode Sequences

M24M01

CURRENT
ADDRESS
READ

RANDOM
ADDRESS
READ

SEQUENTIAL
CURRENT
READ

SEQUENTIAL
RANDOM
READ

ACK

DEV SEL DATA OUT

R/W

START

ACK

DEV SEL * BYTE ADDR BYTE ADDR

R/W

START

ACK ACK ACK NO ACK

DEV SEL DATA OUT 1

R/W

START

ACK ACK ACK

DEV SEL * BYTE ADDR BYTE ADDR

NO ACK

STOP

ACK ACK ACK

DEV SEL * DATA OUT

R/W

START

DATA OUT N

STOP

ACK ACK

DEV SEL * DATA OUT 1

NO ACK

STOP

R/W

START

ACK NO ACK

DATA OUT N

STOP

Note: 1. The seven most si gnificant bits of the Devi ce Select Co de of a Random Rea d (i n the 1st and 4th bytes) must be identical.

must

Read Operations

Read operations are performed independently of
the state of the Write Control (WC

) signal.

Random Address Read

A dummy Write is performed to load the address
into the address counter (as shown in Figure 9) but

without

sending a Stop condition. Then, t he bus
master sends another Start condition, and repeats
the Device Select Code, with t he RW

bit set to 1.

The device acknowledges this, and outputs the

the transfer with a Stop condition.

Current Address Read

The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read operation, following a Start
condition, the bus master only sends a Device Se­lect Code with the RW
knowledges this, an d outpu ts the byt e address ed
by the internal address counter. The counter is
then incremented. The bus master term inates the

START

not

acknowledge the byte, and terminates

R/W

AI01105C

bit set to 1. The device ac-

contents of the addressed byte. The bus master

9/19

M24M01

transfer with a Stop condition, a s shown i n Figure
9,

without

acknowledging the byte.

Sequenti a l Rea d

This operation can be used after a Current Ad­dress Read or a Random Address Read. The bus

does

master

acknowledge the data byte output,
and sends additional clock pulses so that the de­vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must

not

acknowledge the last byte, and

must

generate a Stop condition, as shown in Figure 9.
The output data comes from consecutive address-

es, with the internal address counter automatically

incremented after each byte output. After the last

memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.

Acknowledge in Read Mode

For all Read commands, the device waits, after
each byte read, for an acknowledgment during the

th

9

bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi­nates the data transfer and s witches to its St and­by mode.

10/19

MAXI MUM RATI N G

Stressing the device ab ove the rating listed in the
Absolute Maximum Ratings" table may cause per­manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions ab ove those i ndicated in t he

plied. Exposure to Absolute Maximum Rating con­ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and ot her relevant quality docu­ments.

Operating sections of this specificat ion is not im-

Table 4. Absolute Maximum Ratings

Symbol Parameter Min. Max. Unit

T

T

STG

LEAD

Storage Temperature –65 150 °C

Lead Temperature during Soldering

LGA: 20 seconds (max)

1

235

M24M01

°C

V

IO

V

CC

V

ESD

Note: 1. IPC/JEDEC J-STD-020A

2. JEDEC Std JESD 22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

Input or Output range –0.6 4.2 V
Supply Voltage –0.3 4.2 V

Electrostatic Discharge Voltage (Human Body model)

2

–3000 3000 V

11/19

M24M01

DC AND AC PARAMETERS

This section summarizes the operat ing and mea­surement conditions, and the DC and AC charac­teristics of the device. The parameters in t he DC
and AC Characteristic tables that follow are de­rived from tests performed under the Measure-

Table 5. Operating Conditions (M24M01-V)

Symbol Parameter Min. Max. Unit

ment Conditions summarized in the relevant
tables. Designers should chec k th at the o perat ing
conditions in their circuit matc h the meas urement
conditions when relying on the quoted parame­ters.

V

CC

T

A

Supply Voltage 2.7 3.6 V
Ambient Operating Temperature –40 8 5 °C

Table 6. Operating Conditions (M24M01-S)

Symbol Parameter Min. Max. Unit

V

CC

T

A

Supply Voltage 1.8 3.6 V
Ambient Operating Temperature –40 8 5 °C

Table 7. AC Measurement Conditions

Symbol Parameter Min. Max. Unit

C

L

Load Capacitance 30 pF
Input Rise and Fall Times 50 ns

to 0.8V

Input Pulse Voltages
Input and Output Timing Reference Voltages

Note: 1. Output Hi-Z is defined as the poin t where data out is no l onger driven.

0.2V

0.3V

CC

to 0.7V

CC

CC

CC

Figure 10. AC Measurement I/O Waveform

Input Levels

0.8V

CC

0.2V

CC

Input and Output

Timing Reference Levels

0.7V

CC

0.3V

CC

AI00825B

V
V

Table 8. Capacitance

Symbol Parameter Test Condition Min. Max. Unit

C

IN

C

IN

t

NS

Note: 1. TA = 25 °C, f = 400 kHz

2. Sampled only, not 100% tested.

12/19

Input Capacitanc e (SDA) 8 pF
Input Capacitance (other pins) 6 pF
Pulse width ignored

(Input Filter on SCL and SDA)

50 ns

Table 9. Power-Up Timing and Vth Threshol d

Symbol Parameter

Test Condition

M24M01

1

Min. Max. Unit

t
V

Note: 1. These paramet e rs are chara ct erized only.

Time delay to Read or Write instruction 200

PU

Threshold Voltage 1.1 1.4 V

th

Table 10. DC Characteristics (M24M01-V)

Symbol Parameter

Input Leakage Current

I

LI

I

LO

I

CC

I

CC1

V

IL

V

IH

V

OL

(SCL, SDA, E1, E2, W

Output Leakage Current
Supply Current
Stand-by Supply Current V
Input Low Voltage

(E1, E2, SCL, SDA, WC
Input High Voltage

(E1, E2, SCL, SDA, WC
Output Low Voltage IOL = 2.5 mA, 2.7 V ≤ VCC ≤ 3.6 V 0.4 V

C)

V

)

)

Table 11. DC Characteristics (M24M01-S)

Symbol Parameter

Input Leakage Current

I

LI

I

LO

I

CC

I

CC1

V

IL

(SCL, SDA, E1, E2, WC
Output Leakage Current
Supply Current
Stand-by Supply Current V
Input Low Voltage

(E1, E2, SCL, SDA, WC

)

V

)

Test Condition

(in addition to those in Table 5)

= VSS or V

V

IN

0V ≤ V

=3.6V, fc=400kHz (rise/fall time < 30ns)

CC

= VSS or V

IN

≤ V

OUT

, 2.7 V ≤ VCC ≤ 3.6 V 2 µA

CC

CC

SDA in Hi-Z

CC,

Test Condition

(in addition to those in Table 6)

= VSS or V

V

IN

0V ≤ V

=3.6V, fc=400kHz (rise/fall time < 30ns)

CC

IN

≤ V

OUT

= VSS or V

CC

SDA in Hi-Z

CC,

, VCC=3.6 V 2 µA

CC

Min. Max. Unit

± 1 µA

± 2 µA

2mA

CC

0.3V

VCC+1

CC

– 0.3

0.7V

Min. Max. Unit

± 1 µA

± 2 µA

2mA

– 0.3

0.3V

CC

s

µ

V

V

V

V

V

Input High Voltage

IH

(E1, E2, SCL, SDA, WC

Output Low Voltage

OL

)

= 2.5 mA, 2.7 V ≤ VCC ≤ 3.6 V 0.4 V

I

OL

R

= 2.2 kΩ, 1.8 V ≤ VCC ≤ 3.6 V 0.2V

L

0.7V

CC

VCC+1

CC

V

V

13/19

M24M01

Table 12. AC Characteristics

Test conditions specified in Table 7 and Table 5 or Table 6

Symbol Alt. Parameter Min. Max. Unit

f

C

t

CH1CH2

t

CL1CL2

t

CHCL

t

CLCH

2

t

DH1DH2

2

t

DL1DL2

t

DXCX

t

CLDX

t

CLQX

3

t

CLQV

1

t

CHDX

t

DLCL

t

CHDH

t

DHDL

t

W

Note: 1. For a reSTART condition, or following a Wr i te cycle.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

f

SCL

t

R

t

F

t

HIGH

t

LOW

t

R

t

F

t

SU:DAT

t

HD:DAT

t

DH

t

AA

t

SU:STA

t

HD:STA

t

SU:STO

t

BUF

t

WR

Clock Frequency 400 kHz
Clock Rise Time 20 300 ns
Clock Fall Time 20 300 ns
Clock Pulse Width High 600 ns
Clock Pulse Width Low 1300 ns
SDA Rise Time 20 300 ns

SDA Fall Time 20 300 ns
Data In Set Up Time 100 ns
Data In Hold Time 0 ns
Data Out Hold Time 200 ns
Clock Low to Next Data Valid (Access Time) 205 900 ns
Start Condition Set Up Time 600 ns
Start Condition Hold Time 600 ns
Stop Condition Set Up Time 600 ns
Time between Stop Condition and Next Start

Condition

1300 ns

Write Time 10 ms

14/19

Figure 11. AC Waveforms

M24M01

SCL

SDA In

SCL

SDA In

SCL

tCHCL

tDLCL

tCHDX

START

Condition

tCHDH

STOP

Condition

tCLQV tCLQX

SDA

Input

tCLCH

SDA

Change

tW

Write Cycle

tDXCXtCLDX

tCHDH tDHDL

tCHDX

START

Condition

STOP

Condition

START

Condition

SDA Out

Data Valid

AI00795C

15/19

M24M01

PACKAGE MECHANICAL

LGA8 - 8 lead Land Grid Array, Package Outline

E

A1

Notes: 1. Drawing is not to scale.

D

T1

A2

D1

LGA8 - 8 lead Land Grid Array, Package Mechanical Data

Symb.

Typ. Min. Max. Typ. Min. Max.

mm inches

CONTACT 1

T2

T3

E1

E2

k

E3

A

ddd

LGA-Z01B

16/19

A 1.040 0.940 1.140 0.0409 0.0370 0.0449
A1 0.340 0.300 0.380 0.0134 0.0118 0.0150
A2 0.700 0.640 0.760 0.0276 0.0252 0.0299

D 8.000 7.900 8.100 0.3150 0.3110 0.3189
D1 0.100 – – 0.0039 – –

E 5.000 4.900 5.100 0.1969 0.1929 0.2008
E1 1.270 – – 0.0500 – –
E2 3.810 – – 0.1500 – –
E3 0.390 – – 0.0154 – –

k 0.100 – – 0.0039 – –
T1 0.410 – – 0.0161 – –
T2 0.670 – – 0.0264 – –
T3 0.970 – – 0.0382 – –

ddd 0.100 – – 0.0039 – –

PART NUMBERING

Table 13. Ordering Information Scheme

Example: M24M01 –VLA6T

Device Type

2

M24 = I

Device Function

M01 = 1 Mbit (131,072 x 8)

Operating Voltage

V = V
S = V

Package

LA = LGA8 (Land Grid Array)

Temperature Range

6 = –40 to 85 °C

C serial access EEPROM

= 2.7 to 3.6V

CC

= 1.8 to 3.6V

CC

M24M01

Option

T = Tape & Reel Packing

For a list of available options (speed, package,
etc.) or for further information on any aspect of this

device, please contact your nearest ST Sales O f­fice.

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M24M01

REVISION HIST ORY

Table 14. Document Revision History

Date Rev. Description of Revision

02-Oct-2001 1.0

21-Jun-2002 1.1

08-Jan-2003 1.2 Added LGA maximum rating for soldering temperature

LGA8 Package mechanical data updated
Datasheet released as Product Preview

Table added on Power-up Timing
Full Datasheet released

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M24M01

Information furnished is believed to be ac curate and reliable. However, STMicroelec t ronics assu m es no responsib ility for the con sequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or oth erwise under any patent or patent rights of STMicroe l ectronics. Specifications mentioned in this publicati on are s ubject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems wi t hout expre ss wri t ten approval of STMicroelectronics.

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19/19