Page 1
Features
SO8 (MN)
150 mil width
TSSOP8 (DW)
WLCSP (CS)
■ Compatible with all I
– 1 MHz Fast-mode Plus
– 400 kHz Fast mode
– 100 kHz Standard mode
■ Memory array:
– 1 Mbit (128 Kbytes) of EEPROM
– Page size: 256 bytes
– Additional Write lockable page
(M24M01-D order codes)
■ Write
– Byte Write within 5 ms
– Page Write within 5 ms
■ Single supply voltage: 1.7 V to 5.5 V
■ Operating temperature range: from -40 °C up
to +85 °C
■ Random and sequential Read modes
■ Write protect of the whole memory array
■ Enhanced ESD/Latch-Up protection
■ More than 4 million Write cycles
■ More than 200-year data retention
■ Packages
– RoHS compliant and halogen-free
(ECOPACK
2
®
)
C bus modes:
M24M01-R M24M01-DF
1-Mbit serial I²C bus EEPROM
Datasheet − production data
April 2012 Doc ID 12943 Rev 9 1/41
This is information on a product in full production.
www.st.com
1
Page 2
Contents M24M01-R M24M01-DF
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Chip Enable (E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Write Control (WC
2.5 V
(ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SS
2.6 Supply voltage (V
2.6.1 Operating supply voltage V
2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.3 Write Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . 18
5.1.4 Lock Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . 18
5.1.5 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 19
5.1.6 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 20
5.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/41 Doc ID 12943 Rev 9
Page 3
M24M01-R M24M01-DF Contents
5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3 Read Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . . 22
5.4 Read the lock status (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4.1 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Doc ID 12943 Rev 9 3/41
Page 4
List of tables M24M01-R M24M01-DF
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. DC characteristics (voltage range R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13. DC characteristics (voltage range F, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 16. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 33
Table 17. SO8N – 8 lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 34
Table 18. WLCSP8 – Wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . 35
Table 19. WLCSP – Wafer level chip size package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4/41 Doc ID 12943 Rev 9
Page 5
M24M01-R M24M01-DF List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. WLCSP connections for die identified by process letter A (bump side view) . . . . . . . . . . . . 7
Figure 4. WLCSP connections for die identified by process letter K (bump side view) . . . . . . . . . . . . 8
Figure 5. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. I
Figure 8. Write mode sequences with WC
Figure 9. Write mode sequences with WC
Figure 10. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. Maximum R
Figure 14. Maximum R
Figure 15. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 34
Figure 18. Standard WLCSP8 – Wafer level chip scale package outline (for die
Figure 19. Thin WLCSP – Wafer level chip size package outline (for die identified
2
C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
= 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16
= 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 17
value versus bus parasitic capacitance (C
2
an I
C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2
an I
C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
bus
value versus bus parasitic capacitance C
bus
bus
bus
) for
) for
identified by process letter A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
by process letter K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 12943 Rev 9 5/41
Page 6
Description M24M01-R M24M01-DF
3$!
6
##
7#
3#,
6
33
%%
-XXX
.47
1 Description
The M24M01 is a 1 Mb I2C-compatible EEPROM (Electrically Erasable PROgrammable
Memory) organized as 128 K × 8 bits.
The M24M01-R can operate with a supply voltage from 1.8 V to 5.5 V, and the M24M01-DF
can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of
-40 °C / +85 °C.
The M24M01-D offers an additional page, named the Identification Page (256 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1. Logic diagram
Table 1. Signal names
Signal name Function Direction
E1, E2 Chip Enable Input
SDA Serial Data I/O
SCL Serial Clock Input
WC
V
CC
V
SS
6/41 Doc ID 12943 Rev 9
Write Control Input
Supply voltage
Ground
Page 7
M24M01-R M24M01-DF Description
-36
3$!6
33
3#,
7#%
$5 6
##
%
--
-36
6
##
6
33
7#
3#, 3$!
$5
% %
)NDEX
Figure 2. 8-pin package connections
1. DU: Don't Use (if connected, must be connected to VSS)
2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Figure 3. WLCSP connections for die identified by process letter A (bump side
view)
1. DU: Don't Use (if connected, must be connected to VSS)
2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Doc ID 12943 Rev 9 7/41
Page 8
Description M24M01-R M24M01-DF
MS30220V1
SDA
SCL
V
SS
E2E1
DU
V
CC
W
Figure 4. WLCSP connections for die identified by process letter K (bump side
view)
1. DU: Don't Use (if connected, must be connected to VSS)
2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form by STMicroelectronics must never be
exposed to UV light.
8/41 Doc ID 12943 Rev 9
Page 9
M24M01-R M24M01-DF Signal description
Ai12806
V
CC
M24xxx
V
SS
E
i
V
CC
M24xxx
V
SS
E
i
2 Signal description
2.1 Serial Clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to
output the data on SDA(out).
2.2 Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open
drain output that may be wire-OR’ed with other open drain or open collector signals on the
bus. A pull up resistor must be connected (Figure 13 indicates how to calculate the value of
the pull-up resistor).
2.3 Chip Enable (E1, E2)
These input signals are used to set the value that is to be looked for on the two bits (b3, b2)
of the 7-bit device select code. These inputs must be tied to V
device select code as shown in Figure 5. When not connected (left floating), these inputs
are read as low (0,0).
or VSS, to establish the
CC
Figure 5. Device select code
2.4 Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC
driven low or left floating.
When Write Control (WC
acknowledged, Data bytes are not acknowledged.
) is driven high. Write operations are enabled when Write Control (WC) is either
) is driven high, device select and address bytes are
Doc ID 12943 Rev 9 9/41
Page 10
Signal description M24M01-R M24M01-DF
2.5 VSS (ground)
VSS is the reference for the VCC supply voltage.
2.6 Supply voltage (VCC)
2.6.1 Operating supply voltage V
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V
(min), VCC(max)] range must be applied (see Operating conditions
CC
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the V
nF to 100 nF) close to the V
CC
CC/VSS
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (t
2.6.2 Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
(see Operating conditions in Section 8: DC and AC parameters) and the rise time must not
vary faster than 1 V/µs.
2.6.3 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until V
internal reset threshold voltage. This threshold is lower than the minimum V
voltage (see Operating conditions in Section 8: DC and AC parameters). When V
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until V
specified [V
parameters).
(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC
CC
CC
line with a suitable capacitor (usually of the order of 10
package pins.
).
W
has reached the
CC
reaches a valid and stable DC voltage within the
CC
operating
CC
CC
passes
In a similar way, during power-down (continuous decrease in V
accessed when V
drops below VCC(min). When VCC drops below the internal reset
CC
threshold voltage, the device stops responding to any instruction sent to it.
2.6.4 Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
10/41 Doc ID 12943 Rev 9
), the device must not be
CC
Page 11
M24M01-R M24M01-DF Memory organization
-36
7#
#ONTROLLOGIC
(IGHVOLTAGE
GENERATOR
)/SHIFTREGISTER
!DDRESSREGISTER
ANDCOUNTER
$ATA
REGISTER
PAGE
8DECODER
9DECODER
)DENTIFICATIONPAGE
%
%
3#,
3$!
3 Memory organization
The memory is organized as shown in Figure 6.
Figure 6. Block diagram
Doc ID 12943 Rev 9 11/41
Page 12
Device operation M24M01-R M24M01-DF
SCL
SDA
SCL
SDA
SDA
START
Condition
SDA
Input
SDA
Change
AI00792B
STOP
Condition
1 23 7 89
MSB
ACK
START
Condition
SCL
1 23 7 89
MSB ACK
STOP
Condition
4 Device operation
The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
Figure 7. I
2
C bus protocol
12/41 Doc ID 12943 Rev 9
Page 13
M24M01-R M24M01-DF Device operation
4.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
4.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9
th
clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
4.5 Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Ta ble 7 (on Serial Data (SDA), most significant bit first).
Table 2. Device select code
Device type identifier
When accessing
the memory
When accessing
the Identification
page
1. The most significant bit, b7, is sent first.
2. E2,E1 are compared against the external pin on the memory device.
b7 b6 b5 b4 b3 b2 b1 b0
1010 E2 E1A16RW
1011 E2 E1A16RW
(1)
Chip Enable
address
(2)
Address bits RW
Doc ID 12943 Rev 9 13/41
Page 14
Device operation M24M01-R M24M01-DF
When the device select code is received, the device only responds if the Chip Enable
address is the same as the value on its Chip Enable E2,E1 inputs.
th
The 8
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9
th
bit time. If the device does not match
the device select code, the device deselects itself from the bus, and goes into Standby
mode.
14/41 Doc ID 12943 Rev 9
Page 15
M24M01-R M24M01-DF Instructions
5 Instructions
5.1 Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Table 3. Most significant address byte
A15 A14 A13 A12 A11 A10 A9 A8
Table 4. Least significant address byte
A7 A6 A5 A4 A3 A2 A1 A0
The 128 Kbytes (1 Mb) are addressed with 17 address bits, the 16 lower address bits being
defined by the two address bytes and the most significant address bit (A16) being included
in the Device Select code (see Tabl e 2 ).
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10
cycle t
th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
is triggered. A Stop condition at any other time slot does not trigger the internal
W
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (t
), the
W
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 9.
Doc ID 12943 Rev 9 15/41
Page 16
Instructions M24M01-R M24M01-DF
Stop
Start
Byte Write Dev sel Byte addr
Byte addr Data in
WC
Start
Page Write Dev sel Byte addr Byte addr Data in 1
WC
Data in 2
AI01106d
Page Write (cont'd)
WC (cont'd)
Stop
Data in N
ACK
R/W
ACK ACK ACK
ACK ACK ACK ACK
R/W
ACKACK
5.1.1 Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 8.
) being driven high, the
Figure 8. Write mode sequences with WC
= 0 (data write enabled)
16/41 Doc ID 12943 Rev 9
Page 17
M24M01-R M24M01-DF Instructions
Stop
Start
Byte Write Dev sel Byte addr Byte addr Data in
WC
Start
Page Write Dev sel Byte addr Byte addr Data in 1
WC
Data in 2
AI01120d
Page Write (cont'd)
WC (cont'd)
Stop
Data in N
ACK ACK ACK NO ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK NO ACK
5.1.2 Page Write
The Page Write mode allows up to 256 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, b16-b8, are the same. If more bytes are sent than will fit up to the end
of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the
page are overwritten.
The bus master sends from 1 to 256 bytes of data, each of which is acknowledged by the
device if Write Control (WC
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in Figure 9. After each transferred byte, the internal page address counter is
incremented.
The transfer is terminated by the bus master generating a Stop condition.
) is low. If Write Control (WC) is high, the contents of the
Figure 9. Write mode sequences with WC
= 1 (data write inhibited)
Doc ID 12943 Rev 9 17/41
Page 18
Instructions M24M01-R M24M01-DF
5.1.3 Write Identification Page (M24M01-D only)
The Identification Page (256 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences:
● Device type identifier = 1011b
● MSB address bits A16/A8 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A7/A0 define the byte address inside the Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
5.1.4 Lock Identification Page (M24M01-D only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
● Device type identifier = 1011b
● Address bit A10 must be ‘1’; all other address bits are don't care
● The data byte must be equal to the binary value xxxx xx1x, where x is don't care
18/41 Doc ID 12943 Rev 9
Page 19
M24M01-R M24M01-DF Instructions
5.1.5 ECC (Error Correction Code) and Write cycling
The Error Correction Code (ECC) is an internal logic function which is transparent for the
2
I
C communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group
(a)
. As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Table 9: Cycling performance by groups of four bytes.
(a)
. Inside a group, if a
a. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an
integer.
Doc ID 12943 Rev 9 19/41
Page 20
Instructions M24M01-R M24M01-DF
Write cycle
in progress
AI
d
AI01847e
Next
Operation is
addressing the
memory
Start condition
Device select
with RW = 0
ACK
returned
YES
NO
YESNO
ReStart
Stop
Data for the
Write cperation
Device select
with RW = 1
Send Address
and Receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YESNO
StartCondition
Continue the
Write operation
Continue the
Random Read operation
5.1.6 Minimizing Write delays by polling on ACK
The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC
parameters, but the typical time is shorter. To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 10, is:
● Initial condition: a Write cycle is in progress.
● Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
● Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 10. Write cycle polling flowchart using ACK
20/41 Doc ID 12943 Rev 9
1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the
figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling
instruction in the figure).
01847
Page 21
M24M01-R M24M01-DF Instructions
Start
Dev sel * Byte addr Byte addr
Start
Dev sel Data out 1
AI01105d
Data out N
Stop
Start
Current
Address
Read
Dev sel Data out
Random
Address
Read
Stop
Start
Dev sel * Data out
Sequential
Current
Read
Stop
Data out N
Start
Dev sel * Byte addr Byte addr
Sequention
Random
Read
Start
Dev sel * Data out1
Stop
ACK
R/W
NO ACK
ACK
R/W
ACK ACK ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK
ACK ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK
5.2 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
Figure 11. Read mode sequences
5.2.1 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 11) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
Doc ID 12943 Rev 9 21/41
bit set to 1. The device
Page 22
Instructions M24M01-R M24M01-DF
5.2.2 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 11, without acknowledging the byte.
bit set to 1. The device acknowledges this, and
5.2.3 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 11.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
5.3 Read Identification Page (M24M01-D only)
The Identification Page (256 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A16/A8 are don't
care, the LSB address bits A7/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary (e.g.: when
reading the Identification Page from location 100d, the number of bytes should be less than
or equal to 156, as the ID page boundary is 256 bytes).
5.4 Read the lock status (M24M01-D only)
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit if the Identification page is unlocked,
otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
● Start: the truncated command is not executed because the Start condition resets the
device internal logic,
● Stop: the device is then set back into Standby mode by the Stop condition.
5.4.1 Acknowledge in Read mode
For all Read instructions, the device waits, after each byte read, for an acknowledgment
during the 9
time, the device terminates the data transfer and switches to its Standby mode.
22/41 Doc ID 12943 Rev 9
th
bit time. If the bus master does not drive Serial Data (SDA) low during this
Page 23
M24M01-R M24M01-DF Initial delivery state
6 Initial delivery state
The device is delivered with all bits set to 1 (both in the memory array and in the
Identification page - that is, each byte contains FFh).
Doc ID 12943 Rev 9 23/41
Page 24
Maximum rating M24M01-R M24M01-DF
7 Maximum rating
Stressing the device outside the ratings listed in Ta bl e 5 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 5. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
Ambient operating temperature –40 130 °C
T
STG
T
LEAD
V
IO
I
OL
V
CC
V
ESD
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with JEDEC Std
JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).
3. 3000 V for previous devices (process letter A or B).
Storage temperature –65 150 °C
Lead temperature during soldering see note
(1)
°C
Input or output range –0.50 VCC+0.6 V
DC output current (SDA = 0) - 5 mA
Supply voltage –0.50 6.5 V
Electrostatic pulse (Human Body model)
(2)
- 4000
(3)
V
24/41 Doc ID 12943 Rev 9
Page 25
M24M01-R M24M01-DF DC and AC parameters
-36
6
##
6
##
6
##
6
##
)NPUTANDOUTPUT
4IMINGREFERENCELEVELS
)NPUTVOLTAGELEVELS
8 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 6. Operating conditions (voltage range R)
Symbol Parameter Min. Max. Unit
V
CC
T
f
C
Table 7. Operating conditions (voltage range F)
Supply voltage 1.8 5.5 V
Ambient operating temperature –40 85 °C
A
Operating clock frequency - 1 MHz
Symbol Parameter Min. Max. Unit
V
CC
T
f
C
Table 8. AC measurement conditions
Supply voltage 1.7 5.5 V
Ambient operating temperature –40 85 °C
A
Operating clock frequency - 1 MHz
Symbol Parameter Min. Max. Unit
C
bus
Load capacitance 100 pF
SCL input rise/fall time, SDA input fall time 50 ns
Input levels 0.2 V
Input and output timing reference levels 0.3 V
to 0.8 V
CC
to 0.7 V
CC
CC
CC
Figure 12. AC measurement I/O waveform
V
V
Doc ID 12943 Rev 9 25/41
Page 26
DC and AC parameters M24M01-R M24M01-DF
Table 9. Cycling performance by groups of four bytes
Symbol Parameter Test condition
(1)
Max. Unit
Ncycle
1. Cycling performance for products identified by process letter K.
2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1,
4*N+2, 4*N+3] where N is an integer. The Write cycle endurance is defined by characterization and
qualification.
3. A Write cycle is executed when either a Page Write, a Byte Write, a Write Identification Page or a Lock
Identification Page instruction is decoded. When using the Byte Write, the Page Write or the Write
Identification Page, refer also to Section 5.1.5: ECC (Error Correction Code) and Write cycling.
Table 10. Memory cell data retention
Write cycle
endurance
(2)
TA ≤ 25 °C, 1.8 V < VCC < 5.5 V 4,000,000
TA = 85 °C, 1.8 V < VCC < 5.5 V 1,200,000
Write
cycle
Parameter Test condition Min. Unit
Data retention
1. For products identified by process letter K. The data retention is not tested in production but defined from
characterization and qualification results.
Table 11. Input parameters
Symbol Parameter
C
IN
C
IN
Z
L
Z
H
1. Sampled only, not 100% tested.
(1)
(1)
TA = 55 °C 200 Year
Test condition Min. Max. Unit
Input capacitance (SDA) 8 pF
Input capacitance (other pins) 6 pF
Input impedance (WC)
< 0.3 V
V
IN
VIN > 0.7 V
CC
CC
30 kΩ
400 kΩ
(3)
26/41 Doc ID 12943 Rev 9
Page 27
M24M01-R M24M01-DF DC and AC parameters
.
Table 12. DC characteristics (voltage range R, device grade 6)
Symbol Parameter
Input leakage current
I
LI
(E1, E2, SCL, SDA)
I
Output leakage current
LO
I
Supply current (Read)
CC
I
Supply current (Write) During t
CC0
Test conditions (in addition to
those in Tabl e 6)
= VSS or V
V
IN
CC
device in Standby mode
SDA in Hi-Z, external voltage
applied on SDA: V
V
= 1.8 V, fc= 400 kHz 1
CC
V
= 2.5 V, fc =400 kHz 1 mA
CC
V
= 5.5 V, fc =400 kHz 1.5
CC
= 1 MHz 1.5
f
c
W
SS
or V
CC
Device not selected,
= VSS or VCC, VCC = 1.8 V
V
IN
I
CC1
Standby supply current
Device not selected,
V
= VSS or VCC, VCC = 2.5 V
IN
Device not selected,
V
= VSS or VCC, VCC = 5.5 V
IN
Input low voltage
V
IL
(SCL, SDA, WC)
Input high voltage
V
IH
(SCL, SDA)
V
1. Devices identified by process letter A or B offer ICC = 0.8 mA
2. The previous product identified by process letter A or B was specified with I
3. Devices identified by process letter A or B offer ICC = 2.5 mA.
4. Characterized only, not tested in production.
5. The previous product identified by process letter A or B was characterized with I
6. Devices identified by process letter A or B offer I
7. Devices identified by process letter A or B offer I
8. Devices identified by process letter A or B offer I
Output low voltage
OL
1.8 V ≤ V
2.5 V ≤ V
1.8 V ≤ V
2.5 V ≤ V
I
= 1.0 mA, VCC = 1.8 V 0.2 V
OL
= 2.1 mA, VCC = 2.5 V 0.4 V
I
OL
= 3.0 mA, VCC = 5.5 V 0.4 V
I
OL
< 2.5 V –0.45 0.25 V
CC
< 5.5 V –0.45 0.30 V
CC
< 2.5 V 0.75 V
CC
< 5.5 V 0.70 VCC0 VCC+1 v
CC
cc(max)
= 1 µA.
CC1
= 2 µA.
CC1
= 3 µA.
CC1
Min. Max. Unit
± 2 µA
± 2 µA
CCVCC
= 2 mA.
cc0(max)
(4)(5)
2
3
3
5
= 5 mA.
(1)
(6)
(7)
(8)
(2)
(3)
CC
CC
+1 v
mA
mA
mA
mA
µA
µA
µA
V
V
Doc ID 12943 Rev 9 27/41
Page 28
DC and AC parameters M24M01-R M24M01-DF
Table 13. DC characteristics (voltage range F, device grade 6)
Symbol Parameter
Input leakage current
I
LI
(E1, E2, SCL, SDA)
I
Output leakage current
LO
I
Supply current (Read)
CC
I
Supply current (Write) During t
CC0
Test conditions (in addition to
V
IN
device in Standby mode
SDA in Hi-Z, external voltage
applied on SDA: V
V
CC
V
CC
V
CC
= 1 MHz 1.5 mA
f
c
Device not selected,
V
IN
I
CC1
Standby supply current
Device not selected,
V
IN
Device not selected,
V
IN
Input low voltage
V
IL
(SCL, SDA, WC)
Input high voltage
V
IH
(SCL, SDA)
V
1. Characterized only, not tested in production.
Output low voltage
OL
1.7 V ≤ V
2.5 V ≤ V
1.7 V ≤ V
2.5 V ≤ V
= 1.0 mA, VCC = 1.7 V 0.2 V
I
OL
I
= 2.1 mA, VCC = 2.5 V 0.4 V
OL
= 3.0 mA, VCC = 5.5 V 0.4 V
I
OL
those in Tabl e 6)
= VSS or V
CC
SS
or V
CC
Min. Max. Unit
± 2 µA
± 2 µA
= 1.7 V, fc= 400 kHz 1 mA
= 2.5 V, fc =400 kHz 1 mA
= 5.5 V, fc =400 kHz 1.5 mA
(1)
W
= VSS or VCC, VCC = 1.7 V
= VSS or VCC, VCC = 2.5 V
= VSS or VCC, VCC = 5.5 V
< 2.5 V –0.45 0.25 V
CC
< 5.5 V –0.45 0.30 V
CC
< 2.5 V 0.75 V
CC
< 5.5 V 0.70 VCC0 VCC+1 v
CC
2
3µA
3µA
5µA
CCVCC
mA
CC
CC
+1 v
V
V
28/41 Doc ID 12943 Rev 9
Page 29
M24M01-R M24M01-DF DC and AC parameters
Table 14. 400 kHz AC characteristics
Symbol Alt. Parameter Min. Max. Unit
t
CHCL
t
CLCH
t
QL1QL2
t
XH1XH2
t
XL1XL2
t
DXCH
t
CLDX
t
CLQX
t
CLQV
t
CHDL
t
DLCL
t
CHDH
t
DHDL
t
WLDL
t
DHWH
t
NS
f
t
W
C
(7)(2)
(8)(2)
(2)
(4)
(6)
(1)
f
SCL
t
HIGH
t
LOW
t
F
t
R
t
F
t
SU:DAT
t
HD:DAT
t
DH
t
AA
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
SU:WC
t
HD:WC
t
WR
Clock frequency - 400 kHz
Clock pulse width high 600 - ns
Clock pulse width low 1300 - ns
SDA (out) fall time 20
Input signal rise time
Input signal fall time
(2)
(3)
(3) (3)
300 ns
(3)
ns
ns
Data in set up time 100 - ns
Data in hold time 0 - ns
Data out hold time 100
(5)
-ns
Clock low to next data valid (access time) - 900 ns
Start condition setup time 600 - ns
Start condition hold time 600 - ns
Stop condition set up time 600 - ns
Time between Stop condition and next Start
condition
1300 - ns
WC set up time (before the Start condition) 0 - µs
WC hold time (after the Stop condition) 1 - µs
Internal Write cycle duration - 5 ms
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-80
(9)
ns
1. Characterized only, not tested in production.
2. With CL = 10 pF.
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
< 400 kHz.
C
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. The previous product identified by process letter A was specified with t
6. t
7. WC=0 set up time condition to enable the execution of a WRITE command.
8. WC=0 hold time condition to enable the execution of a WRITE command.
9. The previous product identified by process letter A or B was specified with tNS = 100 ns (max).
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
CLQV
0.7V
, assuming that R
CC
bus
× C
time constant is within the values specified in Figure 13.
bus
= 200 ns (min).
CLQX
Doc ID 12943 Rev 9 29/41
Page 30
DC and AC parameters M24M01-R M24M01-DF
Table 15. 1 MHz AC characteristics
Symbol Alt. Parameter Min. Max. Unit
t
CHCL
t
CLCH
t
XH1XH2
t
XL1XL2
t
QL1QL2
t
DXCX
t
CLDX
t
CLQX
t
CLQV
t
CHDL
t
t
CHDH
t
DHDL
t
WLDL
t
DHWH
t
f
C
DLCL
(4)(8)
(5)(8)
t
W
(6)
NS
(2)
(3)
(8)
f
SCL
t
HIGH
t
LOW
t
R
t
F
t
F
t
SU:DAT
t
HD:DAT
t
DH
t
AA
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
SU:WC
t
HD:WC
t
WR
Clock frequency 0 1 MHz
Clock pulse width high 300 - ns
Clock pulse width low 400 - ns
Input signal rise time
Input signal fall time
(1)
(1) (1)
(1)
ns
ns
SDA (out) fall time - 120 ns
Data in setup time 80 - ns
Data in hold time 0 - ns
Data out hold time 50 - ns
Clock low to next data valid (access time) - 500 ns
Start condition setup time 250 - ns
Start condition hold time 250 - ns
Stop condition setup time 250 - ns
Time between Stop condition and next Start
condition
500 - ns
WC set up time (before the Start condition) 0 - µs
WC hold time (after the Stop condition) 1 - µs
Write time - 5 ms
Pulse width ignored (input filter on SCL and
SDA)
-80
(7)
ns
1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when
fC<1MHz.
2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
3. t
4. WC=0 set up time condition to enable the execution of a WRITE command.
5. WC=0 hold time condition to enable the execution of a WRITE command.
6. Characterized only, not tested in production.
7. The previous product identified by process letter A or B was specified with tNS = 50 ns (max).
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
CLQV
0.7 V
, assuming that the Rbus × Cbus time constant is within the values specified in Figure 14.
CC
30/41 Doc ID 12943 Rev 9
Page 31
M24M01-R M24M01-DF DC and AC parameters
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Figure 13. Maximum R
2
an I
C bus at maximum frequency fC = 400 kHz
Figure 14. Maximum R
2
an I
C bus at maximum frequency fC = 1MHz
value versus bus parasitic capacitance (C
bus
value versus bus parasitic capacitance C
bus
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Doc ID 12943 Rev 9 31/41
Page 32
DC and AC parameters M24M01-R M24M01-DF
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T$,#,
T#,#(
T8(8(
T8,8,
T8,8,
7#
T7,$,
T$(7(
Figure 15. AC waveforms
32/41 Doc ID 12943 Rev 9
Page 33
M24M01-R M24M01-DF Package mechanical data
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 16. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters inches
Symbol
Typ. Min. Max. Typ. Min. Max.
(1)
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α 0° 8° 0° 8°
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 12943 Rev 9 33/41
Page 34
Package mechanical data M24M01-R M24M01-DF
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
Figure 17. SO8N – 8 lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scale.
Table 17. SO8N – 8 lead plastic small outline, 150 mils body width, package data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 1.750 0.0689
A1 0.100 0.250 0.0039 0.0098
A2 1.250 0.0492
b 0.280 0.480 0.0110 0.0189
c 0.170 0.230 0.0067 0.0091
ccc 0.100 0.0039
D 4.900 4.800 5.000 0.1929 0.1890 0.1969
E 6.000 5.800 6.200 0.2362 0.2283 0.2441
E1 3.900 3.800 4.000 0.1535 0.1496 0.1575
e 1.270 0.0500
h 0.250 0.500 0.0098 0.0197
k 0°8° 0°8°
L 0.400 1.270 0.0157 0.0500
L1 1.040 0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
(1)
34/41 Doc ID 12943 Rev 9
Page 35
M24M01-R M24M01-DF Package mechanical data
Orientation reference
Wafer back side Side view Bump side
Orientation
reference
Detail A
Bump
Seating plane
(3)
Detail A rotated by 90°
D
E
A2
A
F
e1
e2
e
e2
G
A1
b(8X)
(2)
Note 4
(4X)
eee Z
Z
aaa
E1_ME_b
Figure 18. Standard WLCSP8 – Wafer level chip scale package outline (for die
identified by process letter A)
1 Drawing is not to scale and corresponds to preliminary data.
2 The dimension is measured at the maximum bump diameter parallel to primary datum Z.
3 The primary datum Z and seating plane are defined by the spherical crowns of the bump.
4 Bump position designation per JESD 95-1, SPP-010.
Table 18. WLCSP8 – Wafer level chip scale package mechanical data
millimeters inches
Symbol
Typ Min Max Typ Min Max
(1)
(2)
A 0.580 0.555 0.605 0.0228 0.0219 0.0238
A1 0.230 0.0091
A2 0.350 0.0138
b 0.322 0.0127
D 3.570 3.685 0.1406 0.1451
E 2.050 2.165 0.0807 0.0852
e 0.600 0.0236
e1 2.400 0.0945
e2 1.200 0.0472
F 0.585 0.0230
G 0.424 0.0167
aaa 0.110 0.0043
bbb 0.110 0.0043
ccc 0.110 0.0043
ddd 0.060 0.0024
eee 0.060 0.0024
N (number of bumps) 8
1. Preliminary data.
2. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 12943 Rev 9 35/41
Page 36
Package mechanical data M24M01-R M24M01-DF
$ETAIL
ROTATED
!
"UMP
$ETAIL!
!
!
%
$
7AFERBACKSIDE
"UMPSIDE
-36
E
E
6$$BALLMARKING
E
E
E
Figure 19. Thin WLCSP – Wafer level chip size package outline (for die identified
by process letter K)
Table 19. WLCSP – Wafer level chip size package mechanical data
millimeters inches
Symbol
Typ. Min. Max. Typ. Min. Max.
A 0.300 0.280 0.320 0.0118 0.0110 0.0126
A1 0.100 0.0039
A2 0.200 0.0079
b 0.126 0.0050
D 2.560 0.1008
E 1.698 1.823 0.0669 0.0676
e 1.000 0.0394
e1 1.200 0.0472
e2 1.100 0.0433
e3 0.500 0.0197
1. Values in inches are converted from mm and rounded to four decimal digits.
(1)
36/41 Doc ID 12943 Rev 9
Page 37
M24M01-R M24M01-DF Part numbering
10 Part numbering
Table 20. Ordering information scheme
Example: M24M01-D R MN 6 T P /K
Device type
2
M24 = I
C serial access EEPROM
Device function
M01 = 1 Mbit (128 Kb × 8 bits)
Device family
Blank: Without Identification page
-D: With additional Identification page
Operating voltage
R = V
= 1.8 V to 5.5 V
CC
F = VCC = 1.7 V to 5.5 V
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
(1)
(1)
CS = standard WLCSP
CT = thin WLCSP
Device grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
Option
blank = standard packing
T = Tape and reel packing
Plating technology
®
P = ECOPACK
Process
(2)
(RoHS compliant)
/A, /B or /K= Manufacturing technology code
1. RoHS-compliant and halogen-free (ECOPACK2®)
2. The process letter applies to WLCSP devices only.
For a list of available options (speed, package, etc.) or for further information on any aspect
of the devices, please contact your nearest ST sales office.
Doc ID 12943 Rev 9 37/41
Page 38
Revision history M24M01-R M24M01-DF
11 Revision history
Table 21. Document revision history
Date Revision Changes
07-Dec-2006 1 Initial release.
Document status promoted from Preliminary Data to full Datasheet.
Section 2.6: Supply voltage (VCC) updated.
Note 1 updated to latest standard revision below Table 5: Absolute
maximum ratings.
02-Oct-2007 2
26-Nov-2007 3
18-Mar-2008 4
, VIH modified and, rise/fall time corrected in Test conditions in
V
IL
Table 11: DC characteristics (M24M01-R and M24M01-HR).
Package values in inches calculated from mm and rounded to 4
decimal digits (note added below package mechanical data tables in
Section 7: Package mechanical data.
1 MHz maximum clock frequency added:
– Figure 6: Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 1MHz
– Table 14: AC characteristics at 1 MHz (M24M01-HR) added.
moved from Table 8: Input parameters to Table 13: AC
t
NS
characteristics at 400 kHz (M24M01-R and M24M01-W). Note
removed below Ta bl e 8 . In Ta bl e 1 3 , t
removed, t
XH1XH2
, t
XL1XL2
added, t
DL1DL2
, t
CH1CH2
CL1CL2
max modified, notes
and t
DL1DL2
modified.
Figure 5: Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 400 kHz modified.
Figure 13: AC waveforms modified. Small text changes.
M24M01-HR root part number added. Small text changes.
Figure 6: Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 1MHz modified.
Most significant address bits modified in Section 3.8: Page Write on
page 15.
Test conditions modified for I
, ICC and VOL in Table 11: DC
LI
characteristics (M24M01-R and M24M01-HR).
TW and TNS values corrected in Table 13: AC characteristics at
400 kHz (M24M01-R and M24M01-W).
Cross-reference corrected in Note 5 below Table 14: AC
characteristics at 1 MHz (M24M01-HR).
38/41 Doc ID 12943 Rev 9
Page 39
M24M01-R M24M01-DF Revision history
Table 21. Document revision history (continued)
Date Revision Changes
Added: M24M01-W part number in device grade 3 temperature range
(see Table 8: Operating conditions (M24M01-W), Table 12: DC
characteristics (M24M01-W) and Table 17: Ordering information
scheme (M24M01-x products sold in packages)).
M24M01-R offered as a bare die (see Section 8: Part numbering and
Table 18: Ordering information scheme (M24M01-R sold as bare
dice)).
In Table 13: AC characteristics at 400 kHz (M24M01-R and M24M01-
02-Sep-2008 5
12-Mar-2009 6
26-Jun-2009 7
W), Note 1 modified, Note 2 added, t
XH1XH2
, t
values modified.
In Table 14: AC characteristics at 1 MHz (M24M01-HR), Note 1
modified, Note 3 added, t
t
CHDX
, t
DL1DL2
and t
DXCX
, t
XH1XH2
changed to t
XL1XL2
CHDL
and t
, t
respectively (see Ta bl e 1 3 , Tab l e 14 and Figure 13).
Table 19: Available M24M01-x products (package, voltage range,
frequency, temperature grade) added.
Small text changes.
WLCSP8 package added (see Figure 3: WLCSP8 connections
(bumps side view) and Section 7: Package mechanical data).
Section 2.6: Supply voltage (VCC) updated.
added to Table 5: Absolute maximum ratings.
I
OL
added to Table 11: DC characteristics (M24M01-R and
V
RES
M24M01-HR) and Table 12: DC characteristics (M24M01-W).
ECOPACK text updated.
Section : Features updated.
NC pin changed to DU in Figure 2: SO connections.
Device select code Chip enable address bits updated in Section 2.3.
Internal reset threshold modified in Section 2.6.3: Device reset.
Figure 6: Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 1MHz updated.
removed, and I
V
RES
conditions modified in Table 11: DC
CC1
characteristics (M24M01-R and M24M01-HR), and Table 12: DC
characteristics (M24M01-W). V
removed from Table 12: DC
RES
characteristics (M24M01-W).
t
R and M24M01-W). t
updated in Table 13: AC characteristics at 400 kHz (M24M01-
XH1XH2
updated, and Note 5 updated in Ta b l e 1 4:
XH1XH2
AC characteristics at 1 MHz (M24M01-HR).
Command replaced by instruction in the whole document.
XL1XL2
DL1DL2
QL1QL2
and t
DL1DL2
values modified.
and t
DXCH
,
Doc ID 12943 Rev 9 39/41
Page 40
Revision history M24M01-R M24M01-DF
Table 21. Document revision history (continued)
Date Revision Changes
Updated Features on page 1.
Updated Figure 3: WLCSP8 connections (bumps side view), Figure 5:
Maximum Rbus value versus bus parasitic capacitance (Cbus) for an
I2C bus at maximum frequency fC = 400 kHz and Figure 6: Maximum
Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at
maximum frequency fC = 1MHz.
02-May-2011 8
23-Apr-2012 9
Updated Table 10: DC characteristics (M24M01-R and M24M01-HR).
Updated footnote 5 of Table 14: AC characteristics at 1 MHz
(M24M01-HR).
Modified description of Write Control in Section 3.6: Write operations.
Replaced C
with C
L
Changed note 4 about t
in Table 7: AC measurement conditions.
bus
in Table 13: AC characteristics at
CLQV
400 kHz (M24M01-R and M24M01-W).
Datasheet split into:
– M24M01-R, M24M01-DF (this datasheet) for standard products
(range 6),
– M24M01-125 datasheet for automotive products (range 3).
40/41 Doc ID 12943 Rev 9
Page 41
M24M01-R M24M01-DF
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