Page 1
M24C64
M24C32
64Kbit and 32Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
M24C64
M24C32
2
C Serial Interface
M24C64
M24C64-W
M24C64-R
M24C32
M24C32-W
M24C32-R
■ Two-Wire I
Supports 400kHz Protocol
■ Single Supply Voltage:
– 4.5 to 5.5V for M24Cxx
– 2.5 to 5.5V for M24Cxx-W
– 1.8 to 5.5V for M24Cxx-R
■ Write Control Input
■ BYTE and PAGE WRITE (up to 32 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Timed Programming Cycle
■ Automatic Address Incr em ent ing
■ Enhanced ESD/Latch-Up Protection
■ More than 1 Million Erase/Write Cycles
■ More than 40-Year Data Retention
Table 1. Product List
Reference Part Number
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8 (MB)
2x3mm² (MLP)
1/26January 2005
Page 2
M24C64, M24C32
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP, SO, TSSOP and UFDFPN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Control (WC
Figure 4. Maximum R
Figure 5. I
2
Table 3. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Least Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Value versus Bus Capacitance (C
L
) for an I2C Bus . . . . . . . . . . . . . . . . 5
BUS
C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Write Mode Sequences with WC
=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Write Mode Sequences with WC
=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10.Read Mode Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/26
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M24C64, M24C32
Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Operating Conditions (M24Cxx-6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Operating Conditions (M24Cxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. Operating Conditions (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 13. DC Characteristics (M24Cxx
Table 14. DC Characteristics (M24Cxx-W6 and M24Cxx-W3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 15. DC Characteristics (M24Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 16. AC Characteristics (M24Cxx-6, M24Cxx-W6 and M24Cxx-W3) . . . . . . . . . . . . . . . . . . . 18
Table 17. AC Characteristics (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
(1)
, M24Cxx-W6 and M24Cxx-W3). . . . . . . . . . . . . . . . . . . 16
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 20
Table 18. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 20
Figure 14.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 21
Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 22
Table 20. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 22
Figure 16.UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm. . . 23
Table 21. UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 23. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
Page 4
M24C64, M24C32
SUMMARY DESCRIPTION
These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192 x 8 bits (M24C64) and 4096 x 8 bits
(M24C32).
Table 2. Signal Names
E0, E1, E2 Chip Enable
SDA Serial Data
Figure 2. Logic Diagram
V
CC
3
E0-E2 SDA
SCL
WC
2
I
C uses a two-wire serial interf ace, comprisi ng a
M24C64
M24C32
V
SS
AI01844B
bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
The device behaves as a slave in the I
2
C bus definition.
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device
Select Code and Read/Write
bit (RW) (as described in Table 3.), terminated by an acknowledge bit.
When writing data to the memory , the device inserts an acknowled ge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledge s the rec eipt o f the d ata by te
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
SCL Serial Clock
WC
V
CC
V
SS
Power On Reset: V
Write Control
Supply Voltage
Ground
Lock-Out Write Protect
CC
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included . At Power-up, the
internal reset i s he ld a cti ve unti l V
has reached
CC
the Power On Reset (POR) threshold voltage, and
all operations are disabled – the device will not respond to any command. In the sam e way, when
V
drops from the operat ing voltage, below the
CC
Power On Reset (PO R) threshold voltage, a ll operations are disabl ed and the device will not respond to any command.
A stable and valid V
(as defined in Table 9. and
CC
Table 10.) must be applied before applying any
logic signal.
Figure 3. DI P, SO, TSSOP and UFDFPN Connections
M24C64
M24C32
E0 V
1
2
E2
3
4
SS
Note: See PACKA GE MECHANICAL section for package dimen-
sions, and how to identify pin-1.
8
7
6
5
AI01845C
CC
WCE1
SCL
SDAV
4/26
Page 5
SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to
strobe all data in and out of the device. In applications where this signal is used by slave devices to
synchronize the bus to a slower clock, the bus
master must have an open drain output, and a
pull-up resistor must be connected from Serial
Clock (SCL) to V
value of the pull- up resi stor can be calc ulate d). In
most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, pro vided that the bus master
has a push-pull (rather than open drain) output.
Serial Data (SDA). This bi-directional signal is
used to transfer data in or out of the device. It is an
open drain output that may be wire-OR’ed with
other open drain or ope n collector signals on the
bus. A pull up resistor must be connected from Se-
. (Figure 4. indicates how the
CC
M24C64, M24C32
rial Data (SDA) to V
the value of the pull-up resistor can be calculated).
Chip Enable (E0, E1, E2). These input signals
are used to set the value that is to be looked for on
the three least significant bits (b3, b2, b1) of the 7bit Device Select Code. These inputs must be tied
to V
or VSS, to establish the Device Select
CC
Code.
Write Control (WC
for protecting the entire content s of the memory
from inadvertent write operations. Write operations are disabled to the entire memory array when
Write Control (WC
nected, the signal is internally read as V
Write operations are allowed.
When Write Contr ol (WC
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
. (Figure 4. indicates how
CC
). This input signal is useful
) is driven High. When uncon-
, and
IL
) is driven High, Device
Figure 4. Maximum R
20
16
12
8
Maximum RP value (kΩ)
4
0
10
Value versus Bus Capacitance (C
L
fc = 100kHz
fc = 400kHz
100
C
(pF)
BUS
) for an I2C Bus
BUS
MASTER
1000
V
CC
R
SDA
SCL
R
L
C
BUS
L
C
BUS
AI01665
5/26
Page 6
M24C64, M24C32
Figure 5. I2C Bus Protocol
SCL
SDA
SCL
SDA
SCL
SDA
START
Condition
START
Condition
1 23 7 89
MSB
1 23 7 89
MSB
SDA
Input
SDA
Change
STOP
Condition
ACK
ACK
STOP
Condition
AI00792B
Table 3. Device Select Code
Device Type Identifier
1
Chip Enable Address
b7 b6 b5 b4 b3 b2 b1 b0
Device Select Code1010E2E1E0RW
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective exte rnal pins on the memory device.
2
RW
Table 4. Most Significant Byte Table 5. Least Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
6/26
Page 7
MEMORY ORGANIZATION
The memory is organized as shown in Figure 6..
Figure 6. Block Diagram
WC
E0
E1
E2
SCL
Control Logic
M24C64, M24C32
High Voltage
Generator
SDA
Address Register
and Counter
I/O Shift Register
Data
Register
Y Decoder
1 Page
X Decoder
AI06899
7/26
Page 8
M24C64, M24C32
DEVICE OPERATION
The device supports the I2C protocol. This is summarized in Figure 5.. Any device that sends d ata
on to the bus is defined to be a transmitter, and
any device that reads the data to be a rec eiver.
The device that controls the data transfer is known
as the bus master, an d th e other a s the s lave device. A data transfer can only be initiated by the
bus master, which will also provide the serial clock
for synchr oniz atio n. Th e M24C xx de vice is alwa ys
a slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command . The device continuou sly
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Cloc k (S CL) is s tab le a nd d ri ven High. A Stop condition t ermi nate s co mm uni ca tion between the device and the bus master. A
Read command that is follow ed by NoA ck can be
followed by a Sto p condition to force the device
into the Stand-by mode. A S top condition at the
end of a Write command triggers the internal Write
cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be
bus master or sl ave device, releas es Serial Data
(SDA) after sending ei ght bits of da ta. During the
th
9
clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change
only
when Serial Cl ock ( SCL ) i s dr iv-
en Low.
Memory Addressing
To start communica tion between the bus master
and the slave device, the b us mas ter m u st ini ti ate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 3.
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4bit Device Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I
2
C bus. Each one is gi ven a un ique 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received, the device only respond s if the Chip Enabl e Address is
the same as the value on the Chip Enable (E0, E1,
E2) inputs.
th
The 8
bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) du ring the 9
th
bit time. If the
device does not match the Devic e Select code, it
deselects itself from the bus, and goes into Standby mode.
Table 6. Operating Modes
Mode RW bit
Current Address Read 1 X 1 START, Device Select, RW
Random Address Read
Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0
Page Write 0
Note: 1. X = V
8/26
IH
or V
.
IL
0X
1 X reSTART, Device Select, RW
WC
V
V
1
IL
IL
Bytes Initial Sequence
= 1
1
START, Device Select, RW
1 START, Device Select, RW = 0
≤ 32 START, Device Select, RW = 0
= 0, Address
= 1
Page 9
Figure 7. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK ACK ACK NO ACK
BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN
M24C64, M24C32
R/W
START
WC
ACK ACK ACK NO ACK
PAGE WRITE DEV SEL BYTE ADDR
R/W
START
WC (cont'd)
NO ACK NO ACK
PAGE WRITE
(cont'd)
DATA IN N
STOP
Write Operations
Following a Start co ndition the bus mas ter sends
a Device Select Code with the Read/Write
(RW
) reset to 0. The device acknowledges this, as
bit
shown in Figure 8., and waits for two address
bytes. The devi ce res ponds to e ach addres s by te
with an acknowledge bit, and then waits for the
data byte.
Writing to the memory may be inhibited if Write
Control (WC
with Write Control (WC
) is driven Hi gh. Any W rite instruction
) driven High (duri ng a pe riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are
not
acknowledged, as shown in Figure 7..
Each data byte in the memory ha s a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 4.) is sent first, foll owed by the Least Signifi-
cant Byte (Table 5.). Bits b15 to b0 form the
address of the byte in memory.
When the bus master gener ates a Stop conditi on
immediately after t he Ac k bi t (i n th e “1 0
th
bit” time
STOP
BYTE ADDR DATA IN 1
DATA IN 2
AI01120C
slot), either at the end of a Byte Write or a Page
Write, the internal W rite c ycle is tri ggered. A Stop
condition at any other time slot does not trigger the
internal Write cycle.
After the Stop condition, the delay t
, and the suc-
W
cessful completion of a Write operation, the device’s internal address counter is incremented
automatically, to point to the next byte address after the last one that was modified.
During the internal Write cycl e, Serial Data (SDA)
is disabled intern ally, a nd the devic e does n ot respond to any requests.
Byte Write
After the Device Select code and the address
bytes, the bus mas ter sends one d ata byte. If the
addressed location is Write-protected, by Write
Control (WC
) being driven High, the device replies
with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master
terminates the transf er by gener ating a St op condition, as shown in Figure 8..
9/26
Page 10
M24C64, M24C32
Page Write
The Page Write mode a llows up to 32 by tes to be
written in a single Wr ite cycle, provided tha t they
are all located in th e same ’row’ in the memory:
that is, the most significant m emory address bits
(b12-b5 for M24C64, and b11-b5 for M24C32) are
the same. If more by tes a re sen t th an will fi t up to
the end of the row, a condition known as ‘roll-over’
occurs. This should be av oided, as data starts to
become overwritten in a n implementation de pendent way.
Figure 8. Write Mode Sequences with WC
WC
BYTE WRITE DEV SEL BYTE ADDR
START
WC
=0 (data write enabled)
ACK
R/W
The bus master sends from 1 to 32 byte s of data,
each of which is acknowledged by the device if
Write Control (WC
) is Low. If Write Control (WC) is
High, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred,
the internal byte add ress cou nter (th e 5 leas t significant address bits only) is incremented. The
transfer is termina ted by the bus master gener ating a Stop condition.
ACK ACK ACK
BYTE ADDR DATA IN
STOP
ACK ACK ACK ACK
PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1
R/W
START
WC (cont'd)
ACKACK
PAGE WRITE
(cont'd)
DATA IN N
STOP
DATA IN 2
AI01106C
10/26
Page 11
Figure 9. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
NO
Returned
M24C64, M24C32
First byte of instruction
with RW = 0 already
decoded by the device
ReSTART
STOP
YES
Next
Operation is
Addressing the
Memory
DATA for the
WRITE Operation
Continue the
WRITE Operation
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device disconnects itself from the bus, an d writes a copy of the
data from its internal lat ches to the me mory ce lls.
The maximum Write time (t
) is shown in Table
w
16. and Table 17., but the typical time is shorter.
To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 9., is:
YESNO
Send Address
and Receive ACK
START
Condition
YESNO
DEVICE SELECT
with RW = 1
Continue the
Random READ Operation
AI01847C
– Initial condition: a Write cycle is in progress.
– Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first
byte of the new instruction).
– Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the
bus master goes back to Step 1. If the device
has terminated the internal Write cycle, it
responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).
11/26
Page 12
M24C64, M24C32
Figure 10. Read Mode Sequences
CURRENT ADDRESS READ
RANDOM ADDRESS READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
ACK
DEV SEL DATA OUT
R/W
START
ACK
DEV SEL * BYTE ADDR BYTE ADDR
R/W
START
ACK ACK ACK NO ACK
DEV SEL DATA OUT 1
R/W
START
ACK ACK ACK
DEV SEL * BYTE ADDR BYTE ADDR
NO ACK
STOP
ACK ACK ACK
DEV SEL * DATA OUT
R/W
START
DATA OUT N
STOP
ACK ACK
DEV SEL * DATA OUT 1
NO ACK
STOP
R/W
START
ACK NO ACK
DATA OUT N
STOP
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical.
Read Operations
Read operations are per formed independently of
the state of the Write Control (WC
) signal.
After the successful completion of a Read operation, the device’s internal address counter is incremented by one, to point to the next byte address.
Random Address Read
A dummy Write is fi rst performed to load th e address into this addres s counter (as s hown in Fig-
ure 10.) but
without
sending a Stop condition.
Then, the bus master sends anoth er Start condition, and repeats the Device Select Code, with the
Read/Write
bit (RW) set to 1. The device acknowl-
dressed byte. The bus master must
acknowledge the byte, and terminates the transfer
with a Stop condition.
Current Address Read
For the Current Address Read operation, following
a Start condition, the bus master only sends a Device Select Code with the Read/Write
to 1. The device acknowle dges this, and outputs
the byte addressed by the internal address
counter. The counter is then incremented. The bus
master terminates th e transfer with a S top condition, as shown in Figure 10.,
ing the by te.
START
R/W
without
AI01105C
bit (RW) set
acknowledg-
edges this, and outputs the contents of the ad-
not
12/26
Page 13
M24C64, M24C32
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The bus
master
and sends additional cloc k pulses so that the device continues to output the next byte in sequence.
To terminate the s tream of by tes, the bu s master
must
generate a Stop condition, as shown in Figure 10..
The output data comes from consecutive addresses, with the internal address counter automatically
incremented after e ach byte outpu t. After the la st
memory address, the addres s cou nter ‘r ol ls- ov er ’,
and the device continues to output data from
memory address 00h.
does
acknowledge the data byte output,
not
acknowledge the last byte, and
must
Acknowledge in Read Mode
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
th
9
bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device terminates the data transfer and switches to its Stand by mode.
INITIAL DELIVERY STATE
The device is delivered with all bits in the memory
array set to 1 (each byte contains FFh).
13/26
Page 14
M24C64, M24C32
MAXIMUM RATING
Stressing the devi ce outside the ratings li sted in
Table 7. may cause permanent damage to the de-
vice. These are stress ratings only, and oper ation
of the device at these, or any other conditions outside those indicated in the Oper ating sections of
Table 7. Absolute Maximum Ratings
Symbol Parameter Min. Max. Unit
T
STG
T
LEAD
V
IO
V
CC
V
ESD
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
Storage Temp era tur e –65 150 °C
Lead Temperature during Soldering
Input or Output range –0.50 6.5 V
Supply Voltage –0.50 6.5 V
Electrostatic Discharg e Voltage (Human Body mode l)
this specificatio n, is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods may affect de vice rel iability. Refer also to
the STMicroelectroni cs SURE Program and othe r
relevant quality documents.
See note
2
–4000 4000 V
1
°C
14/26
Page 15
M24C64, M24C32
DC AND AC PARAMETERS
This section summ arizes the operati ng and measurement conditions , and the D C an d AC charac teristics of the device. The parameters in th e DC
and AC Characteristic tables that follow are derived from tests performed under the Measure-
Table 8. Operating Conditions (M24Cxx-6)
Symbol Parameter Min. Max. Unit
V
CC
Supply Voltage
1
ment Conditions summarized in the relevant
tables. Designers sho uld c heck tha t th e operating
conditions in thei r circui t match the measur ement
conditions when relying on the quoted parameters.
4.5 5.5 V
T
A
Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.
Ambient Operating Temperature –40 85 °C
Table 9. Operating Conditions (M24Cxx-W)
Symbol Parameter Min. Max. Unit
V
CC
T
A
Supply Voltage 2.5 5.5 V
Ambient Operating Temperature (Device Grade 6) –40 85 °C
Ambient Operating Temperature (Device Grade 3) –40 125 °C
Table 10. Operating Conditions (M24Cxx-R)
Symbol Parameter Min. Max. Unit
V
CC
T
A
Supply Voltage 1.8 5.5 V
Ambient Operating Temperature –40 85 °C
15/26
Page 16
M24C64, M24C32
Table 11. AC Measurement Conditions
Symbol Parameter Min. Max. Unit
C
L
Load Capacitance 100 pF
Input Rise and Fall Times 50 ns
Input Levels
Input and Output Timing Referen ce Le ve ls
Figure 11. AC Measurement I/O Waveform
Input Levels
0.8V
CC
0.2V
CC
Table 12. Input Parameters
Symbol
C
IN
C
IN
Z
WCL
Z
WCH
t
NS
Note: 1. TA = 25°C, f = 400kHz
2. Sampled only, not 100% tested.
Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
WC Input Impedance VIN < 0.3V
WC Input Impedance VIN > 0.7V
Pulse width ignored
(Input Filter on SCL and SDA )
Parameter
1,2
0.2V
0.3V
Input and Output
Timing Reference Levels
0.7V
CC
0.3V
CC
AI00825B
to 0.8V
CC
to 0.7V
CC
CC
CC
V
V
Test Condition Min. Max. Unit
CC
CC
50 200 kΩ
500 kΩ
200 ns
Table 13. DC Characteristics (M24Cxx
Symbol Parameter
Input Leakage Current
I
LI
(SCL, SDA, E2, E1, E0)
I
I
I
CC1
V
V
V
Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.
Output Leakage Current
LO
Supply Current
CC
Stand-by Supply Current
Input Low Voltage –0.45
IL
Input High Voltage
IH
Output Low Voltage
OL
(1)
, M24Cxx-W6 and M24Cxx-W3)
Test Condition
(in addition to those in Table 8.)
V
= VSS or V
IN
CC
device in Stand-by mode
V
= VSS or V
OUT
V
=5V, fc=400kHz (rise/fall time < 30ns)
CC
V
= VSS or VCC, V
IN
I
= 3 mA, VCC = 5 V
OL
SDA in Hi-Z
CC,
CC
= 5 V
16/26
Min. Max. Unit
± 2 µA
± 2 µA
2mA
10 µA
0.3V
CC
0.7V
CC
VCC+1
0.4 V
V
V
Page 17
Table 14. DC Characteristics (M24Cxx-W6 and M24Cxx-W3)
Symbol Parameter
Input Leakage Current
I
LI
(SCL, SDA, E2, E1, E0)
I
V
I
I
CC1
V
V
Output Leakage Current
LO
Supply Current
CC
Stand-by Supply Current
Input Low Voltage –0.45
IL
Input High Voltage
IH
Output Low Voltage IOL = 2.1 mA, VCC = 2.5 V 0.4 V
OL
(in addition to those in Table 9.)
V
CC
Test Condition
V
= VSS or V
IN
device in Stand-by mode
V
= VSS or V
OUT
CC,
=2.5V, fc=400kHz (rise/fall tim e <
30ns)
V
= VSS or VCC, V
IN
Table 15. DC Characteristics (M24Cxx-R)
Symbol Parameter
Input Leakage Current
I
LI
(SCL, SDA, E2, E1, E0)
Output Leakage Current V
LO
Supply Current
CC
Stand-by Supply Current
Input Low Voltage –0.45
IL
Input High Voltage
IH
Output Low Voltage
OL
I
V
I
I
CC1
V
V
(in addition to those in Table 10.)
V
CC
Test Condition
V
= VSS or V
IN
device in Stand-by mode
= VSS or V
OUT
CC,
=1.8V, fc=100kHz (rise/fall time <
30ns)
V
= VSS or VCC, V
IN
I
= 0.7 m A, VCC = 1.8 V
OL
M24C64, M24C32
Min. Max. Unit
CC
SDA in Hi-Z
= 2.5 V
CC
0.7V
CC
Min. Max. Unit
CC
SDA in Hi-Z ± 2 µA
= 1.8 V
CC
0.7V
CC
± 2 µA
± 2 µA
1mA
2µA
0.3V
CC
VCC+1
± 2 µA
0.8 mA
0.2 µA
0.3 V
CC
VCC+1
0.2 V
V
V
V
V
17/26
Page 18
M24C64, M24C32
Table 16. AC Characteristics (M24Cxx-6, M24Cxx-W6 and M24Cxx-W3)
Test conditions specified in Table 11. and Table 8. or Table 9.
Symbol Alt. Parameter Min. Max. Unit
f
C
t
CHCL
t
CLCH
t
DL1DL2
t
DXCX
t
CLDX
t
CLQX
3
t
CLQV
1
t
CHDX
t
DLCL
t
CHDH
t
DHDL
t
W
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or risin g edge of SDA.
4. The Write Time of 5 ms only applies to devices bearing the process letter “B” in the package marking (on the top side of the package), otherwise (for devices bea ring the proce ss letter “N”) the Write Time is 10 ms. For fur ther details, please contac t your nearest
ST sales office, and ask for a copy of t he Product Change Notice PCEE0036.
f
SCL
t
HIGH
t
LOW
2
t
SU:DAT
t
HD:DAT
t
t
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
WR
Clock Frequency 400 kHz
Clock Pulse Width High 600 ns
Clock Pulse Width Low 1300 ns
t
SDA Fall Time 20 300 ns
F
Data In Set Up Time 100 ns
Data In Hold Time 0 ns
Data Out Hold Time 200 ns
DH
Clock Low to Next Data Valid (Access Time) 200 900 ns
AA
Start Condition Set Up Time 600 ns
Start Condition Hold Time 600 ns
Stop Condition Set Up Time 600 ns
Time between Stop Condition and Next Start Condition 1300 ns
Write Time
5 or
4
10
ms
Table 17. AC Characteristics (M24Cxx-R)
Test conditions specified in Table 11. and Table 10.
Symbol Alt. Parameter Min. Max. Unit
f
C
t
CHCL
t
CLCH
t
DL1DL2
t
DXCX
t
CLDX
t
CLQX
3
t
CLQV
1
t
CHDX
t
DLCL
t
CHDH
t
DHDL
t
W
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or risin g edge of SDA.
f
SCL
t
HIGH
t
LOW
2
t
SU:DAT
t
HD:DAT
t
t
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
WR
Clock Frequency 400 kHz
Clock Pulse Width High 600 ns
Clock Pulse Width Low 1300 ns
t
SDA Fall Time 20 300 ns
F
Data In Set Up Time 100 ns
Data In Hold Time 0 ns
Data Out Hold Time 200 ns
DH
Clock Low to Next Data Valid (Access Time) 200 900 ns
AA
Start Condition Set Up Time 600 ns
Start Condition Hold Time 600 ns
Stop Condition Set Up Time 600 ns
Time between Stop Condition and Next Start Condition 1300 ns
Write Time 10 ms
18/26
Page 19
Figure 12. AC Waveforms
M24C64, M24C32
SCL
SDA In
SCL
SDA In
SCL
tCHCL
tDLCL
tCHDX
START
Condition
tCHDH
STOP
Condition
tCLQV tCLQX
SDA
Input
tCLCH
SDA
Change
tW
Write Cycle
tDXCXtCLDX
tCHDH tDHDL
tCHDX
START
Condition
STOP
Condition
START
Condition
SDA Out
Data Valid
AI00795C
19/26
Page 20
M24C64, M24C32
PACKAGE MECHANICAL
Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
b2
A2
A1AL
be
D
8
E1
1
Note: Drawing is not to scale.
E
c
eA
eB
PDIP-B
Table 18. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
Symbol
Typ. Min. Max. Typ. Min. Max.
A5.330.210
A1 0.38 0.015
A2 3.30 2.92 4.95 0.130 0.115 0.195
b 0.46 0.36 0.56 0.018 0.014 0.022
b2 1.52 1.14 1.78 0.060 0.045 0.070
c 0.25 0.20 0.36 0.010 0.008 0.014
D 9.27 9.02 10.16 0.365 0.355 0.400
E 7.87 7.62 8.26 0.310 0.300 0.325
E1 6.35 6.10 7.11 0.250 0.240 0.280
e 2.54 – – 0.100 – –
eA 7.62 – – 0.300 – –
eB 10.92 0.430
L 3.30 2.92 3.81 0.130 0.115 0.150
millimeters inches
20/26
Page 21
M24C64, M24C32
Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
Note: Drawing is not to scale.
B
SO-a
A
e
D
N
1
CP
E
H
C
LA1 α
Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Symbol
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N8 8
CP 0.10 0.004
millimeters inches
21/26
Page 22
M24C64, M24C32
Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
1
CP
Note: Drawing is not to scale.
5
EE1
4
α
A2A
A1
eb
L
L1
TSSOP8AM
Table 20. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
Symbol
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α 0° 8° 0° 8°
mm inches
c
22/26
Page 23
M24C64, M24C32
Figure 16. UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm
D
e
L3
E
b
L1
E2
L
A
D2
ddd
A1
UFDFPN-01
Note: Drawing is not to scale.
Table 21. UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm,
Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A 0.55 0.50 0.60 0.022 0.020 0.024
A1 0.00 0.05 0.000 0.002
b 0.25 0.20 0.30 0.010 0.008 0.012
D 2.00 0.079
D2 1.55 1.65 0.061 0.065
ddd 0.05 0.002
E3.00 0.118
E2 0.15 0.25 0.006 0.010
e 0.50 – – 0.020 – –
L 0.45 0.40 0.50 0.018 0.016 0.020
L1 0.15 0.006
L3 0.30 0.012
N8 8
millimeters inches
23/26
Page 24
M24C64, M24C32
PART NUMBERING
Table 22. Ordering Information Scheme
Example: M24C32 – W MN 6 T P
Device Type
2
M24 = I
Device Function
64 = 64 Kbit (8192 x 8)
32 = 32 Kbit (4096 x 8)
Operating Voltage
blank
W = V
R = V
Package
BN = PDIP8
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MB = UFDFPN8 (MLP8)
C serial access EEPROM
(2)
= VCC = 4.5 to 5.5V
= 2.5 to 5.5V
CC
= 1.8 to 5.5V
CC
(3)
Device Grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
(1)
3 = Automotive: device tested with High Reliability Certified Flow
over –40 to 125 °C.
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P or G = RoHS compliant
Note: 1. ST strongly recommends the use of the Automotive Grade devic es fo r use in an aut omotiv e envir onmen t. The High Reliabi lity Cer-
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy .
2. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.
3. The UFDFPN8 package is available in M24C32 devices only. It is not av ailable in M24C64 devices.
device, please conta ct yo ur nearest ST Sal es Office.
24/26
Page 25
M24C64, M24C32
REVISION HISTORY
Table 23. Document Revision History
Date Rev. Description of Revis io n
22-Dec-1999 2.3 TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo, PackageMechData).
28-Jun-2000 2.4 TSSOP8 package data corrected
31-Oct-2000 2.5
20-Apr-2001 2.6
16-Jan-2002 2.7
02-Aug-2002 2.8
04-Feb-2003 2.9 SO8W package removed. -S voltage range removed
27-May-2003 2.10 TSSOP8 (3x3mm² body size) package (MSOP 8) rem o ved
22-Oct-2003 3.0
01-Jun-2004 4.0
04-Nov-2004 5.0
05-Jan-2005 6.0 UFDFPN8 package added. Small text changes.
References to Temperature Range 3 removed from Ordering Information
Voltage range -S added, and range -R removed from text and tables throughout.
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP changed to PDIP and Package Mechanical data updated
Test condition for I
made more precise, and val ue of ILI for E2-E0 and WC added
LI
-R voltage range added
Document reformatted using new template.
TSSOP8 (3x3mm² bo dy siz e) packa ge (MS OP 8) ad de d.
5ms write time offered for 5V and 2.5V devices
Table of contents, and Pb-free options added. Minor wording changes in Summary
Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations.
(min) improved to -0.45V.
V
IL
Absolute Maximum Ratings for V
(min) and VCC(min) improved. Soldering temperature
IO
information clarified for RoHS compliant devices. Device Grade clarified
Product List summary table added. Device Grade 3 added. 4.5-5.5V range is Not for New
Design. Some minor wording changes. AEC-Q100-002 compliance. t
VIL(min) is the same on all input pins of the device. Z
WCL
changed.
(max) changed.
NS
25/26
Page 26
M24C64, M24C32
Information furnished is be lieved to be a ccur ate and reli able. Howe ver, STMicroele ctronic s assu mes no r esponsib ilit y for th e consequences
of use of such information nor for any infrin gement of patent s or other rights of third parties which ma y result from it s use. No license is granted
by implication or otherwi se under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without not ice. This pub licat ion su persed es and repl aces all in format ion previou sly su pplie d. STMicroele c tronic s prod ucts ar e no t
authorized for use as critical compone nts in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
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