Datasheet M24C64-WMW6T, M24C64-WMW6, M24C64-WMN6T, M24C64-WMN6, M24C64-W Datasheet (SGS Thomson Microelectronics)

1/19December 1999

M24C64
M24C32

64/32 Kbit Serial I²C Bus EEPROM

■ Compat ible with I

2

C Extended Addressing

■ Two Wire I

2

C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 4.5V to 5.5V for M24Cxx
– 2.5V to 5.5V for M24Cxx-W
– 1.8V to 3.6V for M24Cxx-R

■ Hardware Write Control

■ BYTE and PAGE WRITE (up to 32 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Tim ed P ro g ra m ming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ 1 Million Erase/Write Cycles (minimum)

■ 40 Year Data Retention (minimum)

DESCRIPTION

These I

2

C-compatible electrically erasable pro­grammable memory (EEPROM) devices are orga­nized as 8192x8 bits (M24C64) and 4096x8 bits
(M24C32), and operate down to 2.5 V (for the -W
version of each device), and down to 1.8 V (for the

-R version of each device).
The M24C64 and M24C32 are available in Plastic

Dual-in-Line, Plastic Small Outline and Thin Shrink
Small Outline packages.

Figure 1. Logic Diagram

AI01844B

3

E0-E2 SDA

V

CC

M24C64
M24C32

WC

SCL

V

SS

Table 1. Signal Names

E0, E1, E2 Chip Enable Inputs
SDA Serial Data/Address Input/

Output
SCL Serial Clock
WC

Write Control
V

CC

Supply Voltage
V

SS

Ground

PSDIP8 (BN)

0.25 mm frame

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

8

1

8

1

8

1

SO8 (MW)

200 mil width

8

1

M24C64, M24C32

2/19

These memory devices are compatible with the
I

2

C extended memory standard. This is a two wire
serial interface that uses a bi-directiona l data bus
and serial clock. The memory carries a built-in 4­bit unique Device Type Identifier code (1010) in
accordance with the I

2

C bus definition.

The memory behaves as a slave device in the I

2

C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, gene rated by the
bus master. The START condition is followed by a
Device Select Code and RW

bit (as described in

Table 3), terminated by an acknowledge bit.
When writing data to the memory, the mem ory in-

serts an acknowledge bit during the 9

th

bit time,

following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by

a STOP condition after an Ack for WRITE, and af­ter a NoAck for READ.

Power On Reset: V

CC

Lock-Out Write Protect

In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re­set (POR) circuit is included. The internal reset is
held active until the V

CC

voltage has reached the
POR threshold value, and all operations are dis­abled – the device will not respond to any com­mand. In the same way, when V

CC

drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any com ma nd. A s table a nd v alid V

CC

must be applied before applying any logic signal.

SIGNAL DESCRIPTION
Serial Clock (SCL)

The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slow-

Figure 2A. DIP Connections

SDAV

SS

SCL

WCE1

E0 V

CC

E2

AI01845B

M24C64
M24C32

1
2
3
4

8
7
6
5

Figure 2B. SO and TSSOP Connections

1

AI01846B

2
3
4

8
7
6
5

SDAV

SS

SCL

WCE1

E0 V

CC

E2

M24C64
M24C32

Table 2. Absolute Maximum Ratings

1

Note: 1. Exc ept for the rating “Operating Temperature Range”, stresses above those l i sted in the Table “Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indica te d i n the Operating secti ons of this specification is not im plied. Exposure to Absolute Ma xim um Rating condi­tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL -STD-883C, 3015.7 (100 pF, 1500 Ω)

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature -40 to 125 °C

T

STG

Storage Temperature -65 to 150 °C

T

LEAD

Lead Temperature during Soldering

PSDIP8: 10 seconds
SO8: 40 seconds
TSSOP8: 40 second s

260
215
215

°C

V

IO

Input or Output range -0.6 to 6.5 V

V

CC

Supply Voltage -0.3 to 6.5 V

V

ESD Electrostatic Discharge Voltage (Human Body model)

2

4000 V

3/19

M24C64, M24C32

er clock, the master must have an open drain out­put, and a pull-up resistor must be connected from
the SCL line to V

CC

. (Figure 3 indicates how the
value of the pull-up res istor c an be calculated). In
most applications, though, this method of synchro­nization is not employed, and so the pull-up resis­tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.

Serial Data (SDA)

The SDA pin is bi-directional, and is used to trans­fer data in or out of the memory. It is an open drain

output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V

CC

. (Figure 3 indicates how the value of the

pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs may be driven dynamically or tied to
V

CC

or VSS to establish the device select code (but

note that the V

IL

and VIH levels for the inputs are

CMOS compatible, not TTL compatible).

Write Control (WC

)

The hardware Write Control pin (WC

) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC

=VIL) or disable (WC=VIH)
write instructions to the entire memory area. When
unconnected, the WC

input is internally read as

V

IL

, and write operations are allowed.

When WC

=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl­edged.

Please see the Application Note

AN404

for a more

detailed description of the Write Control feature.

DEVICE OPERATION

The memory device supports the I

2

C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note

AN1001

. Any device that sends data on to the bus
is defined to be a transm itter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is k nown as the master,
and the other as the slave. A data transfer can only
be initiated by the mas ter, which wi ll also provide
the serial clock for synchronization. The memory
device is always a slave device in all comm unica­tion.

Start Condition

START is identified by a high t o low transition of
the SDA line while the clock, SCL, is stable i n the
high state. A START condition must precede any
data transfer comman d. Th e m em ory devi ce con­tinuously monitors (except during a program ming
cycle) the SDA and SCL lines for a START condi­tion, and will not respond unless one is given.

Stop Condition

STOP is identified by a low to high transition of the
SDA line wh ile th e clock S CL is sta ble in the h igh
state. A STO P condition terminates c ommunica­tion between the memory device and the bus mas­ter. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the interna l EEPRO M write cycle.

Figure 3. Maximum R

L

Value versus Bus Capacitance (C

BUS

) for an I2C Bus

AI01665

V

CC

C

BUS

SDA

R

L

MASTER

R

L

SCL

C

BUS

100

0

4

8

12

16

20

C

BUS

(pF)

Maximum RP value (kΩ)

10 1000

fc = 400kHz

fc = 100kHz

M24C64, M24C32

4/19

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a suc­cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9

th

clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.

Data Input

During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi­tion, and the data must change

only

when the SCL

line is low.

Memory Addressing

To start communication betwee n the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus

line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code i s fur­ther su bdi v i d ed i n to : a 4 -b i t D e vi c e T y pe Iden t if i er,

and a 3-bit Chip Enable “Address” (E2, E1, E0).
To address the memory array, the 4-bit Device

Type Identifier is 1010b.
Up to eight memory devices can be connected on

a single I

2

C bus. Each one is given a uniq ue 3-bit
code on its Chip Enable inputs. When the Dev ice
Select Code is received on the SDA bus, the mem­ory only responds if the Chip Select Code is the
same as the pattern applied to its Chip Enable
pins.

The 8

th

bit is th e RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Cod e, th e corresponding mem­ory gives an acknowledgment on the SDA bus dur­ing the 9

th

bit time. If the memo ry does n ot ma tch

Figure 4. I

2

C Bus Protocol

SCL

SDA

SCL

SDA

SDA

START

CONDITION

SDA

INPUT

SDA

CHANGE

AI00792

STOP

CONDITION

1 23 789

MSB

ACK

START

CONDITION

SCL

1 23 789

MSB ACK

STOP

CONDITION

5/19

M24C64, M24C32

the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.

There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the m aster and
the slave is ended with a STOP condition.

Each data byte in the m emory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta­ble 4) is sent first, f ollowed by the Least significant
Byte (Table 5). Bits b15 to b0 form t he addre ss of
the byte in memory. Bits b15 to b13 are treated as

a Don’t Care bit on the M24C64 memory. Bits b15
to b12 are treated as Don’t Care bits on the
M24C32 me m o r y .

Write Operations

Following a START con dition the ma ster sends a
Device Select Code with the RW

bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory re­sponds to each address byte with an acknowledge
bit, and then waits for the data byte.

Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC

=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the me mory c ontents, and t he ac­companying data bytes will

not

be acknowledged

(as shown in Figure 5).

Byte Write

In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed lo cation is write

protected by the WC

pin, the memory replies with
a NoAck, and the location is not modified. If, in­stead, the WC

pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.

Page Write

The Page Write mode allows u p to 32 by tes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory add ress bits
(b12-b5 for the M24C64 and b11-b5 for the
M24C32) are the same. If more bytes are sent
than will fit up to the end of t he row, a condit ion
known as ‘roll-over’ occurs. Data starts to become
overwritten (in a way not formally specified in this
data sheet).

The master sends from one up to 32 bytes of data,
each of which is acknow ledged by the memory if
the W C

pin is low. If the WC pin is high, the con­tents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte i s tran sferred, the i nte rnal

Table 3. Device Select Code

1

Note: 1. The most significant bit, b7, is sent first.

Device Type Identifier Chip Enable RW

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 E2 E1 E 0 RW

Table 4. Most Significant Byte

Note: 1. b15 to b13 are Don’t Care on the M24C6 4 series.

b15 to b12 are Don’t Care on the M 24C32 serie s.

Table 5. Least Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8

b7 b6 b5 b4 b3 b2 b1 b0

Table 6. Operating Modes

Note: 1. X = V

IH

or V

IL

.

Mode RW bit

WC

1

Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW

= ‘1’

Random Address Read

0X

1

START, Device Select, RW

= ‘0’, Address

1 X reSTART, Device Select, RW

= ‘1’
Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0 V

IL

1 START, Device Select, RW = ‘0’

Page Write 0 V

IL

≤ 32 START, Device Select, RW = ‘0’

M24C64, M24C32

6/19

Figure 5. Wri te Mo de S e qu e nces with WC=1 (data write inhib i ted)

STOP

START

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

WC

START

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

WC

DATA IN 2

AI01120B

PAGE WRITE
(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK ACK ACK NO ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK NO ACK

byte address counter (the 5 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.

When the master generates a STOP condition im-

mediately after the Ack bit (in the “10

th

bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not t rig­ger the internal write cycle.

During the internal write cycle, the SDA input is
disabled internally, and the device does not re­spond to any requests.

7/19

M24C64, M24C32

Figure 6. Wri te Mo de S e qu e nces with WC=0 (data write enab led )

STOP

START

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

WC

START

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

WC

DATA IN 2

AI01106B

PAGE WRITE
(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK

R/W

ACK ACK ACK

ACK ACK ACK ACK

R/W

ACKACK

M24C64, M24C32

8/19

Read Operations

Read operations are performed independently of
the state of the WC

pin.

Random Address Read

A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then,

without

sending a STOP condition, the mas­ter sends another START condi tion, and repeats
the Device Select Code, with the RW

bit set to ‘1’.
The memory acknowledge s this, and outputs the
contents of the addressed byte. The master m ust

not

acknowledge the by te output, and terminates

the transfer with a STOP condition.

Current Address Read

The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read m ode, following a START
condition, the master sends a Device Select Code
with the RW

bit set to ‘1’. The memory acknowl-

edges this, and outputs the byte addressed by the

Minimizing System Delays by Polling On ACK

During the internal write cycle, the memory discon­nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi­mum write time (t

w

) is shown in Table 9, but the
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.

The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the m aster issues a ST ART condition

followed by a Device Select Code (the first byte
of the new instruction).

– Step 2: if the memory is busy with the internal

write cycle, no Ack will be returned and the mas­ter goes back to Step 1. If the memory has ter­minated the internal write cycle, it responds with
an Ack, indicating that the m emory is ready to
receive the second part of the nex t instruction
(the first byte of this instruction having been sent
during Step 1).

Figure 7. Wri te Cy cle Pol l in g Fl owchart using A CK

WRITE Cycle

in Progress

AI01847

Next

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

NO

YESNO

ReSTART

STOP

Proceed

WRITE Operation

Proceed

Random Address

READ Operation

Send

Byte Address

First byte of instruction
with RW = 0 already
decoded by M24xxx

9/19

M24C64, M24C32

The output data comes from consecutive address­es, with the internal address counter automatically
incremented after each byte output. After the last

memory address, the address coun ter ‘rolls-over’
and the memory continues to output data from
memory address 00h.

Acknowledge in Read Mode

In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9

th

bit time. If the master does n ot pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.

internal address counter. The counter is then in­cremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8,

with-

out

acknowledging the byte output.

Sequenti a l Rea d

This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master

does

acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must

not

acknowledge the last

byte output, and

must

generate a STOP condition.

Figure 8. Read Mode Sequences

Note: 1. The seven most signi fi cant bits of the D evice Select Code of a Random Read (in the 1st and 4th bytes) must be i d entica l.

START

DEV SEL * BYTE ADDR BYTE ADDR

START

DEV SEL DATA OUT 1

AI01105C

DATA OUT N

STOP

START

CURRENT
ADDRESS
READ

DEV SEL DATA OUT

RANDOM
ADDRESS
READ

STOP

START

DEV SEL * DATA OUT

SEQUENTIAL
CURRENT
READ

STOP

DATA OUT N

START

DEV SEL * BYTE ADDR BYTE ADDR

SEQUENTIAL
RANDOM
READ

START

DEV SEL * DATA OUT 1

STOP

ACK

R/W

NO ACK

ACK

R/W

ACK ACK ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK

ACK ACK ACK

R/W

ACK ACK

R/W

ACK NO ACK

M24C64, M24C32

10/19

Table 7. DC Characteristics

(T

A

= 0 to 70 °C or –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5 V)

(T

A

= 0 to 70 °C or –20 to 85 °C; VCC = 1.8 to 3.6 V)

Note: 1. This is preliminary data.

Table 8. Input Parameters1 (TA = 25 °C, f = 400 kHz)

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min. Max. Unit

I

LI

Input Leakage Current
(SCL, SDA)

0V ≤ V

IN

≤ V

CC

± 2 µA

I

LO

Output Leakage Current 0 V ≤ V

OUT

≤ V

CC,

SDA in Hi-Z ± 2 µA

I

CC

Supply Current

V

CC

=5V, fc=400kHz (rise/fall time < 30ns)

2mA

-W series:

V

CC

=2.5V, fc=400kHz (rise/fall time < 30ns)

1mA

-R series:

V

CC

=1.8V, fc=100kHz (rise/fall time < 30ns)

0.8

1

mA

I

CC1

Supply Current
(Stand-by)

V

IN

= VSS or V

CC

, V

CC

= 5 V 10 µA

-W series: V

IN

= VSS or V

CC

, V

CC

= 2.5 V 2 µA

-R series: V

IN

= VSS or V

CC

, V

CC

= 1.8 V

1

1

µA

V

IL

Input Low Voltage
(E0-E2, SCL, SDA)

– 0.3 0.3 V

CC

V

V

IH

Input High Voltage
(E0-E2, SCL, SDA)

0.7V

CC

VCC+1 V

V

IL

Input Low Voltage (WC) – 0.3 0.5 V

V

IH

Input High Voltage (WC)

0.7V

CC

VCC+1

V

V

OL

Output Low
Voltage

I

OL

= 3 mA, VCC = 5 V

0.4 V

-W series: I

OL

= 2.1 mA, VCC = 2.5 V 0.4 V

-R series:

I

OL

= 0.7 mA, VCC = 1.8 V

0.2

1

V

Symbol Parameter Test Condition Min. Max. Unit

C

IN

Input Capacitance (SDA) 8 pF

C

IN

Input Capacitance (other pins) 6 pF

Z

L

WC Input Impedance VIN < 0.5 V 5 20 kΩ

Z

H

WC Input Impedance VIN > 0.7V

CC

500 kΩ

t

NS

Low Pass Filter Input Time
Constant (SCL and SDA)

100 ns

11/19

M24C64, M24C32

Table 9. AC Characteristics

Note: 1. For a r eS T ART conditio n, or following a w ri te cycle.

2. Samp l ed only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

4. This i s preliminary dat a.

Symbol Alt. Parameter

M24C64 / M24C32

Unit

V

CC

=4.5 to 5.5 V

T

A

=0 to 70°C or

–40 to 85°C

V

CC

=2.5 to 5.5 V

T

A

=0 to 70°C or

–40 to 85°C

V

CC

=1.8 to 3.6 V

T

A

=0 to 70°C or

–20 to 85°C

4

Min Max Min Max Min Max

t

CH1CH2

t

R

Clock Rise Time 300 300 1000 ns

t

CL1CL2

t

F

Clock Fall Time 300 300 300 ns

t

DH1DH2

2

t

R

SDA Rise Time 20 300 20 300 20 1000 ns

t

DL1DL2

2

t

F

SDA Fall Time 20 300 20 300 20 300 ns

t

CHDX

1

t

SU:STA

Clock High to Input Transition 600 600 4700 ns

t

CHCL

t

HIGH

Clock Pulse Width High 600 600 4000 ns

t

DLCLtHD:STA

Input Low to Clock Low (START) 600 600 4000 ns

t

CLDXtHD:DAT

Clock Low to Input Transition 0 0 0 µs

t

CLCH

t

LOW

Clock Pulse Width Low 1.3 1.3 4.7 µs

t

DXCXtSU:DAT

Input Transition to Clock
Transition

100 100 250 ns

t

CHDHtSU:STO

Clock High to Input High (STOP) 600 600 4000 ns

t

DHDL

t

BUF

Input High to Input Low (Bus
Free)

1.3 1.3 4.7 µs

t

CLQV

3

t

AA

Clock Low to Data Out Valid 200 900 200 900 200 3500 ns

t

CLQX

t

DH

Data Out Hold Time After Clock
Low

200 200 200 ns

f

C

f

SCL

Clock Frequency 400 400 100 kHz

t

W

t

WR

Write Time 10 10 10 ms

Table 10. AC Measurement Conditions

Input Rise and Fall Times ≤ 50 ns
Input Pulse Voltages

0.2V

CC

to 0.8V

CC

Input and Output Timing
Reference Voltages

0.3V

CC

to 0.7V

CC

Figure 9. AC Testing Input Output Waveforms

AI00825

0.8V

CC

0.2V

CC

0.7V

CC

0.3V

CC

M24C64, M24C32

12/19

Figure 10. AC Waveforms

SCL

SDA IN

SCL

SDA OUT

SCL

SDA IN

tCHCL

tDLCL

tCHDX

START

CONDITION

tCLCH

tDXCX

tCLDX

SDA

INPUT

SDA

CHANGE

tCHDH

tDHDL

STOP &

BUS FREE

DATA VALID

tCLQV tCLQX

DATA OUTPUT

tCHDH

STOP

CONDITION

tCHDX

START

CONDITION

WRITE CYCLE

tW

AI00795B

13/19

M24C64, M24C32

Table 11. Ordering Information Scheme

Note: 1. Temperature range available onl y on request.

2. For conformity to the High Reliability Certified Flow (HRCF), please contact your nearest ST Sales Office.

3. The -R version (V

CC

range 1.8 V t o 3. 6 V) only availab l e i n temperature ranges 5 or 1.

Example: M24C64 –R MN 6 T

Memory Capacity Option

64 64 Kbit (8K x 8) T Tape and Reel Packing
32 32 Kbit (4K x 8)

Operating Voltage

blank 4.5 V to 5.5 V
W 2.5V to 5.5 V

R

4

1.8 V to 3.6 V

Package Temperature Range

BN PSDIP8 (0.25 mm frame)

1

2

0 °C to 70 °C
MN SO8 (150 mil width) 6 –40 °C to 85 °C
MW SO8 (200 mil width)

3

3

–40 °C to 125 °C
DW TSSOP8 (169 mil width) 5 –20 °C to 85 °C

ORDERING INFORMATION

Devices are shipped from the factory with the

memory content set at all ‘1’s (FFh).
The notation used for the device number is as

shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.

M24C64, M24C32

14/19

Figure 11. PSDIP8 (BN)

Note: 1. Drawing is not to sc al e.

PSDIP-a

A2

A1AL

e1

D

E1 E

N

1

C

eA

eB

B1

B

Table 12. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 3.90 5.90 0.154 0.232

A1 0 .49 – 0.019 –

A2 3 .30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022

B1 1 .15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390
E 7.62 – – 0. 300 – –

E1 6 .00 6.70 0.236 0.264

e1 2.54 – – 0. 100 – –
eA 7 .80 – 0.307 –
eB 10.00 0.394

L 3.00 3.80 0.118 0.150
N8 8

15/19

M24C64, M24C32

Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1 .75 0.053 0.069

A1 0 .10 0.25 0.004 0.010

B 0.33 0 .51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4 .00 0.150 0.157
e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N8 8

CP 0.10 0.004

Figure 12. SO8 narrow (MN)

Note: 1. Drawing is not to sc al e.

SO-a

E

N

CP

B

e

A

D

C

LA1 α

1

H

h x 45˚

M24C64, M24C32

16/19

Table 14. SO8 - 8 lead Plastic Small Outline, 200 mils body width

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 2.03 0.080
A1 0 .10 0.25 0.004 0.010
A2 1.78 0.070

B 0.35 0 .45 0.014 0.018

C 0.20 – – 0.008 – –

D 5.15 5.35 0.203 0.211

E 5.20 5 .40 0.205 0.213

e 1.27 – – 0.050 – –

H 7.70 8.10 0.303 0.319

L 0.50 0.80 0.020 0.031

α 0° 10° 0° 10°

N8 8

CP 0.10 0.004

Figure 13. SO8 wide (MW)

Note: 1. Drawing is not to sc al e.

SO-b

E

N

CP

B

e

A2

D

C

LA1 α

H

A

1

17/19

M24C64, M24C32

Table 15. TSSOP8 - 8 lead Thin Shrink Small Outline

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.10 0.043
A1 0 .05 0.15 0.002 0.006
A2 0 .85 0.95 0.033 0.037

B 0.19 0 .30 0.007 0.012

C 0.09 0.20 0.004 0.008

D 2.90 3.10 0.114 0.122

E 4.30 4 .50 0.169 0.177

e 0.65 – – 0.026 – –

H 6.25 6.50 0.246 0.256

L 0.50 0.70 0.020 0.028

α 0° 8° 0° 8°

N8 8

CP 0.08 0.003

Figure 14. TSSOP8 (DW)

Note: 1. Drawing is not to sc al e.

TSSOP

1

N

CP

N/2

DIE

C

L

A1

EE1

D

A2A

α

eB

M24C64, M24C32

18/19

Table 16. Revision History

Date Description of Revision

22-Dec-1999 TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo, PackageMechData).

19/19

M24C64, M24C32

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent right s of STMicroelectronics . S pecifications mentioned i n this public ation ar e subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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