Datasheet M24C08-WMN6TP, M24C08-WBN6P Specification

with User-Defined Block Write Protection

1 MILLION ERASE/WRITE CYCLES with
40 YEARS DAT A RE TENTION

SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x08 versions
– 2.5V to 5.5V for ST25x08 versions
HARDWARE WRITE CONT ROL VERSIONS:

ST24W08 and ST25W08
PROGRAMMABLE WRITE PROTECTION
TWO WIRE SERIAL INTERFACE, FULLY I2C

BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 8

BYTES)
PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ

MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREME NTING
ENHANCE D ESD/LATCH UP

PERFOR MAN C ES

ST24C08, ST25C08

ST24W08, ST25W08

8 Kbit Serial I2C Bus EEPROM

8

1

PSDIP8 (B)

0.25mm Frame

Figure 1. Logic Diagram

8

1

SO8 (M)

150mil Width

V

CC

DESCRIPTION

2

This specification covers a range of 8 Kbits I

C bus
EEPROM products, the ST24/25C08 and the
ST24/25W08. In the text, products are referred to
as ST24/25x08, where "x" is: "C" for Standard
version and "W" for Hardware Write Control ver­sion.

T ab le 1. Signal Names

PRE Write Protect Enable
E Chip Enable Input
SDA Serial Data Address Input/Output
SCL Serial Clock

MODE
WC Write Control (W version)

V

CC

V

SS

February 1999 1/16

Multibyte/Page Write Mode
(C version)

Supply Voltage
Ground

MODE/WC*

Note:

WC signal is only available for ST24/25W08 products.

E SDA

PRE

SCL

ST24x08
ST25x08

V

SS

AI00860E

ST24/25C08, ST24/25W08

Figure 2A. DIP Pin Connections

ST24x08
ST25x08

1

PRE V

2
3

E

4

SS

Warning:

NC = Not Connected.

T ab le 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

T

V

Notes:

T

STG

LEAD

V

V

ESD

Ambient Operating Temperature –40 to 125

A

Storage Temperature –65 to 150
Lead Temperature, Soldering (SO8 package)

Input or Output Voltages –0.6 to 6.5 V

IO

Supply Voltage –0.3 to 6.5 V

CC

Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress rating s only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).

3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

8
7
6
5

AI00861E

CC

MODE/WCNC
SCL
SDAV

(1)

(PSDIP8 package)

Figure 2B. SO Pin Connections

ST24x08
ST25x08

8
7
6
5

AI01073E

215
260

4000 V

500 V

Warning:

(2)

(3)

PRE V

1
2
3

E

SS

NC = Not Connected.

40 sec
10 sec

4

CC

MODE/WCNC
SCL
SDAV

C

°

C

°

C

°

DESCRIPTION (cont’d)
The ST24/25x08 are 8 Kbit electrically erasable

programmable memories (EEPROM), organized
as 4 blocks of 256 x8 bits. They are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur­ance of one million erase/write cycles with a data
retention of 40 years.

Both Plastic Dual-in-Line and Plastic Small Out line
packages are available.

2

The memories are compatible with the I

C stand-

ard, two wire serial interface which uses a bi-direc-

2/16

tional data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I2C bus defini­tion. This is used together with 1 chip enable input
(E) so that up to 2 x 8K devices may be attached

2

to the I
ries behave as a slave device in the I

C bus and selected individually. The memo-

2

C protocol
with all memory operations synchronized by the
serial clock. Read and write operations are initiated
by a STAR T condition generated by the bus master .
The START condition is followed by a stream of 7
bits (identification code 1010), plus one read/write
bit and terminated by an acknowledge bit.

T ab le 3. Device Select Code

ST24/25C08, ST24/25W08

Device Code

Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 E A9 A8 R

Note:

The MSB b7 is sent first.

T ab le 4. Operating Modes

Mode RW bit MODE Bytes Initial Sequence

Current Address Read ’ 1’ X 1 STAR T, Device Select, R

Random Address Read

Sequential Read ’1’ X 1 to 1024 Similar to Current or Random Mode
Byte Write ’0’ X 1 START, Device Select, R

IH

or V

(2)

IL

Multibyte Write
Page Write ’0’ V

Notes:

1. X = V

2. Multibyte Write not available in ST24/25W08 versions.

(1)

’0’
’1’ reSTART, Device Select, R

’0’ V

X1

IH

IL

8 START, Device Select, RW = ’0’

16 START, Device Select, RW = ’0’

Chip

Enable

START, Device Select, R

Block

Select

W = ’1’
W = ’0’, Address,

W = ’1’

W = ’0’

R

W

W

When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi­nated with a STOP condition.

Power On Reset: V

lock out write protect . In

CC

order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the V

CC

voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any c ommand.
In the same way, when V

drops down from the

CC

operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V

CC

must be applied before applying any logic signal.

SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to

synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V

CC

to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA pin is bi-directional

and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed

with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V

to act as pull up (see Figure 3).

CC

Chip Enable (E). This chip enable input is used to
set one least significant bit (b3) of the device select
byte code. This input may be driven dynamically or
tied to V

or VSS to establish the device select

CC

code.
Protect Enable (PRE). The PRE input pin, in ad-

dition to the status of the Block Address Pointer bit
(b2, location 3FFh as in Figure 7), sets the PRE
write protection active.

Mode (M ODE). The MO DE input is available on pin
7 (see also
cally. It must be at V
mode, V

WC feature) and may be driven dynami-

or VIH for the Byte Write

for Multibyte Write mode or VIL for Page

IH

IL

Write mode. When unconnected, the MODE input
is internally read as a V

Write Control (

(

WC) feature is offered only for ST24W08 and

WC) . An hardware Write Control

(Multibyte Write mode).

IH

ST25W08 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control sig­nal is used to enable (

) the internal write protection. When uncon-

V

IL

nected, the

WC input is internally read as VIL and

WC = VIH) or disable (WC =

the memory area is not write protected.

3/16

ST24/25C08, ST24/25W08

SIGNAL DESCRIPTIONS (cont’d)

The devices with this Write Control feature no
longer support the Multibyte Write mode of opera­tion, however all other write modes are fully sup­ported.

Refer to the AN404 Application Note for more de­tailed information about Write Control feature.

DEVICE O PERATION

2

C Bus Background

I

The ST24/25x08 support the I

2

C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The devic e that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn­chronisation. The ST24/25x08 are always slave
devices in all communications.

Start Condition . START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A ST AR T condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x08 con­tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.

Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi­nates communication between the ST24/25x08
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.

Acknowledge B it ( ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, eit her master or s lave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls t he SDA
bus low to acknowledge the receipt of the 8 bits of
data.

Data Input. During data input the ST24/25x08
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera­tion the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.

Memory Addressing. To start communication be­tween the bus master and the slave ST24/25x08,
the master must initiate a ST ART condition. Follow­ing this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.

Figure 3. Maximum RL Value versus Bus Capacitance (C

20

16

12

max (kΩ)

L

R

8

4

0

VCC = 5V

100 200 300 400

C

(pF)

BUS

) for an I2C Bus

BUS

V

CC

MASTER

SDA

SCL

R

R

BUS

L

C

BUS

AI01100

L

C

4/16

ST24/25C08, ST24/25W08

T able 5. Input Parameters

(1)

(TA = 25 °C, f = 100 kHz )

Symbol Parameter Test Condition Min Max Unit

C

IN

C

IN

Z

WCL

Z

WCH

t

LP

Note:

1. Sampled only, not 100% tested.

Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
WC Input Impedance (ST24/25W08) VIN ≤ 0.3 V
WC Input Impedance (ST24/25W08) VIN ≥ 0.7 V
Low-pass filter input time constant

(SDA and SCL)

CC

CC

520k

500 k

100 ns

T ab le 6. DC Characteristics
(T

= 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V or 2.5V to 5.5V)

A

Symbol Parameter Test Condition Min Max Unit

I

I

V

V

V

I

LI

I

LO

I

CC

CC1

CC2

V

V

OL

IL

IH

IL

IH

Input Leakage Current 0V ≤ VIN ≤ V
Output Leakage Current

Supply Current (ST24 series)
Supply Current (ST25 series) V

Supply Current (Standby)
(ST24 series)

Supply Current (Standby)
(ST25 series)

0V ≤ V

SDA in Hi-Z

V

= 5V, fC = 100kHz

CC

(Rise/Fall time < 10ns)

= 2.5V, fC = 100kHz 1 mA

CC

V

= VSS or VCC,

IN

V

CC

V

= VSS or VCC,

IN

V

= 5V, fC = 100kHz

CC

= VSS or VCC,

V

IN

V

CC

V

= VSS or VCC,

IN

V

= 2.5V, fC = 100kHz

CC

≤ VCC

OUT

= 5V

= 2.5V

CC

Input Low Voltage (SCL, SDA) –0.3 0.3 V
Input High Voltage (SCL, SDA) 0.7 V
Input Low Voltage

(E, PRE, MODE,

WC)

Input High Voltage
(E, PRE, MODE,

WC)

CC

–0.3 0.5 V

V

– 0.5 VCC + 1 V

CC

2

±

2

±

2mA

100

300

5

50

CC

VCC + 1 V

Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V
Output Low Voltage (ST25 series) I

= 2.1mA, VCC = 2.5V 0.4 V

OL

Ω
Ω

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

V

5/16

ST24/25C08, ST24/25W08

T ab le 7. AC Characteristics

(T

= 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V or 2.5V to 5.5V)

A

Symbol Alt Parameter Min Max Unit

t

CH1CH2

t

CL1CL2

t

DH1DH2

t

DL1DL1

(1)

t

CHDX

t

CHCL

t

DLCL

t

CLDX

t

CLCH

t

DXCX

t

CHDH

t

DHDL

(2)

t

CLQV

t

CLQX

f

C
(3)

t

W

Notes:

1. For a reSTART condition, or following a write cycle.

2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.

3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.

t

R

t

F

t

R

t

F

t

SU:STA

t

HIGH

t

HD:STA

t

HD:DAT

t

LOW

t

SU:DAT

t

SU:STO

t

BUF

t

AA

t

DH

f

SCL

t

WR

Clock Rise Time 1
Clock Fall Time 300 ns
Input Rise Time 1
Input Fall Time 300 ns
Clock High to Input Transition 4.7
Clock Pulse Width High 4
Input Low to Clock Low (START) 4
Clock Low to Input Transition 0
Clock Pulse Width Low 4.7
Input Transition to Clock Transition 250 ns
Clock High to Input High (STOP) 4.7
Input High to Input Low (Bus Free) 4.7
Clock Low to Next Data Out Valid 0.3 3.5
Data Out Hold Time 300 ns
Clock Frequency 100 kHz
Write Time 10 ms

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

T ab le 8. AC Measurement Conditions

Input Rise and Fall Times
Input Pulse Voltages 0.2V
Input and Output Timing Ref.

Voltages

50ns

≤

0.3V

to 0.8V

CC

to 0.7V

CC

CC

CC

Figure 4. AC Testing Input Output Waveforms

0.8V

6/16

0.2V

CC

CC

0.7V

0.3V

AI00825

CC

CC

DEVICE OPERATION (cont’d)
The 4 most significant bits of the device select code

are the device type identifier, corresponding to the

2

C bus definition. For these memories the 4 bits

I
are fixed as 1010b. The following bit identifies the
specific memory on the bus. It is matched to the
chip enable signal E. Thus up to 2 x 8K memories
can be connected on the same bus giving a mem­ory capacity total of 16 Kbits. After a START condi­tion any memory on the bus will identify the device
code and compare the following bit to its chip
enable input E.

The 6th and 7th bits sent, select the block number
(one block = 256 bytes). The 8th bit sent is the read
or write bit (R

W), this bit is set to ’1’ for read and ’0’
for write operations. If a match is found, the corre­sponding memory will acknowledge the identifica­tion on the SDA bus during the 9th bit time.

Figure 5. AC Waveforms

ST24/25C08, ST24/25W08

SCL

SDA IN

SCL

SDA OUT

SCL

tCHCL

tDLCL

tCHDX

START

CONDITION

tCLQV tCLQX

tCLDX

SDA

INPUT

DATA VALID

DATA OUTPUT

SDA

CHANGE

tW

tCLCH

tDXCX

tCHDH

tDHDL

STOP &

BUS FREE

SDA IN

tCHDH

STOP

CONDITION

Write Operations

The Multibyte Write mode (only available on the
ST24/25C08 versions) is selected when the MODE
pin is at V
pin is at V

and the Page Write mode when MODE

IH

. The MODE pin may be driven dynami-

IL

cally with CMOS input levels.
Following a START condition the master sends a

device select code with the R

W bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. The byte address of 8 bits provides ac­cess to one block of 256 bytes of the memory . After

tCHDX

WRITE CYCLE

START

CONDITION

AI00795B

receipt of the byte address the device again re­sponds with an acknowledge.

For the ST24/25W08 versions, any write command

WC = 1 will not modify the memory content.

with
Byte Write. In the Byte Write mode the master

sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition. The Write mode
is independant of the state of the MODE pin whic h
could be left floating if only this mode was to be
used. However it is not a recommended operating
mode, as this pin has to be connected to either V
or VIL, to minimize the standby current.

IH

7/16

ST24/25C08, ST24/25W08

Figure 6. I2C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

CONDITION

START

CONDITION

SDA

INPUT

1 23 789

MSB

1 23 789

MSB ACK

SDA

CHANGE

CONDITION

ACK

STOP

STOP

CONDITION

AI00792

Multibyte Write. For the Multibyte Write mode, the
MODE pin must be at V

. The Multibyte Write

IH

mode can be started from any address in the
memory . The master sends from one up to 8 bytes
of data, which are each acknowledged by the mem­ory. The transfer is terminat ed by the master gen­erating a STOP condition. The duration of the write
cycle is t

= 10ms maximum except when bytes

W

are accessed on 2 rows (that is have different
values for the 5 most significant addr ess bits A7­A3), the programming time is then doubled to a
maximum of 20ms. Writing more than 8 bytes in the
Multibyte Write mode may modify data bytes in an

8/16

adjacent row (one row is 16 bytes long). However,
the Multibyte Write can properly write up to 16
consecutive bytes only if the first address of these
16 bytes is the first address of the row, the 15
following bytes being written in the 15 following
bytes of this same row.

Page Wri te . For the Page Write mode the MODE
pin must be at V

. The Page Write mode allows up

IL

to 16 bytes to be written in a single write cycle,
provided that they are all located in the same ’row’
in the memory: that is the 4 most significant mem­ory address bits (A7-A4) are the same inside one
block. The master sends from one up to 16 bytes

ST24/25C08, ST24/25W08

of data, which are each acknowledged by the mem­ory . After each byte is transfered, the internal byte
address counter (4 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the
STOP condition starts the internal memory pro­gram cycle. All inputs are disabled until the comple­tion of this cycle and t he m emory will not respond
to any request.

Minimizing System Delays by Polling On ACK.

During the internal write cycle, the memory discon­nects itself from the bus in order to copy the data
from the internal latches to the m emory cells. The
maximum value of the write time (t

) is given in the

W

AC Characteristics table, since the t ypical time is
shorter, the time seen by the system may be re­duced by an ACK polling sequence issued by the
master.

Figure 8. Write Cycle Polling using ACK

WRITE Cycle

in Progress

Figure 7. Memory Protection

Page
pointer

b7 b2

3FFh

300h

Protect Flag
Enable = 0
Disable = 1

b4

0

XX

Block 3

Block 0

AI01121B

First byte of instruction
with RW = 0 already
decoded by ST24xxx

ReSTART

STOP

START Condition

DEVICE SELECT

with RW = 0

ACK

NO

Returned

YES

Next

Operation is

Addressing the

Memory

WRITE Operation

YESNO

Proceed

Send

Byte Address

Proceed

Random Address

READ Operation

AI01099B

9/16

ST24/25C08, ST24/25W08

Figure 9. Write Modes Sequence (ST24/25C08)

BYTE WRITE DEV SEL BYTE ADDR DATA IN

ACK ACK ACK

MULTIBYTE
AND
PAGE WRITE

R/W

START

ACK ACK ACK

DEV SEL BYTE ADDR

R/W

START

ACK ACK

DATA IN N

DATA IN 1 DATA IN 2

STOP

STOP

AI00793

DEVICE O PERATION (cont’d) boundary in steps of 16 bytes. The sequence to use

the Write Protected feature is:

The sequence is as follows:
– Initial condition: a Write is in progress (see Fig-

ure 8).

– Step 1: the Master issues a ST A R T condition

followed by a Device Select byte (1st byte of
the new instruction).

– Step 2: if the memory is busy with the internal

write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory
has terminated the internal write cycle, it will
respond with an ACK, indicating that the mem­ory is ready to receive the second part of the
next instruction (the first byte of this instruc­tion was already sent during Step 1).

Write Protection. Data in the upper block of 256
bytes of the memory may be write protected. The
memory is write protected between a boundary
address and the top of memory (address 3FFh)
when the PRE input pin is taken high and when the
Protect Flag (bit b2 in location 3FFh) is set to ’0’.
The boundary address is user defined by writing it
in the Block Address Pointer. The Block Address
Pointer is an 8 bit EEPROM regis ter located at the
address 3FFh. It is composed by 4 MSB s Addr ess
Pointer, which defines the bottom boundary ad­dress, and 4 LSBs which must be programmed at
’0’. This Address Pointer can therefore address a

– write the data to be protected into the top of

the memory , up to, but not including, location
3FFh;

– set the protection by writing the correct bottom

boundary address in the Address pointer (4
MSBs of location 3FFh) with the bit b2 (Protect
flag) set to ’0’.

Note that for a correct fonctionality of the memory,
all the 4 LSBs of the Block Address Pointer must
also be programmed at ’0’. The area will now be
protected when the PRE input pin is taken High.
While the PRE input pin is read at ’0’ by the mem­ory, the location 3FFh can be used as a normal
EEPROM byte.

Caution:

Special attention must be used when
using the protect mode together with the Multibyte
Write mode (MODE input pin High). If the Multibyte
Write starts at the location right below the first byte
of the Write Protected area, then the instruction will
write over the first 7 bytes of the Write Protected
area. The area protected is therefore smaller than
the content defined in the location 3FF h, by 7 bytes.
This does not apply to the Page Write mode as the
address counter ’roll-over’ and thus cannot go
above the 16 bytes lower boundary of the protected
area.

10/16

ST24/25C08, ST24/25W08

Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W08)

WC

ACK ACK NO ACK

BYTE WRITE DEV SEL BYTE ADDR DATA IN

R/W

START

WC

ACK ACK NO ACK

PAGE WRITE DEV SEL BYTE ADDR

R/W

START

WC (cont'd)

NO ACK NO ACK

PAGE WRITE
(cont'd)

DATA IN N

STOP

DATA IN 1

STOP

DATA IN 2

AI01161B

Read Operations

Read operations are independent of the state of the
MODE pin. On delivery , the mem ory content is set
at all "1’s" (or FFh).

Current Address Read. The memory has an inter­nal byte address counter . Each time a byte is read,
this counter is incremented. For the Current Ad­dress Read mode, following a START condition,
the master sends a memory address with the R

W
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter. This counter is then incremented.
The master does NOT acknowledge the byte out­put, but terminates the tr ansfer with a STOP con­dition.

Random Address Read. A dummy write is per­formed to load the address into the address counter
(see Figure 1 1). This is followed by another ST AR T
condition from the master and the byte address is
repeated with the R

W bit set t o ’1’. The memory
acknowledges this and outputs the byte ad­dressed. The master have to NOT acknowledge
the byte output, but terminates the transfer with a
STOP condition.

Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad­dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in s e­quence. To terminate the stream of bytes, the

11/16

ST24/25C08, ST24/25W08

DEVICE O PERATION (cont’d)

master must NOT acknowledge the last byte out­put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat­ically incremented after each byte output. After a
count of the last memory address, the address

Figure 11. Read Modes Sequence

ACK

CURRENT
ADDRESS
READ

RANDOM
ADDRESS
READ

DEV SEL DATA OUT

R/W

START

ACK

DEV SEL * BYTE ADDR

counter will ’roll-over’ and the memory will continue
to output data.

Acknowledge in Read Mode. In all re ad modes
the ST24/25x08 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24/25x08 terminate the
data transfer and switches to a standby state.

NO ACK

STOP

ACK ACK

DEV SEL * DATA OUT

NO ACK

SEQUENTIAL
CURRENT
READ

SEQUENTIAL
RANDOM
READ

R/W

START

ACK ACK ACK NO ACK

DEV SEL DATA OUT 1

R/W

START

ACK ACK

DEV SEL * BYTE ADDR

R/W

START

ACK NO ACK

DATA OUT N

STOP

R/W

START

DATA OUT N

ACK ACK

DEV SEL * DATA OUT 1

R/W

START

STOP

STOP

AI00794C

Note:

* The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.

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ORDERING INFORMATION SCHEME

Example: ST24C08 M 1 TR

ST24/25C08, ST24/25W08

Operating Voltage

ST24C08 3V to 5.5V
ST24W08 3V to 5.5V
ST25C08 2.5V to 5.5V
ST25W08 2.5V to 5.5V

Notes:

1. Temperature range on special request only.

Standard
Hardware Write Control
Standard
Hardware Write Control

Range

Package

B PSDIP8

0.25mm Frame

M SO8 150mil Width

Temperature Range

1 0 to 70 °C

(1)

5

–20 to 85 °C
6 –40 to 85 °C
3 –40 to 125 °C

Option

TR Tape & Reel

Packing

Devices are shipped from the factory with the memory content set at all "1’s" (FFh).

For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the STMicroelectronics Sales Office nearest to you. to you.

13/16

ST24/25C08, ST24/25W08

PSDIP8 - 8 pin Plastic S ki nny DIP, 0.25mm lead frame

Symb

Typ Min Max Typ Min Max

A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390

E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264

e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB – 10.00 – 0.394

L 3.00 3.80 0.118 0.150

N8 8

mm inches

Drawing is not to scale

14/16

A2

A1AL

B

e1

B1

D

N

C

eA
eB

E1 E

1

PSDIP-a

ST24/25C08, ST24/25W08

SO8 - 8 lead Plastic Small Outline, 150 mils body width

Symb

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e1.27– –0.050– –
H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α

N8 8

CP 0.10 0.004

mm inches

0

°

8

°

0

°

8

°

Drawing is not to scale

B

SO-a

h x 45˚

A

C

e

CP

D

N

E

H

1

LA1 α

15/16

ST24/25C08, ST24/25W08

Information furnished is believ ed to be accura te a nd rel i abl e. However, STMicroelec tronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and repl aces all information previously supplied. STMicroelectron ics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelect roni cs

© 1999 STMicroelectronics - All Rights Reserved

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