Page 1
1 MILLION ERASE /WRI T E CYCLES with
40 YEARS DATA RETENTION
SINGL E SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x01 versions
– 2.5V to 5.5V for ST25x01 versions
– 1.8V to 5.5V for ST24C01R version only
HARDWARE WRITE CONTROL VERSIONS:
ST24W01 and ST25W01
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 4
BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQ UE NTIA L READ
MODES
SELF TIME D PRO G RA MM ING CY C LE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD /LATCH UP
PERFORMA NCES
ST24C/W01 are replaced by the M24C01
ST25C/W01 are replaced by the M24C01-W
ST24C01R is replaced by the M24C01-R
DESCRIP TION
2
This specification cov ers a range of 1K bits I
C bus
EEPROM products, the ST24/25C01, the
ST24C01R and the ST24/ 25W01. In the tex t, products are referred to as ST24/25x01, where "x" is:
"C" for Standard version and "W" for hardware
Write Control version.
T able 1. Signal Names
ST24/25C01, ST24C01R
ST24/25W01
SERIAL 1K (128 x 8) EEPROM
NOT FOR NEW DESIGN
8
1
PSDIP8 (B)
0.25mm Frame
Figure 1. Logic Diag ra m
V
CC
3
E0-E2 SDA
ST24x01
SCL
MODE/WC*
ST25x01
ST24C01R
8
1
SO8 (M)
150mil Width
E0-E2 Chip Enable Inputs
SDA Serial Data Address Input/Output
SCL Serial Clock
MODE
WC Write Control (W version)
V
CC
V
SS
November 1997 1/16
This is information on a product still in production but not recommended for new design
Multibyte/Page Write Mode
(C version)
Supply Voltage
Ground
Note: WC signal is only available for ST24/25W01 products.
V
SS
AI00839D
Page 2
ST24/25C01, ST24C01R, ST24/25W01
Figure 2A. DIP Pin Connect io ns
ST24x01
ST25x01
ST24C01R
1
E0 V
2
3
E2
4
SS
T ab le 2. Absolut e Maximu m Ra t ings
Symbol Parameter Value Unit
T
T
T
STG
LEAD
Ambient Operating Temperature –40 to 125 °C
A
Storage Temperature –65 to 150 °C
Lead Temperature, Soldering (SO8 package)
8
7
6
5
AI00840D
CC
MODE/WCE1
SCL
SDAV
(1)
(PSDIP8 package)
Figure 2B. SO Pin Connecti ons
ST24x01
ST25x01
ST24C01R
E0 V
1
2
E2
SS
40 sec
10 sec
3
4
8
7
6
5
AI00841E
215
260
CC
MODE/WCE1
SCL
SDAV
°C
V
V
V
ESD
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
DESCRIP TION (co nt’d)
The ST24/25x01 are 1K bit electrically erasable
programmable memories (EEPROM), organized
as 128 x 8 bits. They are manufactured in SGSTHOMSON’s Hi-Endurance Advanced CMOS
technology which guarantees an endurance of one
million erase/write cycles with a data retention of
40 years. The memories operate with a power
supply value as low as 1.8V for the ST24C01R only .
Both Plastic Dual- in-Line and Plastic Small Out line
packages are available.
The memories are compatible with the I
Input or Output Voltages –0.6 to 6.5 V
IO
Supply Voltage –0.3 to 6.5 V
CC
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicat ed in the Operati ng sections of this specific ati on is not implied. Expos ure to Absolut e Maximum
Rating conditions for extended periods may affect device rel i abi lity. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
(2)
(3)
4000 V
500 V
tional data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I
2
C bus definition. This is used t ogether with 3 chip enable inputs
(E2, E1, E0) so that up to 8 x 1K devices may be
attached to the I
2
C bus and selected individually.
The memories behave as a s lave devic e in the I
protocol with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition generated by the
bus master . The START condition is followed by a
stream of 7 bits (identification code 1010), plus one
2
C stand-
read/write bit and terminated by an acknowledge
bit.
ard, two wire serial interface whic h uses a bi- direc-
2
C
2/16
Page 3
ST24/25C01, ST24C01R, ST24/25W01
T ab le 3. Device Select Co de
Device Code Chip Enable RW
Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 E2 E1 E0 R
Note: The MSB b7 is sent first.
W
T ab le 4. Operating Modes
Mode RW bit MODE Bytes Initial Sequence
Current Address Read ’1’ X 1 START, Device Select, R
Random Address Read
Sequential Read ’1’ X 1 to 128 Similar to Current or Random Mode
Byte Write ’0’ X 1 START, Device Select, R
Multibyte Write
Page Write ’0’ V
Notes: 1. X = VIH or V
2. Multibyte Write not available in ST24/25W01 versions.
(2)
IL
When writing data to the mem ory it responds to th e
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master , it acknowledges the receipt of the data
bytes in the same way. Data transfers are terminated with a STOP condition.
Power On Reset: V
CC
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the V
voltage has reached the POR threshold v alue, th e
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when V
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
must be applied before applying any logic signal.
SIGNAL DES CRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V
to act as a pull up (see Figure 3).
(1)
’0’
’1’ reSTART, Device Select, R
’0’ V
X1
IH
IL
4 START, Device Select, RW = ’0’
8 START, Device Select, RW = ’0’
START, Device Select, R
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory .
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A res istor must be connected from the SDA
to act as pull up (see Figure 3).
CC
lock out write protect. In
bus line to V
Chip Enable (E0 - E2). These chip enable inputs
are used to set the 3 least significant bits (b3, b2,
b1) of the 7 bit device select code. These inputs
CC
may be driven dynamically or t ied to VCC or VSS to
establish the device select code.
Mode (MO DE). T he MODE input is available on pin
drops down from the
CC
7 (see also
cally. It must be at V
mode, V
WC feature) and may be driven dynami-
for Multibyte Write mode or VIL for Page
IH
Write mode. When unconnected, the MODE input
CC
is internally read as V
Write Control (
feature (
WC) is offered only for ST24W01 and
WC). An hardware Write Control
ST25W01 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cy cle. The W rite Control s ig-
CC
nal is used to enable (
V
) the internal write protection. When uncon-
IL
nected, the
WC input is internally read as VIL and
W = ’1’
W = ’0’, Address,
W = ’1’
W = ’0’
or VIH for the Byte Write
IL
(Multibyte Writ e mode) .
IH
WC = VIH) or disable (WC =
the memory area is not write protected.
3/16
Page 4
ST24/25C01, ST24C01R, ST24/25W01
SIGNAL DESCRIPTION (cont’d)
The devices with this Write Control feature no
longer support the Multibyte Write mode of operation, however all other write modes are fully supported.
Refer to the AN404 Application Note for more detailed information about Write Contr ol feature.
DEVICE OPER ATION
2
C Bus Background
I
The ST24/25x01 support the I2C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device t hat reads
the data as a receiver . The device that c ontrols th e
data transfer is known as the master and the other
as the slave. The master will alway s initiate a dat a
transfer and will provide the serial clock for synchronisation. The ST24/25x01 are always slave
devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x01 continuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition terminates communication between the ST24/25x01
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter , either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input the ST24/25x01
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device operation the SDA signal must be stable during the c lock
low to high transition and the data must change
ONLY when the SCL line is lo w.
Memory Addressi ng. To start com munic ation between the bus master and the slave ST24/25x01,
the master must initiate a ST ART co ndition. Following this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.
Figure 3. Maximum RL Value versus Bus Capacitance (C
20
16
12
max (kΩ)
L
R
8
4
0
VCC = 5V
100 200 300 400
C
(pF)
BUS
) for an I2C Bus
BUS
V
CC
SDA
MASTER
SCL
R
R
BUS
L
C
BUS
AI01100
L
C
4/16
Page 5
ST24/25C01, ST24C01R, ST24/25W01
T able 5. Input Parameters
(1)
(TA = 25 °C, f = 100 kHz )
Symbol Parameter Test Condition Min Max Unit
C
IN
C
IN
Z
WCL
Z
WCH
t
LP
Note: 1. Sampled only, n ot 100% tested.
Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
WC Input Impedance (ST24/25W01) VIN ≤ 0.3 V
WC Input Impedance (ST24/25W01) VIN ≥ 0.7 V
Low-pass filter input time constant
(SDA and SCL)
CC
CC
520kΩ
500 kΩ
100 ns
T ab le 6. DC Characteristics
= 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
(T
A
Symbol Parameter Test Condition Min Max Unit
I
I
I
I
V
I
I
I
CC
CC1
CC2
CC3
CC4
V
V
V
V
LI
LO
IL
IH
IL
IH
Input Leakage Current 0V ≤ VIN ≤ V
Output Leakage Current
Supply Current (ST24 series)
Supply Current (ST25 series) V
Supply Current (Standby)
(ST24 series)
Supply Current (Standby)
(ST25 series)
Supply Current (Standby)
(ST24C01R)
Supply Current (Standby)
(ST24C01R)
0V ≤ V
SDA in Hi-Z
V
= 5V, fC = 100kHz
CC
(Rise/Fall time < 10ns)
= 2.5V, fC = 100kHz 1 mA
CC
= VSS or VCC,
V
IN
V
CC
V
= VSS or VCC,
IN
= 5V, fC = 100kHz
V
CC
= VSS or VCC,
V
IN
V
CC
V
= VSS or VCC,
IN
V
= 2.5V, fC = 100kHz
CC
= VSS or VCC,
V
IN
V
CC
V
= VSS or VCC,
IN
V
= 3.6V, fC = 100kHz
CC
V
= VSS or VCC,
IN
V
CC
V
= VSS or VCC,
IN
= 1.8V, fC = 100kHz
V
CC
≤ VCC
OUT
= 5V
= 2.5V
= 3.6V
= 1.8V
CC
Input Low Voltage (SCL, SDA) –0.3 0.3 V
Input High Voltage (SCL, SDA) 0.7 V
Input Low Voltage
(E0-E2, MODE,
WC)
Input High Voltage
(E0-E2, MODE,
WC)
CC
–0.3 0.5 V
V
– 0.5 VCC + 1 V
CC
Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V
OL
Output Low Voltage (ST25 series) I
Output Low Voltage
(ST24C01R)
= 2.1mA, VCC = 2.5V 0.4 V
OL
= 1mA, VCC = 1.8V 0.3 V
I
OL
±2 µA
±2 µA
2mA
100 µA
300 µA
5 µA
50 µA
20 µA
60 µA
10 µA
20 µA
CC
VCC + 1 V
V
5/16
Page 6
ST24/25C01, ST24C01R, ST24/25W01
T ab le 7. AC Characteristics
= 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
(T
A
Symbol Alt Parameter Min Max Unit
t
CH1CH2
t
CL1CL2
t
DH1DH2
t
DL1DL1
(1)
t
CHDX
t
CHCL
t
DLCL
t
CLDX
t
CLCH
t
DXCX
t
CHDH
t
DHDL
(2)
t
CLQV
t
CLQX
f
C
(3)
t
W
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted ST ART and/or STOP
conditions.
3. In the Multibyte Write m ode only , if accessed bytes are on two consecutiv e 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.
t
R
t
F
t
R
t
F
t
SU:STA
t
HIGH
t
HD:STA
t
HD:DAT
t
LOW
t
SU:DAT
t
SU:STO
t
BUF
t
AA
t
DH
f
SCL
t
WR
Clock Rise Time 1 µs
Clock Fall Time 300 ns
Input Rise Time 1 µs
Input Fall Time 300 ns
Clock High to Input Transition 4.7 µs
Clock Pulse Width High 4 µs
Input Low to Clock Low (START) 4 µs
Clock Low to Input Transition 0 µs
Clock Pulse Width Low 4.7 µs
Input Transition to Clock Transition 250 ns
Clock High to Input High (STOP) 4.7 µs
Input High to Input Low (Bus Free) 4.7 µs
Clock Low to Next Data Out Valid 0.3 3.5 µs
Data Out Hold Time 300 ns
Clock Frequency 100 kHz
Write Time 10 ms
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times ≤ 50ns
Input Pulse Voltages 0.2V
Input and Output Timing Ref. Voltages 0.3VCC to 0.7V
to 0.8V
CC
CC
CC
Figure 4. AC T estin g Inpu t Outp ut Waveforms
0.8V
6/16
0.2V
CC
CC
0.7V
0.3V
AI00825
CC
CC
DEVICE OPERATION (cont’d)
The 4 most significant bits of the devic e select code
are the device type identifier , corres ponding to the
2
C bus definition. For these memories the 4 bits
I
are fixed as 1010b. T he following 3 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1, E0. Thus up to 8 x
1K memories can be connected on the same bus
giving a memory capacity total of 8K bits. After a
ST AR T condition a ny memory on the bus will identify the device code and compare the following 3
bits to its chip enable inputs E2, E1, E0.
The 8th bit sent is the read or write bit (R
W), this
bit is set to ’1’ for read and ’0’ for write operations.
If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.
Page 7
Figure 5. AC Waveforms
ST24/25C01, ST24C01R, ST24/25W01
SCL
SDA IN
SCL
SDA OUT
SCL
tCHCL
tDLCL
tCHDX
START
CONDITION
tCLQV tCLQX
tDHDL
tCLDX
SDA
INPUT
DATA VALID
DATA OUTPUT
SDA
CHANGE
tW
tCLCH
tDXCX
tCHDH
tDHDL
STOP &
BUS FREE
SDA IN
tCHDH
STOP
CONDITION
WRITE CYCLE
tCHDX
START
CONDITION
AI00795
7/16
Page 8
ST24/25C01, ST24C01R, ST24/25W01
Figure 6. I2C Bus Protocol
SCL
SDA
SCL
SDA
SCL
SDA
START
CONDITION
START
CONDITION
SDA
INPUT
1 23 789
MSB
1 23 789
MSB ACK
SDA
CHANGE
CONDITION
ACK
STOP
STOP
CONDITION
Write Operations
The Multibyte Write mode (only available on the
ST24/25C01 and the ST24C01R versions) is selected when the MODE pin is at V
Write mode when MODE pin is at V
and the Page
IH
. The MODE
IL
pin may be driven dynamically with CMOS input
levels.
Following a START condition the master sends a
device select code with the R
W bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. The byte address of 7 bits (the Most
Significant Bit is ignored) provides access to any of
the 128 bytes of the memory. After receipt of the
byte address the device again responds with an
acknowledge.
8/16
AI00792
For the ST24/25W01 versions , any write command
WC = 1 (during a period of time from the
with
ST ART condition untill the end of the By te Address)
will not modify data and will NOT be acknowledged
on data bytes, as in Figure 9.
Byte Write. In the Byte Write mode the master
sends one data byte, w hich is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition. The Write mode
is independant of the state of the MODE pin which
could be left floating if only this mode was to be
used. However it is not a recommended operatin g
mode, as this pin has to be co nnected to either V
or VIL, to minimize the stand-by current.
IH
Page 9
ST24/25C01, ST24C01R, ST24/25W01
Multibyte W rite. For the Multiby te Write mode, t he
MODE pin must be at V
. The Multibyte Write
IH
mode can be started from any address in the
memory . The mast er sends from one up to 4 bytes
of data, which are each acknowledged by the memory. The transfer is terminated by the master generating a ST OP co ndition. The durat ion of the write
cycle i s t
= 10ms maximum except when bytes
W
are accessed on 2 rows (that is have different
values for the 5 most significant address bits A6A2), the programming time is then doubled to a
maximum of 20ms. Wr iting more than 4 bytes in th e
Multibyte W rite mode m ay modify data byt es in a n
adjacent row (one row is 8 bytes long). However,
the Multibyte Write can properly write up to 8
consecutive bytes only if the first address of these
8 bytes is the first address of the row , the 7 following
bytes being written in the 7 following bytes of this
same row.
Figure 7. Write Cycle Polling u sing A CK
WRITE Cycle
in Progress
START Condition
Page Write. For the Page Wr ite mode, the MODE
pin must be at V
. The Page Write mode allows up
IL
to 8 bytes to be written in a single write cycle,
provided that they are all locat ed in the s ame ’r ow’
in the memory: that is the 5 most significant memory address bits (A7-A3) are the s ame. The master
sends from one up to 8 bytes of data, which are
each acknowledged by the memory. After each
byte is transfered, the internal byte address count er
(3 least significant bits only) is incremented. The
transfer is terminated by the master generating a
STOP condition. Care must be taken to avoid address counter ’roll-over’ which could result in data
being overwritten. Note that, for any write mode,
the generation by the master of the STOP c ondition
starts the internal memory program cycle. All inputs
are disabled until the completion of this cycle and
the memory will not respond to any request.
First byte of instruction
with RW = 0 already
decoded by ST24xxx
ReSTART
STOP
DEVICE SELECT
with RW = 0
ACK
NO
Returned
YES
Next
Operation is
Addressing the
Memory
WRITE Operation
YESNO
Proceed
Send
Byte Address
Proceed
Random Address
READ Operation
AI01099B
9/16
Page 10
ST24/25C01, ST24C01R, ST24/25W01
Figure 8. Write Mod es Sequen ce (ST24/25C01 an d ST24C01R)
ACK ACK ACK
BYTE WRITE DEV SEL BYTE ADDR DATA IN
START
MULTIBYTE
AND
PAGE WRITE
DEV SEL BYTE ADDR
START
ACK ACK
DATA IN N
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory dis connects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (tW) is given in
the AC Character istics table, sinc e th e typical time
is shorter, the time seen by the system may be
reduced by an ACK polling sequence issued by the
master . The sequence is as follows:
– Initial c ondition: a Write is in progress (see Fig-
ure 7).
– Step 1: the Master issues a START condition
followed by a Device Select byte (1st byte of
the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no ACK will be returned and th e
master goes back to Step 1. If the memory
has terminated the internal write cycle, it will
respond with an ACK, indicating that the mem ory is ready to receive the second part of the
next instruct i on (the first byte of this ins truc tion was already sent during Step 1).
R/W
ACK ACK ACK
DATA IN 1 DATA IN 2
R/W
STOP
STOP
AI00793
Read Operations
Read operations are independent of the state of the
MODE pin. On delivery, the memory content is set
at all "1’s" (or FFh).
Current Address Read. T he memory has an internal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Address Read mode, following a START condition,
the master sends a memory address with the R
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter . This counter is then inc remented.
The master does NOT acknowledge the byte output, but terminates the transfer with a STOP condition.
Random Address Read. A dummy write is performed to load the address into the address
counter , see Figure 10. This i s followed by an other
START condition from the master and the byte
address is repeated with the R
W bit set to ’1’. The
memory acknowledges this and outputs the byte
addressed. The master have to NOT acknowledge
the byte output, but terminates the transfer with a
STOP condition.
W
10/16
Page 11
ST24/25C01, ST24C01R, ST24/25W01
Figure 9. Write Modes Seq uence w ith W rite Co n tro l = 1 (ST24/25W01)
WC
ACK ACK NO ACK
BYTE WRITE DEV SEL BYTE ADDR DATA IN
R/W
START
WC
ACK ACK NO ACK
PAGE WRITE DEV SEL BYTE ADDR DATA IN 1
R/W
START
WC (cont'd)
NO ACK NO ACK
PAGE WRITE
(cont'd)
DATA IN N
STOP
STOP
DATA IN 2
AI01161B
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Address Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in sequence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte output, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll- over’ and the memory will continue
to output data.
Acknowledge in Read Mode. In all read modes
the ST24/25x01 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24/25x01 terminate t he
data transfer and switches to a standby state.
11/16
Page 12
ST24/25C01, ST24C01R, ST24/25W01
Figure 10. Read Modes Sequ en ce
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
ACK
DEV SEL DATA OUT
R/W
START
ACK
DEV SEL * BYTE ADDR
R/W
START
ACK ACK ACK NO ACK
DEV SEL DATA OUT 1
R/W
START
ACK ACK
DEV SEL * BYTE ADDR
NO ACK
STOP
ACK ACK
DEV SEL * DATA OUT
R/W
START
DEV SEL * DATA OUT 1
NO ACK
STOP
DATA OUT N
STOP
ACK ACK
R/W
START
ACK NO ACK
DATA OUT N
STOP
Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.
START
R/W
AI00794C
12/16
Page 13
ORDERI NG INFO RM ATION SCH EM E
Example: ST24C01 M 1 TR
ST24/25C01, ST24C01R, ST24/25W01
Operating Voltage
ST24C01 3V to 5.5V
ST24W01 3V to 5.5V
ST25C01 2.5V to 5.5V
ST25W01 2.5V to 5.5V
ST24C01R 1.8V to 5.5V
Notes: 3 * Temperature range on special request only.
5 * Temperature range for ST24C01R only.
Standard
Hardware Write Control
Standard
Hardware Write Control
Standard
M SO8 150mil Width
Range
Package
B PSDIP8
0.25mm Frame
Temperature Range
1 0 to 70 °C
5 * –20 to 85 °C
6 –40 to 85 °C
3 * –40 to 125 °C
Option
TR Tape & Reel
Packing
Parts are shipped with the memory content set at all "1’s" (FFh).
For a list of available options (Operating Voltage, Range, Package, etc...) refer to the current Memory
Shortform catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.
13/16
Page 14
ST24/25C01, ST24C01R, ST24/25W01
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
Symb
Typ Min Max Typ Min Max
A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209
B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065
C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390
E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264
e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394
L 3.00 3.80 0.118 0.150
N8 8
PSDIP8
mm inches
Drawing is not to scale.
14/16
A2
A1AL
B
e1
B1
D
N
C
eA
eB
E1 E
1
PSDIP-a
Page 15
ST24/25C01, ST24C01R, ST24/25W01
SO8 - 8 lead Plastic Small Outline, 150 mils body width
Symb
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N8 8
CP 0.10 0.004
SO8
mm inches
Drawing is not to scale.
B
SO-a
h x 45˚
A
C
e
CP
D
N
E
H
1
LA1 α
15/16
Page 16
ST24/25C01, ST24C01R, ST24/25W01
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificat ions mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
© 1997 SGS-THOMSON Microelectronics - All Rights Reserved
2
Purchase of I
2
C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to
I
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
C Components by SGS-THOMSON Microelectronics, conveys a license under the Philips
2
C Standard Specifications as defined by Philips.
the I
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
16/16
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