Datasheet M24512 Datasheet (ST)

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M24512

512 Kbit Serial I²C Bus EEPROM

FEATURES SUMMARY

■ Two-Wire I

Supports 400 kHz Protocol

■ Supply Voltage Ranges:

– 1.8V to 5.5V (M24512 − R)
– 2.5V to 5.5V (M24512 − W)

■ Write Control Input

■ BYTE and PAGE WRITE (up to 128 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Timed Programming Cycle

■ Automatic Address Incr em ent ing

■ Enhanced ESD/Latch-Up Protection

■ More than 100,000 Erase/Write Cycles

■ More than 40-Year Data Retention

Table 1. M24512 devices

Reference Part Number

M24512

2

C Serial Interface

M24512 − W

M24512 − R

Figure 1. Packages

8

1

PDIP8 (BN)

8

1

SO8 (MW)

208 mil width

8

1

SO8 (MN)

150 mil width

TSSOP8 (DW)

1/24February 2005

M24512

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 1. M24512 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Write Control (WC
Figure 4. Maximum R
Figure 5. I

2

Table 3. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 5. Least Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Value versus Bus Parasitic Capacitance (C) for an I2C Bus . . . . . . . . . . . . 5

P

C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. Write Mode Sequences with WC

=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. Write Mode Sequences with WC

=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 8. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 9. Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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M24512

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 8. Operating Conditions (M24512 – W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 9. Operating Conditions (M24512 – R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 10. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 11. Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 12. DC Characteristics (M24512 – W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 13. DC Characteristics

Table 14. AC Characteristics (M24512 – W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 15. AC Characteristics

Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 18

Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data. . . . . . . . . . 18

Figure 13.SO8W – 8 lead Plastic Small Outline, 208 mils body width, Package Outline . . . . . . . . 19

Table 17. SO8W – 8 lead Plastic Small Outline, 208 mils body width, Package Mechanical Data. 19

Figure 14.SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package Outline. . . . . . . . . 20

Table 18. SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . 20

Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 21

Table 19. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 21

(1)

(M24512 – R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

(1)

(M24512 – R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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M24512

SUMMARY DESCRIPTION

These I2C-compatible electrically erasable pro­grammable memory (EEPROM) devices are orga­nized as 64K x 8 bits.

Figure 2. Logic Diagram

V

CC

3

E0-E2

SCL

WC

M24512

V

SS

Table 2. Signal Names

E0, E1, E2 Chip Enable

SDA

AI02275

ter. The Start condition is followed by a Device
Select Code and Read/Write

bit (RW) (as de­scribed in Table 3.), terminated by an acknowl­edge bit.

When writing data to the memory , the device in­serts an acknowled ge bit during the 9

th

bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledge s the rec eipt o f the d ata byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.

Power On Reset

In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included . At Power-up, the
device will not respond to any command until V

CC

has reached the Power On Rese t threshold volt­age (this threshold is lower than the V

min oper-

CC

ating voltage defined in Tables 8 and 9). In the
same way, as soon as V

drops from the normal

CC

operating voltage, below the Power On Reset
threshold voltage, the dev ice stops to respond to
any command.

Prior to selecting and issuing commands to the
memory, a valid and s table V

voltage must be

CC

applied. This voltage must remain stable and valid
until the end of t he transmiss ion of the command
and, for a Write instruction, until the completion of
the internal write cycle (t

).

W

SDA Serial Data
SCL Serial Clock
WC
V

CC

V

SS

2

I

C uses a two-wire serial interf ace, comprisi ng a

Write Control
Supply Voltage
Ground

bi-directional data line and a clock line. The devic­es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I

The device behaves as a slave in the I

2

C bus definition.

2

C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat­ed by a Start condition, generated by the bus mas-

Figure 3. DIP, SO and TSSOP Connections

M24512

E0 V

E2

SS

Note: See PACKAGE MECHANICAL section for package dimen-

sions, and how to identify pin-1.

1
2
3
4

AI04035B

8
7
6
5

CC

WCE1
SCL
SDAV

4/24

SIGNAL DESCRIPTION

Serial Clock (SCL). This input signal is used to

strobe all data in and out of the device. In applica­tions where this signal is used by slave devices to
synchronize the bus to a slower clock, the bus
master must have an open drain output, and a
pull-up resistor must be connected from Serial
Clock (SCL) to V
value of the pull- up resi stor can be calc ulate d). In
most applications, though, this method of synchro­nization is not employed, and so the pull-up resis­tor is not necessary, pro vided that the bus master
has a push-pull (rather than open drain) output.

Serial Data (SDA). This bi-directional signal is
used to transfer data in or out of the device. It is an
open drain output that may be wire-OR’ed with
other open drain or ope n collector signals on the
bus. A pull up resistor must be connected from Se­rial Data (SDA) to V
the value of the pull-up resistor can be calculated).

. (Figure 4. indicates how the

CC

. (Figure 4. indicates how

CC

M24512

Chip Enable (E0, E1, E2). These input signals

are used to set the value that is to be looked for on
the three least significant bits (b3, b2, b1) of the 7­bit Device Select Code. These inputs must be tied
to V
Code. When not connected (left floating), these in­puts are read as Low (0,0,0).

Write Control (WC

for protecting the entire content s of the memory
from inadvertent write operations. Write opera­tions are disabled to the entire memory array when
Write Control (WC
nected, the signal is internally read as V
Write operations are allowed.

When Write Contr ol (WC
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.

or VSS, to establish the Device Select

CC

). This input signal is useful

) is driven High. When uncon-

) is driven High, Device

, and

IL

Figure 4. Maximum R

20

16

12

8

Maximum RP value (kΩ)

4

0

10

Value versus Bus Parasitic Capacitance (C) for an I2C Bus

P

V

CC

SDA

fc = 400kHz

100

C (pF)

fc = 100kHz

MASTER

1000

SCL

R

R

P

P

C

C

AI01665b

5/24

M24512

Figure 5. I2C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

Condition

START

Condition

1 23 7 89

MSB

1 23 7 89

MSB

SDA
Input

SDA

Change

STOP

Condition

ACK

ACK

STOP

Condition

AI00792B

Table 3. Device Select Code

Device Type Identifier

1

Chip Enable Address

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code1010E2E1E0RW

Note: 1. The most significant bit, b7, is sent first.

2. E0, E1 and E2 are compared against the respective external pins on the memory device.

2

RW

Table 4. Most Significant Byte Table 5. Least Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

6/24

DEVICE OPERATION

The device supports the I2C protocol. This is sum­marized in Figure 5.. Any device that sends d ata
on to the bus is defined to be a transmitter, and
any device that reads the data to be a rec eiver.
The device that controls the data transfer is known
as the bus master, an d th e other a s the s lave de­vice. A data transfer can only be initiated by the
bus master, which will also provide the serial clock
for synchronization. The M24512 device is always
a slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command . The device continuou sly
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.

Stop Condition

Stop is identified by a rising edge of Serial Data
(SDA) while Serial Cloc k (S CL) is s tab le a nd d ri v­en High. A Stop condition t ermi nate s co mm uni ca ­tion between the device and the bus master. A
Read command that is follow ed by NoA ck can be
followed by a Sto p condition to force the device
into the Stand-by mode. A S top condition at the
end of a Write command triggers the internal Write
cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a success­ful byte transfer. The bus transmitter, whether it be
bus master or sl ave device, releas es Serial Data
(SDA) after sending ei ght bits of da ta. During the

th

9

clock pulse period, the receiver pulls Serial

M24512

Data (SDA) Low to acknowledge the receipt of the
eight data bits.

Data Input

During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change
en Low.

Memory Addressing

To start communica tion between the bus master
and the slave device, the b us mas ter m u st ini ti ate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 3.
(on Serial Data (SDA), most significant bit first).

The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4­bit Device Type Identifier is 1010b.

Up to eight memory devices can be connected on
a single I
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received, the de­vice only respond s if the Chip Enabl e Address is
the same as the value on the Chip Enable (E0, E1,
E2) inputs.

th

The 8
set to 1 for Read and 0 for Write operations.

If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) du ring the 9
device does not match the Devic e Select code, it
deselects itself from the bus, and goes into Stand­by mode.

only

when Serial Cl ock ( SCL ) i s dr iv-

2

C bus. Each one is gi ven a un ique 3-bit

bit is the Read/Write bit (RW). This bit is

th

bit time. If the

Table 6. Operating Modes

Mode RW bit

Current Address Read 1 X 1 START, Device Select, RW

Random Address Read

Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0
Page Write 0

Note: 1. X = V

IH

or V

.

IL

0X
1 X reSTART, Device Select, RW

WC

V
V

1

IL

IL

Bytes Initial Sequence

= 1

1

START, Device Select, RW

1 START, Device Select, RW = 0

≤ 128 START, Device Select, RW = 0

= 0, Address

= 1

7/24

M24512

Figure 6. Write Mode Sequences with WC=1 (data write inhibited)

WC

ACK ACK ACK NO ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

R/W

START

WC

ACK ACK ACK NO ACK

PAGE WRITE DEV SEL BYTE ADDR

R/W

START

WC (cont'd)

NO ACK NO ACK

PAGE WRITE
(cont'd)

DATA IN N

STOP

BYTE ADDR DATA IN 1

STOP

DATA IN 2

AI01120C

Write Operations

Following a Start co ndition the bus mas ter sends
a Device Select Code with the Read/Write
(RW

) reset to 0. The device acknowledges this, as

bit

shown in Figure 7., and waits for two address
bytes. The devi ce res ponds to e ach addres s by te
with an acknowledge bit, and then waits for the
data byte.

Writing to the memory may be inhibited if Write
Control (WC
with Write Control (WC

) is driven Hi gh. Any W rite instruction

) driven High (duri ng a pe ­riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are

not

acknowledged, as shown in Figure 6..

Each data byte in the memory ha s a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-

ble 4.) is sent first, foll owed by the Least Signifi-

cant Byte (Table 5.). Bits b15 to b0 form the
address of the byte in memory.

8/24

When the bus master gener ates a Stop conditi on
immediately after t he Ac k bi t (i n th e “1 0

th

bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal Write cycle is tri ggere d. A St op
condition at any other time slot does not trigger the
internal Write cycle.

After the Stop condition, the delay t

, and the suc-

W

cessful completion of a Write operation, the de­vice’s internal address counter is incremented
automatically, to point to the next byte address af­ter the last one that was modified.

During the internal Write cycl e, Serial Data (SDA)
is disabled intern ally, a nd the devic e does n ot re­spond to any requests.

Byte Write

After the Device Select code and the address
bytes, the bus mas ter sends one d ata byte. If the
addressed location is Write-protected, by Write
Control (WC

) being driven High, the device replies
with NoAck, and the location is not modified. If, in­stead, the addressed location is not Write-protect-

M24512

ed, the device replies with Ack. The bus master
terminates the transf er by gener ating a St op con­dition, as shown in Figure 7.

Page Write

The Page Write mode allows up to 128 bytes to be
written in a single Wr ite cycle, provided tha t they
are all located in th e same ’row’ in the memory:
that is, the most significant m emory address bits
(b15-b7) are the same. If more bytes are sent than
will fit up to the end of the row, a condi tion kn own
as ‘roll-over’ occ urs. This should be avoided, as

Figure 7. Write Mode Sequences with WC

WC

BYTE WRITE DEV SEL BYTE ADDR

START

WC

=0 (data write enabled)

ACK

R/W

data star ts t o be com e ov erwr itt en i n a n imp lem en­tation dependent way.

The bus master sends from 1 to 128 bytes of data,
each of which is acknowledged by the device if
Write Control (WC

) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca­tion are not modified, and each data byte is fol­lowed by a NoAck. After each byte is transferred,
the internal byte add ress cou nter (th e 7 leas t sig­nificant address bits only) is incremented. The
transfer is termina ted by the bus master gener at­ing a Stop condition.

ACK ACK ACK

BYTE ADDR DATA IN

STOP

ACK ACK ACK ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

R/W

START

WC (cont'd)

ACKACK

PAGE WRITE
(cont'd)

DATA IN N

STOP

DATA IN 2

AI01106C

9/24

M24512

Figure 8. Write Cycle Polling Flowchart using ACK

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

ACK

NO

Returned

First byte of instruction
with RW = 0 already
decoded by the device

ReSTART

STOP

YES

Next

Operation is

Addressing the

Memory

DATA for the

WRITE Operation

Continue the

WRITE Operation

Minimizing System Delays by Polling On ACK

During the internal Write cycle, the device discon­nects itself from the bus, an d writes a copy of the
data from its internal lat ches to the me mory ce lls.
The maximum Write time (t

) is shown in Table

w

14., but the typical time is shorter. To make use of

this, a polling sequence can be us ed by the bus
master.

The sequence, as shown in Figure 8., is:

YESNO

Send Address

and Receive ACK

START

Condition

YESNO

DEVICE SELECT

with RW = 1

Continue the

Random READ Operation

AI01847C

– Initial condition: a Write cycle is in progress.
– Step 1: the bus master issues a Start condition

followed by a Device Select Code (the first
byte of the new instruction).

– Step 2: if the device is busy with the internal

Write cycle, no Ack will be returned and the
bus master goes back to Step 1. If the device
has terminated the internal Write cycle, it
responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).

10/24

Figure 9. Read Mode Sequences

M24512

CURRENT
ADDRESS
READ

RANDOM
ADDRESS
READ

SEQUENTIAL
CURRENT
READ

SEQUENTIAL
RANDOM
READ

ACK

DEV SEL DATA OUT

R/W

START

ACK

DEV SEL * BYTE ADDR BYTE ADDR

R/W

START

ACK ACK ACK NO ACK

DEV SEL DATA OUT 1

R/W

START

ACK ACK ACK

DEV SEL * BYTE ADDR BYTE ADDR

NO ACK

STOP

ACK ACK ACK

DEV SEL * DATA OUT

R/W

START

DATA OUT N

STOP

ACK ACK

DEV SEL * DATA OUT 1

NO ACK

STOP

R/W

START

ACK NO ACK

DATA OUT N

STOP

Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical.

Read Operations

Read operations are per formed independently of
the state of the Write Control (WC

) signal.

After the successful completion of a Read opera­tion, the device’s internal address counter is incre­mented by one, to point to the next byte address.

Random Address Read

A dummy Write is fi rst performed to load th e ad­dress into this addres s counter (as s hown in Fig-

ure 9.) but

without

sending a Stop condition. Then,
the bus master sends another Start condition, and
repeats the Device Select Code, with the Read/
Write

bit (RW) set to 1. The dev ice ac kn owle dge s

this, and outputs the contents of the addressed
byte. The bus ma ster must
byte, and terminates the transfe r with a Stop con ­dition.

Current Address Read

For the Current Address Read operation, following
a Start condition, the bus master only sends a De­vice Select Code with the Read/Write
to 1. The device acknowle dges this, and outputs
the byte addressed by the internal address
counter. The counter is then incremented. The bus
master terminates th e transfer with a S top condi­tion, as shown in Figure 9.,
the byte.

START

R/W

AI01105C

not

acknowledge the

bit (RW) set

without

acknowledging

11/24

M24512

Sequential Read

This operation can be used after a Current Ad­dress Read or a Random Address Read. The bus
master
and sends additional cloc k pulses so that the de­vice continues to output the next byte in sequence.
To terminate the s tream of by tes, the bu s master
must
generate a Stop condition, as shown in Figure 9.

The output data comes from consecutive address­es, with the internal address counter automatically
incremented after e ach byte outpu t. After the la st
memory address, the addres s cou nter ‘r ol ls- ov er ’,
and the device continues to output data from
memory address 00h.

does

acknowledge the data byte output,

not

acknowledge the last byte, and

must

Acknowledge in Read Mode

For all Read commands, the device waits, after
each byte read, for an acknowledgment during the

th

9

bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi­nates the data transfer and switches to its Stand ­by mode.

INITIAL DELIVERY STATE

The device is delivered with all bits in the memory
array set to 1 (each byte contains FFh).

12/24

M24512

MAXIMUM RATING

Stressing the devi ce outside the ratings li sted in

Table 7. may cause permanent damage to the de-

vice. These are stress ratings only, and oper ation
of the device at these, or any other conditions out­side those indicated in the Oper ating sections of

Table 7. Absolute Maximum Ratings

Symbol Parameter Min. Max. Unit

T

A

T

STG

T

LEAD

V

IO

V

CC

V

ESD

Note: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and

the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU

2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A1 14A, C1=100pF, R1=1500Ω, R2=500Ω)

Ambient Operating Temperature –40 125 °C
Storage Temperature –65 150 °C
Lead Temperature during Soldering
Input or Output range –0.50 6.5 V
Supply Voltage –0.50 6.5 V

Electrostatic Discharg e Voltage (Human Body mode l)

this specificatio n, is not implied. Exposure to Ab­solute Maximum Rating conditions for extended
periods may affect de vice rel iability. Refer also to
the STMicroelectroni cs SURE Program and othe r
relevant quality documents.

See note

2

–4000 4000 V

(1)

°C

13/24

M24512

DC AND AC PARAMETERS

This section summ arizes the operati ng and mea­surement conditions , and the D C an d AC charac ­teristics of the device. The parameters in th e DC
and AC Characteristic tables that follow are de­rived from tests performed under the Measure-

Table 8. Operating Conditions (M24512 – W)

Symbol Parameter Min. Max. Unit

ment Conditions summarized in the relevant
tables. Designers sho uld c heck tha t th e operating
conditions in thei r circui t match the measur ement
conditions when relying on the quoted parame­ters.

V

CC

T

A

Supply Voltage 2.5 5.5 V
Ambient Operating Temperature –40 85 °C

Table 9. Operating Conditions (M24512 – R)

Symbol Parameter Min. Max. Unit

V

CC

T

A

Supply Voltage 1.8 5.5 V
Ambient Operating Temperature –40 85 °C

Table 10. AC Measurement Conditions

Symbol Parameter Min. Max. Unit

C

L

Load Capacitance 100 pF
Input Rise and Fall Times 50 ns

0.2V

0.3V

to 0.8V

CC

to 0.7V

CC

CC

CC

Input Levels
Input and Output Timing Referen ce Le ve ls

Figure 10. AC Measurement I/O Waveform

V
V

14/24

Input Levels

0.8V

CC

0.2V

CC

Input and Output

Timing Reference Levels

0.7V

CC

0.3V

CC

AI00825B

M24512

Table 11. Input Parameters

Symbol

C

IN

C

IN

(3)

Z

L

(3)

Z

H

t

NS

Note: 1. TA = 25 °C, f = 400 kHz

2. Sampled only, not 100% tested.

3. E2,E1,E0: Input impedance when the memor y is selected (after a Start condition).

Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
Input Impedance

(E2, E1, E0, WC
Input Impedance

(E2, E1, E0, WC
Pulse width ignored

(Input Filter on SCL and SDA )

Parameter

Table 12. DC Characteristics (M24512 – W)

Symbol Parameter Test Condition Min. Max. Unit

Input Leakage Current

I

LI

(SCL, SDA, E0, E1, E2)

I

I

I

CC1

V

V

V

Note: 1. When the device is selected (after a START condition), the Ei inputs have a different input impedance, as defined in Table 11.

Output Leakage Current

LO

Supply Current

CC

Stand-by Supply Current

Input Low Voltage

IL

(SCL, SDA, WC
Input High Voltage

IH

(SCL, SDA, WC
Output Low Voltage

OL

(1,2)

)

)

Test Condition Min. Max. Unit

VIN < 0.3V

> 0.7V

V

IN

CC

CC

30 kΩ

500 kΩ

Single glitch 100 ns

V

= VSS or V

IN

device in Standby mode

V

= VSS or V

OUT

V

= 2.5V, fc=400kHz (rise/fall time < 30ns)

CC

= 5.5V, fc=400kHz (rise/fall time < 30ns)

V

CC

V

= VSS or V

IN

V

= VSS or V

IN

)

)

I

= 2.1 mA , VCC = 2.5 V

OL

SDA in Hi-Z

CC,

, V

CC

CC

, V

CC

CC

CC

(1)

± 2 µA

± 2 µA

1mA
2mA

= 2.5 V

2µA

= 5.5 V 5 µA

CC

0.3V

VCC+1

CC

–0.45

0.7V

0.4 V

V

V

Table 13. DC Characteristics

(1)

(M24512 – R)

Symbol Parameter Test Condition Min. Max. Unit

V

Input Leakage Current

I

LI

(SCL, SDA, E2, E1, E0)

I

I

I

CC1

V
V

V

Note: 1. The information contained in Ta ble 13. is related to the new M24512 (process letter “A”) and is subject to change without previo us

Output Leakage Current

LO

Supply Current

CC

Standby Supply Current
Input Low Voltage –0.45

IL

Input High Voltage

IH

Output Low Voltage

OL

notice.

device in Stand-by mode

V

OUT

V

=1.8V, fc = 400kHz (rise/fall time <

CC

V

IN

I

= VSS or V

IN

= VSS or V

CC

SDA in Hi-Z

CC,

30ns)

= VSS or V

= 0.7 mA, VCC = 1.8 V

OL

CC

, V

CC

= 1.8 V

0.7V

CC

± 2 µA

± 2 µA

1mA

2µA

0.3 V
VCC+1

CC

V
V

0.2 V

15/24

M24512

Table 14. AC Characteristics (M24512 – W)

Symbol Alt. Parameter Min. Max. Unit

f

C

t

CHCL

t

CLCH

t

CH1CH2

t

CL1CL2

(2)

t

DH1DH2

(2)

t

DL1DL2

t

DXCX

t

CLDX

t

CLQX

(3)

t

CLQV

(1)

t

CHDX

t

DLCL

t

CHDH

t

DHDL

t

W

Note: 1. For a reSTART condition, or following a Write cycl e.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP co nditions, a minimum delay is placed bet ween SCL=1 and the falling or risin g edge of SDA.

4. For M24512 devices whose package marking shows the process letter “A” t
package marking shows the proces s let ter “V” t

f

SCL

t

HIGH

t

LOW

t

R

t

F

t

R

t

F

t

SU:DAT

t

HD:DAT

t

DH

t

AA

t

SU:STA

t

HD:STA

t

SU:STO

t

BUF

t

WR

Clock Frequency 400 kHz
Clock Pulse Width High 600 ns
Clock Pulse Width Low 1300 ns
Clock Rise Time 300 ns
Clock Fall Time 300 ns
SDA Rise Time 20 300 ns

SDA Fall Time 20 300 ns
Data In Set Up Time 100 ns
Data In Hold Time 0 ns
Data Out Hold Time 200 ns
Clock Low to Next Data Valid (Access Time) 200 900 ns
Start Condition Set Up Time 600 ns
Start Condition Hold Time 600 ns
Stop Condition Set Up Time 600 ns
Time between Stop Condition and Next Start Condition 1300 ns
Write Time

(max) = 10ms

W

(max) = 5ms whereas for M24512 devices whose

W

5 or 10

(4)

ms

Table 15. AC Characteristics

(1)

(M24512 – R)

Symbol Alt. Parameter Min. Max. Unit

f

C

t

CHCL

t

CLCH

(3)

t

DL1DL2

t

DXCX

t

CLDX

t

CLQX

(4)

t

CLQV

(2)

t

CHDX

t

DLCL

t

CHDH

t

DHDL

t

W

Note: 1. The information contained in Ta ble 15. is related to the new M24512 (process letter “A”) and is subject to change without previo us

notice.

2. For a reSTART condition, or following a Write cycle.

3. Sampled only, not 100% tested.

4. To avoid spurious START and STOP co nditions, a minimum delay is placed bet ween SCL=1 and the falling or risin g edge of SDA.

f

SCL

t

HIGH

t

LOW

t

t

SU:DAT

t

HD:DAT

t

DH

t

AA

t

SU:STA

t

HD:STA

t

SU:STO

t

BUF

t

WR

Clock Frequency 400 kHz
Clock Pulse Width High 600 ns
Clock Pulse Width Low 1300 ns
SDA Fall Time 20 300 ns

F

Data In Set Up Time 100 ns
Data In Hold Time 0 ns
Data Out Hold Time 200 ns
Clock Low to Next Data Valid (Access Time) 200 900 ns

Start Condition Set Up Time 600 ns
Start Condition Hold Time 600 ns
Stop Condition Set Up Time 600 ns
Time between Stop Condition and Next Start Condition 1300 ns
Write Time 10 ms

16/24

Figure 11. AC Waveforms

M24512

SCL

SDA In

SCL

SDA In

SCL

tCHCL

tDLCL

tCHDX

START

Condition

tCHDH

STOP

Condition

tCLQV tCLQX

SDA

Input

tCLCH

SDA

Change

tW

Write Cycle

tDXCXtCLDX

tCHDH tDHDL

tCHDX

START

Condition

STOP

Condition

START

Condition

SDA Out

Data Valid

AI00795C

17/24

M24512

PACKAGE MECHANICAL

Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline

b2

A2

A1AL

be

D

8

E1

1

Note: Drawing is not to scale.

E

c

eA
eB

PDIP-B

Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A5.330.210
A1 0.38 0.015
A2 3.30 2.92 4.95 0.130 0.115 0.195

b 0.46 0.36 0.56 0.018 0.014 0.022
b2 1.52 1.14 1.78 0.060 0.045 0.070

c 0.25 0.20 0.36 0.010 0.008 0.014

D 9.27 9.02 10.16 0.365 0.355 0.400

E 7.87 7.62 8.26 0.310 0.300 0.325
E1 6.35 6.10 7.11 0.250 0.240 0.280

e 2.54 – – 0.100 – –
eA 7.62 – – 0.300 – –
eB 10.92 0.430

L 3.30 2.92 3.81 0.130 0.115 0.150

millimeters inches

18/24

Figure 13. SO8W – 8 lead Plastic Small Outline, 208 mils body width, Package Outline

M24512

Note: Drawing is not to scale.

A2

B

e

D

N

1

SO-b

CP

E

H

A

C

LA1 α

Table 17. SO8W – 8 lead Plastic Small Outline, 208 mils body width, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A2.030.080
A1 0.10 0.25 0.004 0.010
A2 1.78 0.070

B 0.35 0.45 0.014 0.018

C 0.20 – – 0.008 – –
D 5.15 5.35 0.203 0.211

E 5.20 5.40 0.205 0.213

e 1.27 – – 0.050 – –

H 7.70 8.10 0.303 0.319

L 0.50 0.80 0.020 0.031

α 0° 10° 0° 10°

N8 8

CP 0.10 0.004

millimeters inches

19/24

M24512

Figure 14. SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package Outline

h x 45˚

A2

A

C

B

e

ddd

D

8

E

H

1

Note: Drawing is not to scale.

LA1 α

SO-A

Table 18. SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197

ddd 0.10 0.004

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α 0° 8° 0° 8°

N8 8

millimeters inches

20/24

Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline

D

M24512

8

5

c

EE1

1

4

α

A1

A2A

CP

eb

Note: Drawing is not to scale.

L

L1

TSSOP8AM

Table 19. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413

b 0.190 0.300 0.0075 0.0118

c 0.090 0.200 0.0035 0.0079

CP 0.100 0.0039

D 3.000 2.900 3.100 0.1181 0.1142 0.1220

e 0.650 – – 0.0256 – –

E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772

L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394

α 0° 8° 0° 8°

N8 8

millimeters inches

21/24

M24512

PART NUMBERING

Table 20. Ordering Information Scheme

Example: M24512 – W MW 6 T P

Device Type

2

M24 = I

Device Function

512 = 512 Kbit (64K x 8)

Operating Voltage

W = V
R = V

Package

BN = PDIP8
MW = SO8 (208 mil width)
MN = SO8 (150 mil body width)
DW = TSSOP8

C serial access EEPROM

= 2.5 to 5.5V

CC

= 1.8 to 5.5V

CC

Device Grade

6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow

Option

blank = Standard Packing
T = Tape and Reel Packing

Plating Technology

blank = Standard SnPb plating
P or G = Lead-Free and RoHS compliant

For a list of available options (speed, package,
etc.) or for further information on any aspect of this

device, please conta ct yo ur nearest ST Sal es Of­fice.

22/24

REVISION HISTORY

Table 21. Document Revision History

Date Revision Description of Revision

Lead Soldering Temperature in the Absolute Maximum Ratings table amended

29-Jan-2001 1.1

10-Apr-2001 1.2

16-Jul-2001 1.3 LGA8 Package given the designator “LA”

02-Oct-2001 1.4 LGA8 Package mechanical data updated

13-Dec-2001 1.5

12-Jun-2001 1.6 Document promoted to Full Datasheet

22-Oct-2003 2.0

02-Sep-2004 3.0

22-Feb-2005 4.0

Write Cycle Polling Flow Chart using ACK illustration updated
LGA8 and SO8(wide) packages added
References to PSDIP8 changed to PDIP8, and Package Mechanical data updated

LGA8 Package Mechanical data and illustration updated
SO16 package removed

Document becomes Preliminary Data
Test conditions for ILI, ILO, ZL and ZH made more precise
VIL and VIH values unified. tNS value changed

Table of contents, and Pb-free options added. Minor wording changes in Summary
Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations.

(min) improved to –0.45V.

V

IL

LGA8 package is Not for New Design. 5V and -S supply ranges, and Device Grade 5
removed. Absolute Maximum Ratings for V

IO

temperature information clarified for RoHS compliant devices. Device grade information
clarified. AEC-Q100-002 compliance. V

specification unified for SDA, SCL and WC

IL

INITIAL DELIVERY STATE is FFh (not necessarily the same as Erased).

LGA package removed, TSSOP8 and SO8N packages added (see PACKAGE

MECHANICAL section and Table 20., Ordering Information Scheme).

Voltage range R (1.8V to 5.5V) also offered. Minor wording changes.

Test Conditions modified in Table 11., Input Parameters and Not e 3. added.

Z

L

I

CC

and I

values for VCC = 5.5V added to Table 12., DC Characteristics (M24512 – W).

CC1

Note added to Table 12., DC Characteristics (M24512 – W).

Power On Reset paragraph specified.

max value modified in Table 14., AC Characte ris tic s (M2 451 2 – W) and note 4 added.

t

W

Plating technology changed in Table 20., Ordering Information Scheme.
Resistance and capacitance renamed in Figure 4.,Maximum R

2

Parasitic Capacitance (C) for an I

C Bus.

M24512

(min) and VCC(min) changed. Soldering

Value versus Bus

P

23/24

M24512

Information furnished is be lieved to be a ccur ate and reli able. Howe ver, STMicroele ctronic s assu mes no r esponsib ilit y for th e consequences
of use of such information nor for any infrin gement of patent s or other rights of third parties which ma y result from it s use. No license is granted

by implication or otherwi se under any patent or patent rights of STMicroelectronic s. Specifications mentioned in this publication ar e subject

to change without not ice. This pub licat ion su persed es and repl aces all in format ion previou sly su pplie d. STMicroele c tronic s prod ucts ar e no t

authorized for use as critical compone nts in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

ECOPACK is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

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24/24