Datasheet M24256B-W, M24256B, M24128B-W, M24128B Datasheet (SGS Thomson Microelectronics)

1/19

PRELIMINARY DATA

February 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M24256-B
M24128-B

256/128 Kbit SerialI C Bus EEPROM

With Three Chip Enable Lines

■ Compatible with I

2

C Extended Addressing

■ Two Wire I

2

C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 4.5V to 5.5V for M24xxx-B
– 2.5V to 5.5V for M24xxx-BW
– 1.8V to 3.6V for M24xxx-BR

■ Hardware Write Control

■ BYTE and PAGE WRITE (up to 64 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Timed Programming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ 100000 Erase/Write Cycles (minimum)

■ 40 Year Data Retention (minimum)

DESCRIPTION

These I2C-compatible electrically erasable pro­grammable memory (EEPROM) devices are orga­nized as 32Kx8 bits (M24256-B) and 16Kx8 bits
(M24128-B).

These memory devices are compatible with the
I2C extended memory standard. Thisis a two wire
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4­bit unique Device Type Identifier code (1010) in
accordance with the I2C bus definition.

Figure 1. Logic Diagram

AI02809

SDA

V

CC

M24256-B
M24128-B

WC

SCL

V

SS

3

E0-E2

Table 1. Signal Names

E0, E1, E2 Chip Enable Inputs
SDA Serial Data/Address Input/

Output
SCL Serial Clock
WC Write Control
V

CC

Supply Voltage
V

SS

Ground

PSDIP8 (BN)

0.25 mm frame

SO8 (MN)

150 mil width

TSSOP8(DW)

169 mil width

8

1

8

1

8

1

TSSOP14 (DL)

169 mil width

14

1

M24256-B, M24128-B

2/19

The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by theserial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition isfollowed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.

When writing data to the memory, the memory in­serts an acknowledge bit during the 9thbit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af­ter a NoAck for READ.

Power On Reset: VCCLock-Out Write Protect

In order to preventdata corruptionand inadvertent
write operationsduring power up, a Power On Re-

Figure 2A. PSDIP8 Connections

Figure 2B. SO8 and TSSOP8 Connections

SDAV

SS

SCL

WCE1

E0 V

CC

E2

AI02810

M24256-B
M24128-B

1
2
3
4

8
7
6
5

1

AI02811

2
3
4

8
7
6
5 SDAV

SS

SCL

WCE1

E0 V

CC

E2

M24256-B
M24128-B

Figure 2C. TSSOP14 Connections

Note: 1. NC = Not Connected

1

AI02812

2
3
4

14

9

10

8 SDAV

SS

E2 SCL

E0

WC

M24256-B
M24128-B

NC

E1

NC

NC NC

NC

NC

5
6
7

12

13

11

V

CC

Table 2. Absolute Maximum Ratings

1

Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may

cause permanent damage tothe device.These are stress ratings only, and operation of thedevice at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi­tions forextended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature -40 to 125 °C

T

STG

Storage Temperature -65 to 150 °C

T

LEAD

Lead Temperature during Soldering

PSDIP8: 10 seconds
SO8: 40 seconds
TSSOP8: 40 seconds
TSSOP14: 40 seconds

260
215
215
215

°C

V

IO

Input or Output range -0.6 to 6.5 V

V

CC

Supply Voltage -0.3 to 6.5 V

V

ESD Electrostatic Discharge Voltage (Human Body model)

2

4000 V

3/19

M24256-B, M24128-B

set (POR) circuit is included. The internal reset is
held active until the VCCvoltage has reached the
POR threshold value, and all operations are dis­abled – the device will not respond to any com­mand. In the same way,when VCCdrops from the
operating voltage, below thePOR thresholdvalue,
all operations are disabled and the device will not
respond to any command. A stable and valid V

CC

must be applied before applying any logic signal.

SIGNAL DESCRIPTION
Serial Clock (SCL)

The SCL input pin is used to strobeall data in and
out of the memory. In applications where this line
is used by slaves to synchronize thebus to a slow­er clock, the master must have an open drain out­put, and apull-up resistor mustbe connected from
the SCL line to VCC. (Figure 3 indicates how the
value of the pull-up resistor can be calculated). In
most applications,though, thismethod ofsynchro­nization is not employed, and so thepull-up resis­tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.

Serial Data (SDA)

The SDA pin is bi-directional, and isused to trans­fer datain or out of the memory. It is anopen drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to VCC. (Figure 3 indicates how the value of the
pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs areused toset the value
that isto be looked for on the three leastsignificant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs must be tied directly to VCCor VSSto

establish the device select code. When uncon­nected, the E2, E1 and E0 inputs are internally
read as VIL(see Table 7 and Table 8)

Write Control (WC)

The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertenterase/write. TheWrite Control signalis
used to enable (WC=VIL) or disable (WC=VIH)
write instructions to the entire memoryarea. When
unconnected, the WC input is internally read as
VIL, and write operations are allowed.

When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl­edged.

Please seethe Application Note

AN404

for amore

detailed description of the Write Control feature.

DEVICE OPERATION

The memory device supports the I2C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note

AN1001

. Any device thatsends data on to the bus
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
andthe otheras the slave.A datatransfer canonly
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all communica­tion.

Start Condition

START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device con­tinuously monitors (except during a programming

Figure 3. Maximum RLValue versus Bus Capacitance (C

BUS

) for an I2C Bus

AI01665

V

CC

C

BUS

SDA

R

L

MASTER

R

L

SCL

C

BUS

100

0

4

8

12

16

20

C

BUS

(pF)

Maximum RP value (kΩ)

10 1000

fc = 400kHz

fc =100kHz

M24256-B, M24128-B

4/19

cycle) the SDA and SCL lines for a START condi­tion, and will not respond unless one is given.

Stop Condition

STOP isidentified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communica­tion between the memory device and the bus mas­ter. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a suc­cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9thclock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.

Data Input

During data input, thememory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, theSDA signal
must be stable during the clock low-to-high transi­tion, and the data must change

only

whenthe SCL

line is low.

Memory Addressing

To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this,the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit DeviceSelect Code, andthe 1-bit Read/Write
Designator (RW). The Device Select Code is fur­ther subdivided into:a 4-bitDevice Type Identifier,
and a 3-bit Chip Enable “Address” (E2, E1, E0).

To address the memory array, the 4-bit Device
Type Identifier is 1010b.

Figure 4. I2C Bus Protocol

SCL

SDA

SCL

SDA

SDA

START

CONDITION

SDA

INPUT

SDA

CHANGE

AI00792

STOP

CONDITION

123 789

MSB

ACK

START

CONDITION

SCL

123 789

MSB ACK

STOP

CONDITION

5/19

M24256-B, M24128-B

Up to eight memory devices can be connected on
a single I2C bus. Each one is given a unique 3-bit
code on its Chip Enable inputs. When the Device
Select Codeis received onthe SDA bus, the mem­ory only responds if the Chip Select Code is the
same as the pattern applied to its Chip Enable
pins.

The 8thbit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem­ory gives an acknowledgment onthe SDA bus dur­ing the 9thbit time. If the memory does not match
the Device SelectCode, itdeselects itself fromthe
bus, and goes into stand-by mode.

There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the master and
the slave is ended with a STOP condition.

Each data byte in the memory has a 16-bit (two
byte wide)address. The MostSignificantByte (Ta­ble 4) issent first, followed by the Least significant
Byte (Table 5). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as a Don’t
Care bit on the M24256-B memory. Bits b15 and
b14 aretreated as Don’t Carebits on the M24128­B memory.

Write Operations

Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown inTable 6.The memoryacknowledges this,
and waits for two address bytes. The memory re-

sponds to each address bytewith an acknowledge
bit, and then waits for the data byte.

Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the memory contents, and the ac­companying data bytes will

not

be acknowledged,

as shown in Figure 5.

Byte Write

In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed location is write
protected by the WC pin, the memory replies with
a NoAck, and the location is not modified. If, in­stead, the WC pinhas been held at0, asshown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.

Page Write

The Page Write mode allows up to 64 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:

Table 3. Device Select Code

1

Note: 1. The most significant bit, b7, is sent first.

Device Type Identifier Chip Enable RW

b7 b6 b5 b4 b3 b2 b1 b0

Device Select Code 1 0 1 0 E2 E1 E0 RW

Table 4. Most Significant Byte

Note: 1. b15 is treated as Don’t Care on the M24256-B series.

b15 and b14 are Don’t Care on the M24128-B series.

Table 5. Least Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8

b7 b6 b5 b4 b3 b2 b1 b0

Table 6. Operating Modes

Note: 1. X = V

IH

or V

IL

.

Mode RW bit

WC

1

Data Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW = ‘1’

Random Address Read

0X

1

START, Device Select, RW = ‘0’, Address

1 X reSTART, Device Select, RW = ‘1’
Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0 V

IL

1 START,Device Select, RW = ‘0’

Page Write 0 V

IL

≤ 64 START, Device Select, RW = ‘0’

M24256-B, M24128-B

6/19

Figure 5. Write Mode Sequences with WC=1 (data write inhibited)

STOP

START

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

WC

START

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

WC

DATA IN 2

AI01120B

PAGE WRITE
(cont’d)

WC (cont’d)

STOP

DATA IN N

ACK ACK ACK NO ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK NO ACK

that is the most significant memory address bits
(b14-b6 for the M24256-B and b13-b6 for the
M24128-B) are the same. If more bytes are sent
than will fit up to the end of the row, a condition
known as ‘roll-over’ occurs. Data starts to become
overwritten (in a way not formally specified in this
data sheet).

The mastersends from one up to 64 bytes ofdata,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the con­tents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 6 least significant bits
only) is incremented.The transfer is terminated by
the master generating a STOP condition.

When the master generates a STOP condition im­mediately after the Ack bit (in the “10thbit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.

A STOP condition at any other time does not trig­ger the internal write cycle.

During the internal write cycle, the SDA input is
disabled internally, and the device does not re­spond to any requests.

7/19

M24256-B, M24128-B

Figure 6. Write Mode Sequences with WC=0 (data write enabled)

STOP

START

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

WC

START

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1

WC

DATA IN 2

AI01106B

PAGE WRITE
(cont’d)

WC (cont’d)

STOP

DATA IN N

ACK

R/W

ACK ACK ACK

ACK ACK ACK ACK

R/W

ACKACK

Minimizing System Delays by Polling On ACK

During theinternal write cycle, the memorydiscon­nects itself from the bus, and copiesthe data from
its internal latches to the memory cells. The maxi­mum write time (tw) is shown in Table 9, but the
typical time is shorter. To makeuse of this,an Ack
polling sequence can be used by themaster.

The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition

followed by a Device Select Code (the first byte
of the new instruction).

– Step 2: if the memory is busy with the internal

write cycle, no Ack willbe returned and the mas­ter goes back to Step 1. If the memory has ter­minated theinternal writecycle, it responds with
an Ack, indicating that the memory is ready to
receive the second part of the next instruction
(thefirst byteofthis instructionhaving been sent
during Step 1).

Read Operations

Read operations are performed independently of
the state of the WC pin.

Random Address Read

A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then,

without

sending a STOP condition, themas­ter sends another START condition, and repeats
the Device Select Code, with the RW bit set to ‘1’.
The memory acknowledges this, and outputs the
contents of the addressed byte. The master must

not

acknowledge the byte output, and terminates

the transfer with a STOP condition.

Current Address Read

The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to ‘1’. The memory acknowl­edges this, and outputs the byte addressed by the

M24256-B, M24128-B

8/19

Acknowledge in Read Mode

In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9

th

bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.

internal address counter. The counter is then in­cremented. The master terminates the transfer
with a STOP condition, as shown in Figure8,

with-

out

acknowledging the byte output.

Sequential Read

This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master

does

acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must

not

acknowledge the last

byte output, and

must

generate a STOP condition.

The output data comes fromconsecutive address­es, withthe internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from
memory address 00h.

Figure 7. Write Cycle Polling Flowchart using ACK

WRITE

Cycle

in Progress

AI01847

Next

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

NO

YESNO

ReSTART

STOP

Proceed

WRITE Operation

Proceed

Random

Address

READ Operation

Send

Byte Address

First byte of

instruction

with RW = 0

already

decoded by M24xxx

9/19

M24256-B, M24128-B

Figure 8. Read Mode Sequences

Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1stand 4thbytes) must be identical.

START

DEV SEL * BYTE ADDR BYTE ADDR

START

DEV SEL DATA OUT 1

AI01105C

DATA OUT N

STOP

START

CURRENT
ADDRESS
READ

DEV SEL DATA OUT

RANDOM
ADDRESS
READ

STOP

START

DEV SEL * DATA OUT

SEQUENTIAL
CURRENT
READ

STOP

DATA OUT N

START

DEV SEL * BYTE ADDR BYTE ADDR

SEQUENTIAL
RANDOM
READ

START

DEV SEL * DATAOUT 1

STOP

ACK

R/W

NO ACK

ACK

R/W

ACK ACK ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK

ACK ACK ACK

R/W

ACK ACK

R/W

ACK NO ACK

M24256-B, M24128-B

10/19

Table 7. DC Characteristics

(TA= –40 to 85 °C; VCC= 4.5 to 5.5 V or 2.5 to 5.5 V)
(TA= –20 to 85 °C; VCC= 1.8 to 3.6 V)

Note: 1. This is preliminary data.

Table 8. Input Parameters1(TA=25°C, f = 400 kHz)

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min. Max. Unit

I

LI

Input Leakage Current

(SCL, SDA)

0V≤ V

IN

≤ V

CC

± 2 µA

I

LO

Output Leakage Current 0 V ≤ V

OUT

≤ V

CC,

SDA in Hi-Z ± 2 µA

I

CC

Supply Current

V

CC

=5V, fc=400kHz (rise/falltime < 30ns)

2mA

-W series:

V

CC

=2.5V,fc=400kHz (rise/fall time < 30ns)

1mA

-R series:

V

CC

=1.8V,fc=100kHz (rise/fall time < 30ns)

0.5

1

mA

I

CC1

Supply Current
(Stand-by)

V

IN=VSS

orVCC,VCC=5V 10 µA

-W series: V

IN=VSS

orVCC,VCC= 2.5 V 2 µA

-R series: V

IN=VSS

orVCC,VCC= 1.8 V

1

1

µA

V

IL

Input Low Voltage(SCL, SDA) –0.3

0.3V

CC

V

V

IH

Input High Voltage (SCL, SDA)

0.7V

CC

VCC+1

V

V

IL

Input Low Voltage
(E0-E2, WC)

–0.3 0.5 V

V

IH

Input High Voltage
(E0-E2, WC)

0.7V

CC

VCC+1 V

V

OL

Output Low
Voltage

I

OL

= 3 mA, VCC=5V

0.4 V

-W series: I

OL

= 2.1 mA, VCC= 2.5 V 0.4 V

-R series:

I

OL

= 0.7 mA, VCC= 1.8 V

0.2

1

V

Symbol Parameter Test Condition Min. Max. Unit

C

IN

Input Capacitance (SDA) 8 pF

C

IN

Input Capacitance (other pins) 6 pF

Z

L

Input Impedance (E0-E2, WC) VIN≤ 0.5 V 50 kΩ

Z

H

Input Impedance (E0-E2, WC)

V

IN

≥ 0.7V

CC

500 kΩ

t

NS

Pulse width ignored
(Input Filter on SCL and SDA)

Single glitch 100 ns

11/19

M24256-B, M24128-B

Table 9. AC Characteristics

Note: 1. For a reSTART condition, or following a write cycle.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

4. This is preliminary data.

Symbol Alt. Parameter

M24256-B / M24128-B

Unit

V

CC

=4.5 to 5.5 V

T

A

=–40 to 85°C

V

CC

=2.5 to 5.5 V

T

A

=–40 to 85°C

V

CC

=1.8 to 3.6 V

T

A

=–20 to 85°C

4

Min Max Min Max Min Max

t

CH1CH2

t

R

Clock Rise Time 300 300 300 ns

t

CL1CL2

t

F

Clock Fall Time 300 300 300 ns

t

DH1DH2

2

t

R

SDA Rise Time 20 300 20 300 20 300 ns

t

DL1DL2

2

t

F

SDA FallTime 20 300 20 300 20 300 ns

t

CHDX

1

t

SU:STA

Clock High to Input Transition 600 600 600 ns

t

CHCL

t

HIGH

Clock Pulse Width High 600 600 600 ns

t

DLCLtHD:STA

Input Low to Clock Low (START) 600 600 600 ns

t

CLDXtHD:DAT

Clock Low to Input Transition 0 0 0 µs

t

CLCH

t

LOW

Clock Pulse Width Low 1.3 1.3 1.3 µs

t

DXCXtSU:DAT

Input Transition to Clock
Transition

100 100 100 ns

t

CHDHtSU:STO

Clock High to Input High (STOP) 600 600 600 ns

t

DHDL

t

BUF

Input High to Input Low (Bus
Free)

1.3 1.3 1.3 µs

t

CLQV

3

t

AA

Clock Low to Data OutValid 200 900 200 900 200 900 ns

t

CLQX

t

DH

Data Out Hold Time After Clock
Low

200 200 200 ns

f

C

f

SCL

Clock Frequency 400 400 400 kHz

t

W

t

WR

Write Time 10 10 10 ms

Table 10. AC Measurement Conditions

Input Rise and Fall Times ≤ 50 ns
Input Pulse Voltages

0.2V

CC

to 0.8V

CC

Input and Output Timing
Reference Voltages

0.3V

CC

to 0.7V

CC

Figure 9. AC Testing Input Output Waveforms

AI00825

0.8V

CC

0.2V

CC

0.7V

CC

0.3V

CC

M24256-B, M24128-B

12/19

Figure 10. AC Waveforms

SCL

SDA IN

SCL

SDA OUT

SCL

SDA IN

tCHCL

tDLCL

tCHDX

START

CONDITION

tCLCH

tDXCX

tCLDX

SDA

INPUT

SDA

CHANGE

tCHDH

tDHDL

STOP &

BUS FREE

DATA VALID

tCLQV tCLQX

DATA OUTPUT

tCHDH

STOP

CONDITION

tCHDX

START

CONDITION

WRITE CYCLE

tW

AI00795B

13/19

M24256-B, M24128-B

Table 11. Ordering Information Scheme

Note: 1. Available only on request.

Example: M24256 – B W MN 6 T

Memory Capacity Option

256 256 Kbit (32K x 8) T Tapeand Reel Packing
128 128 Kbit (16K x 8)

Temperature Range

6 –40 °Cto85°C
5 –20 °Cto85°C

Operating Voltage Package

blank

1

4.5 V to 5.5 V BN PSDIP8 (0.25 mm frame)
W 2.5 V to 5.5 V MN SO8 (150 mil width)
R 1.8 V to 3.6 V DW TSSOP8 (169 mil width)

DL TSSOP14 (169 mil width)

ORDERING INFORMATION

Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).

The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or forfurther informationon
any aspect of this device, please contact your
nearest ST Sales Office.

M24256-B, M24128-B

14/19

Figure 11. PSDIP8 (BN)

Note: 1. Drawing isnot to scale.

PSDIP-a

A2A1A

L

e1

D

E1 E

N

1

C

eA
eB

B1

B

Table 12. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.014

D 9.20 9.90 0.362 0.390

E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264
e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394

L 3.00 3.80 0.118 0.150

N8 8

15/19

M24256-B, M24128-B

Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α 0° 8° 0° 8°

N8 8

CP 0.10 0.004

Figure 12. SO8 narrow (MN)

Note: 1. Drawing isnot to scale.

SO-a

E

N

CP

B

e

A

D

C

LA1 α

1

H

hx45°

M24256-B, M24128-B

16/19

Table 14. TSSOP8 - 8 lead Thin Shrink Small Outline

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.10 0.043
A1 0.05 0.15 0.002 0.006
A2 0.85 0.95 0.033 0.037

B 0.19 0.30 0.007 0.012

C 0.09 0.20 0.004 0.008

D 2.90 3.10 0.114 0.122

E 6.25 6.50 0.246 0.256
E1 4.30 4.50 0.169 0.177

e 0.65 – – 0.026 – –

L 0.50 0.70 0.020 0.028

α 0° 8° 0° 8°

N8 8

CP 0.08 0.003

Figure 13. TSSOP8 (DW)

Note: 1. Drawing isnot to scale.

TSSOP

1

N

CP

N/2

DIE

C

L

A1

EE1

D

A2A

α

eB

17/19

M24256-B, M24128-B

Table 15. TSSOP14 - 14 lead Thin Shrink Small Outline

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.10 0.043
A1 0.05 0.15 0.002 0.006
A2 0.85 0.95 0.033 0.037

B 0.19 0.30 0.007 0.012

C 0.09 0.20 0.004 0.008

D 4.90 5.10 0.193 0.197

E 6.25 6.50 0.246 0.256
E1 4.30 4.50 0.169 0.177

e 0.65 – – 0.026 – –

L 0.50 0.70 0.020 0.028

α 0° 8° 0° 8°

N14 14

CP 0.08 0.003

Figure 14. TSSOP14 (DL)

Note: 1. Drawing isnot to scale.

TSSOP

1

N

CP

N/2

DIE

C

L

A1

EE1

D

A2A

α

eB

M24256-B, M24128-B

18/19

Table 16. Revision History

Date Description of Revision

28-Dec-1999 TSSOP8 package added (pp 1, 2, OrderingInfo, PackageMechData).

24-Feb-2000

E2, E1, E0 must be tied to Vcc or Vss, on page 3
Low Pass Filter Time Constant changed to Glitch Filter in Table8

19/19

M24256-B, M24128-B

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