Datasheet LXT332QE, LXT332PE Datasheet (Level One Communications)

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TPOS

TNEG

JASEL

RNEG
RPOS

RCLK

LOS

B8ZS/HDB3

Unipolar
Encoder

Encoder

Enable

Decoder

Enable

B8ZS/HDB3

Unipolar
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RLOOP

Enable

Remote

Loopback

L1

QRSS / BPV Generator

Serial Word

Jitter

Attenuator

QRSS Detector

Loopback

Local

Transmit
Timing &

Control

TAOS

Enable

Timing and

Data

Recovery

LOS

Processor

LLOOP
Enable

Equalizer

LEN Select

Data Slicers

LOS/Clear

Monitor

Internal

Clock

Generator

DFM

Transceiver 0

Line Drivers

Serial

Port

Peak

Detector

Transceiver 1

TTIP

TRING
DFM

INT0/1
PS0/1
CLKE
SCLK
SDI
SDO
MCLK

HFC

RTIP
RRING

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êä ì TRSTE DI T ristate Output Enable Input Pin. Forces all output pins to high-Z tri-state

éí ë TCLK0 DI T ransmit Clock - Port 0. 1.544 MHz for T1, 2.048 MHz for E1. The trans-

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when held High. Enables Bipolar I/O mode when held Low. In this mode
the framer interface is bipolar (TPOS/TNEG and RPOS/RNEG), and the
B8ZS/HDB3 encoders are disabled. Enables Unipolar I/O mode when
clocked by MCLK. In this mode the framer interface is unipolar (TDATA
and RDATA), and the TNEG and RNEG pins are re-mapped. The TNEG
pins are re-mapped as Encoder Enable (ECE) to individually enable the
B8ZS/HDB3 encoder/decoder for each port. The RNEG pins are re-mapped
as Bipolar Violation (BPV) indicators to report BPVs received at the respec­tive ports.

mit data inputs are sampled on the falling edge of TCLK.

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ìæRCLK0 DO Receive Clock - Port 0. This clock is recovered from the input signal.

ëåSCLK DI Serial Clock. The Serial Clock shifts data into or out from the serial inter-

êäVCQ0 DI/O Provides Violation insert, High Frequency Clock, or QRSS generation/detec-

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TNEG0

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RNEG0

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RPOS0

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DIDITransmit Positive and Negative Data - Por t 0. In the Bipolar I/O mode,

these pins are the positive and negative sides of a bipolar input pair for port

0. Data to be transmitted onto the twisted-pair line is input at these p ins.
However, when the TRSTE pin is clocked by MCLK, the LXT332 switches
to a unipolar mode. Table 2 describes Unipolar mode pin functions.

DODOReceive Positive and Negative Data - Port 0. In the Bipolar I/O mode,

these pins are the data outputs from port 0. A signal on RNEG corresponds
to receipt of a negative pulse on RTIP/RRING. A signal on RPOS corre­sponds to receipt of a positive pulse on RTIP/RRING. RNEG/RPOS outputs
are Non-Return-to-Zero (NRZ). In Host mode, CLKE determines the clock
edge at which these outputs are stable and valid.

Under Loss of Signal (LOS) conditions, this output is derived from MCLK.

face register of the selected port.

tion functions for Port 0. Pin operation is determined by the VCQE pin.

Violation Insertion Function. When the Violation insertion function is
enabled, this pin is sampled on the falling edge of TCLK to control bipolar
violation (BPV) insertion. If High, a BPV is inserted at the next available
mark transmitted from port 0. A Low-to-High transition is required for each
subsequent violation insertion. (B8ZS and HDB3 zero suppression codes are
not violated.)

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Clock Function. When the Clock function is enabled, this pi n outputs a
High Frequency Clock (12.352 MHz for T1, 16.384 MHz for E1) tied to the
jitter attenuated clock of port 0. If no JA clock is available, HFC is locked to
the 8x receive timing recovery clock.

Quasi Random Signal Source (QRSS) Function. When the QRSS function
is enabled, a High on this pin enables the QRSS detection circuit and causes
the LXT332 to transmit the QRSS pattern onto the twis ted-pair line from
port 0. For error-free QRSS transmission, TPOS0 must be held Low. To
insert errors into the pattern, TPOS must transition from Low to High (TPOS
is sampled on the falling edge of MCLK). A Low-to-High transition is
required for each subsequent violation insertion. (B8ZS and HDB3 zero
suppression codes are not violated.)

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çìëMCLK DI Master Clock. The master clock (1.544 MHz for T1, 2.048 MHz for E1)

æìêGND – Ground. Ground return for power supply VCC.

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INT1
INT0

DODOInterrupt Outputs. The interrupt outputs go Low to flag the host processor

that the respective port has changed state. INT0 and INT1 are open drain
outputs. Each must be tied to VCC through a resistor.

input must be independent, free-running, continuously active and jitter free
for receiver oper ation. Since the transceivers derive their RCLK timing from
the MCLK input on Loss of Signal (LOS), MCLK cannot be derived from
RCLK.

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äìèTGND0 – Ground. Ground return for power supply TVCC0.

ìí ìç TVCC0 I + 5 volt power supply input for the port 0 transmit driver. TVCC0 must

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ìê ìä PS0

ìé ëí PD0 DO Pattern Detect - P ort 0. Unless the QRSS function is selected by the VCQE

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Transmit Tip and Ring - Port 0. The tip and ring pins for each port are dif­ferential dri v er out p uts des igned to dr ive a 35 - 200 Ω load. Line matching
resistors and transformers can be selected to give the desired pulse height.
See Figures 19 through 21.

not vary from TVCC1 or VCC by more th an ± 0.3 V.

in one or both ports.

I Port Select - Port 0. This input accesses the serial interface registers for

port 0. For each read or write operation, PS must transition from High to
Low, and remain Low.

pin, PD0 functions as an AIS alarm indicator. The AIS pattern is detected by
the receiver, independent of any loopback mode. AIS goes High when less
than three zeros have been detected in any string of 2048 bits. AIS returns
Low when the received signal contains more than three zeros in 2048 bits.
(LOS is available via the SIO register and interrupt.)

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If the QRSS function is enabled by the VCQE pin , PD 0 remains High until
pattern sync is reached with the received signal. Once pattern lock is
obtained, PD0 goes Low. (The sync/out-of-sync criteria is less than 3/4
errors in 128 bits.) After sync acquisition, bit errors cause PD0 to go High
for half a clock cycle. This output can be used to trigger an external error
counter.

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RRING0

RRING1

RTIP1

TRING1

TTIP1

DIDIReceive Tip and Ring - Port 0. RTIP and RRING comprise the receive line

interface. This input pair should be connected to the line through a center­tapped 1:2 transformer.

puts are valid on the falling edge of RCLK, and SDO is valid on the rising
edge of SCLK. When CLKE is Low, RPOS/RNEG or RDATA outputs are
valid on the rising edge of RCLK, and SDO is valid on the falling edge of
SCLK.

AIAIReceive Tip and Ring - Port 1. RTIP and RRING comprise the receive line

interface. This input pair should be connected to the line through a center­tapped 1:2 transformer.

PD0 signal description for details.

DI Port Select - Port 1. This input accesses the serial interface registers for

port 1. For each read or write operation, PS must transition from High to
Low, and remain Low.

AOAOTransmit Tip and Ring - Port 1. The tip and ring pins for each port are dif-

ferential dri v er out p uts des igned to dr ive a 35 - 200 Ω load. Line matching
resistors and transformers can be selected to give the desired pulse height.
See Figures 13 through 15.

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ëé êí TVCC1 AI + 5 volt power supply input for the port 1 transmit driver. TVCC1 must

ëè êì TGND1 – Ground. Ground return for power supply TVCC1.
ëæ êê VCC AI +5 VDC power supply input for all circuits, except the transmit drivers.
ëå êé JASEL DI Jitter Attenuation Select. Selects jitter attenuation for both ports. When

ëä êè VCQ1 DI/O Violation insert, Clock, or QRSS. Functi on (Violation insert, Clock, or

êí êç SPE DI Serial Port Enable. SPE must be clock ed with MCLK to enable Ho st Mode

êì êæ VCQE DI Violation - Clock - QRSS Enable. When set High, enables the Bipolar

êë êå SDO DO Serial Data Output. If CLKE is High, SDO is valid on the rising edge of

êê êä RCLK1 DO Receive Clock - Port 1. This clock is recovered from the input signal.

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êå éé TCLK1 DI Transmit Clock - Port 1. 1.544 MHz for T1, 2.048 MHz for E1. The trans-

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RPOS1

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RNEG1

(Bipolar)

TNEG1

(Bipolar)

TPOS1

(Bipolar)

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not vary from TVCC0 or VCC by more th an ± 0.3 V.

JA SEL = 1, JA circuits are placed in the receive paths. When JASEL = 0, JA
circuits are placed in the transmit paths. When JASEL is clocked with
MCLK, the JA circuit is disabled.

QRSS) is determined by the VCQE pin. Provides Violation Insertion, High
Frequency Clock or QRSS Generation functions for Port 1. Refer to VCQ0
signal description for detai ls.

control through the serial port.

Violation In sert fun ctions of VCQ0 and VCQ1 pins. When set Low, enables
the High Frequency Clock functions of VCQ0 and VCQ1. When clocked
with MCLK, enables the QRSS functions of VCQ0 and VCQ1, and enables
the QRSS Generate and Detect function of PD0 and PD1 pins.

SCLK. If CLKE is Low, SDO is valid on the falling edge of SCLK.

Under Loss of Signal (LOS) conditions, this output is derived from MCLK.

DODOReceive Positive and Negative Data - Port 1. In the Bipolar I/O mode,

these pins are the data outputs from port 1. A signal on RPOS corresponds to
receipt of a positive pulse on RTIP/RRING. A signal on RNEG corresponds
to receipt of a negative pulse on RTIP/RRING. RNEG/RPOS outputs are
Non-Return-to-Zero (NRZ). CLKE determines the clock edge at which
these outputs are stable and valid.

DIDITransmit Positive and Negative Data - Por t 1. In the Bipolar I/O mode,

these pins are TPOS and TNEG, the positive and negative sides of a bipolar
input pair for port 1. Data to be transmitted onto the twisted-pair line is input
at these pins. However, when TRSTE is clocked by MCLK, the LXT332
switches to a unipol ar mode. Unipo lar mode pin f unction s are desc ribed sep ­arately .

mit data inputs are sampled on the falling edge of TCLK.

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onto the twisted-pair line from port 0 is input at this pin.

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ECE0 DI Encoder Enable - Port 0. In the Unipolar mode, a High on this pin enables

the B8ZS or HDB3 encoder and decoder for port 0.

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BPV0 DO Bipolar Violation - Port 0. In the Unipolar mode this indicator output goes

High when a bipolar violation is received at port 0.

éé ç

RDATA0 DO Receive Data - Port 0. In the Unipolar mode, RDATA is a Non-Return-to-

Zero (NRZ) output. CLKE determines the RCLK edge which RDATA is
stable and valid.

êé éí

RDATA1 DO Receive Data - Port 1. In the Unipolar mode, RDATA is a Non-Return-to-

Zero (NRZ) output. CLKE determines the RCLK edge which RDATA is
stable and valid.

êè éì

BPV1 DO Bipolar Violation - Port 1. In the Unipolar mode this indicator output goes

High when a bipolar violation is received at port 1.

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ECE1 DI Encoder Enable - Port 1. In the Unipolar mode, a High on this pin enables

the B8ZS or HDB3 encoder and decoder for port 1.

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TDATA1 DI Transmit Data - Port 1. In the Unipolar mode, the data to be transmitted

onto the twisted-pair line from port 1 is input at this pin.

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TRSTE DI Tristate Output Enable Input Pin. Forces all output pins to high-Z Tri-state

when held High. Enables Bipolar I/O mode when held Low. In this mode the
framer interface is bipolar (TPOS/TNEG and RPOS/RNEG), and the B8ZS/
HDB3 encoders are disabled. Enables Unipolar I/O mode when clocked by
MCLK. In this mode the framer interface is unipolar (TDATA and RDATA),
and the TNEG and RNEG pins are re-mapped. The TNEG pins are re-mapped
as Encoder Enable (ECE) to individually enable the B8ZS/HDB3 encoder/
decoder for each port. The RNEG pins are re-mapped as Bipolar Violation
(BPV) indicators to report BPVs received at the respective ports.

éí ë

TCLK0 DI Transmit Clock - Port 0. 1.544 MHz for T1, 2.048 MHz for E1. The trans-

mit data inputs are sampled on the falling edge of TCLK.

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TPOS0

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TNEG0

(Bipolar)

RNEG0

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RPOS0

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DI Transmit Data Positive and Negative - Port 0. In the Bipolar I/O mode,

these pins are the positive and neg at ive sides of a b ipol ar i npu t pair for port 0.
Data to be transmitted onto the twp line is input at these pins. However, when
TRSTE is clocked by MCLK, the LXT332 switches to a unipolar mode. Uni­polar mode pin functions are described separately.

DO Receive Data Positive and Negative - Port 0. In the Bipolar I/O mode, a sig-

nal on RNEG corresponds to receipt of a negative pulse on RTIP/RRING. A
signal on RPOS corresponds to receipt of a positive pulse on RTIP/RRING.
RNEG/RPOS outputs are Non-Return-to-Zero (NRZ). RPOS and RNEG are
stable and valid on the rising edge of RCLK.

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ìæRCLK0 DO Receive Clock - Port 0. This clock is recovered from the input signal. Under

ëåTAOS0 DI Transmit All Ones Enable - Port 0. When TAOS is High and RLOOP is

ê
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çìëMCLK DI Master Clock. The master clock (1.544 MHz for T1, 2.0 48 MHz for E1) input

æìêGND – Ground. Ground return for power supply VCC.

å

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äìèTGND0 – Ground. Ground return for power supply TVCC0.

ìí ìç TVCC0 AI + 5 volt power supply input for the port 0 transmit driver. TVCC0 must not

ìë ìå DFM DO Driver Fail Monitor. This signal goes High to indicate a driver output short

ìê ìä RLOO P0 DI Remote Loopback Enable - Port 0. When RLOOP = 1, the port 0 clock and

ìé ëí LOS0 DO Loss of Signal - Port 0. LOS goes High when 175 consecutive spaces have

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ìæ ëê LLOOP0 DI Local Loopback Enable - Port 0. When LLOOP is High, the RTIP/RRING

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TTIP0

TRING0AOAO

RTIP0

RRING0AIAI

RRING1

RTIP1

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Loss of Signal (LOS) conditions, this output is derived from MCLK.

Low, the TPOS/TNEG or TDATA input is ignored and port 0 transmits a
stream of ones at the TCLK frequency. If TCLK is not provided, the MCLK
input is used as the transmit reference.

DI

Line Length Equalizer Inputs - Port 0. This pins determine the shape and

DI

amplitude of the transmit pulse.

DI

must be independent, free-running, continuous ly active and jitter free for
receiver operation. Since the transceivers derive their RCLK timing from the
MCLK input on Loss of Signal (LOS), MCLK cannot be derived from RCLK.

Transmit Tip and Ring - Port 0. The tip and ring pins for each port are dif­ferential driver outputs designed to drive a 35 - 200 Ω load. Line matching
resistors and transformers can be selected to gi v e the desired p ulse height. See
Figures 13 thro ugh 15.

vary from TVCC1 or VCC by more than ± 0.3 V.

in one or both ports.

data inputs from the framer are igno red and the data receiv ed fr om the twisted­pair line is transmitted back onto the line at the RCLK frequency. (LLOOP0

must be Low for RLOOP0 to occur.)

been detected. LOS returns Low when the received signal reaches a mark den­sity of 12.5% (det ermin ed b y re ceip t of f our marks with a slid ing 32- bit p eriod
with no more than 15 consecutive zeros). Received marks are output on
RPOS/RNEG or RDATA even when LOS is High.

Receive Tip and Ring - Port 0. RTIP and RRING comprise the receive line
interface. This input pair should be connected to the line through a center­tapped 1:2 transformer.

inputs from the port 0 line are disconnected and the transmit data inputs are
routed back into the receive inputs (through JA if enabled). (RLOOP0 must

be Low for LLOOP0 to occur.)

AIAIReceive Tip and Ring - Port 1. RTIP and RRING comprise the receive line

interface. This input pair should be connected to the line through a center­tapped 1:2 transformer.

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ëí ëç LOS1 DO Loss of Signal - Port 1. LOS goes High when 175 consecutive spaces have

ëì ëæ LLOOP1 DI Local Loopb ack En abl e - P ort 1. (RLOOP 1 must be Lo w f or LLOO P1 to

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ëé êí TVCC1 AI + 5 volt power supply input for the port 1 transmit driver. TVCC1 must not

ëè êì TGND1 – Ground. Ground return for power supply TVCC1.
ëæ êê VCC AI +5 VDC power supply input for all circuits, except the transmit drivers.
ëå êé JASEL DI Jitter Attenuation Select. Selects jitter attenuation for both ports. When

ëä
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êë êå RLOO P1 DI Remote Loopback Enable - Port 1. (LLOOP1 must = 0 for RLOOP to

êê êä RCLK1 DO Receive Clock - Port 1. This clock is recovered from the twisted-pair input

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TTIP1

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RPOS1

(Bipolar)

RNEG1

(Bipolar)

TNEG1

TPOS1

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been detected. LOS returns to a logic 0 when the received signal reaches a
mark density of 12.5% (refer to LOS0 signal description for details).

occur.)

occur.)

AOAOTransmit Ring - Port 1. The tip and ring pins for each port are differential

driver outputs designed to drive a 35 - 200 Ω load. Line matching resistors
and transformers can be selected to give the desired pulse height. See Figures
19 through 21.

vary from TVCC0 or VCC by more than ± 0.3 V.

JASEL = 1, JA circuits are placed in the receive paths. When JASEL = 0, JA
circuits are placed in the transmit paths. When J ASEL is clocked with MCLK,
the JA circuit is disabled.

DI

Line Length Equalizer inputs - Port 1. These pins determine the shape and

DI

amplitude of the transmit pulse.

DI

occur.)

signal. Under Loss of Signal (LOS) conditions, this output is derived from
MCLK.

DODOReceive Data Positiv e a nd Negative - Port 1. In the Bipolar I/O mode, these

pins are the data outputs from port 1. A signal on RPOS corresponds to
receipt of a positive pulse on RTIP/RRING. A signal on RNEG corresponds
to receipt of a negative pulse on RTIP/RRING. RNEG/RPOS outputs are
Non-Return-to-Zero (NRZ). RPOS and RNEG are stable and valid on the ris­ing edge of RCLK.

DIDITransmit Data Positive and Negative - Port 1. In the Bipolar I/O mode,

these pins are TPOS and TNEG, the positive and negative sides of a bipolar
input pair for port 1. Data to be transmitted onto the twisted-p air line is input
at these pins. However, when the TRSTE pin is clocked by MCLK, the
LXT332 switches to a unipolar mode. Unipolar mode pin functions are
described separately.

mit data inputs are sampled on the falling edge of TCLK.

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41 3 TDATA0 DI Transmit Data - Port 0. In the Unipolar mode, the data to be transmitted

42 4 ECE0 DI Encoder Enable - Port 0. In the Unipolar mode, a High on this pin enab les

43 5 BPV0 DO Bipolar Viola tion - P ort 0. In the Unipolar mode t his indicator output goes

44 6 RDATA0 DO Receive Data - Port 0. In the Unipolar mode, RDATA is a Non-Return-to-

34 40 RDATA1 DO Receive Data - Port 1. In the Unipolar mode, RDATA is a Non-Return-to-

35 41 BPV1 DO Bipolar Violation - Port 1. In the Unipolar mode this indi cator output goes

36 42 ECE1 DI Encoder Enable - Port 1. In the Unipolar mode, a High on this pin enables

37 43 TDATA1 DI Transmit Data - Port 1. In the Unipolar mode, the data to be transmitted

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onto the line from port 0 is input at this pin.

the B8ZS or HDB3 encoder and decoder for port 0.

High when a bipolar violation is received at port 0.

Zero (NRZ) output. RDATA is stable and valid on the rising edge of
RCLK.

Zero (NRZ) output. RDATA is stable and valid on the rising edge of
RCLK.

High when a bipolar violation is received at port 1.

the B8ZS or HDB3 encoder and decoder for port 1.

onto the line from port 1 is input at this pin.

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Performance Loop

Pub 62411

Dec 1990

1.5 UI @ 20 Hz

ITU G.823 Mar 1993

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