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The figure on the front page of this section is a block diagram of the LXT310. The transceiver may be controlled by
a microprocessor through t he serial port (Host Mode) , or by
individual pin settings (Hardware Mode). The jitter attenuator may be positioned in either the transmit or receive
path.
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The LXT310 is a low-power CMOS device. It operates
from a single +5 V power supply which can be connected
externally to both the transmitter and receiver. However,
the two inputs must be within ± .3 V of each other, and
decoupled to their respective grounds separately. Refer to
Application Information for typical decoupling circuitry.
Isolation between the transmit and receive circuits is provided internally.
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The twisted-pair input is received via a 1:1 transformer.
Recovered data is output at RPOS/RNEG (RDATA in unipolar mode), and the recovered clock is output at RCLK.
Refer to Test Specifications for receiver timing.
The signal received at RPOS and RNEG is processed
through the receive equalizer. The Equalizer Gain Limit
(EGL) input determines the maximum gain that may be applied at the equalizer. When set Low, u p to 36 dB of ga in
may be applied.
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The equalized signal is filtered and applied to the peak detector and data slicers. The peak detector samples the inputs and determines the maximum value of the received
signal. A percentage of the peak value is provided to the
data slicers as a threshold level to ensure optimum signalto-noise ratio. The threshold is set to 50% of the peak value. The receiver is capable of accurately recovering signals
with up to 36 dB of cable attenuation (from 2.4 V)
After processing through the data slicers, the received signal is routed to the data and timing recovery section, then
to the B8ZS decoder (if selected) and to the LOS p rocessor.
The LOS Processor loads a digital counter at the RCLK frequency. The count is incremented each time a zero (space)
is received, and reset to zero each time a one (mark) is received. Upon receipt of 175 consecutive zeros the LOS pin
goes High, and a smooth transition replaces the RCLK output with the MCLK. (During LOS if MCLK is not supplied
and JASEL = 1, the RCLK output is replaced with the centered crystal clock.)
Received marks will be output regardless of the LOS status, but the LOS pin will not reset u ntil the ones density
reaches 12.5 %. This level is based on receipt of at least 4
ones in any 32-bit period.
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Input data (bipolar or unipolar) for transmission onto the
line is clocked serially into the device. Bipolar data is input
at pin 3 (TPOS) and pin 4 (TNEG). Unipolar data is input
at pin 3 (TDATA) only. (Unipolar mode is enabled by
holding pin 4 high for 16 RCLK cycles) . Input data may be
passed through the Jitter Attenuator and/or B8ZS encoder,
if selected. In Host Mode, B8ZS is selected by setting bit
D3 of the input data byte. In Hardware Mode, B8ZS is
selected by connecting the MODE pin to RCLK. Input
synchronization is supplied by the transmit clock (TCLK).
Timing requirements for TCLK and the Master Clock
(MCLK) are defined in Test Specifications.
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LBO settings are input through the serial port in the Host
Mode. In the Hardware Mode, LBO inputs are applied
through individual pins. Shaped pulses meeting the various T1 CSU and ISDN PRI requirements are applied to the
AMI line driver for transmission onto the line at TTIP and
TRING. Refer to Test Specifications for T1 pulse mask
specifications.
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The LXT310 transmits data as a 50% AMI line code as
shown in Figure 3. Power consumption is reduced by activating the AMI line driver only to transmit a mark. The
output driver is disabled during transmission of a space.
Biasing of the transmit DC level is on-chip.
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In Hardware Mode the transceiver is accessed and controlled through individual pins. With the exception of the
INT and CLKE functions, Hardware Mode provides all the
functions provided in the Host Mode. In the Hardware
Mode RPOS/RNEG or RDATA outputs are valid on the
rising edge of RCLK. The LXT310 operates in Hardware
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Figure 7 is a typical 1.544 Mbps ISDN PRI application
with the LXT310, a T1/ESF framer and an LXP600A clock
adapter. The LXT310 is operating in th e Hardware Mode
with B8ZS encoding enabled (MODE pin 5 tied to RCLK).
As in the T1/CSU application, Figure 6, this configuration
is illustrated with a single power supply bus. CMOS con trol logic is used to set both LBO p ins high, s electing the
22.5 dB LBO, and the EGL pin is tied low, allowing for full
receiver gain. The TAOS, LLOOP and RLOOP diagnostic
modes are individually controllable. The RCLK inpu t to
the OR gate at RLOOP allows for clocking of the RLOOP
pin, which enables network loopback detection. The
receive and transmit line interfaces are identical to the Host
Mode application shown in Figure 6.
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