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during Remote Loopback.
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status. Setting MODE Low puts the LXT300Z in the Hardware (H/W) mode. In the
Hardware Mode, the serial interface is disabled and hard-wired pins are used to control
configuration and report status.
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5HFHLYH 1HJDWLYH 'DWDâ 5HFHLYH 3RVLWLYH 'DWDï Received data outputs. A signal on
RNEG corresponds to receipt of a negative pulse on RTIP and RRING. A signal on
RPOS corresponds to receipt of a positive pulse on RTIP and RRING. RNEG and
RPOS outputs are Non-Return-to-Zero (NRZ). Both outputs are stable and valid on the
rising edge of RCLK.
LXT300Z only: In the Host Mode, CLKE determines the clock edge at which these outputs are stable and valid. In the Hardware Mode both outputs are stable and valid on
the rising edge of RCLK.
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5HFRYHUHG &ORFNï This is the clock recovered from the signal received at RTIP and
RRING.
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&U\VWDO ,QSXWâ &U\VWDO 2XWSXW õ/;7êíí=ôï An external crystal operating at four
times the bit rate (6.176 MHz for DSX-1, 8.192 MHz for E1 applications with an 18.7
pF load) is required to enable the jitter attenuation function o f the LXT30 0Z. These
pins may also be used to disable the jitter attenuator by connecting the XTALIN pin to
the positive supply through a resistor, and floating the XTALOUT pin.
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High until a signal is detected.
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LOS returns Low when a mark is detected.
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7UD Q V P L W 7LSâ 7U D Q V PLW 5LQJï Differential Driver Outputs. These outputs are
designed to drive a 25 Ω load. The transmitter will drive 100 Ω shielded twisted-pair
cable through a 1:2 step-up transformer without additional components. To drive
75 Ω coaxial cable, two 2 .2 Ω resist ors are required in series with the transformer.
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5HFHLYH 7LSâ 5HFHLYH 5LQJï The AMI signal received from the line is applied at these
pins. A center-tapped, center-grounded, 2:1 step-up transformer is required on these
pins. Data and clock from the signal applied at these pins are recovered and output on
the RPOS/RNEG and RCLK pins.
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,QWHUUXSW õ+RVW 0RGHôï This LXT300Z Host Mode output goes Low to flag the host
processor when LOS or DPM go activ e. INT is an open-drain output and should be tied
to power su ppl y RV+ through a resisto r. INT
is reset by clearing the respective register
bit (LOS and/or DPM).
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(TXDOL]HU &RQWURO ì õ+î: 0RGHôï The signal applied at this pin in the LXT300Z Hard-
ware Mode an d LXT3 01Z is used in conjunction with EC2 and EC3 inputs to determine
shape and amplitude of AMI output transmit pulses.
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6HULDO 'DWD ,Q õ+RVW 0RGHôï The serial data input stream is applied to this pin when the
LXT300Z operates in the Host Mode. SDI is sampled on the rising edge of SCLK.
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ware Mode an d LXT3 01Z is used in conjunction with EC1 and EC3 inputs to determine
shape and amplitude of AMI output transmit pulses.
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6HULDO 'DWD 2XW õ+RVW 0RGHôï The serial data from the on-chip register is output on
this pin in the LXT300Z Host Mode. If CLKE is High, SDO is valid on the rising edge
of SCLK. If CLKE is Low SDO is valid on the falling edge of SCLK. This pin goes to
a high-impedance state when the serial port is being written to and when CS
is High.
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ware Mode an d LXT3 01Z is used in conjunction with EC1 and EC2 inputs to determine
shape and amplitude of AMI output transmit pulses.
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LXT300Z Host Mode. For each read or write operation, CS
must transition from High
to Low, and remain Low.
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5HPRWH /RRSEDFN õ+î: 0RGHôï This input controls loopback functions in the
LXT300Z Hardware Mode and LXT 301Z. Setting RLOOP High enables the Remo te
Loopback mode. Setting both RLOOP and LLOOP High causes a Reset.
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6HULDO &ORFN õ+RVW 0RGHôï This clock is used in the LXT300Z Host Mode to write data
to or read data from the serial interface registers.
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/RFDO /RRSEDFN õ+î: 0RGHôï This input controls loopback functions in the LXT300Z
Hardware Mode and LXT301Z. Setting LLOOP High enables the Local Loopback
Mode.
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&ORFN (GJH õ+RVW 0RGHôï Setting CLKE High causes RPOS and RNEG to be valid on
the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. When
CLKE is Low, RPOS and RNEG are valid on the rising edge of RCLK, and SDO is
valid on the falling edge of SCLK.
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7UD Q V P L W $OO 2QHV õ+î: 0RGHôï When High, TAOS causes the LXT300Z (Hardware
Mode) and LXT301 Z to tran smit a con tin uou s stream of mark s at the TCLK f requ enc y.
Activatin g TAOS caus es TPOS and TNEG inputs to be ignored. TAOS is inhi b ited during Remote Loopback.
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The LXT300Z and LXT301Z are fully integrated PCM
transceivers for both 1.544 Mbps (DSX-1) and 2.048
Mbps (E1) applications. Both transceivers allow fullduplex transmission of d igital data over existing twistedpair installations. The first page of this data sheet shows a
simplified block diagram of the LXT300Z; Figure 2
shows the LXT301Z. The LXT301Z is similar to the
LXT300Z, but does not incorporate the Jitter Attenuator
and associated Elastic Store, or the serial interface port.
The LXT300Z and LXT301Z transceivers each interface
with two twisted-pair lines (one twisted-pair for transmit,
one twisted-pair for receive) through standard pulse transformers and appropriate resistors.
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The LXT300Z and LXT301Z are low-power CMOS
devices. Each operates from a single +5 V power supply
which can be connected externally to both the transmitter
and receiver . Ho wev er , the two inputs must be within ± .3V
of each other, and decoupled to their respective grounds
separately. Refer to Application Information for typical
decoupling circuitry. Isolation between the transmit and
receive circuits is provided internally.
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Upon power up, the transceiver is held static until the
power supply reaches approximately 3 V. Upon crossing
this threshold, the device begi ns a 32 ms reset cycle to calibrate the transmit and receive delay lines and lock the
Phase Lock Loop to the receive line. A reference clock is
required to calibrate the delay lines. The transmitter reference is provided by TCLK. MCLK provides the receiver
reference for the LXT301Z. The crystal oscillator provides the receiver reference in the LXT300Z. If the
LXT300Z crystal oscillator is grounded, MCLK is used as
the receiver reference clock.
The transceiver can also be reset from the Host or Hardware Mode. In Host Mode, reset is commanded by simultaneously writing RLOOP and LLOOP to the register. In
Hardware Mode, reset is commanded by holding RLOOP
and LLOOP High simultaneously for 200 ns. Reset is initiated on the falling edge of the reset request. In either
mode, reset clears and sets all registers to 0 and then be gins
calibration.
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The transceiver incorporates an advanced Driver Performance Monitor (DPM) in parallel with the TTIP and
TRING at the output transformer . The DPM circuitry uses
four comparators and a 150 ns pulse d iscri minato r to filter
glitches.The DPM output le vel goes hi gh upon d etection of
63 consecutive zeros, and is cleared when a one is detected
on the transmit line, or when a reset command is received.
The DPM output also goes High to indicate a ground on
TTIP or TRING. A grou nd fault induced DPM f lag is automatically cleared when the ground condition is corrected
(chip reset is not required).
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LXT300Z Only: The LXT300Z can be controlled by a
microprocessor through a serial interface (Host Mode).
The mode of operation is set by the MODE pin l ogic le vel.
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Mode RPOS and RNEG outputs are valid on the rising
edge of RCLK. The LXT301Z operates in Hardware
Mode at all times.
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must be set Low. Equalizer Control signals (EC1 through
EC3) are input on the Interrupt, Serial Data In and Serial
Data Out pins. Diagnostic control for Remote Loopback
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CRC4 framer. Resistors are installed in line with the transmit transformer for loading a 75 Ω coaxial cable. The inline resistors are not required for transmission on 120 Ω
shielded twisted-pair lines. As in the T1 application Figure
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and RLOOP are individually controllable, and the LLOOP
and RLOOP lines are also tied to a single control for the
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