Datasheet LVT22V10-DN, LVT22V10-DD, LVT22V10-DA, LVT22V10-BN, LVT22V10-BD Datasheet (Philips)

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LVT22V10

3V high speed, universal PLD device

Product specification Supersedes data of 1996 Mar 12 IC13 Data Handbook

1998 Feb 10

INTEGRATED CIRCUITS

Page 2

Philips Semiconductors Product specification

LVT22V103V high speed, universal PLD device

1998 Feb 10 853-1759 18947

FEA TURES

•Fastest 3V PLD

•Supports 3/5V mixed systems

•Low ground bounce (<1.1V worst case)

•Live insertion/extraction permitted

•Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

•Metastable hardened device

•High output drive capability: 32mA/–16mA

•Varied product term distribution with up to 16 product terms per

output for complex functions

•Programmable output polarity

•Available in 300 mil-wide 24-pin Plastic Small Outline Package

•Design support provided for third party CAD development and

programming hardware

DESCRIPTION

The LVT22V10 is a versatile PAL device fabricated on the Philips BiCMOS QUBiC process.

The QUBiC process produces very high speed 3V devices (7.5ns) which have excellent noise characteristics. Ground bounce of an output held low while the remaining 9 outputs switch from high to low is typically less than 0.7V. V

bounce of an output held high while the remaining 9 outputs switch from low to high is typically less than 1.0V .

The LVT22V10 was designed to support mixed 3/5V systems. The inputs are capable of handling 7V while the outputs can be pulled up to 7V .

The designer can interface directly from 5V outputs (CMOS full rail or totem pole) to a 3V LVT input. A 3V LVT output can drive a 5V TTL input directly , or in the case of a CMOS input, the LVT output can interface with the use of an external pull-up resistor. Finally, no external pull-up resistors are needed on unused input pins due to a bus-hold data structure designed into the LVT input.

The LVT22V10 has been designed with high drive outputs (32mA sink and 16mA source currents), which allows for direct connection to a backplane bus. This feature eliminates the need for additional, standalone bus drivers, which are traditionally required to boost the drive of a standard PLDs.

The LVT22V10 outputs are designed to support Live Insertion/Extraction into powered up systems. The output is specially designed so that during V

ramp, the output remains

3-Stated until V

 2.1V . At that time the outputs become fully functional depending upon device inputs. (See DC Electrical Characteristics, Symbol I

PU/PD,

Page 5). In addition when an

LVT22V10 output is tied to a 5V bus, no bus current is loaded. The LVT22V10 uses the familiar AND/OR logic array structure,

which allows direct implementation of sum-of-products equations. This device has a programmable AND array which drives a fixed OR

array. The OR sum of products feeds an “Output Macro Cell” (OMC) which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.

PIN CONFIGURATIONS

1234 5 6 7 8 9

10 11

12 13 14 15 16 17

262728

1 2 3 4 5 6 7 8

9 10 11 12 13

D and N Packages

I0/CLK

I1 I2 I3 I4 I5 I6 I7 I8 I9

I10

F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 I11

GND

A Package (standard)

CLK/

I1I2

I3 I4 I5

GND

I9 I10

GND

I11 F0 F1

F7 F6 F5

F8F9V

A = Plastic Leaded Chip Carrier

N = Plastic Dual In-Line Package (300mil-wide) D = Plastic Small Outline Large (300mil-wide) Package

SP00436

1234 5 6 7 8 9

10 11

12 13 14 15 16 17

262728

A Package (evolutionary)

CLK/

I1I2

I3 I4 I5

I9 I10

GND

I11 F0 F1

F7 F6 F5

F8F9V

A = Plastic Leaded Chip Carrier

GND

PAL is a registered trademark of Advanced Micro Devices, Inc.

Page 3

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

ORDERING INFORMATION

PACKAGES ORDER CODE DWG NUMBER

24-Pin Plastic DIP (300mil) LVT22V10-7N (8.0ns device) SOT222-1 28-Pin PLCC (standard pinout) LVT22V10B7A (7.5ns device) SOT261-3 28-Pin PLCC (evolutionary pinout) LVT22V10-7A (7.5ns device) SOT261-3 24-Pin Plastic SOL LVT22V10-7D (8.0ns device) SOT137-1

PIN LABEL DESCRIPTIONS

SYMBOL DESCRIPTION

I1 – I11 Dedicated Input

F0 – F9 Macro Cell Input/Output

CLK/I0 Clock Input/Dedicated Input

Supply Voltage

GND Ground

NC No Connection

THERMAL RATINGS

TEMPERATURE

Maximum junction 150°C Maximum ambient 75°C Allowable thermal rise ambient to junction 75°C

OPERATING RANGES

RATINGS

SYMBOL

PARAMETER

MIN MAX

UNIT

Supply voltage +3.0 +3.6 V

amb

Operating free-air temperature

0 +75 °C

ABSOLUTE MAXIMUM RATINGS

RATINGS

SYMBOL

PARAMETER

MIN MAX

UNIT

Supply voltage

–0.5 +4.6 V

Input voltage

–0.5 7 V

OUT

Output voltage

–0.5 5.5 V

Input currents –30 +30 mA

OUT

Output currents +100 mA

stg

Storage temperature range –65 +150 °C

NOTES:

1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

2. Except in programming mode.

3. Outputs can be pulled up to 7V via external pull-up resistor.

Page 4

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

TEST CIRCUIT AND WAVEFORMS

AMP (V)

NEGATIVE PULSE

10% 10%

90%

AMP (V)

POSITIVE PULSE

90% 90%

10%

THL

(tF)

TLH

(tR)t

THL

(tF)

TLH

(tR)

VM = 1.5V

DEFINITIONS

=Load resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

see AC CHARACTERISTICS for value.

=Termination resistance should be equal to Z

OUT

of pulse

generators.

INPUT PULSE REQUIREMENTS

FAMILY

LVT

PULSE

GENERATOR

D.U.T.

OUT

Test Circuit for 3-State Outputs

6.0V

OPEN

GND

SWITCH POSITION

TEST SWITCH

PLH/tPHL

Open

PLZ/tPZL

PHZ/tPZH

GND

SP00385

Input Pulse Definition

Amplitude Rep. Rate t

3.0V 10MHz 500ns 2.5ns 2.5ns

Page 5

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

DC ELECTRICAL CHARACTERISTICS

Over operating ranges.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN MAX

UNIT

Input voltage

Low VCC = MIN 0.8 V

High VCC = MAX 2.0 V

Clamp VCC = MIN, IIN = –18mA –1.2 V

Output voltage

VCC = MIN to MAX, VI = V

or VILIOH = –100 µA VCC–0.2 V

High-level output voltage

IOH = –16mA 2.0 V

MIN, V

IOH = –5.5 mA 2.4 V

VCC = MIN to MAX, VI = VIH or VILIOL = 100µA 0.2 V

Low-level output voltage

IOL = 32 mA 0.5 V

MIN, V

IOL = 16 mA 0.4 V

Input current

Low VCC = MAX, VIN = 0.0V –10 µA

High VCC = MAX, VIN = V

10 µA

Max input current VCC = MAX, VIN = 5.5V 10 µA

Pin 1 (program) VCC = MAX, VIN = 5.5V 20 µA

BHL

Bus hold low sustaining current

VCC = 3V, VI = 0.8V 75 µA

BHH

Bus hold high sustaining current

VCC = 3V, VI = 2V –75 µA

BHLO

Bus hold low overdrive current

4, 9

VCC = 3.6V 500 µA

BHHO

Bus hold high overdrive current

5, 9

VCC = 3.6V –500 µA

Output current

OFF

Output off current VCC = 0V, VI or VO = 0 to 4.5V ±10 µA

Current into an output in high state when VO > V

VO = 5.5V, VCC = 3.0V ±100 µA

PU/PD

Power-up/down 3-State output current

VCC <1.2V; VO = 0.5V to VCC;

VI = GND or VCC; OE/OE = X

100 µA

VCC = MAX

OZH

Output leakage

VIN = VIL or VIH, V

OUT

= 5.5V 10 µA

OZL

Output leakage

VIN = VIL or VIH, V

OUT

=0V –10 µA

Short circuit

OUT

= 0.5V –30 –220 mA

VCC supply current VCC = 3.6V, Outputs enabled, VI = VCC or GND; IO = 0 170 mA

Ground/VCC Bounce MIN TYP MAX UNIT

OHV

Maximum dynamic V

VCC = 3.0V , 25°C,

CL = 50pF (including jig capacitance)

2.2 2.3 V

VCC = 3.3V , 25°C, CL = 50pF

LVT22V10-7 0.7 1.1 V

OLP

Maximum dynamic V

, ,

(including jig capacitance)

LVT22V10B7 1.0 1.1 V

NOTES:

1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

2. The bus hold circuit can sink at least the minimum low sustaining current at V

MAX. I

BHL

should be measured after lowering VIN to GND

and then raising it to V

MAX.

3. The bus hold circuit can source at least the minimum high sustaining current at V

MIN. I

BHL

should be measured after raising VIN to V

and then lowering it to V

IH MIN.

4. An external driver must source at least I

BHLO

to switch this node from low to high.

5. An external driver must sink at least I

BHHO

to switch this node from high to low.

6. I/O pin leakage is the worst case of I

OZX

or IIX (where X = H or L).

7. No more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. V

OUT

= 0.5V has been

chosen to avoid test problems caused by tester ground degradation.

8. This parameter is valid for any V

between 0V and 1.2 V with a transition time up to 10 mS. From VCC = 1.2 to VCC = 3.3V ±0.3V a

transition time of 100 µS is permitted. X = Don’t care.

9. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where input

current may be affected.

Page 6

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

AC ELECTRICAL CHARACTERISTICS

Over commercial operating temperature range.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

Input or feedback to non-registered output

Active-LOW 7.5 ns

PLCC package

Active-HIGH 7.5 ns

Input or feedback to non-registered output

Active-LOW 8.0 ns

DIP and SOL packages

Active-HIGH 8.0 ns

Setup time from input, feedback or SP to Clock 5.5 ns

Hold time 0 ns

Clock to output 5.0 ns

Clock to feedback

3.0 ns

Asynchronous Reset to registered output 12.0 ns

ARW

Asynchronous Reset width 5.0 ns

ARR

Asynchronous Reset recovery time 5.0 ns

SPR

Synchronous Preset recovery time 5.0 ns

Width of Clock LOW 3.0 ns

Width of Clock HIGH 3.0 ns Maximum frequency;

External feedback 1/(tS + tCO)

95 MHz

MAX

Maximum frequency; Internal feedback 1/(tS + tCF)

118 MHz

Input to Output Enable

8.5 ns

Input to Output Disable

8.5 ns

Capacitance

Input Capacitance (Pin 1) VIN = 2.0V

6 pF

Input Capacitance (Others) VIN = 2.0V

= 3.3V,

amb

= 25°C,

6 pF

OUT

Output Capacitance V

OUT

= 2.0V

f = 1MHz

8 pF

NOTES:

1. Test Conditions: R

= 500Ω, R2 =500Ω

2. t

is tested with switch S1 open and CL = 50pF (including jig capacitance). VIH = 3V, VIL = 0V, VT = 1.5V .

3. Calculated from measured f

MAX

internal.

4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency

may be affected.

5. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and

closed for high-impedance to Low tests. Output disable times are tested with C

= 5pF. High-to-High impedance tests are made to an output

voltage of V

= (VOH – 0.3V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.3V) level with S1 closed.

6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where

capacitance may be affected.

Page 7

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

PRODUCT FEATURES Low Ground Bounce

The Philips Semiconductors BiCMOS QUBiC process results in exceptional noise immunity. Ground bounce is noise that is generated on a non-switching active low output when other outputs on the device switch from high to low. The worst case condition occurs when 9 outputs simultaneously switch from high to low and the tenth output is active low. The ground bounce on this tenth output for Philips LVT22V10 is typically less than 0.7V.

VCC Bounce

VCC bounce occurs on a non-switching active high output when other outputs are making a low to high transition. This specification is important to consider in 3.3V designs because of the reduced noise margin between V

and VOH of only 1.3V relative to the traditional 5V system’s noise margin of 3V. The Philips LVT22V10 V

bounce of an output held high while the remaining 9 outputs

switch from low to high is typically less than 1.0V in magnitude.

Live Insertion/Extraction Capability

There are some inherent problems associated with inserting or extracting an unpowered module from a powered-up, active system. The LVT22V10 outputs have been designed such that any chance of bus contention, glitching or clamping is eliminated.

Detailed information on this feature is provided in an application note AN051:

Philips PLDs Support Live Insertion Applications

Bus Hold Input Structure

Bus Hold is a feature that maintains the input state of the device by incorporating a weak latch into the input structure. This latch maintains the input state until a minimum level of current (called the overdrive current) is supplied to change the input state. This is useful in bus applications where the bus is placed into a high impedance state. The LVT22V10’s inputs, in this high impedance situation, maintain valid logic levels until the bus is actively driven to a new state.

Improved Fuse Verification Circuitry Increases Reliability

Philips has developed a new means of testing the integrity of fuses, both blown and intact fuses, which insures that all the fuses have been correctly programmed and that each and every fuse – whether “blown” or “intact” – is at the appropriate and optimal fuse resistance. This dual verify scheme represents a significant improvement over single reference voltage comparisons schemes that have been used for bipolar devices since the late 1980s. Detailed information on this feature is provided in an application note entitled

Dual Verify Technique Increases Reliability of PLDs

Programmable 3-stage Outputs

Each output has a 3-Stage output buffer with 3-State control. A product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feedback. The combinatorial output provides a bidirectional I/O pin, and may be configured as a dedicated input if the buffer is always disabled.

Programmable Output Polarity

The polarity of each macro cell output can be Active-HIGH or Active-LOW, either to match output signal needs or to reduce

product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts.

Selection is controlled by programmable bit S

in the Output Macro Cell, and affects both registered and combinatorial outputs. Selection is automatic, based on the design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be Active-HIGH (S

= 1).

Preset/Reset

For initialization, the LVT22V10 has additional Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous Preset (SP) product term is asserted high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the Asynchronous Reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW, independent of the clock.

Note that Preset and Reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected.

Power-Up Reset

All flip-flops power-up to a logic LOW for predictable system initialization. Outputs of the LVT22V10 will depend on the programmed output polarity. The V

rise must be monotonic and

the reset delay time is 1–10µs maximum.

Security Fuse

After programming and verification, LVT22V10 designs can be secured by programming the security fuse link. Once programmed, this fuse defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the security fuse is programmed, the array will read as if every fuse is programmed.

Quality and Testability

The LVT22V10 offers a very high level of built-in quality. Extra programmable fuses provide a means of verifying performance of all AC and DC parameters. In addition, this verifies programmability and functionality of the device to provide the highest programming and post-programming functional yields.

T echnology

The BiCMOS LVT22V10 is fabricated with the Philips Semiconductors process known as QUBiC. QUBiC combines an advanced, state-of-the-art 1.0µm (drawn feature size) CMOS process with an ultra fast bipolar process to achieve superior speed and drive capabilities. QUBiC incorporates three layers of Al/Cu interconnects for reduced chip size, and our proven Ti-W fuse technology ensures highest programming yields.

Programming

The LVT22V10 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL

CUPL and PALASM 90

design software packages also support the LVT22V10 architecture. All packages allow Boolean and state equation entry formats, SNAP,

ABEL and CUPL also accept, as input, schematic capture format.

ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. PALASM is a registered trademark of AMD Corp.

Page 8

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

Output Register Preload

The register on the LVT22V10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. The procedure for preloading follows:

1. Raise V

to 3.3V ± 0.3V .

2. Set pin 2 or 3 to V

to disable outputs and enable preload.

3. Apply the desired value (V

ILP/VIHP

) to all registered output pins.

Leave combinatorial output pins floating.

4. Clock Pin 1 from V

ILP

to V

IHP

5. Remove V

ILP/VIHP

from all registered output pins.

6. Lower pin 2 or 3 to V

ILP

7. Enable the output registers according to the programmed

pattern.

8. Verify V

OL/VOH

at all registered output pins. Note that the output

pin signal will depend on the output polarity.

PRELOAD SET -UP

LIMITS

SYMBOL PARAMETER MIN REC MAX UNIT

Super-level input voltage 9.5 9.5 10 V

ILP

Low-level input voltage 0 0 0.8 V

IHP

High-level input voltage 2.4 3.3 3.6 V

Delay time 100 200 1000 ns

I/O

I/O valid after Pin 2 or 3 drops from VHH to V

ILP

100 ns

IHP

ILP

IHP

ILP

I/O

PINS 2, 3

REGISTERED OUTPUTS

CLOCK

Output Register Preload Waveform

DATA IN DATA OUT

ILP

SP00373

Page 9

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

L VT22V10 TIMING CHARACTERIZATION

Normalized tCO vs Temperature

= 3.3V , output capacitance = 50pF, 5outputs switching)

Normalized t

vs Temperature

= 3.3V , output capacitance = 50pF, 5 outputs switching)

Normalized t

vs V

(temp = 25°C, output capacitance = 50pF, 5 outputs switching)

Temperature (°C) Temperature (°C)

Supply Voltage (V) Supply Voltage (V)

Normalized t

1.20

1.10

1.00

0.90

0.80

RISE FALL

Normalized tPD vs V

(temp = 25°C, output capacitance = 50pF, 5 outputs switching)

The timing characterization represents the average values of a representative sample for each parameter. The data can be used to derate the MAX AC CHARACTERIZATION based upon the specific user design. Philips guarantees the MAX AC CHARACTERIZATION specifications.

SP00386

1.05

1.00

0.95

0.85 025 50 75

1.10

1.00

0.90

0.80 0255075

1.20

1.10

1.00

0.90

0.80

3.0 3.1 3.2 3.3 3.4 3.5

RISE FALL

0.90

RISE FALL

3.6

RISE FALL

3.0 3.1 3.2 3.3 3.4 3.5 3.6

Page 10

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

L VT22V10 TIMING CHARACTERIZATION

Delta t

vs Number of Outputs Switching

= 3.3V , temp = 25°C, output capacitance = 50pF)

Delta t

vs Number of Outputs Switching

= 3.3V , temp = 25°C, output capacitance = 50pF)

Delta t

vs Output Capacitance

(VCC = 3.3V , temp = 25°C, 5 Outputs Switching)

Delta tPD vs Output Capacitance

(VCC = 3.3V , temp = 25°C, 5 Outputs Switching)

100

–300

–500

–700

12345678910

Number of Outputs Switching Number of Outputs Switching

Output Capacitance Output Capacitance

Delta t (ns)

Delta t (ps)

Delta t (ns)

SP00387

–100

0.10

0.00

–0.20

–0.50

–0.60

–0.90

–1.10

1234 56 78910

–0.10

–0.40

–0.70

–1.00

10 50 100 200 400

5.00

4.00

1.00

–2.00

3.00

0.00

10 50 100 200 400

RISE FALL

–400

–600

–200

RISE FALL

–1.00

2.00

6.00

7.00

RISE FALL

–0.30

–0.80

RISE FALL

5.00

4.00

1.00

–2.00

3.00

0.00

–1.00

2.00

6.00

7.00

Delta t (ns)

Page 11

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

LOGIC DIAGRAM

NOTE:

Programmable connection.

1 1 0 0

0 1 0 1

Q Q

0 1

1 1 0 0

0 1 0 1

0 1

1 1 0 0

0 1 0 1

0 1

1 1 0 0

0 1 0 1

0 1

1 1 0 0

0 1 0 1

0 1

1 1 0 0

0 1 0 1

0 1

1 1 0 0

0 1 0 1

0 1

1 1 0 0

0 1 0 1

0 1

1 1 0 0

0 1 0 1

0 1

1 1 0 0

0 1 0 1

0 1

0 3 4 7 8 1112 1516 1920 2324 2728 3132 3536 3940 43

CLK/I0

I10

GND

I11

0 1

110

111

121

122

130

131

SP00059

Page 12

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

FUNCTIONAL DIAGRAM

OUTPUT

MACRO

CELL

CLK/I0 I1 – I11

F0 F1 F2 F3 F4 F5 F6 F7 F8 F9

PROGRAMMABLE AND ARRAY

(44 × 132)

1 11

81012141616141210 8

SP00060A

OUTPUT

MACRO

CELL

OUTPUT

MACRO

CELL

OUTPUT

MACRO

CELL

OUTPUT

MACRO

CELL

OUTPUT

MACRO

CELL

OUTPUT

MACRO

CELL

OUTPUT

MACRO

CELL

OUTPUT

MACRO

CELL

OUTPUT

MACRO

CELL

RESET

PRESET

Figure 1. Functional Diagram

FUNCTIONAL DESCRIPTION

The LVT22V10 allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function.

Product terms with all fuses opened assume the logical HIGH state; product terms connected to both True and Complement of any single input assume the logical LOW state.

The LVT22V10 has 12 inputs and 10 I/O Macro Cells (Figure 1). The Macro Cell allows one of four potential output configurations,

registered output or combinatorial I/O, Active-HIGH or Active-LOW (see Figure 2). The configuration choice is made according to the user’s design specification and corresponding programming of the configuration bits S

–S1. Multiplexer controls are connected to ground (0) through a programmable fuse link, selecting the “0” path through the multiplexer. Programming the fuse disconnects the control line from GND and it floats to V

(1), selecting the “1” path.

Page 13

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

OUTPUT MACRO CELL

1CLK

OUTPUT CONFIGURATION

0 = Unprogrammed fuse 1 = Programmed fuse

Registered/Active-LOW

Registered/Active-HIGH

Combinatorial/Active-LOW

Combinatorial/Active-HIGH

SP00375

Figure 2. Output Macro Cell Logic Diagram

CLK

= 0

a. Registered/Active-LOW

CLK

S0 = 1 S

= 0

b. Registered/Active-HIGH

= 0

= 1

c. Combinatorial/Active-LOW

d. Combinatorial/Active-HIGH

= 1

SP00376

Figure 3. Output Macro Cell Configurations

Registered Output Configuration

Each Macro Cell of the LVT22V10 includes a D-type flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the registered configuration (S1 = 0), the array feedback is from Q of the flip-flop.

Combinatorial I/O Configuration

Any Macro Cell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (S

= 1). In the

combinatorial configuration, the feedback is from the pin.

Variable Input/Output Pin Ratio

The LVT22V10 has twelve dedicated input lines, and each Macro Cell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity.

Page 14

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

INTERFACING IN MIXED 3V/5V SYSTEMS 3V Logic Driving 5V Logic

The LVT family has outputs that swing virtually between the power supply rails, thereby allowing direct interfacing with TTL switching levels.

When interfacing the outputs of any of our 3V logic ICs with standard TTL-level logic inputs (bipolar or CMOS HCT), the output levels from the 3V logic are sufficient to directly drive the 5V logic.

When driving CMOS-level devices (such as HC or AC), the output voltage from the 3V logic is insufficient to ensure reliable operation. This problem can be easily resolved by using a pull-up resistor at the interface.

5V Logic Driving 3V Logic

Since the LVT ICs do not have protection diodes between their inputs and V

, the inputs of these devices can therefore withstand higher levels than the supply voltage, and they can be directly connected to 5V CMOS logic outputs. For the LVT family, the combination of low power dissipation with the live insertion feature, bus hold and full 5V input/output capability make this logic ideal for

3.3V backplane interfacing.

INTERFACING 3 VOLT AND 5 VOLT LOGIC

FROM TO METHOD

TTL Inputs Direct

LVT Output

CMOS inputs Pull-up

CMOS Rail LVT Input Direct

Totem-Pole L VT Input Direct

Open Drain LVT Input Pull-up

LVT22V10 METASTABLE HARDENED CHARACTERISTICS

Metastable Hardened Characteristics

What is metastable hardened? Philips Semiconductors uses the term “metastable hardened” to describe a combination of two characteristic features. The first is a patented Philips circuit that prevents the outputs from glitching, oscillating, or remaining in the linear region under any circumstances, including setup and hold time violations. The second is the flip-flops’ inherent ability of resolving the metastable condition. Philips provides complete data on the LVT22V10’s metastable characteristics

With the LVT22V10, any tendency towards internal metastability is resolved by Philips Semiconductors patented circuitry. If a

metastable event occurs within the flop, the only outward manifestation of the event will be an increased clock-to-Q delay. This delay is a function of the metastability characteristics of the device, defined by τ and T

as described below. Since the outputs never glitch, oscillate, or remain in the linear region, the only metastable failure that can propagate further into the system is when the next flip-flop in the system samples the LVT22V10’s output at precisely the same time it is making a logic transition. By allowing sufficient time for any increased clock-to-Q delay , propagation of metastable failures can be avoided. The following design example illustrates this concept.

Design Example

Suppose a designer wants to use the LVT22V10 for synchronizing asynchronous data that is arriving at 2MHz (as measured by a frequency counter), in a 3.3V system that has a clock frequency of 33MHz, at an ambient temperature of 25°C. She has decided that she would like to sample the output of the LVT22V10 15ns after the clock edge to ensure that any clock-to-Q delays that were the result of the LVT22V10 internal metastability resolution circuitry have completed and the outputs have transitioned. The MTBF for this situation can be calculated by using the equation below:

MTBF = e(t’/τ )/T

OFCF1

In this formula, FC is the frequency of the clock, F1 is the average input event frequency , and t’ is the time after the clock pulse that the output is sampled (t’ > T

). TO and τ are device parameters provided by the semiconductor manufacturer (refer to the following table for the LVT22V10 metastability specifications). T

and τ are derived from tests and can be most nearly be defined as follows: τ is a function of the rate at which a latch in a metastable state resolves that condition. T

is a function of the measurement of the propensity

of a latch to enter a metastable state. T

is also a normalization constant, which is a very strong function of the normal propagation delay of the device.

In this situation the F

will be twice the data frequency, or 4MHz, because input events consist of both of low and high transitions. Thus, in this case, F

is 33MHz, F1 is 4MHz, τ is 317ps, t’ is 15ns,

and T

is 4.27 × 10-3 seconds. Using the above formula the actual

MTBF for this situation is 1.26 × 10

seconds or 39 years for the

LVT22V10.

Summary

The Philips LVT22V10 has on-chip circuitry that completely eliminates any output glitches, oscillations, or other output anomalies associated with metastable conditions. For outputs that are then used to generate clocks, control signals or other asynchronous data this represents an unparalleled level of reliability in a PLD. In addition, a complete set of metastability data is provided, that allows designers the ability to design robust systems where data is synchronously pipelined.

L VT22V10 VALUES FOR τ AND T

0°C 25°C 75°C

τ T

3.0V 829.00ps 1.16E–08 691.00ps 1.09E–07 429.00ps 2.27E–04

3.3V 358.00ps 2.36E–04 317.00ps 4.27E–03 329.00ps 5.75E–03

3.6V 237.00ps 2.66E–01 230.00ps 6.47E–01 250.00ps 1.13E+00

Page 15

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

SWITCHING W AVEFORMS

Combinatorial Output

Registered Output

Clock to Feedback (f

MAX

Internal)

(See Path at Right)

Clock Width Input to Output Disable/Enable

Asynchronous Reset Synchronous Preset

INPUT OR

FEEDBACK

COMBINATORIAL

OUTPUT

INPUT OR

FEEDBACK

CLOCK

REGISTERED

OUTPUT

tS + t

CLOCK

LOGIC REGISTER

CLK

CLOCK

VOH – 0.3V V

+ 0.3V

INPUT

OUTPUT

ARW

ARR

CLOCK

REGISTERED

OUTPUT

INPUT ASSERTING

ASYNCHRONOUS

RESET

SPR

INPUT ASSERTING

SYNCHRONOUS

PRESET

CLOCK

REGISTERED

OUTPUT

SP00388

Clock to Feedback

NOTES:

1. V

= 1.5V .

2. Input pulse amplitude 0V to 3.0V.

3. Input rise and fall times 1.5ns max.

Page 16

Philips Semiconductors Product specification

LVT22V10

3V high speed, universal PLD device

1998 Feb 10

“AND” ARRAY – (I, B)

I, B

P, D

CODE

STATE

INACTIVE

CODESTATE CODESTATE CODESTATE

TRUE

HL—

P, D

I, B

P, D

I, B

P, D

I, B

COMPLEMENT DON’T CARE

SP00008

I, B I, B I, B I, B

NOTE:

1. This is the initial state.

POWER-UP RESET

The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation

of the power-up reset and the wide range of ways V

can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are:

1. The V

rise must be monotonic.

2. Following reset, the clock input must not be driven from LOW to

HIGH until all applicable input and feedback setup times are met.

Power-Up Reset Waveform

2.7V

POWER

REGISTERED

ACTIVE-LOW

OUTPUT

CLOCK

SP00389

LIMITS

SYMBOL PARAMETER MIN MAX UNIT

Power-up Reset Time 1 µs

Input or Feedback Setup Time See AC Electrical

Clock Width LOW Characteristics

Page 17

Philips Semiconductors Product specification

L VT22V103V high speed, universal PLD device

1998 Feb 10

DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1

Page 18

Philips Semiconductors Product specification

L VT22V103V high speed, universal PLD device

1998 Feb 10

PLCC28: plastic leaded chip carrer; 28 leads; pedestal SOT261-3

Page 19

Philips Semiconductors Product specification

L VT22V103V high speed, universal PLD device

1998 Feb 10

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

Page 20

Philips Semiconductors Product specification

L VT22V103V high speed, universal PLD device

1998 Feb 10

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

Date of release: 02-98

Document order number: 9397 750 03313

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Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Datasheet LVT22V10-DN, LVT22V10-DD, LVT22V10-DA, LVT22V10-BN, LVT22V10-BD Datasheet (Philips)

Specifications and Main Features

Frequently Asked Questions

User Manual