Page 1
Overview
The LV1100 is an audio signal-processing Bi-CMOS LSI
that integrates input and output filters, a delay line (builtin memory), and a delay/reverb function with a maximum
delay of 120 ms on a single chip. It also provides built-in
fixed matrix (L+R, L–R) and front mixing (with level and
phase switching) functions. A full complement of
surround modes can be easily implemented by combining
these functions.
Functions and Features
• Input switching (L+R, L–R, IN–A)
• On-chip memory (12K SRAM)
• Front adder (+3 dB, 0 dB, –3 dB, -∞)
• Input and output filters
• Input filter –7 kHz low-pass filter
• Output filter –5 kHz low-pass filter: switchable with a
3 kHz low-pass filter
• On-chip VDDcircuit
• Input and output muting function
• A simulated surround system can be easily implemented
with only one chip.
• ADM A/D and D/A converters
• Variable delay times
– Short mode; Maximum delay: 60 ms. Delay time
selectable from six delay times in 10-ms steps.
– Long mode; Maximum delay: 120 ms. Delay time
selectable from six delay times in 20-ms steps.
Package Dimensions
unit: mm
3067-DIP24S
Bi-CMOS LSI
Ordering number : EN5506
83196HA (OT) No. 5506-1/10
SANYO: DIP24S
[LV1100]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
Digital Surround Audio Signal-Processing IC
LV1100
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage V
CC
max 12 V
Allowable power dissipation Pd max Ta ≤ 70°C 420 mW
Operating temperature Topr –25 to +70 °C
Storage temperature Tstg –40 to +125 °C
Parameter Symbol Conditions Ratings Unit
Recommended supply voltage V
CC
9V
Operating supply voltage range V
CC
opg 8 to 10 V
Specifications
Absolute Maximum Ratings at Ta = 25°C
Allowable Operating Ranges at Ta = 25°C
Page 2
No. 5506-2/10
LV1100
Electrical Characteristics at Ta = 25°C, VCC= 9 V, RL= 20 kΩ, VIN= 300 mV and f = 1 kHz unless otherwise specified.
Parameter Symbol Conditions
Ratings
Unit
min typ max
Quiescent current I
CCO
15 28 42 mA
V
O
maxA
OUT-A, CLOCK FAST, THD = 10%
0.7 1.0 V
V
CC
= 8 V
Maximum output voltage
V
O
maxL OUT-L, THD = 1% (effect off), VCC= 8 V 1.6 V
V
O
maxR OUT-R, THD = 1% (effect off), VCC= 8 V 1.6 V
V
NO
AF
OUT-A, CLOCK FAST (5 kHz L.P.F)
–89 –80 dBV
JIS A, Rg = 10 kΩ
VNOAS
OUT-A, CLOCK SLOW (3 kHz L.P.F)
–84 –75 dBV
JIS A, Rg = 10 kΩ
Output noise voltage V
NO
L OUT-L (effect off), JIS A, Rg = 10 kΩ –103 –95 dBV
V
NO
R OUT-R (effect off), JIS A, Rg = 10 kΩ –103 –95 dBV
V
NO
LE OUT-L (effect –3 dB), JIS A, Rg = 10 kΩ –88 –80 dBV
V
NO
RE OUT-R (effect –3 dB), JIS A, Rg = 10 kΩ –88 –80 dBV
VGA OUT-A, CLOCK FAST –4 0 4 dB
Output level deviation VGL OUT-L (effect off) –2 0 2 dB
VGR OUT-R (effect off) –2 0 2 dB
THDAF
OUT-A, CLOCK FAST (5 kHz L.P.F):
0.3 1.0 %
400 to 30 kHz BPF
Total harmonic distortion
THDAS
OUT-A, CLOCK SLOW (3 kHz L.P.F):
0.6 1.5 %
400 to 30 kHz BPF
THDL OUT-L (effect off): 400 to 30 kHz B.P.F 0.01 0.03 %
THDR OUT-R (effect off): 400 to 30 kHz B.P.F 0.01 0.03 %
Parameter Symbol Conditions Ratings Unit
Control data
V
IL
0 to 1.5 V
Input low-level voltage
Control data
V
IH
3.5 to 5.5 V
Input high-level voltage
Control Data
Page 3
Test Circuit
Notes: 1. The items D1 through D10 in the figure indicate points that are switched by the serial data.
2. Use capacitors with good high-frequency characteristics for the capacitors on pins 7, 14, and 22. Also, connect 0.1-µF ceramic capacitors in
parallel.
Note: The items D1 through D10 in the figure indicate points that are switched by the serial data.
Application Circuit Example
No. 5506-3/10
LV1100
Page 4
Block Diagram
Functional Description
1.INPUT PHASE SELECT
Selects either the input summation signal (L+R) or the input difference signal (L-R). When set to low, L+R is selected,
and when set to high, L-R is selected.
2.INPUT SELECT
Selects either the IN-L and IN-R input signals, or the IN-A input signal.
3.INPUT FILTER
Selects whether the signal input from either IN-L and IN-R or IN-A is passed through a 7-kHz low-pass filter, or
whether it is directly input to the delay block.
4.DELAY
In clock fast mode, creates one of six delayed signals with delays of 10 to 60 ms in 10-ms steps.
In clock slow mode, creates one of six delayed signals with delays of 20 to 120 ms in 20-ms steps.
5.VOL (effect volume)
Selects the amount of the front L and R signals added to the delayed signal. Possible settings are +3 dB, 0 dB, –3 dB,
and –∞.
6.OUTPUT PHASE SELECT
Selects in-phase (+ setting) or out-of-phase (– setting) with respect to the left channel for the right channel of the VOL
output signal.
7.REVERVE SW
Set this switch to the on position to specify that the surround system output signal be fed back.
8.IN-A OUTPUT FILTER
Allows the signal to be output after passing through a 3-kHz low-pass filter.
No. 5506-4/10
LV1100
Page 5
Command List
LV1100 Control Format
A = L ... Selects the LV1100.
B = L ... When B is low, the mode settings listed below can be made.
B = H ... When B is high, the mode settings listed below can be made.
* = don’t care
No. 5506-5/10
LV1100
L H
D1 IN-A DELAY L+R, L–R DELAY
D2 L+R L–R
D3 DELAY OUT ON; DELAY OUT OFF;
Turns on surround system feedback Turns off surround system feedback
7 kHz L.P.F ON/OFF
D4, D5
LL THROUGH
LH NOT USE
HL FILTER
HH A/D INPUT MUTE
L H
D6 OUT-L, –R MUTE ON OUT-L, –R MUTE OFF
D7 OUT-A MUTE ON OUT-A MUTE OFF
D8 FRONT ADD INPHASE FRONT ADD INVERTED PHASE
(In-phase addition) (Out-of-phase addition)
FRONT ADD EFFECT VOL (Addition to the front left and right channels)
D9, D10
LL +3 dB
LH 0 dB
HL –3 dB
HH MUTE
D1 D2 IN-A output filter
L L 3 kHz L.P.F-OFF
L H 3 kHz L.P.F-ON
D3 D4 D5
* * *
Page 6
No. 5506-6/10
LV1100
Delay Time Data (D6 to D8)
Note: D6, D7, and D8 must not be used for any purposes other than the above commands.
D6 D7 D8 CLK FAST CLK SLOW
L L L 10 ms 20 ms
L L H 20 ms 40 ms
L H L 30 ms 60 ms
L H H 40 ms 80 ms
H L L 50 ms 100 ms
H L H 60 ms 120 ms
L H
D9 SYSTEM MUTE ON SYSTEM MUTE OFF
D10 CLK FAST CLK SLOW
Control Data Format
• Data is read in on the rising edge of the clock.
• The control data consists of 12 bits.
• The input data is latched on the rising edge of the enable signal.
• The clock and enable signals must be held high when not being used to control the LV1100.
• Command interval time
The timing of intervals between enable signals must meet the conditions shown in the figure.
Notes on Mode Control (System Mute Usage)
1 When power is first applied, after the IC is fully operating (about 2 seconds after power is applied) applications must
send commands that turn the system muting off and then on again.
2 Applications must perform system muting on/off operations when switching the delay time or clock fast/slow
settings. After sending a system muting on command along with the new data, send the new data again, this time with
a system muting off command.
Note: By performing the operations described in items 1 and 2 here, the memory contents are initialized, thus preventing incorrect operation.
Page 7
Data Timing
No. 5506-7/10
LV1100
Parameter Symbol Conditions
Ratings
Unit
min typ max
Enable clock delay time tec 5 µs
Data clock delay time tdc 5 µs
Clock high-level hold time tch 5 µs
Clock low-level hold time tcl 5 µs
Clock cycle time tck 10 µs
Timing Characteristics
Page 8
No. 5506-8/10
LV1100
Pin no. Pin Pin voltage Internal equivalent circuit
1 DIGITAL–GND 0 V
2 CLK
Control voltage
Apply a voltage of 0 or 5 V.
3 DATA
Control voltage
Apply a voltage of 0 or 5 V.
4 ENABLE
Control voltage
Apply a voltage of 0 or 5 V.
5 REV-OUT 1/2 V
CC
1/2 V
CC
6 REV-IN Apply the voltage output by pin
5 through an external resistor.
7 V
CC
VCC(Power-supply voltage)
8 IN-L 1/2 V
CC
9 IN-R 1/2 V
CC
10 IN-AUX 1/2 V
CC
11 OUT-AUX 1/2 V
CC
12 DC-CUT 1/2 V
CC
Pin Functions
Continued on next page
Page 9
No. 5506-9/10
LV1100
Continued from preceding page
Pin no. Pin Pin voltage Internal equivalent circuit
13 L.P.F 1/2 V
CC
14 V
REF
1/2 V
CC
15 OUT-R 1/2 V
CC
16 OUT-L 1/2 V
CC
17 ANALOG-GND 0 V
18 DC-CUT 1/2 V
CC
19 A/D integrator 1/2 V
CC
20 A/D noise shaper 1/2 V
CC
21 D/A integrator 1/2 V
CC
22 V
DD
5 V
23
OSC Charged by 0 or 5 V.
24
Page 10
No. 5506-10/10
LV1100
This catalog provides information as of August, 1996. Specifications and information herein are subject to
change without notice.
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁
Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
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