Page 1
Preliminary Data Sheet
(
)
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Overview
The LU5X34F is a low-cost, low-power quad transceiver. It is used for data transmission over fiber or
IEEE
coaxial media in conformance with
Gigabit Ethernet specification and Fibre Channel
†
ANSI
X3T11 at 1.0 Gbits/s and
1.25 Gbits/s.
Each of the four transceivers independently provides
complete serialize/deserialize (SERDES) and transmit and receive functions. The device is available in a
217-pin PBGA package.
The transmitter section accepts TTL compatible data
at the 10-bit parallel input port. The parallel input
data is latched on the rising edge of TXCLKx. It also
accepts the low-speed, TTL compatible system
clock, REFCLK, and uses this clock to synthesize the
internal high-speed serial bit clock. The serialized
data is then available at the differential PECL outputs, terminated in 50 Ω or 75 Ω to drive eit her an
optical transmitter or coaxial media.
The receive section receives high-speed serial data
at its differential PECL input port. This data is fed to
the digital clock recovery section, which generates a
recovered clock and retimes the data. The retimed
data is deserialized and presented as 10-bit parallel
data on the output port. A divided-down version of
the recovered clock, synchronous with parallel data
bytes, is also available as a TTL compatible output.
The receive section recognizes the comma character
and aligns the comma-containing byte on the word
boundary, when ENCDET = 1.
* 802.3z
LU5X34F
Quad Gigabit Ethernet Transceiver
■
100 MHz—125 MHz differential or single-ended
reference clock.
■
10-bit parallel,
■
8-bit/10-bit encoded data.
■
High-speed comma character recognition (K28.1,
K28.5, K28.7
and ali
■
Two 50 MHz—62.5 MHz receive-byte clocks.
■
Single analog PLL design requires no external
nment to word boundary.
components for the fre
■
Novel digital data lock in receiver avoids the need
for multiple analo
■
Expandable beyond four serializer/deserializers.
■
PECL high-speed interface I/O for use with optical
TTL-compatible I/O interface
for latency-sensitive applications
uency synthesizer.
PLLs.
transceiver or coaxial copper media.
■
Requires one external resistor for PECL output reference-level definition.
■
Low-power digital CMOS technology.
■
Less than 2 W total power dissipation per quad
transceiver.
■
3.3 V ± 5% power supply.
■
0 °C—
70 °C ambient temperature.
■
Stand-alone transceiver product.
■
Transceiver ma crocell templat e.
■
Available in 217-pin PBGA package.
.
Features
■
Designed to operate in Ethernet, fibre channel,
Firewire
■
Operationally compliant to
Ethernet specification.
■
Operationally compliant to Fibre Channel
X3T11. Provides FC-0 services at 1.0
1.25 Gbits/s
‡
, or backplane applications.
10-bit encoded data rate).
IEEE
802.3z Gigabit
ANSI
Gbits/s—
*
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
†
ANSI
is a registered trademark of American National Standards
Institute.
‡
FireWire
is a registered trademark of Apple Computer, Inc.
Page 2
LU5X34F Preliminary Data Sheet
Quad Gigabit Ethernet Transceiver July 2000
Table of Contents
Contents Page Table Page
Overview....................................................................1
Features.....................................................................1
Functional Description .................................. ...... .......3
Transmitter Section.................................... ...... .......3
Receiver Section.....................................................3
Lock to Reference...................................................3
Byte Alignment........................................................4
Parallel Output Port.................................................4
Loopback Mode Operation..... ....... ...... ....... .............4
Powerup Sequence.................................................5
Device Reset...........................................................5
Sleep Mode.............................................................5
Block Diagrams.......................................................6
Block Diagrams (continued)....................................7
Input/Output Information ............................................8
Electrical Specifications ...........................................14
Transmitter............................................................14
Receiver................................................................14
Receiver (continued).............................................15
Timing Characteristics .............................................16
Serial Timing.........................................................16
Receiver Section Timing.......................................17
Receiver Port Timing.............................................17
Transmitter Section Timing .... ....... ...... ....... ...........18
Application Section ..................................................19
Test Modes ..............................................................22
Outline Diagram.......................................................24
217-pin PBGA.......................................................24
Ordering Information................................................25
Table 1. Receive Circuit Operating Modes .............3
Table 2. Definition of Bit Transmission/Reception
Order ....................................................................4
Table 3a. Pinout—Channel A I/O............................9
Table 3b. Pinout—Channel B I/O..........................10
Table 3c. Pinout—Channel C I/O..........................11
Table 3d. Pinout—Channel D I/O .........................12
Table 3e. Pinout—Common I/O............................13
Table 3f. Pinout—Power I/O .................................13
Table 4. Reference Clock Specifications
(REFCLK and REFCLKN) ..................................14
Table 5. PLL Specifications ..................................14
Table 6. Output Jitter at 1.0 Gbit/s—1.25 Gbits/s
Data Rate ...........................................................14
Table 7. Input Data Rate.......................................14
Table 8. Data Lock Characteristics.......................14
Table 9. Power Dissipation ...................................15
Table 10. dc Electrical Specifications ...................15
Table 11. Absolute Maximum Ratings ..................15
Table 12. Serial Output Timing Levels..................16
Table 13. Serial Input Interface Timing ................16
Table 14. Receiver Parallel Port Timing ...............17
Table 15. Transmitter Timing at Parallel Interface 18
Table 16. External Resistor Value vs. Differential
Output Level Viewing ............................. ............20
Table 17. External Resistor Value vs. Differential
Output Level Viewing ............................. ............21
Table 18. Test Modes ...........................................22
Figure Page
Figure 1. LU5X34F Quad Gigabit Ethernet Transceiver
Block Diagram........................................................ 6
Figure 2. LU5X34F Single-Channel Transceiver Func-
tional Diagram ........................................................ 7
Figure 3. Pin Designations (Top View) ..................... 8
Figure 4. Serial Interface Timing............................. 16
Figure 5. Receiver Section Timing.......................... 17
Figure 6. Receiver Port Timing ............................... 17
Figure 7. Parallel Interface Transmit Timing........... 18
Figure 8. Reference Clock Connections with Single-
Ended and Differential Sources............................ 19
Figure 9. Typical Termination for a Single-Channel,
High-Speed Serial Transmit-and-Receive Port in a
50 Ω Backplane Application ................................. 20
Figure 10. Typical Termination for a Single-Channel,
High-Speed Serial Transmit Port Interfacing a 5 V
GBIC Transceiver................................................. 21
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Preliminary Data Sheet LU5X34F
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July 2000 Quad Gigabit Ethernet Transceiver
Functional Description
The LU5X34F transceiver provides for data transmission over fiber or coaxial media at 1.0 Gbits/s to
1.25 Gbits/s. The block dia
is shown in Fi
pinout for the 217-pin PBGA packa
Fi
ure 3 and Table 3
ure 1 and the four-channel applica tion
.
Transmitter Section
The transmitter accepts 8b/10b encoded bits in 10-bit
parallel form and converts to serial format for up to
1.25 Gbits/s transmission. The serial nonreturn to zero
(NRZ) bits are then shifted out of the device at a maximum rate of 1.25 Gbits/s. Internally, the device uses
two parallel shift registers that operate at half rate (i.e.,
a maximum of 625 MHz) for reduced power consumption. The two shift registers drive the PECL output
buffer in an interleaved manner to construct the
1.25 Gbits/s output data stream.
The typical transmit-and-receive, high-speed I/O inter-
facing for a single-channel backplane application is
shown in Figure 9.
The transmit shift register and other circuits are driven
with clocks generated from a 500 MHz—625 MHz internal clock. This internal clock is sourced from a voltagecontrolled oscillator (VCO) that is locked to the external
reference of 100 MHz—125 MHz. The internal transmit
phase- lock loop multiplies the frequency of the input
reference clock by a factor of 5, and controls the transmit jitter bandwidth with appropriate design of the jitter
transfer function. The transmit phase-lock loop generates multiple clock phases that are all used by each of
the four receiver circuits. The clock phases are derived
from the transmit VCO.
ram of the quad transceiver
e is given in
Receiver Section
Each of the quad receiver circuits recovers clock from
and retimes the serial input data. The data is input to
the receiver on differential PECL buffers. External termination resistors are supplied by the user in accordance with
differential inputs, HDINP and HDINN, are ac-coupled
to the device and internally biased to the PECL input
common-mode range center. See Figure 9 for the typical application and termination of the transmission
lines.
The receiver data-retiming circuit uses a digital timing
recovery loop that compares the phase of the input
data to multiple phases of the on-device VCO in the
transmit section. One of the phases is chosen to retime
the receive data. A digital low-pass filter is used in the
timing recovery loop to reject jitter from the data input.
A novel phase interpolation circuit permits the retiming
clock’s phase to be stepped with fine resolution for precise alignment of the sampling clock within the data
eye. Use of this digital data locking scheme for each
receiver advantageously avoids the use of multiple
analog phase-lock loops on-device that can potentially
injection lock to one another. Additionally, the digital
data locking loop maintains precise loop dynamics,
hence, the jitter transfer function is process and temperature independent.
ANSI
standard, X3T11. The serial
Lock to Reference
The receive circuit has two modes of operation: lock to
reference, and lock to data with retiming. When no data
or invalid data is present on the HDINP and HDINN
input pins, the user can program the device to ignore
the input data by setting LCKREFN equal to logic 0. In
this mode, neither the PECL input buffer nor the RX
parallel data bus toggles. In normal operation, the
LCKREFN is a logic 1 and the receiver attempts to lock
to the incoming data. If the input data is invalid or outside the nominal ± frequency range, the receive digital
PLL will simply ramp the phase of the output clock until
it locks to data.
Table 1. Receive Circuit Operating Modes
Mode Lock to Reference Lock to Receive Data
LCKREFN = 1 (normal operation) Not applicable. Continually attempts to lock to
LCKREFN = 0 Lock to clock, output data does not
* REFCLK requirements are given in Table 4, and receive PLL specifications are given in Table 5.
Lucent Technologies Inc.
*
data.
Not applicable.
toggle. Disable PECL input buffer.
3
Page 4
LU5X34F Preliminary Data Sheet
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Quad Gigabit Ethernet Transceiver July 2000
Functional Description
(continued)
Byte Alignment
When ENCDET = 1, the LU5X34F recognizes the
comma character and ali
word boundar
COMDET =1 when the parallel output word contains a
te-aligned comma character. The COMDET flag will
b
continue to pulse a lo
comma character is at the parallel output port, independent of ENCDET. When ENCDET = 0, there are two
possible scenarios dependin
character is received.
1. If byte alignment had been previously achieved when
ENCDET had been a logic 1, the COMDET flag will
continue to pulse a logic 1 whenever a byte-aligned
comma character is at the parallel output port. If a
comma character occurs that is not on the word
boundary, no attempt will be made to align this
comma character and the COMDET flag will remain
at a logic 0.
2. If byte alignment had
when ENCDET had been a logic 1, then the first
(and only the first) comma character received will be
aligned to the word boundary. COMDET will pulse
when the comma character is aligned to the word
boundary.
, bits RX[0:9].
ns this 10-bit character to the
ic 1 whenever a byte-aligned
upon when the comma
not
been previously achieved
Parallel Output Port
Timing for the parallel output data and the 50 MHz to
62.5 MHz receive-byte clock is given in Table 14.
Two low data rate receive-byte clocks are available as
TTL compatible outputs during use of the parallel output port in 10-bit mode. RXCLK1 is the receive byte
clock used by the protocol device to register bytes 0
and 2. RXCLK0 is the receive-byte clock used by the
protocol device to register bytes 1 and 3, and it is
180 degrees out of phase with RXCLK1. Both RXCLK1
and RXCLK0 can be stretched during byte alignment
but not truncated or slivered. The maximum allowable
frequency of these two clocks under all circumstances,
excluding start-up, will not exceed 80 MHz. The startup time is specified as 1 ms.
Loopback Mode Operation
A control signal input, EWRAP, selects between two
possible sets of inputs: normal data
internal loopback data. When EWRAP = 1, the serial
output ports, HDOUTP and HDOUTN, remain active.
The serial transmit data prior to the PECL output driver
is directed to the data recover
recovered and data is res
clock. Retimed data and clock then
parallel converter
.
nchronized to the recovered
HDINP, HDINN) or
circuit, where clock is
o to the serial-to-
Table 2. Definition of Bit Transmission/Reception Order
Serial Transmit/
Receive Rate
1.0 Gbits/s to 1.25 Gbits/s TX
* Lower case X signifies channel A, B, C, or D.
[0] bit serially transmitted first at
X
HDOUT
X
TXX[9:0] RXX[9:0]
P, HDOUTXN
*
[0] bit received first at serial inputs
RX
X
HDIN
P, HDINXN
X
4
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Preliminary Data Sheet LU5X34F
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July 2000 Quad Gigabit Ethernet Transceiver
Functional Description
(continued)
Powerup Sequence
The power ramp time for the LU5X34F is specified at
DD
V
> 2.7 V within 20 µs of start-up. Once 2.7 V is
reached, the device is held in reset for 15 µs—70 µs.
The REFCLK mu st be ac tive a nd wit hin spec ific atio n at
this point and remain active while the device is powered up, unless in Reset.
When si
the followin
1. 0 µs—32 µs, the analog PLL is held at minimum fre-
quency to allow dc bias to settle.
2. 32 µs—262 µs, the analog PLL has locked-in and
receiver analog circuits start to lock-in.
3. 262 µs—326 µs, the receiver analog circuits are
locked; receiver starts to lock onto incoming data.
4. After 358 µs, the receiver is locked onto incoming
data and can be viewed at the parallel output ports.
The comma-detect circuit is enabled at this point,
allowing byte alignment if ENCDET = 1.
nals RESET, BYPPLL, and LPWR are all low,
start-up sequence occurs:
Sleep Mode
The LU5X34F has a sleep mode that is activated by
enablin
of the REFCLK is used to refresh the d
within the transceiver. The PLL is powered down in this
mode also. LCKREFN can also be activated to reduce
the power even further. Note that complete powerdown
for I
lo
ceiver. The lock-in se
comin
LPWR. In this mode, a divided-down version
namic circuits
DD
Q testing is not supported due to the dynamic
ic used in the high-speed sections of the trans-
uence timing is needed when
out of sleep mode.
If LCKREFN goes low after the 358 µs, the receiver will
sit idle. When LCKREFN goes high, the receiver will be
locked onto data after 2 µs.
Device Reset
The RESETN input to the device is active-low.
activated with a pulse duration of 1 µs, the RESETN si
nal
lobally resets the device a nd th e follow ing is per-
:
formed
1.
The sin
mum fre
be locked in this condition
2. The HDOUTP, HDOUTN outputs are forced to a
PECL logic 0.
3.
The deserializer clocks, but input data at HDINP,
HDINN is i
their previous state
4. T
he phase interpolation/se lection circu its are deact i-
vated and the selecte d pha se i s r eset.
5.
The receiver di
Normall
althou
PLL circuitr
hi
le analog PLL is forced to operate at the mini-
uency possible for its VCO. The PL L w ill not
.
nored and the RX[9:0] signals remain in
.
ital low-pass filter in the DPLL is r eset.
, a reset is not necessa ry for correct ope ration,
h a reset can aid rapid lock-in of the inter nal
. This active-low pin is internally pulled
.
h
When
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LU5X34F Preliminary Data Sheet
Quad Gigabit Ethernet Transceiver July 2000
Functional Description
Block Diagrams
LPWR RESET
HDINAP
HDINAN
HDOUTAP
HDOUTAN
HDINBP
HDINBN
HDOUTBP
HDOUTBN
REFCLK
REFCLKN
2
2
2
2
2
TRANSCEIVER A
TRANSCEIVER B
ANALOG PLL
(continued)
TXCLK[A:D]*
ENCDET[A:D]
COMDET[A:D]
EWRAP[A:D]
LCKREFN[A:D]
TEST CIRCUITS
OLREF OLRVS
RXA[9:0]
TXA[9:0]
RXB[9:0]
TXB[9:0]
TEST[5:1]
LDST[A:D]
BYPPLL
RXCLK0[A:D]
RXCLK1[A:D]
HDINCP
HDINCN
HDOUTCP
HDOUTCN
HDINDP
HDINDN
HDOUTDP
HDOUTDN
* Synchronous with REFCLK(N).
2
2
2
2
Figure 1. LU5X34F Quad Gigabit Ethernet Transceiver Block Diagram
TRANSCEIVER C
TRANSCEIVER D
RXC[9:0]
TXC[9:0]
RXD[9:0]
TXD[9:0]
5-8808(F)
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Preliminary Data Sheet LU5X34F
July 2000 Quad Gigabit Ethernet Transceiver
Functional Description
Block Diagrams
TX[9:0]
REFCLK
(continued)
DESERIALIZER
(continued)
DATA IN
LOAD
ANALOG PLL
SERIALIZER
PHASE SELECT/
INTERPOLATION
SERIAL DATA
OUT
GLOBAL
CONTROL
OLRVS
OLREF
PECL
TEST[5:1] / LDST
BYPPLL
RESETN
LPWR
ENCDET
EWRAP
HDOUTP
HDOUTN
RX[9:0]
RXCLK0
RXCLK1
COMDET
DIGITAL
LOW-PASS FILTER
DATA RETIMING, SERIAL-TO-PARALLEL
CONVERSION AND COMMA DETECTION
PHASE
DETECTOR
SERIAL
DATA
IN
PECL
Figure 2. LU5X34F Single-Channel Transceiver Functional Diagram
HDINP
HDINN
5-8809(F).a
.
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LU5X34F Preliminary Data Sheet
Quad Gigabit Ethernet Transceiver July 2000
Input/Output Information
A UTRPNMLKJHGFEDCB
1
3
RXCLK0B RXB 9 VSS RXB4
RXB6 RXB2 EWRAPA
RXB7
RXB82
VSS RXB5 RXB1
LCKREFA LCKREFB TEST2 TEST4
ENCDETA EWRAPB RESETN TEST3
N/C LDSTA ENCDETB TEST1
BYPPLL REFCLK ENCDETC ENCDETD
TEST5 REFCLKN LDSTC LDSTD
LPWR EWRAPC LPBKD N/C
LCKREFD TXC1 TXC5 TXC5
TXC0 TXC4 TXC8 VSS
TXC3 TXC7 VSS N/C
N/C
TXCLKC
N/C
4
TXB9 RXCLK1B COMDETB VSS
5
TXB6 TXB8 N/C VDD
6
TXB4 TXB5 TXB7 TXCLKB
7
TXB0 TXB1 TXB3 TXB2
8
RXA1 RXA0 N/C VDD
9
RXA3 RXA4 RXA2 VSS
RXA5 RXA6 RXA8 VDD
0
RXA7 RXA9 RXCLK0A N/C
1
COMDETA RXCLK1A TXCLKA TXA7
2
N/C VDD TXA8 TXA4
3
TXA6 TXA3 VSST HDINAN
TXA9
4
TXA2 VSST HDINAP HDOUTAN
TXA5
5
VSST VSSRA VDDTA VSSRB
TXA1
6
RXB3 RXB0 LDSTB VDD
VSS VSS VSS
VSS VSS VSS
VSS VSS VSS
HDOUTAP HDOUTBP VDDR VSST
HDINBP HDOUTBN VSSP VREG
VSSRB VDDTB VDDP N/C
VSS VDD LCKREFC TXC2
VDDR VSSRC N/C VDDTD
VSSRC VDDTC HDOUTCP HDINDP
OLREF HDINCP HDOUTCN VDDTC
TXC6 VSS RXCLK1C COMDETC
RXCLK0C RXC8 RXC6 RXC4
RXC9 RXC5 RXC3 RXC0
RXC1 RXC2 N/C TXD1
VDD TXD0 TXD2 TXD3
VSS TXD6 TXD4 TXD5
VDD TXD10 TXD8 TXD7
N/C RXCLK1D TXCLKD N/C
RXD6 RXD9 N/C RXCLK0D
RXD2 RXD5 RXD8 COMDETD
VSS RXD1 RXD4 RXD7
HDOUTDN VSS RXD0 RXD3
HDINDN HDOUTDP VSS N/C
RXC7
TXA0 VSSRD VSSRD VDDTD N/C
7
N/C VSSRA VDDTA HDINBN
VDDTB VDDP VSSP N/C
OLRVS N/C HDINCN N/C
Figure 3. Pin Designations (Top View)
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Preliminary Data Sheet LU5X34F
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Input/Output Information
Table 3a. Pinout—Channel A I/O
Name Pin I/O Level Description
TXA9
TXA8
TXA7
TXA6
TXA5
TXA4
TXA3
TXA2
TXA1
TXA0
RXA9
RXA8
RXA7
RXA6
RXA5
RXA4
RXA3
RXA2
RXA1
RXA0
TXCLKA C12 Input TTL/
RXCLK0A C11 Output TTL/
RXCLK1A B12 Output TTL/
ENCDETA E2 Input TTL/
COMDETA A12 Output TTL/
EWRAPA D1 Input TTL/
LCKREFNA E1 Input TTL/
HDINAP,
HDINAN
HDOUTAP,
HDOUTAN
LDSTA F3 Input TTL/
A14
C13
D12
B14
A15
D13
C14
B15
A16
A17
B11
C10
A11
B10
A10
B9
A9
C9
A8
B8
D15, E14 Input PECL
F14, E15 Output PECL
(continued)
Input TTL/
CMOS
Output TTL/
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Channel A, Transmit Data [9:0].
Parallel input bits [9:0], one 10-bit, 8b/10b encoded
data byte, clocked-in on the rising edge of TXCLKA.
TXA0 is the LSB.
Channel A, Receive Data [9:0].
Parallel output bits [9:0], one 10-bit data type, clockedout on the alternate rising edge of RXCLK0A,
RXCLK1A. RXA0 is the LSB.
Transmit Clock (100 MHz—125 MHz).
Used to latch TXA[9:0] data into the LU5X34F.
Synchronous with RE FCLK(N)
Channel A, Receive B
Channel A, Receive B
Channel A, Enable Co mma De tect A.
Channel A, B
Channel A, Loo
Channel A, Lock Recei ver to Clock.
Channel A, Differential Serial In
Channel A, Differential Serial Out
Channel A, Load Test[5:1] In
te-Aligned Comma A.
back at Serial I/ O A.
te-Align Clock 0.
te-Align Clock 1.
uts.
uts.
uts.
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LU5X34F Preliminary Data Sheet
Quad Gigabit Ethernet Transceiver July 2000
Input/Output Information
Table 3b. Pinout—Channel B I/O
Name Pin I/O Level Description
TXB9
TXB8
TXB7
TXB6
TXB5
TXB4
TXB3
TXB2
TXB1
TXB0
RXB9
RXB8
RXB7
RXB6
RXB5
RXB4
RXB3
RXB2
RXB1
RXB0
TXCLKB D6 Input TTL/
RXCLK0B A3 Output TTL/
RXCLK1B B4 Output TTL/
ENCDETB G3 Input TTL/
COMDETB C4 Output TTL/
EWRAPB F2 Input TTL/
LCKREFNB F1 Input TTL/
HDINBP,
HDINBN
HDOUTBP,
HDOUTBN
LDSTB G4 Input TTL/
A4
B5
C6
A5
B6
A6
C7
D7
B7
A7
B3
A2
A1
B1
C2
D3
E4
C1
D2
F4
F15, E17 Input PECL
G14, G15 Output PE CL
(continued)
Input TTL/
CMOS
Output TTL/
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Channel B, Transmit Data [9:0].
Parallel input bits [9:0], one 10-bit, 8b/10b encoded
data byte, clocked-in on the rising edge of TXCLKB.
TXB0 is the LSB.
Channel B, Receive Data [9:0].
Parallel output bits [9:0], one 10-bit data type, clockedout on the alternate rising edge of RXCLK0B,
RXCLK1B. RXB0 is the LSB.
Transmit Clock (100 MHz—125 MHz).
Used to latch TXB[9:0] data into the LU5X34F.
Synchronous with REFCLK(N)
Channel B, Byte-Align Clock 0.
Channel B, Byte-Align Clock 1.
Channel B, Enable Comma Detect.
Channel B, Byte-Aligned Comma.
Channel B, Loopback at Serial I/O.
Channel B, Lock Receiver to Clock.
Channel B, Differential Serial Inputs.
Channel B, Differential Serial Outputs.
Channel B, Load TEST[5:1] inputs.
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Preliminary Data Sheet LU5X34F
July 2000 Quad Gigabit Ethernet Transceiver
Input/Output Information
Table 3c. Pinout—Channel C I/O
Name Pin I/O Level Description
TXC9
TXC8
TXC7
TXC6
TXC5
TXC4
TXC3
TXC2
TXC1
TXC0
RXC9
RXC8
RXC7
RXC6
RXC5
RXC4
RXC3
RXC2
RXC1
RXC0
TXCLKC U2 Input TTL/
RXCLK0C P5 Output TTL/
RXCLK1C R4 Output TTL/
ENCDETC L1 Input TTL/
COMDETC T4 Output TTL/
EWRAPC K3 Input TTL/
LCKREFNC L4 Input TTL/
HDINCP,
HDINCN
HDOUTCP,
HDOUTCN
LDSTC L2 Input TTL/
T1
R2
P3
N4
R1
P2
N3
M4
P1
N2
P6
R5
U4
T5
R6
U5
T6
R7
P7
U6
L16, M17 Input PECL
M15, M16 Output PECL
(continued)
Input TTL/
CMOS
Output TTL/
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Channel C, Transmit Data [9:0].
Parallel input bits [9:0], one 10-bit, 8b/10b encoded
data byte, clocked in on the rising edge of TXCLKC.
TXC0 is the LSB.
Channel C, Receive Data [9:0].
Parallel output bits [9:0], one 10-bit data type, clockedout on the alternate rising edge of RXCLK0C,
RXCLK1C. RXC0 is the LSB.
Transmit Clock (100 MHz—125 MHz).
Used to latch TXC[9:0] data into the LU5X34F.
Synchronous with RE FCLK(N)
Channel C, Byte-Align Clock 0.
Channel C, Byte-Align Clock 1.
Channel C, Enable-Comma Detect.
Channel C, Byte-Aligned Comma.
Channel C, Loopback at Serial I/O.
Channel C, Lock Receiver to Clock.
Channel C, Differential Serial Inputs.
Channel C, Differential Serial Outputs.
Channel C, Load Test[5:1] Input s.
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LU5X34F Preliminary Data Sheet
Quad Gigabit Ethernet Transceiver July 2000
Input/Output Information
Table 3d. Pinout—Channel D I/O
Name Pin I/O Level Description
TXD9
TXD8
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
TXD0
RXD9
RXD8
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
RXD0
TXCLKD T11 Input TTL/
RXCLK0D U12 Output TTL/
RXCLK1D R11 Output TTL/
ENCDETD M1 Input TTL/
COMDETD U13 Output TTL/
EWRAPD L3 Input TTL/
LCKREFND N1 Input TTL/
HDINDP,
HDINDN
HDOUTDP,
HDOUTDN
LDSTD M2 Input TTL/
R10
T10
U10
R10
U9
T9
U8
T8
U7
R8
R12
T13
U14
P12
R13
T14
U15
P13
R14
T15
N15, P16 Input PECL
R16, P15 Output PECL
(continued)
Input TTL/
CMOS
Output TTL/
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Channel D, Transmit Data [9:0].
Parallel input bits [9:0], one 10-bit, 8b/10b encoded
data byte, clocked-in on the rising edge of TXCLKD.
TXD0 is the LSB.
Channel D, Receive Data [9:0].
Parallel output bits [9:0], one 10-bit data type, clockedout on the alternate rising edge of RXCLK0D,
RXCLK1D. RXD0 is the LSB.
Transmit Clock (100 MHz—125 MHz).
Used to latch TXD[9:0] data into the LU5X34F.
Synchronous with REFCLK(N)
Channel D, Byte-Align Clock 0.
Channel D, Byte-Align Clock 1.
Channel D, Enable Comma Detect.
Channel D, Byte-Aligned Comma.
Channel D, Loopback at Serial I/O.
Channel D, Lock Receiver to Clock.
Channel D, Differential Serial Inputs.
Channel D, Differential Serial Outputs.
Channel D, Load Test[5:1] Inputs.
12
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Page 13
Preliminary Data Sheet LU5X34F
July 2000 Quad Gigabit Ethernet Transceiver
Input/Output Information
(continued)
Table 3e. Pinout—Common I/O
Name Pin I/O Level Description
OLREF K16 Input/
Analog
PECL Level Set Resistor Terminal 1.
Output
OLRVS K17 Input/
Analog
PECL Level Set Resistor Terminal 2.
Output
LPWR J3 Input TTL/
Device Low-Power Mode.
CMOS
RESETN G2 Input TTL/
Device Reset (Active-Low).
CMOS
TEST5* J2 Input/
Output
TTL/
CMOS
TEST4* H1 Input TTL/
Global Test Control Input/Output.
Local Test Control Input.
CMOS
TEST3* H2 Input TTL/
Local Test Control Input.
CMOS
TEST2* G1 Input TTL/
Local Test Control Input.
CMOS
TEST1* H3 Input TTL/
Local Test Control Input.
CMOS
BYPPLL J1 Input TTL/
Test Control, PLL Bypass Mode.
CMOS
REFCLK,
REFCLKN
K1, K2 Input PECL or
TTL/
CMOS
Reference Clock Input (100 MHz—125 MHz).
Used by the transmitter PLL to generate the
1.0 Gbits/s— 1.25 Gbits/s serial data; has a +
tolerance requirement.
100 ppm
* For related information, see Table 18, Test Modes.
Table 3f. Pinout—Power I/O
Name Pin Description
V
DD
P G17, H16
V
DD
V
DDTX
R H14, K14
V
DD
V
SS
D5, D8, D10, B13, H4, K4, P8, P10
D16, D17, F17, G16, L15, N16, N14, T17,
B2, C3, D4, D9, H8, H9, H10, J4, J8, J9, J10,
Device Digital Power.
PLL Power.
High-Speed Analog Transmitter Power.
High-Speed Analog Receiver Power.
Device Digital Ground.
K8, K9, K10, P4, P9, P14, R3, R15, T2, T16
V
PH15, H17
SS
T B16, C15, D14, J14
V
SS
V
SSRX
C16, C17, E16, F16, K15, L14, P17, R17
PLL Ground.
High-Speed Analog Transmitter Ground.
High-Speed Analog Receiver Ground.
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LU5X34F Preliminary Data Sheet
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Quad Gigabit Ethernet Transceiver July 2000
Electrical Specifications
Transmitter
Table 4. Reference Clock Specifications
REFCLK and REFCLKN
Parameter Min Max Unit
Frequency Range 100 125 MHz
Frequency Tolerance –100 100 ppm
Duty Cycl e* 40 60 %
Rise Time (PECL) — 0.8 ns
Fall Time (PECL) — 0.8 ns
Rise Time (TTL/CMOS) — 1.5 ns
Fall Time (TTL/CMOS) — 1.5 ns
In-band Jitter, 1 Gbit/s—1.25 Gbits/s — 30 ps
Out-of-Band Jitter — 50 ps
* Measured at 50% amplitude point.
Table 5. PL L Specifications
Parameter Min Typ Max Unit
Bandwidth — 1.5 — MHz
Jitter Peaking — 0.5 — dB
Lock Time — — 230 µs
at 1.0 Gbit/s—1.25 Gbits/s Data Rate
T a bl e 6. Ou t
ut Jitter
p-p
p-p
Parameter Min Max Unit
Deterministic — 0.08 UI
Random — 0.12 UI
Total — 0 .2 UI
Receiver
p-p
p-p
p-p
Table 7. Input Data Rate
Parameter Min Max Unit
Frequency Range 1.0 1.25 Gbits/s
Frequency Tolerance with REFCLK –100 100 ppm
Table 8. Data Lock Characteristics
Parameter Min T
Bandwidth*
Jitter Peakin
*—0.5
0.3
†
—1* MHz
Lock Time* — — 2 µ
* Data pattern: 101010 . . . .
† Data pattern: 1111100000 . . . .
Max
—
Unit
dB
s
14
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Preliminary Data Sheet LU5X34F
July 2000 Quad Gigabit Ethernet Transceiver
Electrical Specifications
Receiver
(continued)
(continued)
Table 9. Power Dissipation *
Parameter Min Typ Max Unit
Power — — 2.0 W
Package Thermal
TBD — TBD °C/W
Resistance
Sleep Mode (LPWR) — TBD — mW
* Depending on application (PCB layout), etc.
Table 10. dc Electrical Specifications
*
Parameter Symbol Condition Min Typ Max Unit
DD
Supply Voltage V
Output Low V
Output High V
Input Low V
Input High V
, VDDP — 3.135 3.3 3.465 V
OL
OH
IL
IH
—0—0.6V
—2.4—VDDV
—0—0.8V
—2.0—VDDV
Diff. PECL Output Load, as in Figure 9. 800 — — mV
Diff. PECL Input Source configuration,
400 — 16 00 mV
as in Figure 9.
* Depending on application (PCB layout), etc.
Table 11. Absolute Maximum Ratings
Parameter Min Typ Max Unit
Supply Voltage 3.135 3.3 3.465 V
TTL High Input Voltage 3.0 — 3.6 V
PECL Output Current — — 16 mA
Junction Operating Temperature 0 — 125 °C
Storage Temperature –65 — 150 °C
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LU5X34F Preliminary Data Sheet
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Quad Gigabit Ethernet Transceiver July 2000
Timing Characteristics
Serial Timing
T a bl e 12. S eri al Output Timing Levels
Description Min Typ Max Unit
Rise Time 20%—80% 0.17 0.2 0.22 ns
Fall Time 80%—20% 0.17 0.2 0.22 ns
Common Mode V
Differential Swing 0.8 — 1.6 V
Load (See Table 16) 50 — 75 Ω
DD
/2 – 0.1 VDD/2 VDD/2 + 0.1 V
WIN
D
DIFF
V
tF/tR
p-p
Table 13. Serial Input Interface Timing
Description Min Max Unit
Rise Ti me
F
Fall Time
Differenti al Swin
t
DIFF
V
Source Impedance
Data E
e Openin
Figure 4. Serial Interface Timing
150 225
150 225
0.4 1.6
50 75
320 —
mV
5-8813(F)
ps
ps
p-p
Ω
ps
16
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Preliminary Data Sheet LU5X34F
[
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[
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)
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July 2000 Quad Gigabit Ethernet Transceiver
Timing Characteristics
Receiver Section Timing
HDNIP
RECOVERED CLOCK
(INTERNAL)
RXCLK1
RXCLK0
RX[9:0] D7.2
COMDET
(continued)
K28.5 D7.2 D0.0 D1.0
K28.5
Figure 5. Receiver Section Timing
5-8813 (F)
Receiver Port Timing
RXCLK PERIOD
RXCLK1 HIGHRXCLK1 LOW
RXCLK1
RXCLK0
tSKEW
RX RX0 RX1 RX2
tS tH tS tH
Figure 6. Receiver Port Timing
Table 14. Receiver Parallel Port Timing
Symbol Parameter Min Ma x Units
—RXCLK
—RXCLK
—RXCLK
tR/F RXCLK
tR/F Data Output
1:0] Frequency* — 62.5 MHz
1:0] Low 7.0 9.0 ns
1:0] High7.09.0ns
1:0] (0.4 V to 2.6 V
0.4 V to 2.6 V
†
†
0.2 0.5 ns
0.2 0.5 ns
tS Setup Time 3.0 — ns
tH Hold Time 2.0 — ns
tSKEW Skew — 1.0 ns
RX3
5-8814(F)
* 1.25 Gbits/s.
† 0.5 pF load.
Lucent Technologies Inc.
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LU5X34F Preliminary Data Sheet
g
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Quad Gigabit Ethernet Transceiver July 2000
Timing Characteristics
(continued)
Transmitter Section Timing
TXCLK*
TX[9:0]
SERIALIZED DATA
SYNTHESIZED CLOCK
* Synchronous with REFCLK(N).
Figure 7. Parallel Interface Transmit Timing
Table 15. Transmitter Timing at Parallel Interface
Description Min Max Unit Conditions
Data Setup 2 — ns
Data Hold 2 — ns
Rise Time — 1 ns
Fall Time — 1 ns
155 126 375 34A
155 126 375
With positive ed
With positive ed
—
—
5-8815(F)
e TXCLK
e TXCLK
18
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Page 19
Preliminary Data Sheet LU5X34F
July 2000 Quad Gigabit Ethernet Transceiver
Application Section
BIAS
CLOCK
SOURCE
REFCLK
REFCLKN
INTERNAL
CLOCK
BIAS
LU5X34F
BIAS
INTERNAL
CLOCK
BIAS
LU5X34F
CLOCK
SOURCE
1.0 nF
SINGLE-ENDED CLOCK SOURCE
REFCLK
REFCLKN
DIFFERENTIAL CLOCK SOURCE
Figure 8. Reference Clock Connections with Single-Ended and Differential Sources
5-8013(F)
Lucent Technologies Inc.
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LU5X34F Preliminary Data Sheet
(
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Quad Gigabit Ethernet Transceiver July 2000
Application Section
TXX[9:0]
TXCLK
OLREF
(continued)
HDOUTP
TRANSMIT
LU5X34F
HDOUTN
OLRVS
*
10
50
50
10
†
Ω
Ω
Ω
†
Ω
Z
O
Z
O
= 50
0.1 µF
= 50
Ω
100
Ω
Ω
0.01 µF
0.01 µF
HDINP
HDINN
RECEIVE
LU5X34F
RXX[9:0]
RXCLKX1
RXCLK
X
0
5-8811(F).c
* External resistor connected between OLREF and OLRVS. See Table 16 for external resistor value.
† Damping resistor, maximum = 10 Ω.
Figure 9. Typical Termination for a Single-Channel, High-Speed Serial
Transmit-and-Receive Port in a 50 Ω Backplane Application
Table 16. External Resistor Value vs. Differential Output Level Viewing
Resistor V a lue
Ω)
T ermination Im
edance
Ω)
Differentia l Out
7.5 k/11.25 k 50/75 0.8
5 k/7.5 k 1.2
4 k/6 k 1.6
ut V oltage
20
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Preliminary Data Sheet LU5X34F
(
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July 2000 Quad Gigabit Ethernet Transceiver
Application Section
TXA[9:0]
REFCLK
TRANSMIT
LU5X34F
OLREF
(continued)
HDOUTP
HDOUTN
OLRVS
*
10
50
50
10
Ω
68
†
Ω
Ω
Ω
†
Ω
ZO = 50
0.1 µF
O
Z
= 50
Ω
Ω
0.01 µF
191
191
0.01 µF
68
TX(+)
Ω
TRANSMIT
GBIC
Ω
TX(–)
Ω
5 V
5-8811(F)b
* External resistor connected between OLREF and OLRVS. See Table 17 for resistor value vs. termination impedance and output swing.
† Damping resistor, maximum = 10 Ω.
Figure 10. Typical Termination for a Single-Channel, High-Speed Serial
Transmit Port Interfacing a 5 V GBIC Transceiver
Table 17. External Resistor Value vs. Differential Output Level Viewing
Resistor Value
Ω)
T ermin ati on Im
edance
Ω)
Differential Out
7.5 k/11.25 k
5 k/7.5 k 1.2
50/75
ut V o ltage
0.8
4 k/6 k 1.6
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LU5X34F Preliminary Data Sheet
Quad Gigabit Ethernet Transceiver July 2000
Test Modes
Note:
Test modes are intended for manufacture test only and are not guaranteed to be operational. They may be
modified or eliminated without prior notice.
The device has per-channel test modes as well as global test modes. The bypass PLL, BYPPLL, is a global test
input because it modifies the operation of the analog PLL. Test bits TEST[4:1] generally operate in the localized
mode. The LDST[A:D] inputs are enable signals that permit the TEST[4:1] signals to be injected into a particular
channel.
For e xample, if LDSTA = 1, the TEST[4:1] signals directly control the test modes in the A channel. Once
LDSTA = 0, the previous values of TEST[4:1] are held for the A channel. The TEST[4:1] signals control the four
channels (A, B, C, D) via level sense latches that are gated with the LDST[A:D] inputs. TEST[5] is a global test pin
used for both injection of signals as well as for monitoring points within the device.
Table 18. Test Modes
Global Local Test Configuration Global Operation
BYPPLL TEST1 TEST2 TEST3 TEST4 TEST5
0 1111 XNormal operation.
0 1110OutputAnalog PLL feedback signal viewed at
TEST5 pin.
0 1101 XTransceiver operates normally except
RX[9:0] output is from digital filter, not
the serial data.
0 1100OutputTransceiver operates normally except
RX[9:0] output is from digital filter and
the analog PLL feedback signal is
viewed at TEST5 pin.
0 1 0 1 P P Digital filter forced to count. Pulses
applied at TEST4 increment accumulator; pulses at TEST5 decrement accumulator.
0 1 0 0 P P RX[9:0] output is from digital filter, not
the serial data. Digital filter forced to
count. Pulses applied at TEST4 increment accumulator; pulses at TEST5
decrement accumulator.
0 0111 XParallel loopback. TX[9:0] = RX[9:0].
RX[9:0] remains active.
0 0110OutputParallel loopback. TX[9:0] = RX[9:0]
and analog PLL feedback signal viewed
at TEST5 pin. RX[9:0] remains active.
0 0101 XRX[9:0] output is from digital filter, not
the serial data. Receive channel is held
in reset. BYPPLL overrides this reset.
0 0100OutputRX[9:0] output is from digital filter, not
the serial data. Receive channel is held
in reset. BYPPLL overrides this reset.
Analog PLL feedback signal viewed at
TEST5 pin
22
Lucent Technologies Inc.
Page 23
Preliminary Data Sheet LU5X34F
July 2000 Quad Gigabit Ethernet Transceiver
Test Modes
Table 18. Test Modes
Global Local Test Configuration Global OPERATION
BYPPLL TEST1 TEST2 TEST3 TEST4 TEST5
0 0 0 1 0 Output Transmitter is held in reset. BYPPLL
0 0 0 0 1 X Transmitter and receiver are held in
0 0 0 0 0 Output Transmitter and receiver are held in
1 X X 1 C-0 C-90 Analog PLL is bypassed for low speed
1 X X 0 C-0 C-90 Analog PLL is bypassed for low-speed
(continued)
(continued)
overrides this reset. Analog PLL feedback signal viewed at TEST5 pin.
reset. RX[9:0] output is from digital filter, not the serial data.
reset. RX[9:0] output is from digital filter, not the serial data. Analog PLL
feedback signal viewed at TEST5 pin.
functional test. A low-speed clock is
input to TEST4, and a quadrature clock
is applied to TEST5. Frequency of
clocks is 5X REFCLK, but here REFCLK is lowered to about 1 MHz.
functional test. A low-speed clock is
input to TEST4, and a quadrature clock
is applied to TEST5. Frequency of
clocks is 5X REFCLK, but here REFCLK is lowered to about 1 MHz.
RX[9:0] output is from digital filter, not
the serial data.
Lucent Technologies Inc.
23
Page 24
LU5X34F Preliminary Data Sheet
Quad Gigabit Ethernet Transceiver July 2000
Outline Diagram
217-pin PBGA
Dimensions are in millimeters.
23.00 ± 0.20
+0.70
19.50
IDENTIFIER ZONE
A1 BALL
–0.00
19.50
+0.70
–0.00
23.00
± 0.20
MOLD
COMPOUND
PWB
A1 BALL
CORNER
0.36 ± 0.04
SOLDER BALL0.60 ± 0.10
16 SPACES @ 1.27 = 20.32
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 1011 121314151617
1.17 ± 0.05
2.13 ± 0.19
SEATING PLANE
0.20
0.75 ± 0.15
16 SPACES
@ 1.27 = 20.32
5-6562 (F)
24
Lucent Technologies Inc.
Page 25
Preliminary Data Sheet LU5X34F
July 2000 Quad Gigabit Ethernet Transceiver
Ordering Information
Device Code Comcode Package Temperature
LU5X34F 108497850 217-pin PBGA 0 °C—70 °C
Lucent Technologies Inc.
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LU5X34F Preliminary Data Sheet
Quad Gigabit Ethernet Transceiver July 2000
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET: http://www.lucent.com/micro
E-MAIL: docmaster@micro.lucent.com
N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
CHINA: Microelectronics Gr oup, Luc en t Technologies ( China) Co . , Ltd., A-F2, 23/F, Zao Fong Uni verse Building, 1800 Zhon g S han Xi Road , S hanghai
JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
Copyright © 2000 Lucent Technologies Inc.
All Rights Reserved
July 2000
DS00-351LAN (Replaces DS00-007LAN)
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
Tel. (65) 778 8833, FAX (65) 777 7495
200233 P. R. China Tel. (86) 21 6440 0468, ext. 325, F A X ( 86) 21 6440 0652
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
Techni cal Inquiries: GERMAN Y: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
FRANCE: (3 3) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 60 7 00 (St ockholm) , FINLAND: (358) 9 4354 2800 (Helsinki),
IT ALY : (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
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