Datasheet LU3X54FT-S208, LU3X54FT-HS208 Datasheet (AGERE)

LU3X54FT

QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/

FX

Data Sheet
July 2000

Introduction

The LU3X54FT is a four-channel, single-chip com­plete transceiver designed specifically for dual-speed
10Base-T, 100Base-TX, and 100Base-FX repeaters
and switches. It supports simultaneous operation in
three separate

IEEE

standard modes: 10Base-T,

100Base-TX, and 100Base-FX.
Each channel implements:

■

10Base-T transceiver function of

IEEE

802.3.

■

Physical coding sublayer (PCS) of

IEEE

802.3u.

■

Physical medium attachment (PMA) of

IEEE

802.3u.

■

Autonegotiation of

IEEE

802.3u.

■

MII management of

IEEE

802.3u.

■

Physical medium dependent (PMD) of

IEEE

802.3.

The LU3X54FT supports operations over two pairs of
unshielded twisted-pair (UTP) cable (10Base-T and
100Base-TX), and over fiber-optic cable (100Base­FX).

It has been designed with a flexible system interface
that allows configuration for optimum performance
and effortless design. The individual per-port inter­face can be configured as 100 Mbits/s MII, 10 Mbits/s
MII, 7-pin 10 Mbits/s serial, or bused mode.

Features

10 Mbits/s Transceiver

■

Compatible with

IEEE

* 802.3 10Base-T standard

for twisted-pair cable

■

Autopolarity detection and correction

■

Adjustable squelch level for extended line length
capability (two levels)

■

Interfaces with

IEEE

802.3u media independent

interface (MII) or a serial 10 Mbits/s 7-pin interface

■

On-chip filtering eliminates the need for external
filters

■

Half- and full-duplex operations

100 Mbits/s TX T r ansceiver

■

Compatib le wit h

IEEE

802.3u MII (clause 22), PCS
(clause 23), PMA (clause 24), autonegotiation
(clause 28), and PMD (clause 25) specifications

■

Scrambler/descrambler bypass

■

Encoder/decoder bypass

■

3-statable MII in 100 Mbits/s mode

■

Selectable carrier sense signal generation (CRS)
asserted during either transmission or reception in
half duplex (CRS asserted during reception only in
full duplex)

■

Selectable MII or 5-bit code group interface

■

Full- or half-duplex operations

■

Optional carrier integrity monitor (CIM)

■

On-chip filtering and adaptive equalization that
eliminates the need for external filters

*

IEEE

is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact

your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.

Table of Contents

Contents Page

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

2 Lucent Technologies Inc.

Introduction ........................ ....................................... ...................................... ................................. .........................1

Features ...................................................................................................................................................................1

10 Mbits/s Transceiver........................................................................................................................................... 1

100 Mbits/s TX Transceiver ................................................................................................................................... 1

100 Mbits/s FX Transceiver ................................................................................................................................... 4

General .................................................................................................................................................................. 4

Description ...............................................................................................................................................................4

Bused MII Mode..................................................................................................................................................... 4

Clocking ................................................................................................................................................................. 5

FX Mode ................................................................................................................................................................ 6

Functional Block Diagrams .................................................................................................................................... 7

Application Diagrams. ...... ...... ....... ...... ....... ...... ....... ...... ....................................... ...... ....... ...... ....... ...... ....... ...... ..... 9

Block Diagrams.................................................................................................................................................... 11

Pin Information .......................................................................................................................................................13

Pin Diagram for Normal MII Mode ....................................................................................................................... 13

Pin Diagram for Bused MII Mode......................................................................................................................... 14

Pin Maps.......................... ...... ....... ...... ....... ...... ....... ...... ....... ...... ....... ................................................................ ... 15

Pin Descriptions..................... ....... ...... ....... ....................................... ...... ...... ....... ...... ...... . ...... ....... ...... ................ 16

MII Station Management .......................................... ...................................... ....... ...... ....... ...... ....... ...... ....... ...... ....29

Basic Operations.................................................................................................................................................. 29

MII Management Frames..................................................................................................................................... 29

Management Registers (MR)............................................................................................................................... 30

Unmanaged Operations....................................................................................................................................... 40

Mode Select..................... ...... ....... ...... ....... ...... ....... ...... ....... ...................................... ....... ...... ....... ...... ....... ...... ... 40

Absolute Maximum Ratings (TA = 25 °C) ............................................................................................................... 41

Electrical Characteristics ........................................................................................................................................41

Package and Thermal Characteristics ....................................................................................................................42

Outline Diagram ......................................................................................................................................................52

208-Pin SQFP...................................................................................................................................................... 52

Tables Page

Table 1. LU3X54FT Crystal Specifications .............................................................................................................. 6

Table 2 . LU3X54FT Pin Maps............................................................................................................................... 15

Table 3. MII/Serial Interface Pins in Normal MII Mode (Four Separate MII Ports)................................................. 16

Table 4. MII/Serial Interface Pins in Bused MII Mode............................................................................................ 18

Table 5. MII Management Pins .............................................................................................................................. 22

Table 6. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins....................................................................................... 22

Table 7. Miscellaneous Pins .................................................................................................................................. 23

Table 8. MII Management Frame Format............................................................................................................... 29

Table 9. MII Management Frames Field Descriptions............................................................................................ 29

Table 10. MII Management Registers (MR)........................................................................................................... 30

Table 11. MR0—Control Register Bit Descriptions................................................................................................ 31

Table 12. MR1—Status Register Bit Descriptions ................................................................................................. 32

Table 13. MR2, 3—PHY Identifier Registers (1 and 2) Bit Descriptions................................................................ 33

Table 14. MR4—Autonegotiation Advertisement Register Bit Descriptions........................................................... 33

Table 15. MR5—Autonegotiation Link Partner (LP) Ability Register (Base Page) Bit Descriptions ....................... 34

Table 16. MR5—Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions........................ 34

Table 17. MR6—Autonegotiation Expansion Register Bit Descriptions................................................................. 35

Table 18. MR7—Next-Page Transmit Register Bit Descriptions ............................................................................ 35

Lucent Technologies Inc. 3

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Table of Contents

Tables Page

Table 19. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions...................................................36

Table 20. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions............................................37

Table 21. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions..............................................38

Table 22. MR31—Device-Specific Register 4 (Quick Status) Bit Descriptions.......................................................39

Table 23. Output Pins.............................................................................................................................................40

Table 24. LU3X54FT Modes...................................................................................................................................40

Table 25 . Absolute Maximum Ratings ...................................................................................................................41

Table 26 . Operating Conditions.............................................................................................................................41

Table 27. dc Characteristics ...................................................................................................................................41

Table 28. Thermal Characteristics..........................................................................................................................42

Table 29. MII Management Interface Timing (25 pF Load).....................................................................................43

Table 30. MII Data Timing (25 pF Load).................................................................................................................44

Table 31. Serial 10 Mbits/s Timing for TPIN, CRS, and RX_CLK...........................................................................46

Table 32. Serial 10 Mbits/s Timing for TX_EN, TPOUT, CRS, and RX_CLK..........................................................46

Table 33. Serial 10 Mbits/s Timing for TX_EN, TPIN, and COL.............................................................................47

Table 34. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD (25 pF Load)................48

Table 35. Serial 10 Mbits/s Timing for RX_CLK and TX_CLK (25 pF Load) ..........................................................49

Table 36. 100 Mbits/s MII Transmit Timing .............................................................................................................50

Table 37. 100 Mbits/s MII Receive Timing..............................................................................................................51

Figures Page

Figure 1. LU3X54FT Device Overview.....................................................................................................................7

Figure 2. LU3X54FT Single-Channel Detail Functions ............................................................................................8

Figure 3. Typical Single-Channel Twisted-Pair (TP) Interface..................................................................................9

Figure 4. Typical Single-Channel Fiber-Optic Interface..........................................................................................10

Figure 5. Smart 10/100 Mbits/s Bused MII Mode...................................................................................................11

Figure 6. Separate 10/100 Mbits/s Bused MII Mode..............................................................................................12

Figure 7. LU3X54FT Pinout for Normal MII Mode..................................................................................................13

Figure 8. LU3X54FT Pinout for Bused MII Mode...................................................................................................14

Figure 9. Thermal Characteristics..........................................................................................................................42

Figure 10. MDIO Input Timing................................................................................................................................43

Figure 11. MDIO Output Timing.............................................................................................................................43

Figure 12. MDIO During TA (Turnaround) of a Read Transaction ..........................................................................43

Figure 13. MII Timing Requirements for LU3X54FT ..............................................................................................45

Figure 14. Serial 10 Mbits/s Timing for TPIN, CRS, and RX_CLK.........................................................................46

Figure 15. Serial 10 Mbits/s Timing for TX_EN, TPOUT, CRS, and RX_CLK........................................................46

Figure 16. Serial 10 Mbits/s Timing for TX_EN, TPIN, and COL ...........................................................................47

Figure 17. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD ...................................48

Figure 18. Serial 10 Mbits/s Timing Diagram for RX_CLK and TX_CLK ...............................................................49

Figure 19. 100 Mbits/s MII Transmit Timing ...........................................................................................................50

Figure 20. 100 Mbits/s MII Receive Timing............................................................................................................51

(continued)

4 Lucent Technologies Inc.

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

Features

(continued)

100 Mbits/s FX Transceiver

■

Compatible with

IEEE

802.3U 100Base-FX standard

■

Reuses existing twisted-pair I/O pins for compatible
fiber-optic transceiver pseudo-ECL (PECL) data:
— No additional data pins required
— Reuses existing LU3X54FT pins for fiber-optic sig-

nal detect (FOSD) inputs

■

Fiber mode automatically configures port:
— Disables autonegotiation
— Disables 10Base-T
— Enables 100Base-FX remote fault signaling
— Disables MLT-3 encoder/decoder
— Disables scrambler/descrambler

■

FX mode enable is pin- or register-selectable on an
individual per-port basis.

General

■

Autonegotiation (

IEEE

802.3u, clause 28):
— Fast link pulse (FLP) burst generator
— Arbitration function

■

Bused interfaces:
— Supports either separate 10 Mbits/s and

100 Mbits/s multiport repeaters (100 Mbits/s
MII and 10 Mbits/s serial data stream), or single­chip multispeed repeaters

— Connects ports to either the 10 Mbits/s or

100 Mbits/s buses controlled by autonegotiation

— Separate TX_EN, RX_EN, CRS, and COL pins for

each port

— Drivers on bused signal can drive up to eight

LU3X54FTs (32 ports)

■

Supports the station management protocol and
frame format (clause 22):
— Basic and extended registers
— Supports next-page function
— Operates up to 12.5 MHz
— Accepts preamble suppression
— Maskable status interrupts

■

Supports the following management functions via
pins if MII station management is unavailable:
— Speed select
— Carrier integrity enable
— Encoder/decoder bypass
— Scrambler/descrambler bypass
— Full duplex
— No link pulse mode
— Carrier sense select
— Autonegotiation

— 10 Mbits/s repeater reference select
— Internal 20 MHz clock synthesizer
— FX mode select

■

Single 25 MHz crystal input or 25 MHz clock input,
optional 20 MHz clock input

■

Supports half- and full-duplex operations

■

Provides six status signals:
— Receive activity
— Transmit activity
— Full duplex
— Collision/jabber
— Link integrity
— Speed indication

■

Optional LED pulse stretching

■

Per-channel powerdown mode for 10 Mbits/s and
100 Mbits/s operation

■

Loopback for 10 Mbits/s and 100 Mbits/s operation

■

Internal pull-up or pull-down resistors to set default
powerup mode

■

0.35 µm, low-power CMOS technology

■

208-pin SQFP or 208-pin SQFPH

■

Single 5 V power supply

Description

Bused MII Mode

The LU3X54FT has been designed for operation in two
basic system interface modes of operation:

■

Normal MII Mode (Four Separate MII Ports).

The
separate mode provides four independent RJ-45 to
MII ports and is similar to having four independent
10/100 transceivers.

■

Bused MII Mode.

This mode is designed specifically
for repeater applications to save pins. In bused
mode:
— Data from all of the ports operating at 100 Mbits/s

will be internally bused to system interface port A
(100 Mbits/s MII interface).

— Data from all of the ports operating at 10 Mbits/s

will be internally bused to system interface port B
(7-pin 10 Mbits/s serial interface).

The LU3X54FT will automatically detect the speed of
each port (10 Mbits/s or 100 Mbits/s) and route the
data to the appropriate port.

Lucent Technologies Inc. 5

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Description

(continued)

Bused MII Mode

(continued)

The bused mode has two additional submodes of
operation:

■

Separate Bused MII Mode.

This mode is designed
to operate with two independent repeater ICs, one
repeater operating at 100 Mbits/s and the other oper­ating at 10 Mbits/s.

Figure 6 shows a block diagram of this mode in which
separate pins (four of each) are used for COL_10(4),
COL_100(4), CRS_10(4), CRS_100(4),
RX_EN10(4), RX_EN100(4), TX_EN10 (4), and
TX_EN100(4).

The signals RX_CLK10, RXD_10, TX_CLK10, and
TXD_10 (all from ports A, B, C, and D) are internally
bused together and connected to MII port B.

The signals TX_CLK25, TXD_100[3:0], TX_ER,
RX_CLK25, RXD_100[3:0], RX_DV, and RX_ER (all
from ports A, B, C, D) are internally bused together
and connected to MII port A.

The repeater ICs will enable the particular port to
which it will communicate by enabling the port with
TX_EN 10, TX_EN100, RX_EN10, or RX_EN100.

■

Smart Bused MII Mode.

This mode is used when
the LU3X54FT is communicating with a single
(smart) 10/100 Mbits/s repeater IC, and allows the
use of the security feature.

Figure 5 shows a block diagram of the smart bused
mode of operation. In this mode, a common set of
pins is used for CRS10/100, RX_EN10/100,
TX_EN10/100, and COL_10/100.

The 10 Mbits/s (7-pin 10 Mbits/s serial interface) sig­nals are still routed to port B (RX_CLK10, RXD_10,
TX_CLK10, and TXD_10).

The 100 Mbits/s signals are still routed to port A
(TX_CLK25, TXD_100[3:0], TX_ER, RX_CLK25,
RXD_100[3:0], RX_DV, and RX_ER).

The bused interface allows each of the four transceiv­ers to be connected to one of two system interfaces:

■

Port A: 100 Mbits/s MII interface.

■

Port B: 7-pin 10 Mbits/s serial interface.

This configuration allows 10/100 Mbits/s segment seg­regation or port switching with conventional multiport
shared-media repeaters.

The port speed configuration and connection to the
appropriate bused output is done automatically and is
controlled by autonegotiation.

Figure 1 gives a functional overview of the LU3X54FT
while Figure 2 details its single-channel functions.

Figure 3 shows how the LU3X54FT single channel
interfaces to the twisted pair (TP).

Clocking

The LU3X54FT requires an internal 25 MHz clock and
a 20 MHz clock to run the 100Base-TX transceiver and
10Base-T transceiver.

These clocks can be supplied as follows:

■

As separate clock inputs: 25 MHz and 20 MHz.

■

The 20 MHz clock can be internally synthesized from
the 25 MHz clock.

■

The 25 MHz clock can also be internally generated
by an on-chip oscillator if an external crystal is sup­plied.

The LU3X54FT will automatically detect if a 25 MHz
clock is supplied, or if a crystal is being used to gener­ate the 25 MHz clock.

6 Lucent Technologies Inc.

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

Description

(continued)

Clocking

(continued)

Either the on-chip 20 MHz clock synthesizer (default
clock) can be used, or H-DUPLED[A]/CLK20_SEL
(pin 198) can be pulled high (sensed on powerup and
reset) to select the external 20 MHz clock input.

The crystal specifications for the device are listed in
Table 1, and the crystal circuit is sh o wn in Fi gure 3 an d
Figure 4.

Table 1. LU3X54FT Crystal Specifications

FX Mode

Each individual port of the LU3X54FT can be operated
in 100Base-FX mode by selecting it through the pin
program option (RXLED[D:A]/FX_MODE_EN[D:A], or
through the register bit (register 29, bit 0). FX mode
can operate in full or half duplex. Each individual chan­nel’s duplex can be set by register zero bit eight (0.8) or
all ports duplex can be hardware configured at power
up or rest by pin 201 FULL_DUP.

When operating in FX mode, the twisted-pair I/O pins
are reused as the fiber-optic transceiver I/O data pins,
and the fiber-optic signal detect (FOSD) inputs are
enabled.

Figure 4 shows a typical FX port interface. Note that no
additional external components, excluding those
needed by the fiber transceiver, are required.

When a port is placed in FX mode, it will automatically
configure the port for 100Base-FX operation (and the
register bit control will be ignored) such that:

■

The far-end fault signaling option will be enabled.

■

The MLT-3 encoding/decoding will be disabled.

■

Scrambler/descrambler will be disabled.

■

Autonegotiation will be disabled.

■

The signal detect inputs will be activated.

■

10Base-T will be disabled.

Parameter Requirement

Type Quartz Fundamental Mode
Frequency 25 MHz
Stability ±25 ppm, 0 °C—70 °C
Shunt Capacitor 7 pF
Load Capacitor 20 pF
Series Resistance <30

Ω

Lucent Technologies Inc. 7

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Description

(continued)

Functional Block Diagrams

Device Overview

5-5137(F).fr2

Figure 1. LU3X54FT Device Overview

10 Mbits/s TRANSCEIVER

AUTONEGOTIATION

PMA

PMA

PMA

PMA

TX PMD/

MUX

MANAGEMENT

PCS

MANAGEMENT

PCS

MANAGEMENT

PCS

MANAGEMENT

PCS

MII/SERIAL

AUTONEGOTIATION

AUTONEGOTIATION

AUTONEGOTIATION

MUX

MUX

MUX

DPLL

10 MHz

25 MHz
125 MHz

LSCLK

INTERFACE

MII/SERIAL

INTERFACE

MII/SERIAL

INTERFACE

MII/SERIAL

INTERFACE

20 MHz

25 MHz

DRIVER AND FILTERS

10 Mbits/s TRANSCEIVER

DRIVER AND FILTERS

10 Mbits/s TRANSCEIVER

DRIVER AND FILTERS

10 Mbits/s TRANSCEIVER

DRIVER AND FILTERS

DRIVER AND

FILTERS

DRIVER AND

FILTERS

DRIVER AND

FILTERS

DRIVER AND

FILTERS

TP

MAGNETICS

INTERFACE

20 MHz

25 MHz

CRYSTAL

FX PORT

FX_MODE_EN

TX PMD/
FX PORT

TX PMD/
FX PORT

TX PMD/
FX PORT

FX_MODE_EN

FX_MODE_EN

FX_MODE_EN

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

8 Lucent Technologies Inc.

Description

(continued)

Functional Block Diagrams

(continued)

Single-Channel Detail Functions

5-5136(F).gr4

Figure 2. LU3X54FT Single-Channel Detail Functions

AUTONEGOTIATION
AND LINK MONITOR

100 OFF

TXD[3:0]

4B/5B

ENCODER

FAR-END

FAULT GEN

SCRAMBLER

PDT

DCRU

SD

PDR

DESCRAMBLER

ALIGNER

5B/4B

DECODER

FAR-END

FAULT DETECT

10 Mbits/s TRANSCEIVER

RX_CLK

RXD[0]

TX_CLK

TX_EN

TXD[0]
CLK20

MDC

MDIO

MII

TPIN

±

TX STATE

MACHINE

SD

COLLISION

DETECT

SD

RX STATE

MACHINE

MII

TX_ER/TXD[4]

TX_EN

TXD[3:0]

TX_CLK

RX_CLK

RX_ER/RXD[4]

RX_DV

RXD[3:0]

COL

CRS

REF10

MANAGEMENT

25 MHz
125 MHz

LSCLK

PMD

TX/

PMD

RX/

SD

TPOUT

±

100 Mbits/s TRANSCEIVER

LC10 LS10

LC100

LS100

CARRIER

CIM

DETECT

RXERR_ST

CAR_STAT

MII

INTERFACE

SERIAL

INTERFACE

DPLL

25 MH

Z

MANAGEMENT

INTERFACE

20 MHz

25 MHz
CRYSTAL

FIBER PORT

FX_MODE_EN

FX_MODE_EN

FIBER
PORT

FOSD

Lucent Technologies Inc. 9

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Description

(continued)

Application Diagrams

Single-Channel Twisted-Pair Interface

5-5433(F).r9

Figure 3. Typical Single-Channel Twisted-Pair (TP) Interface

LU3X54FT

RJ-45

1

2

3

4

5

6

7

8

75

Ω

75

Ω

0.01 µF

1:1

1:1

0.01 µF

0.01 µF

0.01 µF

220

Ω

TPIN+

TPIN–

TPOUT+

TPOUT–

220

Ω

50

Ω

50

Ω

V

DDO

75

Ω

0.01 µF

75

Ω

XTALOUT

XTALIN

88 87

33 pF 33 pF

25 MHz

50

Ω

50

Ω

0.01 µF

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

10 Lucent Technologies Inc.

Description

(continued)

Application Diagrams

(continued)

Single-Channel Fiber-Optic Interface

5-5433(F).dr2

Figure 4. Ty pical Single-Channel Fiber-Optic Interface

LU3X54FT

TD

TDN

SD

RD

RDN

0.01 µF

220

Ω

TPIN+

TPIN–

TPOUT+

TPOUT–

220

Ω

50

Ω

50

Ω

V

DDO

82

Ω

0.01 µF

130

Ω

XTALOUT

XTALIN

88 87

33 pF 33 pF

25 MHz

FOSD

50

Ω

50

Ω

82

Ω

130

Ω

82

Ω

130

Ω

V

DDA

0.01 µF

Lucent Technologies Inc. 11

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Description

(continued)

Block Diagrams

Smart Bused MII Mode

5-5599.br2

Figure 5. Smart 10/100 Mbits/s Bused MII Mode

RX_CLK10
RXD_10
TX_CLK10
TXD_10

COL_100

CRS_100
RX_EN100
TX_EN100

TX_EN10/SECURITY
TX_CLK25

TXD_100[3:0]
TX_ER

RX_CLK25
RXD_100[3:0]
RX_DV
RX_ER

MDC
MDIO

SMART_MODE_SELECT
BUSED_MII_MODE

LU3X54FT

10/100 Mbits/s

REPEATER

RX_CLK10

RXD_10

TX_CLK10

TXD_10

COL_10/100

CRS_10/100
RX_EN10/100
TX_EN10/100

SECURITY10/100

TX_CLK25

TXD_100[3:0]

TX_ER

RX_CLK25

RXD_100[3:0]

RX_DV
RX_ER

MDC

MDIO

SMART

4

4

4

4
4

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

12 Lucent Technologies Inc.

Description

(continued)

Block Diagrams

(continued)

Separate Bused MII Mode

5-5599.ar5

Figure 6. Separate 10/100 Mbits/s Bused MII Mode

RX_CLK10
RXD_10
TX_CLK10
TXD_10
COL_10
CRS_10
RX_EN10
TX_EN10

CRS_100
TX_EN100
TX_CLK25
TXD_100[3:0]
TX_ER
RX_CLK25
RXD_100[3:0]
RX_DV
RX_ER
COL_100
RX_EN100

MDC
MDIO

SMART_MODE_SELECT
BUSED_MII_MODE

LU3X54FT

10 Mbits/s

REPEATER

100 Mbits/s
REPEATER

MANAGEMENT

RX_CLK10

RXD_10

TX_CLK10

TXD_10
COL_10

CRS_10
RX_EN10
TX_EN10

CRS_100

TX_EN100
TX_CLK25

TXD_100[3:0]

TX_ER

RX_CLK25

RXD_100[3:0]

RX_DV
RX_ER

COL_100

RX_EN100

MDC

MDIO

4

4

4

4

4

4

4

4

Lucent Technologies Inc. 13

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Pin Information

Pin Diagram for Normal MII Mode

5-5616(F).ar4

Figure 7. LU3X54FT Pinout for Normal MII Mode

VSS

156

RXD[0][B]

155

RX_CLK[B]

154

RX_ER[B]/RXD[4][B]

153

VDD

152

RX_DV[B]

151

COL[B]

150

CRS[B]

149

TX_CLK[B]

148

VSS

147

TX_EN[B]

146

TX_ER[B]/TXD[4][B]

145

VDD

144

TXD[3][B]

143

TXD[2][B]

142

VSS

141

TXD[1][B]

140

TXD[0][B]

139

MII_EN[A]

138

VDD

137

RXD[3][A]

136

RXD[2][A]

135

RXD[1][A]

134

VSS

133

RXD[0][A]

132

RX_CLK[A]

131

RX_ER[A]/RXD[4][A]

130

VDD

129

RX_DV[A]

128

COL[A]

127

CRS[A]

126

TX_CLK[A]

125

VSS

124

TX_EN[A]

123

TX_ER[A]/TXD[4][A]

122

VDD

121

TXD[3][A]

120

TXD[2][A]

119

VSS

118

TXD[1][A]

117

TXD[0][A]

116

VSS

115

REF10

114

MDC

113

MDIO

112

VDD

111

MII_EN[D]

110

RXD[3][D]

109

RXD[2][D]

108

RXD[1][D]

107

VSS

106

RXD[0][D]

105

GNDA

1

FOSD[C]

2

FOSD[D]

3

VDDA

4

TPIN+/FOIN+[D]

5

TPIN–/FOIN–[D]

6

GNDA

7

VDDA

8

TPIN+/FOIN+[C]

9

TPIN–/FOIN–[C]

10

GNDA

11

VDDA

12

BGREF0

13

GNDA

14

VDDA

15

TPIN+/FOIN+[B]

16

TPIN–/FOIN–[B]

17

GNDA

18

VDDA

19

TPIN+/FOIN+[A]

20

TPIN–/FOIN–[A]

21

GNDA

22

VDDA

23

GNDA

24

BGREF1

25

GNDD

26

CLK20

27

VDDD

28

GNDAA

29

VDDAA

30

GNDO

31

TPOUT+/FOOUT+[D]

32

TPOUT–/FOOUT–[D]

33

VDDO

34

GNDO

35

TPOUT+/FOOUT+[C]

36

TPOUT–/FOOUT–[C]

37

VDDO

38

GNDM

39

VDDM

40

GNDAP

41

ISET_10

42

ISET_100

43

VDDAP

44

GNDO

45

TPOUT+/FOOUT+[B]

46

TPOUT–/FOOUT–[B]

47

VDDO

48

GNDO

49

TPOUT+/FOOUT+[A]

50

TPOUT–/FOOUT–[A]

51

VDDO

52

RX_CLK[D]

104

RX_ER[D]/RXD[4][D]

103

VDD

102

RX_DV[D]

101

COL[D]

100

CRS[D]

99

TX_CLK[D]

98

VSS

97

TX_EN[D]

96

TX_ER[D]TXD[4][D]

95

VDD

94

TXD[3][D]93TXD[2][D]

92

VSS

91

TXD[1][D]90TXD[0][D]

89

XTALOUT

88

LSCLK/XTALIN

87

VSSPD

86

FOSD[B]85FOSD[A]

84

VDDPD

83

VSSPLL

82

CKREF

81

VDDPLL

80

VSS

79

MII_EN[C]

78

VDD

77

RXD[3][C]76RXD[2][C]75RXD[1][C]

74

VSS

73

RXD[0][C]

72

RX_CLK[C]

71

RX_ER[C]/RXD[4][C]

70

VDD

69

RX_DV[C]

68

COL[C]

67

CRS[C]

66

TX_CLK[C]

65

VSS

64

TX_EN[C]

63

TX_ER[C]/TXD[4][C]

62

VDD

61

TXD[3][C]60TXD[2][C]

59

VSS

58

TXD[1][C]57TXD[0][C]

56

MODE[4]

55NC54

MASK_STAT_INT

53

RXD[1][B]

157

RXD[2][B]

158

RXD[3][B]

159

VDD

160

MII_EN[B]

161

TXLED[A]/REF_SEL

162

VSS

163

TXLED[B]/SCRAM_DESC_BYPASS

164

TXLED[C]/ENC_DEC_BYPASS

165

TXLED[D]/CARIN_EN

166

VDD167

RXLED[A]/FX_MODE_EN[A]

168

RXLED[B]/FX_MODE_EN[B]

169

RXLED[C]/FX_MODE_EN[C]

170

RXLED[D]/FX_MODE_EN[D]

171

VDD

172

COLED[A]

173

COLED[B]

174

COLED[C]

175

COLED[D]

176

VSS

177

GNDC

178

VDDC

179

VDDC

180

GNDC

181

GNDA

182

ATEST[A]

183

ATEST[B]

184

VDDA

185

VSS

186

LINKLED[A]/NO_LP

187

LINKLED[B]/PHYADD[0]

188

LINKLED[C]/PHYADD[1]

189

LINKLED[D]/PHYADD[2]

190

SPEEDLED[A]/ISOLATE_MODE

191

SPEEDLED[B]/BUSED_MII_MODE

192

SPEEDLED[C]/SMART_MODE_SELECT

193

SPEEDLED[D]/SPEED

194

VDD

195

3ST_EN

196

AUTO_EN

197

H_DUPLED[A]/CLK20_SEL

198

H_DUPLED[B]/CRS_SEL

199

H_DUPLED[C]/SERIAL_SEL

200

H_DUPLED[D]/FULL_DUP

201

VDD

202

RESET

203

MODE[0]

204

MODE[1]

205

MODE[2]

206

MODE[3]

207

VSS

208

LU3X54FT

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

14 Lucent Technologies Inc.

Pin Information

(continued)

Pin Diagram for Bused MII Mode

5-5616(F).br2

Figure 8. LU3X54FT Pinout for Bused MII Mode

VSS

156

RXD_10

155

RX_CLK10

154

NC

153

VDD

152

NC

151

COL_100[B]/COL_10/100[B]

150

CRS_100[B]/CRS_10/100[B]

149

TX_CLK10

148

VSS

147

TX_EN100[B]/TX_EN10/100

146

NC

145

VDD

144

NC

143

NC

142

VSS

141

NC

140

TXD_10

139

RX_EN100[A]/RX_EN10/100[

A

138

VDD

137

RXD_100[3]

136

RXD_100[2]

135

RXD_100[1]

134

VSS

133

RXD_100[0]

132

RX_CLK25

131

RX_ER

130

VDD

129

RX_DV

128

COL_100[A]/COL_10/100[A]

127

CRS_100[A]/CRS_10/100[A]

126

TX_CLK25

125

VSS

124

TX_EN100[A]/TX_EN10/100

123

TX_ER

122

VDD

121

TXD_100[3]

120

TXD_100[2]

119

VSS

118

TXD_100[1]

117

TXD_100[0]

116

VSS

115

REF10

114

MDC

113

MDIO

112

VDD

111

RX_EN100[D]/RX_EN10/100[

D

110

CRS_10[D]

109

CRS_10[C]

108

CRS_10[B]

107

VSS

106

CRS_10[A]

105

GNDA

1

FOSD[C]

2

FOSD[D]

3

VDDA

4

TPIN+/FOIN+[D]

5

TPIN–/FOIN–[D]

6

GNDA

7

VDDA

8

TPIN+/FOIN+[C]

9

TPIN–/FOIN–[C]

10

GNDA

11

VDDA

12

BGREF0

13

GNDA

14

VDDA

15

TPIN+/FOIN+[B]

16

TPIN–/FOIN–[B]

17

GNDA

18

VDDA

19

TPIN+/FOIN+[A]

20

TPIN–/FOIN–[A]

21

GNDA

22

VDDA

23

GNDA

24

BGREF1

25

GNDD

26

CLK20

27

VDDD

28

GNDAA

29

VDDAA

30

GNDO

31

OUT+/FOOUT+[D]

32

POUT–/FOOUT–[D]

33

VDDO

34

GNDO

35

OUT+/FOOUT+[C]

36

POUT–/FOOUT–[C]

37

VDDO

38

GNDM

39

VDDM

40

GNDAP

41

ISET_10

42

ISET_100

43

VDDAP

44

GNDO

45

POUT+/FOOUT+[B]

46

POUT–/FOOUT–[B]

47

VDDO

48

GNDO

49

POUT+/FOOUT+[A]

50

POUT–/FOOUT–[A]

51

VDDO

52

NC

104NC103

VDD

102NC101

COL_100[D]/COL_10/100[D]

100

CRS_100[D]/CRS_10/100[D]

99NC98

VSS

97

TX_EN100[D]/TX_EN10/100

96NC95

VDD

94

TX_EN10[D]/SECURITY_10/10093TX_EN10[C]/SECURITY_10/100

92

VSS

91

TX_EN10[B]/SECURITY_10/10090TX_EN10[A]/SECURITY_10/100

89

XTALOUT

88

LSCLK/XTALIN

87

VSSPD

86

FOSD[B]85FOSD[A]

84

VDDPD

83

VSSPLL

82

CKREF

81

VDDPLL

80

VSS

79

RX_EN100[C]/RX_EN10/100[C]

78

VDD

77

COL_10[D]76COL_10[C]

75

COL_10[B]

74

VSS

73

COL_10[A]

72NC71NC70

VDD

69NC68

COL_100[C]/COL_10/100[C]

67

CRS_100[C]/CRS_10/100[C]

66NC65

VSS

64

TX_EN100[C]/TX_EN10/100

63NC62

VDD

61

RX_EN10[D]60RX_EN10[C]

59

VSS

58

RX_EN10[B]57RX_EN10[A]

56

MODE[4]

55NC54

MASK_STAT_INT

53

NC

157NC158NC159

VDD

160

RX_EN100[B]/RX_EN10/100[B]

161

TXLED[A]/REF_SEL

162

VSS

163

TXLED[B]/SCRAM_DESC_BYPASS

164

TXLED[C]/ENC_DEC_BYPASS

165

TXLED[D]/CARIN_EN

166

VDD167

RXLED[A]/FX_MODE_EN[A]

168

RXLED[B]/FX_MODE_EN[B]

169

RXLED[C]/FX_MODE_EN[C]

170

RXLED[D]/FX_MODE_EN[D]

171

VDD

172

COLED[A]

173

COLED[B]

174

COLED[C]

175

COLED[D]

176

VSS

177

GNDC

178

VDDC

179

VDDC

180

GNDC

181

GNDA

182

ATEST[A]

183

ATEST[B]

184

VDDA

185

VSS

186

LINKLED[A]/NO_LP

187

LINKLED[B]/PHYADD[0]

188

LINKLED[C]/PHYADD[1]

189

LINKLED[D]/PHYADD[2]

190

SPEEDLED[A]/ISOLATE_MODE

191

SPEEDLED[B]/BUSED_MII_MODE

192

SPEEDLED[C]/SMART_MODE_SELECT

193

SPEEDLED[D]/SPEED

194

VDD

195

3ST_EN

196

AUTO_EN

197

H_DUPLED[A]/CLK20_SEL

198

H_DUPLED[B]/CRS_SEL

199

H_DUPLED[C]/SERIAL_SEL

200

H_DUPLED[D]/FULL_DUP

201

VDD

202

RESET

203

MODE[0]

204

MODE[1]

205

MODE[2]

206

MODE[3]

207

VSS

208

LU3X54FT

Lucent Technologies Inc. 15

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Pin Information

(continued)

Pin Maps

Table 2. LU3X54FT Pin Maps

Normal Mode Pins Bused Mode Pins 10/100 Mbits/s Smart Mode Pins Separate Mode Pins

RXD[D][3:0] CRS_10[D:A] Not used CRS_10

CRS[D:A] CRS_100[D:A] CRS_10 and CRS_100 CRS_100

TXD[C][3:0] RX_EN10[D:A] Not used RX_EN10

MII_EN[D:A] RX_EN100[D:A] RX_EN10 and RX_EN100 RX_EN100

TXD[3:0][D] TX_EN10[D:A] SECURITY_10 and SECURITY_100 TX_EN10

TX_EN[D:A] TX_EN100[D:A] TX_EN10 and TX_EN100 TX_EN100

RXD[3:0][C] COL_10[D:A] Not used COL_10

COL[D:A] COL_100[D:A] COL_10 and COL_100 COL_100

SPEEDLED[C] SMART_MODE_SELECT SMART_MODE_SELECT SMART_MODE_SELECT

SPEEDLED[B] BUSED_MII_MODE BUSED_MII_MODE BUSED_MII_MODE

TX_CLK[A] TX_CLK25 TX_CLK25 TX_CLK25

TX_CLK[B] TX_CLK10 TX_CLK10 TX_CLK10
RX_CLK[B] RX_CLK10 RX_CLK10 RX_CLK10
RX_CLK[A] RX_CLK25 RX_CLK25 RX_CLK25

RXD[B][0] RXD_10 RXD_10 RXD_10

RXD[3:0][A] RXD_100[3:0] RXD_100 RXD_100

RX_DV[A] RX_DV RX_DV RX_DV
RX_ER[A] RX_ER RX_ER RX_ER

TXD[B][0] TXD_10 TXD_10 TXD_10

TXD[A][3:0] TXD_100[3:0] TXD_100 TXD_100

TX_ER[A] TX_ER TX_ER TX_ER

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

16 Lucent Technologies Inc.

Pin Information

(continued)

Pin Descriptions

This section describes the LU3X54FT signal pins. Note that any register bit referenced includes the register num­ber and bit position. For example, register bit [29.8] is register 29, bit 8.

Table 3. MII/Serial Interface Pins in Normal MII Mode (Four Separate MII Ports)

Pin Signal T ype Description

100

67
150
127

COL[D:A] O

Collision Detect.

This signal signifies in half-duplex mode that a collision
has occurred on the network. COL is asserted high whenever there is
transmit and receive activity on the UTP media. COL is the logical AND of
TX_EN and receive activity, and is an asynchronous output. When
SERIAL_SEL is high and in 10Base-T mode, this signal indicates the jab­ber timer has expired.

99

66
149
126

CRS[D:A] O

Carrier Sense.

When CRS_SEL is low, this signal is asserted high when
either the transmit or receive medium is nonidle. This signal remains
asserted throughout a collision condition. When CRS_SEL is high, CRS is
asserted on receive activity only. CRS_SEL is set via the MII management
interface or the CRS_SE L pin.

104

71
154
131

RX_CLK[D:A] O

Receive Clock.

25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output
in 10 Mbits/s nibble mode, 10 MHz in 10 Mbits/s serial mode. RX_CLK has
a worst-case 45/55 duty cycle. RX_CLK provides the timing reference for
the transfer of RX_DV, RXD , and RX_ER signals.

109

76
159
136
108

75
158
135
107

74
157
134
105

72
155
132

RXD[3:0][D:A] O

Receive Data

. 4-bit parallel data outputs that are synchronous to RX_CLK.
When RX_ER[D:A] is asserted high in 100 Mbits/s mode, an error code will
be presented on RXD[3:0][D:A] where appropriate. The codes are as fol­lows:

■

Packet errors: ERROR_CODES = 2h.

■

Link errors: ERROR_CODES = 3h. (Packet and link error codes will only
be repeated if registers [29.9] and [29.8] are enabled.)

■

Premature end errors: ERROR_CODES = 4h.

■

Code errors: ERROR_CODES = 5h.

When SERIAL_SEL is active-high and 10 Mbits/s mode is selected, RXD[0]
is used for data output and RXD[3:1] are 3-stated.

101

68
151
128

RX_DV[D:A] O

Receive Data Valid.

When this pin is high, it indicates the LU3X54FT is
recovering and decoding valid nibbles on RXD[3:0], and the data is syn­chronous with RX_CLK. RX_DV is synchronous with RX_CLK. This pin is
not used in serial 10 Mbits/s mode.

103

70
153
130

RX_ER[D:A]/

RXD[4][D:A]

O

Receive Error.

When high, RX_ER indicates the LU3X54FT has detected
a coding error in the frame presently being transferred. RX_ER is synchro­nous with RX_CLK.

Receive Data[4].

When encoder/decoder bypass (ENC_DEC_BYP ASS) is
selected through the MII management interface, this output serves as the
RXD[4] output. This pin is only valid when the LU3X54FT is in 100 Mbits/s
mode.

Lucent Technologies Inc. 17

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Pin Information

(continued)

Pin Descriptions

(continued)

Table 3. MII/Serial Interface Pins in Normal MII Mode (Four Separate MII Ports)

(continued)

Pin Signal Type Description

98

65
148
125

TX_CLK[D:A] O

T ransmit Cloc k.

25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output
in 10 Mbits/s MII mode, 10 MHz output in 10 Mbits/s serial mode. TX_CLK
provides timing reference for the transfer of the TX_EN, TXD, and TX_ER
signals sampled on the rising edge of TX_CLK.

93, 60

143, 120

92, 59

142, 119

90, 57

140, 117

89, 56

139, 116

TXD[3:0][D:A] I

Transmit Data.

4-bit parallel input synchronous with TX_CLK. When
SERIAL_SEL is active-high and 10 Mbits/s mode is selected, only
TXD[0][D:A] are valid.

96

63
146
123

TX_EN[D:A] I

T ransmit Enable.

When driven high, this signal indicates there is valid data
on TXD[3:0]. TX_EN is synchronous with TX_CLK. When SERIAL_SEL is
active-high and 10 Mbits/s mode is selected, this pin indicates there is valid
data on TXD[0].

95

62
145
122

TX_ER[D:A]/

TXD[4][D:A]

I

Transmit Coding Error.

When driven high, this signal causes the encoder
to intentionally corrupt the byte being transmitted across the MII (00100 will
be transmitted).

Transmit Data[4].

When the encoder/decoder bypass bit is set, this input
serves as the TXD[4] input. When in 10 Mbits/s mode and SERIAL_SEL is
active-high, this pin is ignored.

110

78
161
138

MII_EN[D:A] I

MII Enable.

For normal MII mode of operation (nonbused mode), MII_EN
for each channel must be tied high to enable each individual port being
used.

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

18 Lucent Technologies Inc.

Pin Information

(continued)

Pin Descriptions

(continued)

When operating in bused MII mode, 100 Mbits/s data is bused to MII port A, and 10 Mbits/s data is bused to MII
port B.

Table 4. MII/Serial Interface Pins in Bused MII Mode

Pin Signal Type Description

125 TX_CLK25 O

Shared Transmit Clock (25 MHz).

25 MHz clock output in 100 Mbits/s mode.
TX_CLK25 provides timing reference for the transfer of the TX_EN100,
TXD_100, and TX_ER signals that are sampled on the rising edge of
TX_CLK25.

148 TX_CLK10 O

Shared Transmit Clock (10 MHz).

10 MHz clock output in 10 Mbits/s serial
mode. TX_CLK10 provides timing reference for the transfer of the TX_EN10
and TXD_10 signals that are sampled on the rising edge of TX_CLK10.

When operating in 10 Mbits/s bused mode, the REF10 input clock must be
used, and the REF_SEL pin must be pulled high through a 4.7 kΩ resistor
(TXLED[A] pin).

109
108
107
105

CRS_10[D:A] O

Carrier Sense—10 Mbits/s Mode.

When CRS_SEL is low, this signal is
asserted high when either the transmit or receive medium is nonidle. This sig­nal remains asserted throughout a collision condition. When CRS_SEL is
high, CRS_10 is asserted on receive activity only. CRS_SEL is set via the MII
management interface or the CRS_SEL pin.

When SMART_MODE_SELECT is ass erted, the LU3X54FT will internally OR
together the CRS_10 and the CRS_100 signals and output them on the
CRS_100 signals.

99

66
149
126

CRS_100[D:A]/

CRS_10/100[D:A]

O

Carrier Sense—100 Mbits/s Mode.

When CRS_SEL is low, this signal is
asserted high when either the transmit or receive medium is nonidle. This sig­nal remains asserted throughout a collision condition. When CRS_SEL is
high, CRS_100 is asserted on receive activity only. CRS_SEL is set via the MII
management interface or the CRS_SEL pin.

Carrier Sense—10/100 Mbits/s Smart Mode.

When
SMART_MODE_SELECT is asserted, the LU3X54FT will internally OR
together the CRS_10 and the CRS_100 signals and output them on the
CRS_100 signals.

154 RX_CLK10 O

Shared Receive Clock.

10 MHz clock output in 10 Mbits/s serial mode.
RX_CLK10 has a worst-case 45/55 duty cyc le . RX_CLK10 pro vides the timing
reference f or the transfer of RXD_10 when in the 10 Mbits/s mode. This si gnal
is sampled on the rising edge of RX_CLK10.

131 RX_CLK25 O

Shared Receive Clock.

25 MHz clock output in the 100 Mbits/s mode.
RX_CLK25 has a worst-case 45/55 duty cyc le . RX_CLK25 pro vides the timing
reference for the transfer of RX_DV, RXD_100, and RX_ER signals when in
the 100 Mbits/s mode. These signals are sampled on the rising edge of
RX_CLK100.

155 RXD_10 O

Shared Receive Data.

Serial data output that is synchronous to the falling

edge of RX_CLK10.

Lucent Technologies Inc. 19

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

136
135
134
132

RXD_100[3:0] O

Shared Receive Data.

4-bit parallel data outputs that are synchronous to the
falling edge of RX_CLK25. When RX_ER is asserted high, an error code will
be presented on RXD_100[3:0] where appropriate. The codes are as follows:

■

Packet errors, ERROR_CODES = 2h.

■

Link errors, ERROR_CODES = 3h (packet and link error codes will only be
repeated if registers [29.9] and [29.8] are enabled).

■

Premature end errors, ERROR_CODES = 4h.

■

Code errors, ERROR_CODES = 5h.

60
59
57
56

RX_EN10[D:A] I

Receive Enable—10 Mbits/s Mode.

When SMART_MODE_SELECT is not
enabled and RX_EN10 is driven high, its channel’s data and clock (RXD0 and
RX_CLK) are driven onto the shared serial bus. If the individual channel is not
configured for 10 Mbits/s mode, this input will be ignored. When RX_EN10s
are all set low, the serial bus will float.

Note:

Care should be taken that no more than one RX_EN is asserted at a

time.

When SMART_MODE_SELECT is enabled, these pins are ignored.

110

78
161
138

RX_EN100[D:A]/

RX_EN10/100[D:A]

I

Receive Enable—100 Mbits/s Mode.

When SMART_MODE_SELECT is not
enabled and RX_EN100 is driven high, its channel’s data, clock, and receive
data valid signals (RXD_100, RX_DV, RX_ER, and RX_CLK25) are driven
onto the shared MII bus. If the individual channel is not configured for
100 Mbits/s mode, this input will be ignored. When RX_EN100s are all set low,
the MII bus will float.

Note:

Care should be taken that no more than one RX_EN is asserted at a

time.

Receive Enable—10/100 Mbits/s Smart Mode.

When
SMART_MODE_SELECT is asserted and RX_EN100 is driven high, its chan­nel’s data, clock, and receive data valid signals [RXD, RX_ER (100 Mbits/s
only), RX_D V (100 Mbits/s only), and RX_CLK] are driven onto the shared b us
corresponding to the speed of the channel.

128 RX_DV O

Shared Receive Data Valid.

When this pin is driven high, it indicates that the
LU3X54FT is recovering and decoding valid nibbles on RXD[3:0] and that the
data is synchronous with RX_CLK. RX_D V is synchronous with RX_CLK. This
pin is not used in serial 10 Mbits/s mode.

130 RX_ER O

Shared Receive Error.

When asserted high, it indicates that the LU3X54FT
has detected a coding error in the frame presently being transf erred. RX_ER is
synchronous with RX_CLK25. This signal is not used in 10 Mbits/s mode.

139 TXD_10 I

Shared Transmit Data.

10 Mbits/s serial input synchronous with TX_CLK10.

120
119
117
116

TXD_100[3:0] I

Shared Transmit Data.

4-bit parallel input synchronous with TX_CLK25.

Pin Information

(continued)

Pin Descriptions

(continued)

When operating in bused MII mode, 100 Mbits/s data is bused to MII port A, and 10 Mbits/s data is bused to MII
port B.

Table 4. MII/Serial Interface Pins in Bused MII Mode

(continued)

Pin Signal Type Description

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

20 Lucent Technologies Inc.

93
92
90
89

TX_EN10/[D:A]/

SECURITY_10/100

I

Transmit Enable—10 Mbits/s Mode.

When driven high, this signal indicates
that there is valid data on TXD when the corresponding channel is in
10 Mbits/s serial mode.

Security for 10/100 Mbits/s Smart Mode.

When SMART_MODE_SELECT
is enabled, these pins are redefined to be the security input pins for both
10 Mbits/s and 100 Mbits/s. When security is activated, the LU3X54FT will
ignore the transmit data, and a fixed pattern is transmitted (all 1s for 10Base-T,
alternating 1, 0 for 100TX).

Security should not be asserted until after the entire preamble has been trans­mitted. When in smart mode, the 10 Mbits/s transmit channels will be enabled
through the TX_EN100 inputs.

96

63
146
123

TX_EN100[D:A]/

TX_EN10/100

I

T ransmit Enable—100 Mbits/s Mode.

When SMART_MODE_SELECT is not
enabled and TX_EN100 is driven high, this signal indicates that there is valid
data on TXD_100[3:0] when in 100 Mbits/s mode. If the individual channel is
not configured for 100 Mbits/s mode, this input will be ignored.

Transmit Enable—10/100 Mbits/s Smart Mode.

When
SMART_MODE_SELECT is asserted and TX_EN100 is driven high, this sig­nal indicates that its channel ’s input data is vali d. The input data is s elec ted by
the speed of the corresponding channel.

122 TX_ER I

Shared Transmit Coding Error.

When asserted high, this signal causes the
encoder to intentionally corrupt the byte being transmitted across the MII
(00100 will be transmitted). This signal is not used in 10 Mbits/s mode.

76
75
74
72

COL_10[D:A] O

Collision Detect for 10 Mbits/s Mode.

In half-duplex mode, this signal signi­fies that a collision has occurred on the network. COL_10 is asserted high
whenever there is transmit and receive activity on the UTP media. COL_10 is
the logical AND of TX_EN and receive activity, and it is an asynchronous out­put.

When SERIAL_SEL is high and in 10Base-T mode, this signal indicates that
the jabber timer has e x pired. W hen SM ART_MODE_SELECT is asserted, the
LU3X54FT will internally OR together the COL_10 and COL_100 signals and
output them on the COL_100 pins.

100

67
150
127

COL_100[D:A]/

COL_10/100[D:A]

O

Collision Detect for 100 Mbits/s Mode.

In half-duplex mode, this signal signi­fies that a collision has occurred on the network. COL_100 is asserted high
whenever there i s trans mit and receiv e activity on the UTP media. COL_100 is
the logical AND of TX_EN and receive activity, and it is an asynchronous out­put.

Collision Detect for 10/100 Mbits/s Smart Mode.

When SERIAL_SEL is
high and in 10Base-T mode, this signal indicates that the jabber timer has
expired. When SMART_MODE_SELECT is asserted, the LU3X54FT will inter­nally OR together the COL_10 and COL_100 signals and output them on the
COL_100 pins.

Pin Information

(continued)

Pin Descriptions

(continued)

When operating in bused MII mode, 100 Mbits/s data is bused to MII port A, and 10 Mbits/s data is bused to MII
port B.

Table 4. MII/Serial Interface Pins in Bused MII Mode

(continued)

Pin Signal Type Description

Lucent Technologies Inc. 21

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

65
68
70
71

98
101
103
104

NC O

No Connect.

Do not connect these pins.

62

95
140
142
143
145
151
153
157
158
159

NC I

No Connect.

These inputs should be grounded.

Pin Information

(continued)

Pin Descriptions

(continued)

When operating in bused MII mode, 100 Mbits/s data is bused to MII port A, and 10 Mbits/s data is bused to MII
port B.

Table 4. MII/Serial Interface Pins in Bused MII Mode

(continued)

Pin Signal Type Description

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

22 Lucent Technologies Inc.

Pin Information

(continued)

Pin Descriptions

(continued)

Table 5. MII Management Pins

Table 6. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins

Pin Signal Type Description

113 MDC I

Management Data Clock.

This is the timing reference for the transfer of
data on the MDIO signal. This signal may be asynchronous to RX_CLK and
TX_CLK. The maximum clock rate is 12.5 MHz.

When running MDC above 6.25 MHz, MDC must be synchronous with
LSCLK and have a setup time of 15 ns and a hold time of 5 ns with respect
to LSCLK. When using an external crystal instead of an LSCLK input, the
maximum MDC rate is 6.25 MHz.

112 MDIO I/O

Management Data Input/Output.

This I/O is used to transfer control and
status information between the LU3X54FT and the station management.
Control information is driven by the station management synchronous with
MDC. Status information is driven by the LU3X54FT synchronous with MDC.
This pin requires an external 1.5

kΩ pull-up resistor.

53 MASK_STAT_INT O

Maskable Status Interrupt.

This pin will go high whenever there is a

change in status as defined in Table 22.

Pin Signal Type Description

5

9
16
20

TPIN+/

FOIN+[D:A]

I

Received Data.

Positiv e differential received 125 Mbaud MLT3, or 10 Mbaud

Manchester data from magnetics.

Fiber-Optic Data Input.

Positive differential received 125 Mbaud pseudo-

ECL data from fiber transceiver.

6
10
17
21

TPIN–/

FOIN–[D:A]

I

Received Data.

Negative differential received 125 Mbaud ML T3 or 10 Mbaud

Manchester data from magnetics.

Fiber-Optic Data Input.

Negative differential received 125 Mbaud pseudo-

ECL data from fiber transceiver.

32
36
46
50

TPOUT+/

FOOUT+[D:A]

O

Transmit Data.

Positive differential transmit 125 Mbaud MLT3, or 10 Mbaud

Manchester data to magnetics.

Fiber-Optic Data Output.

Positive differential transmit 125 Mbaud pseudo-

ECL compatible data to fiber transceiver.

33
37
47
51

TPOUT–

FOIN–[D:A]

O

Transmit Data.

Negative differential transmit 125 Mbaud MLT3, 10 Mbaud

Manchester data to magnetics.

Fiber-Optic Data Output.

Negative differential transmit 125 Mbaud pseudo-

ECL compatible data to fiber transceiver.

3

2
85
84

FOSD[D:A] I

Fiber-Optic Signal Detect.

Pseudo-ECL input signal which indicates
whether or not the fiber-optic receive pairs (FOIN+/–) are receiving valid sig­nal levels. These inputs are ignored when not in fiber mode, and should be
grounded.

Lucent Technologies Inc. 23

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Pin Information

(continued)

Pin Descriptions

(continued)

Table 7. Miscellaneous Pins

Pin Signal Type Description

81 CKREF I

Clock Reference.

Connect this pin to a 1 nF ± 10% capacitor to

ground.

184
183

ATEST[B:A] O

Reserved.

For normal operation, leave these pins unconnected.

197 AUTO_EN I

Autonegotiation Enable.

When this pin is high, autonegotiation is
enabled. Pulsing this pin will cause autonegotiation to restart. This
input has the same function as register 0, bit 12. This input and the reg­ister bit are ANDed together.

1, 7,
11, 14,
18, 22,
24, 26,
29, 31,
35, 39,
41, 45,
49, 58,
64, 73,
79, 82,
86, 91,

97, 106,
115, 118,
124, 133,
141, 147,
156, 163,
177, 178,
181, 182,

186, 208

GND/V

SS

PWR

Ground.

(38 pins.)

4, 8, 12,

15, 19,
23, 28,
30, 34,
38, 40,
44, 48,
52, 61,
69, 77,
80, 83,

94, 102,
111, 121,
129, 137,
144, 152,
160, 167,
172, 179,
180, 185,

195, 202

V

DD

PWR

V

DD

.

Single 5.0 V ± 5% power supply. (35 pins.)

196 3ST_EN I

3-State Enable.

When this pin is high, all digital outputs will be

3-stated. For normal operating conditions, pull this pin low.

25
13

BGREF[1:0] I

Band Gap Reference.

Connect these pins to a 24.9 kΩ ± 1% resistor

to ground. The parasitic load capacitance should be less than 15 pF.

42 ISET_10 I

Current Set 10 Mbits/s.

An external resistor (22.1 kΩ) is placed from

this pin to ground to set the 10 Mbits/s TP driver transmit output level.

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

24 Lucent Technologies Inc.

43 ISET_100 I

Current Set 100 Mbits/s.

An external resistor (nominally 24.9 kΩ) is
placed from this pin to ground to set the 100 Mbits/s TP driver transmit
output level.

114 REF10 I

10 MHz Input Clock.

Optional reference clock for 10 Mbits/s repeater
mode for phase alignment. When used, TX_CLK will be driven from
REF10. If not used, let this pin float.

27 CLK20 I

20 MHz Input Clock.

20 MHz (±100 ppm) TTL level clock with
45%—55% duty cycle. If the internal 20 MHz clock synthesizer is being
used, ground this pin (default).

166 TXLED[D]/

CARIN_EN

I/O

Transmit LED[D].

This pin indicates transmit activity on port D. Exter-

nal buffers are necessary to drive the LEDs.

Carrier Integrity Enable.

At powerup or reset, if this pin is pulled high
through a 4.7 kΩ resistor, it will enable the carrier integrity function of
register 29, bit 3, if station management is unavailable.

This pin has an internal 50 kΩ pull-down resistor for normal operation
(CARIN_EN is disabled). This input and register bits [29.3] are ORed
together.

165 TXLED[C]/

ENC_DEC_BYPASS

I/O

Transmit LED[C].

This pin indicates transmit activity on port C. Exter-

nal buffers are necessary to drive the LEDs.

Encoder/Decoder Bypass.

At powerup or reset, if this pin is pulled
high through a 4.7 kΩ resistor, it will enable the ENC_DEC_BYPASS
function of register 29, bit 6, if station management is unavailable.

This pin has an internal 50 kΩ pull-down resistor for normal operation
(encoder/decoder ON). This input and the register bit [29.6] are ORed
together enabling the encoder/decoder bypass function for all four
channels.

164 TXLED[B]/

SCRAM_DESC_BYPASS

I/O

Transmit LED[B].

This pin indicates transmit activity on port B. Exter-

nal buffers are necessary to drive the LEDs.

Scrambler/Descrambler Bypass.

At powerup or reset, this pin may
be used to enable the SCRAM_DESC_BYPASS function by pulling this
pin high through a 4.7 kΩ resistor, if station management is unavail­able. This is the same function as register 29, bit 4.

This pin has an internal 50 kΩ pull-down resistor for normal operation
(scrambler/descrambler ON). This input and the register bit [29.4] are
ORed together during powerup and reset.

162 TXLED[A]/

REF_SEL

I/O

Transmit LED[A].

This pin indicates transmit activity on port A. Exter-

nal buffers are necessary to drive the LEDs.

Reference Select.

At powerup, this pin may be used to select the
10 MHz reference input of pin REF10 by pulling it high through a 4.7 kΩ
resistor , if station management is unav ailable . This is the same function
as register 30, bit 2.

This pin has an internal 50 kΩ pull-down resistor for normal operation
(REF10 not used). This input and the register bit are ORed together.

Pin Information

(continued)

Pin Descriptions

(continued)

Table 7. Miscellaneous Pins

(continued)

Pin Signal Type Description

Lucent Technologies Inc. 25

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

171—168 RXLED[D:A]/

FX_MODE_EN[D:A]

I/O

Receive LED[D:A].

This pin indicates receive activity. External buffers

are necessary to drive the LEDs.

FX Mode Enable.

At powerup or reset, when pulled high through a

4.7 kΩ resistor, this pin will enable the FX mode (10Base-T and
100Base-TX disabled). When pulled low, it will enable 10Base-T and
100Base-TX modes (100Base-FX mode disabled). These pins are
ORed with register 29, bit 0 [29.0].

These pins have internal 50 kΩ pull-down resistors.

176—173 COLED[D:A] O

Collision LED.

This pin indicates collisi on occurrence. Ex ternal buff ers

are necessary to drive the LEDs.
Channels A and B have internal 50 kΩ pull-down resistors but not

channels C and D.

190 LINKLED[D]/

PHYADD[2]

I/O

Link LED[D]

. This pin indicates good link status on port D. External

buffers are necessary to drive the LEDs.

PHY Address 2.

At powerup or reset, this pin is used to set the PHY

address bit 2.
If this pin is pulled high through a 50 kΩ resistor, it will set PHYADD[2]

to a 1. If this pin is pulled low through a 50 kΩ resistor, it will set
PHYADD[2] to a 0.

189 LINKLED[C]/

PHYADD[1]

I/O

Link LED[C].

This pin indicates good link status on port C. External

buffers are necessary to drive the LEDs.

PHY Address 1.

At powerup or reset, this pin is used to set the PHY

address bit 1.
If this pin is pulled high through a 50 kΩ resistor, it will set PHYADD[1]

to a 1. If this pin is pulled low through a 50 kΩ resistor, it will set
PHYADD[1] to a 0.

188 LINKLED[B]/

PHYADD[0]

I/O

Link LED[B].

This pin indicates good link status on port B. External

buffers are necessary to drive the LEDs.

PHY Address 0.

At powerup or reset, this pin may be used to set the

PHY address bit 0.
If this pin is pulled high through a 50 kΩ resistor, it will set PHYADD[0]

to a 1. If this pin is pulled low through a 50 kΩ resistor, it will set
PHYADD[0] to a 0.

187 LINKLED[A]/

NO_LP

I/O

Link LED[A].

This pin indicates good link status on port A. External

buffers are necessary to drive the LEDs.

No Link Pulse.

This pin is used at powerup or reset to select the
NO_LP function of register 30, bit 0 for all four channels by pulling this
pin high through a 4.7 kΩ resistor. This input and the register bit [30.0]
are ORed together.

This pin has an internal 50 kΩ pull-down resistor to set the default to
normal link pulse ON mode.

Pin Information

(continued)

Pin Descriptions

(continued)

Table 7. Miscellaneous Pins

(continued)

Pin Signal Type Description

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

26 Lucent Technologies Inc.

194 SPEEDLED[D]/

SPEED

I/O

Speed LED[D].

This pin indicates the operating speed of port D on the
LU3X54FT. A high on this pin indicates 100 Mbits/s operation. A low
indicates 10 Mbits/s operation. External buffers are necessary to drive
the LEDs.

Speed.

This pin is used at powerup or reset to select the operating
speed on all four channels and is the same function as register 0,
bit 13:

■

This pin is internally pulled high through a 100 kΩ resistor to enable
100 Mbits/s operation (defaults to 100 Mbits/s).

■

If this pin is pulled low through a 4.7 kΩ resistor, it will enable
10 Mbits/s operation.

This pin is ignored when autonegotiation is enabled. This pin and the
register bit are ANDed.

193 SPEEDLED[C]/

SMART_MODE_SELECT

I/O

Speed LED[C].

This pin indicates the operating speed of port C on the
LU3X54FT. A high on this pin indicates 100 Mbits/s operation. A low
indicates 10 Mbits/s operation. External buffers are necessary to drive
the LEDs.

Smart Mode Select.

At powerup or reset, if this pin is pulled high
through a 4.7 kΩ resistor, the smart mode will be selected which
enables the use of the security feature and redefines the CRS, COL,
and TX_EN10 pins. This pin is internally pulled low through a 50 kΩ
pull-down resistor. The default value is SMART_MODE _SELECT dis­abled.

When SMART_MODE_SELECT is asserted, the TX_EN10 inputs are
used as the security inputs for both 10 Mbits/s mode and 100 Mbits/s
mode. When security is activated high, the LU3X54FT will transmit a
jam signal instead of data.

When SMART_MODE_SELECT is asserted high, both the CRS_10
and CRS_100 signals will be output on the CRS_100 pins, and both
the COL_10 and COL_100 signals will be output on the COL_100 pins.

192 SPEEDLED[B]/

BUSED_MII_MODE

I/O

Speed LED[B].

This pin indicates the operating speed of port B on the
LU3X54FT. A high on this pin indicates 100 Mbits/s operation. A low
indicates 10 Mbits/s operation. External buffers are necessary to drive
the LEDs.

Bused MII Mode Select.

At powerup or reset, if the bused MII mode
select pin is pulled high through a 4.7 kΩ resistor, data streams from
ports running at 100 Mbits/s will appear on the single 100 Mbits/s MII
(port A), and data streams from ports running at 10 Mbits/s will appear
at the single 10 Mbits/s serial interface (port B). In addition, control sig­nals TX_EN10, TX_EN100, RX_EN10, RX_EN100, CRS_10, and
CRS_100 become active.

This pin is internally pulled low through a 50 kΩ pull-down resistor . The
default value is bused mode disabled.

Pin Information

(continued)

Pin Descriptions

(continued)

Table 7. Miscellaneous Pins

(continued)

Pin Signal Type Description

Lucent Technologies Inc. 27

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

191 SPEEDLED[A]/

ISOLATE_MODE

I/O

Speed LED[A].

This pin indicates the operating speed of port A on the
LU3X54FT. A high on this pin indicates 100 Mbits/s operation. A low
indicates 10 Mbits/s operation. External buffers are necessary to drive
the LEDs.

Isolate Mode.

As an input, this pin can be used at powerup or reset to

select the isolate operation mode. If this pin is pulled high through a

4.7 kΩ resistor, the LU3X54FT will powerup or reset to the isolate
mode. (MII outputs to high-impedance state.)

This pin is internally pulled low through a 50 kΩ resistor. The default
state is for the LU3X54FT to powerup or reset in a nonisolate mode.
This pin and register bit [10.0] are ORed together during powerup and
reset.

201 H_DUPLED[D]/

FULL_DUP

I/O

Half-Duplex LED[D].

When this output is high, it indicates half-duplex
mode. When it is low, it indicates full duplex. External buffers are nec­essary to drive the LEDs. This output is only valid when the link is up.

Full Duplex.

At powerup, this pin may be used to select full-duplex
operation for all four channels by pulling it high through a 4.7 kΩ resis­tor, if station management is unavailable. This is the same function as
register 0, bit 8. This pin has an internal 50 kΩ pull-down resistor to
default to half duplex for normal operation. This input and the register
bit [0.8] are ORed together during powerup and reset. This pin is
ignored when autonegotiation is enabled.

198 H_DUPLED[A]/

CLK20_SEL

I/O

Half-Duplex LED[A].

When this output is high, it indicates half-duplex
mode. When low , it indicates full duple x. External buff ers are necessary
to drive the LEDs. This output is only valid when the link is up.

20 MHz Clock Select.

When this signal is pulled high through a

4.7 kΩ resistor, it will enable the two-clock input mode (20 MHz and
25 MHz). This pin is internally pulled low through a 50 kΩ resistor to set
the default to internal 20 MHz. When lo w, this signal enables the si ngle­clock input mode (25 MHz with 20 MHz clock internally generated).

This pin has the same function as register 30, bit 6, if station manage­ment is unavailable. This input and the register bit [30.6] are ORed
together during powerup and reset.

87 LSCLK/XTALIN I

CMOS Local Symbol Clock.

A 25 MHz clock, ±100 ppm, 40%—60%

duty cycle.

Crystal Oscillator Input.

A 25 MHz crystal ±25 ppm can be connected

across XTALIN and XTALOUT.

88 XTALOUT I

Crystal Oscillator Output.

A 25 MHz crystal ±25 ppm can be con­nected across XTALIN and XTALOUT. If a single-ended external clock
(LSCLK) is connected to XTALIN, the crystal output pin should be left
floating.

55

207—204

MODE[4:0] I

Test Mode Select.

Reserved for manufacturing testing. These pins

should be tied low for normal operation.

Pin Information

(continued)

Pin Descriptions

(continued)

Table 7. Miscellaneous Pins

(continued)

Pin Signal Type Description

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

28 Lucent Technologies Inc.

203 RESET I

Full Chip Reset.

Reset must be asserted high for at least five LSCLK
cycles. The LU3X54FT will come out of reset after 400 µs. LSCLK must
remain running during reset.

199 H_DUPLED[B]/

CRS_SEL

I/O

Half-Duplex LED[B].

When this output is high, it indicates half-duplex
mode. When it is low, it indicates full duplex. External buffers are nec­essary to drive the LEDs. This output is only valid when the link is up.

Carrier Sense Select.

At powerup, this pin may be used to select the
mode of CRS operation. When this pin is pulled high through a 4.7 kΩ
resistor , CRS will be asse rted on receive activity only. This is the same
function as register 29, bit 10.

This pin has an internal 50 kΩ pull-down resistor for normal mode oper­ation (default: CRS asserted on transmit or receive activity). This input
and the register bit [29.10] are ORed together during powerup and
reset.

200 H_DUPLED[C]/

SERIAL_SEL

I/O

Half-Duplex LED[C].

When this output is high, it indicates half-duplex
mode. When low , it i ndicates full duple x. External buff ers are necessary
to drive the LEDs. This output is only valid when the link is up.

Serial Select.

At powerup, this pin may be used to set the
SERIAL_SEL function of register 30, bit 1 for all four channels by pull­ing it high through a 4.7 kΩ resistor if station management is unavail­able.

This pin has an internal 50 kΩ pull-down resistor for normal mode oper­ation (default). This input and the register bit [30.1] are ORed together
during powerup and reset.

54 NC —

No Connect.

Do not connect these pins.

Pin Information

(continued)

Pin Descriptions

(continued)

Table 7. Miscellaneous Pins

(continued)

Pin Signal Type Description

Lucent Technologies Inc. 29

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

MII Station Management

Basic Operations

The primary function of station management is to trans­fer control and status information about the LU3X54FT
to a management entity. This function is accomplished
by the MDC clock input, which has a maximum fre­quency of 12.5 MHz, along with the MDIO pin. This pin
(112) requires an external 1.5 k

Ω pull-up resistor.

The management interface (MII) uses MDC and MDIO
to physically transport information between the PHY
and the station management entity.

A specific set of registers and their contents (described
in Table 8) defines the nature of the information trans­ferred across this interface. Frames transmitted on the

MII management interface will have the frame structure
shown in Table 8. The order of bit transmission is from
left to right. Note that reading and writing of the man­agement register must be completed without interrup­tion.

Since the LU3X54FT is a four-channel device, each of
the management registers is duplicated four times as
depicted in the functional block diagram shown in
Figure 1. To select a particular channel [D:A], write to
that channel’s unique PHY address as described in
Table 9.

MII Management Frames

The fields and format for management frames are
described in the following tables.

Table 8. MII Management Frame Format

Table 9. MII Management Frames Field Descriptions

Read/Write

(R/W)

Pre ST OP PHYADD REGAD TA DATA Idle

R 1 . . . 1 01 10 AAAAA RRRRR Z0 DDDDDDDDDDDDDDDD Z

W 1 . . . 1 01 01 AAAAA RRRRR 10 DDDDDDDDDDDDDDDD Z

Field Description

Pre

Preamble

. The preamble is a series of 32 ones. The LU3X54FT will accept frames with no pream-

ble. This is indicated by a 1 in register 1, bit 6.

ST

Start of Frame.

The start of frame is indicated by a 01 pattern.

OP

Operation Code

. The operation code for a read transaction is 10. The operation code for a write

transaction is 01.

PHYADD

PHY Address

. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address
bit transmitted and received is the MSB of the address. A station management entity, which is
attached to multiple PHY entities, must have prior knowledge of the appropriate PHY address for
each entity. The address 00000 is the broadcast address. This address will produce a match
regardless of the local address.

The LU3X54FT maps the PHYADD[2:0] to the most significant 3 bits, while the least significant
2 bits address the channel within the LU3X54FT as follows:

00: Channel A.
01: Channel B.
10: Channel C.
11: Channel D.

REGAD

Register Address.

The register address is 5 bits, allowing for 32 unique registers within each PHY.

The first register address bit transmitted and received is the MSB of the address.

TA

Turnaround

. The turnaround time is a 2-bit time spacing between the register address field and the
data field of a frame to avoid drive contention on MDIO during a read transaction. During a write to
the LU3X54FT, these bits are driven to a 10 by the station. During a read, the MDIO is not driven
during the first bit time and is driven to a 0 by the LU3X54FT during the second bit time.

DA TA

Data

. The data field is 16 bits. The first bit transmitted and received is bit 15 of the register being

addressed.

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

30 Lucent Technologies Inc.

MII Station Management

(continued)

Management Registers (MR)

Register Overview

The MII management 16-bit register (MR) set is implemented as described in the table below.

Table 10. MII Management Registers (MR)

Register
Address

Symbol Name

Default

(Hex Code)

0 MR0 Control Register 3000
1 MR1 Status Register 7849
2 MR 2 PHY Identifier Register 1 0180
3 MR 3 PHY Identifier Register 2 7641
4 MR4 Autonegotiation Advertisement Register 01E1
5 MR5 Autonegotiation Link Partner Ability Register

(Base Page)

0000

5 MR5 Autonegotiation Link Partner Ability Register

(Next Page)

—

6 MR6 Autonegotiation Expansion Register 0000
7 MR7 Next-Page Transmit Register 0000

8—27 MR8—MR27 Reserved 0000

28 MR28 Device-Specific Register 1 (Status) —
29 MR29 Device-Specific Register 2 (100Mbits/s Control) 1080
30 MR30 Device-Specific Register 3 (10Mbits/s Control) 0000
31 MR31 Quick Status Register —

Lucent Technologies Inc. 31

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

MII Station Management

(continued)

Management Registers (MR)

(continued)

This section provides a detailed discussion of each management register and its bit definitions.

Table 11. MR0—Control Register Bit Descriptions

1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.

2. R = read, W = write, NA = not applicable.

Register/Bit

1

Type

2

Description

0.15 (SW_RESET) R/W

Reset.

Setting this bit to a 1 will reset the entire (all four ports, even when only
one port is addressed) LU3X54FT . All registers will be set to their default state.
This bit is self-clearing. The default is 0.

0.14 (LOOPBACK) R/W

Loopback.

When this bit is set to a 1, no data transmission will take place on
the media. Any receive data will be ignored. The loopback signal path will con­tain all circuitry up to but not including the PMD. The autonegotiation must be
turned off, then loopback can be initiated, transmit data can start 2 ms after
loopback is initiated. The default value is a 0.

0.13 (SPEED100) R/W

Speed Selection.

The value of this bit reflects the current speed of operation
(1 = 100 Mbits/s, 0 = 10 Mbits/s). This bit will only affect operating speed when
the autonegotiation enable bit (register 0, bit 12) is disabled (0). This bit is
ignored when autonegotiation is enabled (register 0, bit 12). This bit is ANDed
with the SPEEDLED[D] pin during powerup and reset. The default state is a 1.

0.12 (NWAY_ENA) R/W

Autonegotiation Enable.

The autonegotiation process will be enabled by set­ting this bit to a 1. The default state is a 1. This register bit is ANDed with the
AUTO_EN pin during power up and reset.

0.11 (PWRDN) R/W

Powerdown.

The LU3X54FT may be placed in a low-power state by setting
this bit to a 1, both the 10 Mbits/s transceiver and the 100 Mbits/s transceiver
will be powered down. While in the powerdown state, the LU3X54FT will
respond to management transactions. The default state is a 0.

0.10 (ISOLATE) R/W

Isolate Mode.

When this bit is set to a 1, the MII outputs will be brought to the
high-impedance state. The default state is a 0. This bit is ORed with the
SPEEDLED[A]/ISOLA TE_MODE pin during powerup and reset.

0.9 (REDONWAY) R/W

Restart Autonegotiation.

Normally, the autonegotiation process is started at
powerup. The process may be restarted by setting this bit to a 1. The default
state is a 0. The NWAYDONE bit (register 1, bit 5) is reset when this bit goes
to a 1. This bit is self-cleared when autonegotiation restarts.

0.8 (FULL_DUP) R/W

Duplex Mode.

This bit reflects the mode of operation (1 = full duplex, 0 = half
duplex). This bit is ignored when the autonegotiation enable bit (register 0,
bit 12) is enabled. The default state is a 0. This bit is ORed with the
H_DUPLED[D] pin during powerup or reset.

0.7 (COLTST) R/W

Collision Test.

When this bit is set to a 1, the LU3X54FT will assert the COL
signal in response to TX_EN. This bit should only be set when in loopback
mode.

0.6:0 (RESERVED) NA

Reserved.

All bits will read 0.

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

32 Lucent Technologies Inc.

MII Station Management

(continued)

Management Registers (MR)

(continued)

Table 12. MR1—Status Register Bit Descriptions

1. Note that the format for the bit descriptions is as follo ws: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.

2. R = read.

Register/Bit

1

Type

2

Description

1.15 (T4ABLE) R

100Base-T4 Ability.

This bit will always be a 0.

0: Not able.
1: Able.

1.14 (TXFULDUP) R

100Base-TX Full-Duplex Ability.

This bit will always be a 1.

0: Not able.
1: Able.

1.13 (TXHAFDUP) R

100Base-TX Half-Duplex Ability.

This bit will always be a 1.

0: Not able.
1: Able.

1.12 (ENFULDUP) R

10Base-T Full-Duplex Ability.

This bit will always be a 1.

0: Not able.
1: Able.

1.11 (ENHAFDUP) R

10Base-T Half-Duplex Ability.

This bit will always be a 1.

0: Not able.
1: Able.

1.10:7 (RESERVED) R

Reserved.

All bits will read as a 0.

1.6 (NO_PA_OK) R

Suppress Preamble.

This bit is set to a 1 indicating that the LU3X54FT accepts

management frames with the preamble suppressed.

1.5 (NWAYDO NE) R

Autonegotiation Complete.

When this bit is a 1, it indicates the autonegotia­tion process has been completed. The contents of registers MR4, MR5, MR6,
and MR7 are now valid. The default value is a 0. This bit is reset when autone­gotiation is started.

1.4 (REM_FLT) R

Remote Fault.

When this bit is a 1, it indicates a remote fault has been
detected. This bit will remain set until cleared by reading the register. The default
is a 0.

1.3 (NWAYABL E) R

Autonegotiation Ability.

When this bit is a 1, it indicates the ability to perform

autonegotiation. The value of this bit is always a 1.

1.2 (LSTAT_OK) R

Link Status.

When this bit is a 1, it indicates a valid link has been established.
This bit has a latching function: a link failure will cause the bit to clear and stay
cleared until it has been read via the management interface.

1.1 (JABBER) R

Jabber Detect.

This bit will be a 1 whenever a jabber condition is detected. It

will remain set until it is read, and the jabber condition no longer exists.

1.0 (EXT_ABLE) R

Extended Capability.

This bit indicates that the LU3X54FT supports the

extended register set (MR2 and beyond). It will always read a 1.

Lucent Technologies Inc. 33

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

MII Station Management

(continued)

Management Registers (MR)

(continued)

Table 13. MR2, 3—PHY Identifier Registers (1 and 2) Bit Descriptions

1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.

2. R = read.

Table 14. MR4—Autonegotiation Advertisement Register Bit Descriptions

1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.

2. R = read, W = write, NA = not applicable.

Register/Bit

1

Type

2

Description

2.15:0 (OUI[3:18]) R

Organizationally Unique Identifier.

The third through the twenty-fourth bit

of the OUI assigned to the PHY manufacturer by the

IEEE

are to be placed

in bits [2.15:0] and [3.15:10]. The value for bits 15:0 is 0180h.

3.15:10 (OUI[19:24]) R

Organizationally Unique Identifier.

The remaining 6 bits of the OUI. The

value for bits 15:10 is 1Dh.

3.9:4 (MODEL[5:0]) R

Model Number.

6-bit model number of the device. The model number is

54 DEC.

3.3:0 (VERSION[3:0]) R

Revision Number.

The value of the present revision number. The value is

01h for the first version.

Register/Bit

1

Type

2

Description

4.15 (NEXT_PAGE) R/W

Next Page.

The next-page function is activated by setting this bit to a 1.
This will allow the exchange of additional data. Data is carried by optional
next pages of information.

4.14 (ACK) R/W

Acknowledge.

This bit is the acknowledge bit from the link code word.

4.13 (REM_FAULT) R/W

Remote Fault.

When set to 1, the LU3X54FT indicates to the link partner a

remote fault condition.

4.12:11 (RESERVED) NA

Reserved.

These bits will read 0.

4.10 (PAUSE) R/W

Pause.

When set to a 1, it indicates that the LU3X54FT wishes to

exchange flow control information with its link partner.

4.9 (100BASET4) R/W

100Base-T4.

This bit should always be set to 0.

4.8 (100BASET_FD) R/W

100Base-TX Full Duplex.

If written to 1, autonegotiation will advertise that

the LU3X54FT is capable of 100Base-TX full-duplex operation.

4.7 (100BASETX) R/W

100Base-TX.

If written to 1, autonegotiation will advertise that the

LU3X54FT is capable of 100Base-TX operation.

4.6 (10BASET_FD) R/W

10Base-T Full Duplex.

If written to 1, autonegotiation will advertise that

the LU3X54FT is capable of 10Base-T full-duplex operation.

4.5 (10BASET ) R/W

10Base-T .

If written to 1, autonegotiation will advertise that the LU3X54FT

is capable of 10Base-T operation.

4.4:0 (SELECT) R/W

Selector Field

. Reset with the value 00001 for

IEEE

802.3.

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

34 Lucent Technologies Inc.

MII Station Management

(continued)

Management Registers (MR)

(continued)

Table 15. MR5—Autonegotiation Link Partner (LP) Ability Register (Base Page) Bit Descriptions

1. Note that the format for the bit descriptions is as follo ws: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.

2. R = read.

Table 16. MR5—Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions

1. Note that the format for the bit descriptions is as follo ws: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.

2. R = read.

Register/Bit

1

Type

2

Description

5.15 (LP_NEXT_PAGE) R

Link Partner Next Page.

When this bit is set to 1, it indicates that the link

partner wishes to engage in next-page exchange.

5.14 (LP_ACK) R

Link Partner Acknowledge.

When this bit is set to 1, it indicates that the
link partner has successfully received at least three consecutive and consis­tent FLP bursts.

5.13 (LP_REM_FAULT) R

Remote Fault.

When this bit is set to 1, it indicates that the link partner has

a fault.

5.12:5

(LP_TECH_ABILITY)

R

Technology Ability Field.

This field contains the technology ability of the
link partner. These bits are similar to the bits defined for the MR4 register
(see Table 14).

5.4:0 (LP_SELECT) R

Selector Field.

This field contains the type of message sent by the link part-

ner. For

IEEE

802.3u compliant link partners, this field should read 00001.

Register/Bit

1

Type

2

Description

5.15 (LP_NEXT_PAGE) R

Next Page.

When this bit is set to a logic 0, it indicates that this is the last

page to be transmitted. A logic 1 indicates that additional pages will follow.

5.14 (LP_ACK) R

Acknowledge.

When this bit is set to a logic 1, it indicates that the link

partner has successfully received its partner’s link code word.

5.13 (LP_MES_PAGE) R

Message Page.

This bit is used by the NEXT_PAGE function to differenti-

ate a message page (logic 1) from an unformatted page (logic 0).

5.12 (LP_ACK2) R

Acknowledge 2.

This bit is used by the NEXT_PAGE function to indicate
that a device has the ability to comply with the message (logic 1) or not
(logic 0).

5.11 (LP_TOGGLE) R

T oggle.

This bit is used by the arbitration function to ensure synchroniza­tion with the link partner during next-page exchange. Logic 0 indicates that
the previous value of the transmitted link code word was logic 1. Logic 1
indicates that the previous value of the transmitted link code word was
logic 0.

5.10:0 (MCF) R

Message/Unformatted Code Field.

With these 11 bits, there are 2048 pos­sible messages. Mes sage code field defi niti ons are described in annex 28C of
the

IEEE

802.3u standard.

Lucent Technologies Inc. 35

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

MII Station Management

(continued)

Management Registers (MR)

(continued)

Table 17. MR6—Autonegotiation Expansion Register Bit Descriptions

1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.

2. R = read, LH = latched high.

Table 18. MR7—Next-Page Transmit Register Bit Descriptions

1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.

2. R = read, W = write.

Register/Bit

1

Type

2

Description

6.15:5 (RESERVED) R

Reserved.

6.4 (PAR_DET_FAULT) R/LH

Parallel Detection Fault.

When this bit is set to 1, it indicates that a fault has
been detected in the parallel detection function. This fault is due to more than
one technology detecting concurrent link conditions. This bit can only be
cleared by reading this register.

6.3

(LP_NEXT_PAGE_ABLE)

R

Link Partner Next Page Able.

When this bit is set to 1, it indicates that the

link partner supports the next-page function.

6.2 (NEXT_PAGE_ABLE) R

Next Page Able.

This bit is set to 1, indicating that this device supports the

next-page function.

6.1 (PAGE_REC) R/LH

Page Received.

When this bit is set to 1, it indicates that a NEXT_PAGE has

been received.

6.0 (LP_NWAY_ABLE) R

Link Partner Autonegotiation Capable.

When this bit is set to 1, it indicates

that the link partner is autonegotiation capable.

Register/Bit

1

Type

2

Description

7.15 (NEXT_PAGE) R/W

Next Page.

This bit indicates whether or not this is the last NEXT_PAGE to be transmit­ted. When this bit is 0, it indicates that this is the last NEXT_PAGE. When this bit is 1, it
indicates there is an additional NEXT_PAGE.

7.14 (ACK) R

Acknowledge.

This bit is the acknowledge bit from the link code word.

7.13 (MESSAGE) R/W

Message Page.

This bit is used to differentiate a message page from an unformatted
page. When this bit is 0, it indicates an unformatted page. When this bit is 1, it indicates
a formatted page.

7.12 (ACK2) R/W

Acknowledge 2.

This bit is used by the next-page function to indicate that a device has

the ability to comply with the message. It is set as follows:

■

When this bit is 0, it indicates the device cannot comply with the message.

■

When this bit is 1, it indicates the device will comply with the message.

7.11 (TOGGLE) R

Toggle.

This bit is used by the arbitration function to ensure sy nchronization with the link

partner during next-page exchange.
This bit will always take the opposite value of the toggle bit in the previously exchanged

link code word:

■

If the bit is a logic 0, the pre vious value of the transmitted link code word w as a logic 1.

■

If the bit is a 1, the previous value of the transmitted link code word was a 0.

The initial value of the toggle bit in the first next-page transmitted is the inverse of the
value of bit 11 in the base link code word, and may assume a value of 1 or 0.

7.10:0 (MCF) R/W

Message/Unformatted Code Field.

With these 11 bits, there are 2048 possible mes-

sages. Message code field definitions are described in annex 28C of the

IEEE

802.3u

standard.

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

36 Lucent Technologies Inc.

MII Station Management

(continued)

Management Registers (MR)

(continued)

Table 19. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions

1. Note that the format for the bit descriptions is as follo ws: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.

2. R = read, LH = latched high.

Register/Bit

1

Type

2

Description

28.15:9 (R28[15:9]) R

Unused.

Read as 0.

28.8 (BAD_FRM) R/LH

Bad Frame.

If this bit is a 1, it indicates a packet has been received without an

SFD. This bit is only valid in 10 Mbits/s mode.
This bit is latching high and will only clear after it has been read or the device

has been reset. This bit defaults to 0.

28.7 (CODE) R/LH

Code Violation.

When this bit is a 1, it indicates a Manchester code violation
has occurred. The error code will be output on the RXD lines. Refer to Table 3
for a detailed description of the RXD pin error codes. This bit is only valid in
10 Mbits/s mode.

This bit is latching high and will only clear after it has been read or the device
has been reset. This bit defaults to 0.

28.6 (APS) R

Autopolarity Status.

When register 30, bit 3 is set and this bit is a 1, it indi­cates the LU3X54FT has detected and corrected a polarity reversal on the
twisted pair.

If the APF_EN bit (register 30, bit 3) is set, the reversal will be corrected inside
the LU3X54FT. This bit is not valid in 100 Mbits/s operation. This bit defaults
to 0.

28.5 (DISCON) R/LH

Disconnect.

If this bit is a 1, it indicates a disconnect. This bit will latch high

until read. This bit is only valid in 100 Mbits/s mode. This bit defaults to 0.

28.4 (UNLOCKED) R/LH

Unlocked.

Indicates that the TX scrambler lost lock. This bit will latch high until

read. This bit is only valid in 100 Mbits/s mode. This bit defaults to 0.

28.3 (RXERR_ST) R/LH

RX Error Status.

Indicates a false carrier. This bit will latch high until read. This

bit is only valid in 100 Mbits/s mode. This bit defaults to 0.

28.2 (FRC_JAM) R/LH

Force Jam.

This bit will latch high until read. This bit is only valid in 100 Mbits/s

mode. This bit defaults to 0.

28.1 (LNK100UP) R

Link Up 100.

This bit, when se t to a 1, indica te s a 100 Mb its /s tr an scei v er is up

and operational. This bit defaults to 0.

28.0 (LNK10UP) R

Link Up 10.

This bit, when set to a 1, indicates a 10 Mbits/s transceiver is up

and operational. This bit defaults to 0.

Lucent Technologies Inc. 37

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

MII Station Management

(continued)

Management Registers (MR)

(continued)

Table 20. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions

1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.

2. R = read, W = write.

Register/Bit

1

Type

2

Description

29.15 (LOCALRST) R/W

Management Reset.

This is the local management reset bit. Writing a logic 1 to
this bit will cause register (zero) 0 and registers 28 and 29 to be reset to their
default values. This bit is self-clearing. Default state is 0.

29.14 (RST1) R/W

Generic Reset 1.

This register is used for manuf acture test onl y. Default state is 0.

29.13 (RST2) R/W

Generic Reset 2.

This register is used for manuf acture test onl y. Default state is 0.

29.12 (100OFF) R/W

100 Mbits/s Transmitter Off.

When this bit is set to 0, it forces TPOUT+[D:A] low

and TPOUT–[D:A] high. This bit defaults to 1.

29.11 (RESERVED) R/W

Reserved.

Program to zero.

29.10 (CRS_SEL) R/W

Carrier Sense Select.

CRS will be asserted on receive only when this bit is set to
a 1. If this bit is set to logic 0, CRS will by asserted on receive or transmit. This bit
is ORed with the H_DUPLED[B] pin during powerup and reset. Default state is 0.

29.9 (LINK_ERR) R/W

Link Error Indication.

When this bit is a 1, a link error code will be reported on
RXD[3:0] of the LU3X54FT when RX_ER is asserted on the MII. The specific error
codes are listed in the RXD pin description. If it is 0, it will disable this function.
Default state is 0.

29.8 (PKT_ERR) R/W

Packet Error Indication Enable.

When this bit is a 1, a packet error code, which
indicates that the scrambler is not locked, will be reported on RXD[3:0] of the
LU3X54FT when RX_ER is asserted on the MII. When this bit is 0, it will disable
this function. Default state is 0.

29.7 (PULSE_STR) R/W

Pulse Stretching.

When this bit is set to 1, the COLED[D:A], TXLED[D:A], and
RXLED[D:A] output signal will be stretche d between a pproxi mately 42 ms—84 ms .
If this bit is set to 0, it will disable this feature. Default state is 1.

29.6

(ENC_DEC_BYPASS)

R/W

Encoder/Decoder Bypass.

When this bit is set to 1, the 4B/5B encoder and
5B/4B decoder function will be disabled. This bit is ORed with the TXLED[C] pin
during powerup and reset. Default state is 0.

29.5 (SAB) R/W

Symbol Aligner Bypass.

When this bit is set to 1, the aligner function will be dis-

abled. Default state is 0.

29.4

(SCRAM_DESC_BYPASS)

R/W

Scrambler/Descrambler Bypass.

When this bit is set to 1, the scrambling/
descrambling functions will be disabled. This bit is ORed with the TXLED[B] pin
during powerup and reset. Default state is 0.

29.3 (CARIN_EN) R/W

Carrier Integrity Enable.

When this bit is set to a 1, carrier integrity is enabled.
This bit is ORed with the TXLED[D] pin during powerup and reset. Default state
is 0.

29.2 (JAM_COL) R/W

Jam Enable.

When this bit is a 1, it enables JAM associated with carrier integrity

to be ORed with COL. Default state is 0.

29.1 (FEF_EN) R/W

Far-End Fault Enable.

This bit is used to enable the far-end fault detection and
transmission capability. This capability may only be used if autonegotiation is dis­abled. This capability is to be used only with media which does not support auto­negotiation. Setting this bit to 1 enables far-end fault detection and generation.
Logic 0 will disable the function. Default state is 0.

29.0 FX_MODE_EN R/W

FX Mode Enable.

When set high, this bit will enable the FX mode (10Base-T and
100Base-TX disabled). When low, it will enable 10Base-T and 100Base-TX mode
(100Base-FX mode disabled). This bit defaults to zero. It is ORed with the FX
mode enable pin.

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

38 Lucent Technologies Inc.

MII Station Management

(continued)

Management Registers (MR)

(continued)

Table 21. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions

1. Note that the format for the bit descriptions is as follo ws: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.

2 R = read, W = write.

Register/Bit

1

Type

2

Description

30.15:7 (R28[15:7]) R/W

Unused.

Read as 0.

30.6 (CLK_SEL) R/W

20 MHz Cloc k Sel ect

.

When this bit is a 1, it enabl es the two-cloc k input mode
(20 MHz and 25 MHz). When this bit is a 0, it enables the single-clock input
mode (25 MHz with 20 MHz clock internally generated). Default state is 0

.

30.5 (HBT_EN) R/W

Heartbeat Enable .

When this bit is a 1, the heartbeat function will be

enabled. Valid in 10 Mbits/s mode only. Default state is 0.

30.4 (ELL_EN) R/W

Extended Line Length Enable.

When this bit is a 1, the receive squelch lev­els are reduced from a nominal 435 mV to 350 mV, allowing reception of sig­nals with a lower amplitude. Valid in 10 Mbits/s mode only. Default state is 0.

30.3 (APF_DIS) R/W

Autopolarity Function Disable.

When this bit is a 0 and the LU3X54FT is in
10 Mbits/s mode, the autopolarity function will determine if the TP link is wired
with a polarity reversal.

If there is a polarity reversal, the LU3X54FT will assert the APS bit (register
28, bit 6) and correct the polarity reversal. If this bit is a 1 and the device is in
10 Mbits/s mode, the reversal will not be corrected. Default state is 0.

30.2 (REF_SEL) R/W

Reference Select.

When this bit is a 1, the external 10 MHz reference input

clock REF10 is used for phase alignment. Default state is 0.

30.1 (SERIAL _SEL) R/W

Serial Select.

When this bit is set to a 1, 10 Mbits/s serial mode will be
selected. When the LU3X54FT is in 100 Mbits/s mode, this bit will be ignored.
This bit is ORed with the H_DUPLED[C] pin during powerup and reset.
Default state is 0.

30.0 (ENA_NO_LP) R/W

No Link Pulse Mode.

Setting this bit to a 1 will allow 10 Mbits/s operation
with link pulses disabled. If the LU3X54FT is configured for 100 Mbits/s opera­tion, setting this bit will not affect operation. This bit is ORed with the
LINKLED[A] pin during powerup and reset. Default state is 0.

Lucent Technologies Inc. 39

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

MII Station Management

(continued)

Management Registers (MR)

(continued)

Table 22. MR31—Device-Specific Register 4 (Quick Status) Bit Descriptions

1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.

2 R = read; W = write.

Register/Bit

1

Type

2

Description

31.15 (ERROR) R

Receiver Error.

When this bit is a 1, it indicates that a receive error has been
detected. This bit is valid in 100 Mbits/s only. This bit will remain set until cleared by
reading the register. Default is a 0.

31.14 (RXERR_ST)/

(LINK_STAT_CHANGE)

R

False Carrier.

When bit [31.7] is set to 0 and this bit is a 1, it indicates that the carrier
detect state machine has f ound a f al se c arrier . This bit i s v ali d in 10 0 Mbits/s only. This
bit will remain set until cleared by reading the register. Default is 0.

Link Status Change.

When bit [31.7] is set to a 1, this bit is redefined to become the
LINK_STAT_CHANGE bit and goes high whenever there is a change in link status (bit
[31.11] changes state).

31.13 (REM_FLT) R

Remote Fault.

When this bit is a 1, it indicates a remote fault has been detected. This

bit will remain set until cleared by reading the register. Default is a 0.

31.12 (UNLOCKED)/
(JABBER)

R

Unlocked/Jabber .

If this bit is set when operating in 100 Mbits/s mode, it indicates
that the TX descrambler has lost lock. If this bit is set when operating in 10 Mbits/s
mode, it indicates a jabber condition has been detected. This bit will remain set until
cleared by reading the register.

31.11 (LSTAT_OK) R

Link Status.

When this bit is a 1, it indicates a valid link has been established. This bit
has a latching low function: a link failure will cause the bit to clear and stay cleared
until it has been read via the management interface.

31.10 (PAUSE) R

Link Partner Pause.

When this bit is set to a 1, it indicates that the LU3X54FT wishes

to exchange flow control information.

31.9 (SPEED100) R

Link Speed.

When this bit is set to a 1, it indicates that the link has negotiated to
100 Mbits/s. When this bit is a 0, it indicates that the link is operating at 10 Mbits/s.

31.8 (FULL_DUP) R

Duplex Mode.

When this bit is set to a 1, it indicates that the link has negotiated to
full-duplex mode. When this bit is a 0, it indicates that the link has negotiated to half­duplex mode.

31.7 (INT_CONF) R/W

Interrupt Configuration.

When this bit is set to a 0, it defines bit [31.14] to be the
RXERR_ST bit and the interrupt pin (MASK_STAT_INT) goes high whenever any of
bits [31.15:12] go high, or bit [31.11] goes low. When this bit is set high, it redefines
bit [31.14] to become the LINK_STAT_CHANGE bit, and the interrupt pin
(MASK_STAT_INT) goes high only when the link status changes (bit [31.14] goes
high). This bit defaults to 0.

31.6 (INT_MASK) R/W

Interrupt Mask.

When set high, no interrupt is generated by this channel under any

condition. When set low, interrupts are generated according to bit [31.7].

31.5:3

(LOW_AUTO__STATE)

R

Lowest Autonegotiation State.

These 3 bits report the state of the lowest autonego-

tiation state reached since the last register read, in the priority order defined below:
000: Autonegotiation enable.

001: Transmit disable or ability detect.
010: Link status check.
011: Acknowledge detect.
100: Complete acknowledge.
101: FLP link good check.
110: Next-page wait.
111: FLP link good.

31.2:0

(HI_AUTO_STATE)

R

Highest Autonegotiation State.

These 3 bits report the state of the highest autone-

gotiation state reached since the last register read, as defined above for bit [31.5:3].

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

40 Lucent Technologies Inc.

MII Station Management

(continued)

Unmanaged Oper ations

The LU3X54FT allows the user to set some of the station management functions during powerup or reset by strap­ping outputs high or low through weak resistors (50 kΩ). Table 23 shows the functions and their associated output
pin. For detailed information on the function of these output pins, refer to the section on management registers
described earlier in this data sheet. Also, information on how these output pins should be strapped is discussed in
the Pin Descriptions section (Table 3 through Table 7).

Table 23. Output Pins

Mode Select

Table 24. LU3X54FT Modes

Function (Register/Bit) Pin Internal Pull-Up/Pull-Down

PHYADD[2:0] LINKLED[D:B] None

NO_LP LINKLED[A] 50 k

Ω

pull-down

SPEED SPEEDLED[D] 100 k

Ω

up

CARIN_EN TXLED[D] 50 k

Ω

pull-down

ENC_DEC_BYPASS TXLED[C] 50 k

Ω

pull-down

SCRAM_DESC_BYPASS TXLED[B] 50 k

Ω

pull-down

REF_SEL TXLED[A] 50 k

Ω

pull-down

CLK20_SEL H_DUPLED[A] 50 k

Ω

pull-down

FULL _DUP H_DUPLED[D] 50 k

Ω

pull-down

SERIAL_SEL H_DUPLED[C] 50 k

Ω

pull-down

CRS_SEL H_DUPLED[B] 50 k

Ω

pull-down

BUSED_MII_MODE SPEEDLED[B] 50 k

Ω

pull-down

SMART_MODE_SELECT SPEEDLED[C] 50 k

Ω

pull-down

ISOLATE_MODE SPEEDLED[A] 50 k

Ω

pull-down

FX_MODE_EN RXLED[D:A] 50 k

Ω

pull-down

RESERVED COLED[B:A] 50 k

Ω

pull-down

MODE[4:0] Description

00000 Normal operation

00001—11111 Reserved

Lucent Technologies Inc. 41

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Absolute Maximum Ratings

(TA = 25 °C)

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso­lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.

Table 25. Absolute Maximum Ratings

Table 26. Operating Conditions

* Typical power dissipations are specified at 5.0 V and 25 °C. This is the power dissipated by the LU3X54FT. An additional 0.2 W of power is

required for the external twisted-pair driver termination resistors.

Electrical Characteristics

The following specifications apply for VDD = 5 V ± 5%.

Table 27. dc Characteristics

Parameter Symbol Min Max Unit

Ambient Operating Temperature T

A

070°C

Storage Temperature T

stg

–40 125 °C

Pow er Dissipation P

D

—3.5W

Voltage on Any Pin with Respect to Ground — –0.5 V

DD

+ 0.5 V

Maximum Supply Voltage — — 5.5 V

Parameter Symbol Min Typ

*

Max Unit

Operating Supply Voltage — 4.75 5.0 5.25 V
Power Dissipation:

P

D

P

D

P

D

P

D

—
—
—
—

3.0

2.2

2.0

1.5

—
—
—
—

W
W
W
W

All Ports 100 Mbits/s TX
All Ports 100 Mbits/s FX
All Ports 10 Mbits/s
All Ports Autonegotiating

Parameter Symbol Min Typ Max Unit

TTL Inputs:

Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Leakage Current

V

IH

V

IL

I

IH

I

IL

I

L

2.0
—
—
—
—

—
—
—
—
—

—

0.8
50

–400

50

V
V

µA
µA
µA

TTL Outputs:

Output High Voltage
Output Low Voltage
Output Shor t -cir cui t Current

V

OH

V

OL

I

SC

2.4
—

–15

—
—
—

—

0.45
–85

V
V

mA

10 Mbits/s Twisted Pair: Input Voltage V

DIFF

0.35 — 2.0 V

100 Mbits/s Twisted Pair: Input Voltage V

DIFF

——1.5V

10 Mbits/s Twisted Pair: Output Current V

DIFF

45 50 55 mA

100 Mbits/s Twisted Pair: Output Current V

DIFF

19 20 21 mA

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

42 Lucent Technologies Inc.

Package and Thermal Characteristics

The LU3X54FT is packaged in a 208-pin SQFP, plain plastic package (LU3X54FT-S208) or with an internal heat
spreader (LU3X54FT-HS208). Both packages have identical dimensions and conform to the outline diagram in this
data sheet. The heat spreader package provides enhanced thermal performance with a lower Theta-JC and
Theta-JA.

The LU3X54FT-S208 plain package thermal characteristics can be enhanced with the use of an external heat sink.
When a system designer finds that the die temperature exceeds either their or Lucent’s (125 °C) maximum temper­ature limit, a heat sink is then often considered. Heat sink fitness for use needs to be determined by the system
user! Each customers’ requirements tend to be unique, determined by the thermal and physical constraints of the
system; among them are cost, required Theta-CA, headroom above package, direction of airflow, preferred method
of attachment, etc. Table 28. provides the thermal characteristics for each package and for the plain package with
an Aavid Thermal Technology 70035B01100 external heat sink. Figure 9 provides a curve of Theta-JA versus air­flow when using this Aavid heat sink on the plain package. This heat sink is one example of a heat sink that can
work with ou r LU3X54FT transceiver.

Table 28. Thermal Characteristics

Note: The above table is for the LU3X54FT in the 208SQFP style package (die up).

* Aavid 700353B01100.

Figure 9. Thermal Characteristics

Theta-JC

(top)

Theta-JA (°C/W)

(°C/W) 0 fpm 200 fpm 500 fpm

Plain 208SQFP

20 26 22.6 20.9

Plain 208SQFP w/ Heat Sink*

20 23.5 13.5 12

208SQFP w/ Heat Spreader

10 16.1 13.3 12

AIRFLOW (fpm)

θ

-JA (

°

C/W)

10.00

12.00

14.00

16.00

18.00

20.00

22.00

24.00

100 200 300 400 500 6000

Lucent Technologies Inc. 43

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Timing Characteristics (Preliminary)

Table 29. MII Management Interface Timing (25 pF Load)

* When operating MDC above 6.25 MHz, MDC must be synchronous with LSCLK and have a setup time of 15 ns and a hold time of 5 ns,

with respect to LSCLK.

5-4959(F).r1

Figure 10. MDIO Input Timing

5-4960(F).c

Figure 11. MDIO Output Timing

5-5312(F)

Note: MDIO turnaround (TA) time is a 2-bit time spacing between the register address field, and the data field of a frame to avo id drive conten-

tion on MDIO during a read transaction. During a write to the LU3X54FT, these bits are driven to a 10 by the station. During a read, the
MDIO is not driven during the first bit time and is driven to a 0 by the LU3X54FT during the second bit time.

Figure 12. MDIO During TA (Turnaround) of a Read Transaction

Name Parameter Min Typ Max Unit

t1 MDIO Valid to Rising Edge of MDC (setup) 10 — — ns
t2 Rising Edge of MDC to MDIO Invalid (hold) 10 — — ns
t3 MDC Falling Edge to MDIO Valid (prop. delay) 0 — 40 ns
t4 MDC High* — 200 — ns
t5 MDC Low* 40 200 — ns
t6 MDC Period* 80 400 — ns

MDC

MDIO

t1

t2

MDC

MDIO

t5 t4

t6

t3

MDC

MDIO

< R > < Z > < O >

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

44 Lucent Technologies Inc.

Timing Characteristics (Preliminary)

(continued)

Table 30. MII Data Timing (25 pF Load)

* 100 Mbits/s only.

Name Parameter Min Typ Max Unit

t1 RXD[3:0], RX_ER, RX_DV Valid to RX_CLK High 10/100 — — ns
t2 RX_CLK High to RXD[3:0], RX_DV, RX_ER Invalid 10/100 — — ns
t3 RX_CLK High 14/180 — 26/220 ns
t4 RX_CLK Low 14/180 — 26/220 ns
t5 RX_CLK Period — 40 — ns
t6 TX_CLK High 14/180 — 26/220 ns
t7 TX_CLK Low 14/180 — 26/220 ns
t8 TX_CLK Period — 40 — ns

t9 TXD, TX_EN, TX_ER, Setup to TX_CLK 15/140 — — ns
t10 TXD, TX_EN, TX_ER, Hold to TX_CLK 0/0 — — ns
t11 TXD, TX_ER, Setup to LSCLK* 10 — — ns

t11b TX_EN Setup to LSCLK* 10 — — ns

t12 TXD, TX_EN, TX_ER, Hold to LSCLK* 0 — — ns
t13 First Bit of J on TPIN± While Transmitting Data to COL

Assert (half-duplex mode)

——170ns

t14 First Bit of T Received on TPIN± While Transmitting to COL

Deasser ted (half-duplex mode)

——210ns

Lucent Technologies Inc. 45

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Timing Characteristics (Preliminary)

(continued)

5-5432(F).b

Figure 13. MII Timing Requirements for LU3X54FT

TPIN

±

t13

COL

1st BIT OF J

t7

TX_CLK

TXD[3:0]

t6

t8

RX_CLK

RXD[3:0]

t1

t2

TX_EN

t3t4

t5

RX_DV
RX_ER

TX_ER

t9

t10

LSCLK

TXD[3:0]

t11

TX_EN
TX_ER

t12

1st BIT OF T

t14

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

46 Lucent Technologies Inc.

Timing Characteristics (Preliminary)

(continued)

Table 31. Serial 10 Mbits/s Timing for TPIN, CRS, and RX_CLK

5-5293(F).i

Figure 14. Serial 10 Mbits/s Timing for TPIN, CRS, and RX_CLK

Table 32. Serial 10 Mbits/s Timing for TX_EN, TPOUT, CRS, and RX_CLK

5-5293(F).j

Figure 15. Serial 10 Mbits/s Timing for TX_EN, TPOUT, CRS, and RX_CLK

Name Parameter Min Max Unit

t15 TPIN Activity to CRS Assertion 40 500 ns
t16 TPIN Activity to RX_CLK Valid 800 2300 ns
t17 IDL to CRS Deassertion 200 550 ns
t18 Dead Signal to CRS Deassertion 400 1000 ns

Name Parameter Min Max Unit

t19 TX_EN Asserted to Transmit Pair Activity 50 400 ns
t20 TX_EN Asserted to CRS Asserted Due to Internal Loopback 5 1900 ns
t21 TX_EN Asserted to RX_CLK Valid Due to Internal Loopback 1000 1700 ns
t22 TX_EN Deasserted to IDL Transmission 50 300 ns
t23 IDL Pulse Width 250 350 ns

TPIN

±

CRS

(RECEIVE—START OF PACKET) (RECEIVE—END OF PACKET)

(RECEIVE—DEAD SIGNAL)

(NOT IDL)

IDL

t15 t17

t16

t18

RX_CLK

TPOUT

±

CRS

(TRANSMIT—START OF PACKET) (TRANSMIT—END OF PACKET)

IDL

t19

t22

t20

t21

t23

TX_EN

RX_CLK

Lucent Technologies Inc. 47

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Timing Characteristics (Preliminary)

(continued)

Table 33. Serial 10 Mbits/s Timing for TX_EN, TPIN, and COL

5-5293(F).k

Figure 16. Serial 10 Mbits/s Timing for TX_EN, TPIN, and COL

Name Parameter Min Max Unit

t24 Time to Assert COL; LU3X54FT Is Transmitting; Receive Activity Starts 40 400 ns
t25 Time to Deassert COL; LU3X54FT Is Transmitting; Receive Activity Ceases 300 900 ns
t26 Time to Assert COL; LU3X54FT Is Receiving; Transmit Activity Starts 5 400 ns
t27 Time to Deassert COL; LU3X54FT Is Receiving; Transmit Activity Ceases 5 900 ns
t28 COL Pulse Width 100 — ns

TPIN

±

COL

(TRANSMITTING—RECEIVE COLLISION DETECTED) (RECEIVING—TRANSMIT COLLISON DETECTED)

IDL

t24 t25 t26 t27

t28

TX_EN

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

48 Lucent Technologies Inc.

Timing Characteristics (Preliminary)

(continued)

Table 34. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD (25 pF Load)

5-2736(F).dr1

Figure 17. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD

Name Parameter Min Max Unit

t29 RXD Setup Before RX_CLK Rising Edge 30 — ns
t30 RXD Held Past RX_CLK Edge 30 — ns
t31 RX_CLK Low to CRS Deassertion (at end of received packet) 40 — ns
t32 TX_EN Setup Before TX_CLK Rising Edge 30 — ns
t33 TX_EN Held Past TX_CLK Rising Edge 0 — ns
t34 TXD Setup Before TX_CLK Rising Edge 30 — ns
t35 TXD Held Past TX_CLK Rising Edge 0 — ns

t31

t30

t29

RX_CLK

CRS

RXD

t32

t34

t33

t35

LAST BIT

TX_CLK

TX_EN

TXD

(START OF PACKET) (END OF PACKET)

Lucent Technologies Inc. 49

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Timing Characteristics (Preliminary)

(continued)

Table 35. Serial 10 Mbits/s Timing for RX_CLK and TX_CLK (25 pF Load)

5-2737(F).dr1

Figure 18. Serial 10 Mbits/s Timing Diagram for RX_CLK and TX_CLK

Name Parameter Min Max Unit

t36 RX_CLK Low Pulse Width 45 55 ns
t37 RX_CLK High Pulse Width 45 55 ns
t38 TX_CLK Low Pulse Width 45 55 ns
t39 TX_CLK High Pulse Width 45 55 ns

RX_CLK

TX_CLK

t36 t37

t39t38

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

50 Lucent Technologies Inc.

Timing Characteristics (Preliminary)

(continued)

Table 36. 100 Mbits/s MII Transmit Timing

5-3745(F).d

Figure 19. 100 Mbits/s MII Transmit Timing

Name Parameter Min Max Unit

t40 Rising Edge of TX_CLK Following TX_EN Assertion to CRS Assertion — 40 ns
t41 Rising Edge of TX_CLK Following TX_EN Assertion to TPOUT± —60ns
t42 Rising Edge of TX_CLK Following TX_EN Deassertion to CRS Deassertion — 40 ns

TX_CLK

TX_EN

TXD[3:0]

CRS

TPOUT

±

t40

t41

t42

1st BIT OF J 1st BIT OF T

Lucent Technologies Inc. 51

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Timing Characteristics (Preliminary)

(continued)

Table 37. 100 Mbits/s MII Receive Timing

5-3747(F).d

Figure 20. 100 Mbits/s MII Receive Timing

Name Parameter Min Max Unit

t43 TPIN± 1st Bit of J Receive Activity to CRS Asserted — 170 ns
t44 TPIN± Receive Activity to Receive Data Valid — 210 ns
t45 TPIN± Receive Activity Cease (1st bit of T) to CRS Deasserted — 210 ns
t46 TPIN± Receive Activity Cease (1st bit of T) to Receive Data Not Valid — 210 ns

TPIN

±

t43

t45

t46

CRS

RX_CLK

RX_DV

RX_ER

RXD[3:0]

t44

1st BIT OF J 1st BIT OF T

LU3X54FT Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000

52 Lucent Technologies Inc.

Outline Diagram

208-Pin SQFP

Dimensions are in millimeters.

5-2196(F).r13

156

105

30.60 ± 0.20

157208

1

52

53 104

28.00 ± 0.20

28.00

± 0.20

30.60

± 0.20

PIN #1 IDENTIFIER ZONE

4.10 MAX

0.08

3.40 ± 0.20

SEATING PLANE

0.25 MIN

0.50 TYP

DETAIL BDETAIL A

0.50/0.75

GAGE PLANE

SEATING PLANE

1.30 REF

0.25

DETAIL A

DETAIL B

0.17/0.27

0.10

M

0.090/0.200

Lucent Technologies Inc. 53

Data Sheet LU3X54FT
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX

Ordering Information

*Refer to package and thermal characteristics

Device Code Comcode Package Temperature

LU3X54FT-HS208

108193384

208-Pin SQFPH (Heat Spreader)

0 °C to 70 °C

LU3X54FT-S208

108297334

208-Pin SQFP

0 °C to 70 °C*

Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.

Copyright © 2000 Lucent Technologies Inc.
All Rights Reserved

July 2000
DS99-246LAN (Replaces DS98-349LAN)

For additional information, contact your Microelectronics Group Account Manager or the following:

INTERNET:

http://www.lucent.com/micro

E-MAIL:

[e-mail]

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1-800-372-2447

, FAX [phone] (In CANADA:

1-800-553-2448

, FAX [phone])

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Tel. [phone]

, FAX [phone]

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Shanghai 200233 P. R. China

Tel. [phone], ext. 325

, F A X ( 86) 21 6440 0652

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