Datasheet LTC695-3.3, LTC694-3.3 Datasheet (Linear Technology)

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Page 1

FEATURES

■

UL Recognized File # E145770

■

Guaranteed

■

Pin Compatible with LTC694/LTC695

Reset Assertion at VCC = 1V

for 3.3V Systems

■

200µA Typical Supply Current

■

Fast (30ns Typ) On-Board Gating of RAM Chip Enable Signals

■

SO-8 and S16 Packages

■

2.90V Precision Voltage Monitor

■

Power OK/Reset Time Delay: 200ms or Adjustable

■

Minimum External Component Count

■

1µA Maximum Standby Current

■

Voltage Monitor for Power-Fail or Low-Battery Warning

■

Thermal Limiting

■

Performance Specified Over Temperature

APPLICATIO S

■

3.3V Low Power Systems

■

Critical µP Power Monitoring

■

Intelligent Instruments

■

Battery-Powered Computers and Controllers

■

Automotive Systems

LTC694-3.3/LTC695-3.3

3.3V Microprocessor Supervisory Circuits

DESCRIPTIO

The LTC®694-3.3/LTC695-3.3 provide complete 3.3V power supply monitoring and battery control functions. These include power-on reset, battery back-up, RAM write protection, power failure warning and watchdog timing. The devices are pin compatible upgrades of the LTC694/ LTC695 that are optimized for 3.3V systems. Operating power consumption has been reduced to 0.6mW (typical) and 3µW maximum in battery back-up mode. Micropro- cessor reset and memory write protection are provided when the supply falls below 2.9V. The RESET output is guaranteed to remain logic low with VCC as low as 1V.

The LTC694-3.3/LTC695-3.3 power the active RAMs with a charge pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost, auxiliary power, connected to the battery input pin, powers the RAMs in standby through an efficient PMOS switch.

For an early warning of impending power failure, the LTC694-3.3/LTC695-3.3 provide an internal comparator with a user-defined threshold. An internal watchdog timer is also available, which forces the reset pins to active states when the watchdog input is not toggled prior to a preset time-out period.

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO

≥ 5V

51k

18k

LT1129-3.3

OUT

1µF

OUT SENSE

SHDN

GND

MICROPROCESSOR RESET, BATTERY BACK-UP, RAM WRITE PROTECTION, POWER WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP FOR 3.3V MICROPROCESSOR SYSTEM

3.3V

100µF

0.1µF

2.4V

LTC695-3.3

BATT

PFI

GND

OUT

CE IN

CE OUT

RESET

PFO

WDI

0.1µF

100Ω

µP

SYSTEM

694/5-3.3 TA01

µP

POWER

POWER TO CMOS RAM

DECODER OUTPUT RAM CS

µP RESET µP NMI

I/O LINE

0.1µF

RESET Output Voltage vs

Supply Voltage

RESET OUTPUT VOLTAGE (V)

SUPPLY VOLTAGE (V)

694/5-3.3 TA02

Page 2

LTC694-3.3/LTC695-3.3

1 2 3 4

TOP VIEW

BATT

OUT

PFO

PFI

GND

S8 PACKAGE

8-LEAD PLASTIC SO

WDI

RESET

LUTEXI T

WUW

ARB

Terminal Voltage

VCC...................................................... –0.3V to 6V

.................................................. –0.3V to 6V

BATT

All Other Inputs.................. –0.3V to (V

OUT

Input Current

VCC.............................................................. 100mA

............................................................ 25mA

BATT

GND .............................................................. 10mA

PACKAGE

BATT

OUT

GND

BATT ON

LOW LINE

OSC IN

OSC SEL

RDER I FOR ATIO

TOP VIEW

1 2

3 4 5 6 7 8

N PACKAGE

16-LEAD PDIP

= 110°C, θJA = 130°C/W

JMAX

RESET

WDO

CE IN

CE OUT WDI

PFO

PFI

NUMBER

LTC695CN-3.3 LTC695IN-3.3

ORDER PART

U G

+ 0.3V)

(Notes 1 and 2)

Output Current................. Short-Circuit Protected

OUT

Power Dissipation............................................. 500mW

Operating Temperature Range

LTC694C-3.3/LTC695C-3.3.................. 0°C to 70°C

LTC694I-3.3/LTC695I-3.3 ............... –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

(Note 3)

BATT

OUT

GND

BATT ON

LOW LINE

6 7

OSC IN

OSC SEL

16-LEAD PLASTIC WIDE SO

JMAX

TOP VIEW

16 15 14 13 12 11 10

SW PACKAGE

= 110°C, θJA = 130°C/W

RESET RESET WDO CE IN CE OUT WDI PFO PFI

ORDER PART

NUMBER

LTC695CSW-3.3 LTC695ISW-3.3

TOP VIEW

OUT

GND

PFI

N8 PACKAGE 8-LEAD PDIP

= 110°C, θJA = 130°C/W

JMAX

BATT

RESET

WDI

6 5

PFO

LTC694CN8-3.3 LTC694IN8-3.3

= 110°C, θJA = 180°C/W

JMAX

LTC694CS8-3.3 LTC694IS8-3.3

Consult factory for Military grade parts.

PRODUCT SELECTIO GUIDE

RESET CONDITIONAL

PINS (V) TIMER BACK-UP WARNING PROTECT RESET BACK-UP LTC694-3.3 8 2.90 X X X LTC695-3.3 16 2.90 X X X X

LTC690 8 4.65 X X X LTC691 16 4.65 X X X X LTC694 8 4.65 X X X LTC695 16 4.65 X X X X LTC699 8 4.65 X LTC1232 8 4.37/4.62 X X LTC1235 16 4.65 X X X X X X

THRESHOLD WATCHDOG BATTERY POWER-FAIL RAM WRITE PUSH-BUTTON BATTERY

S8 PART

MARKING

6943 694I3

Page 3

LTC694-3.3/LTC695-3.3

LECTRICAL C CHARA TERIST

ICS

range, otherwise specifications are at TA = 25°C. VCC = 3.3V, V

PARAMETER CONDITIONS MIN TYP MAX UNITS Battery Back-Up Switching

Operating Voltage Range V

Output Voltage I

OUT

in Battery Back-Up Mode I

OUT

Supply Current (Exclude I

Supply Current in Battery Back-Up Mode VCC = 0V, V

Battery Standby Current (+ = Discharge, – = Charge) 3.6V > VCC > V

Battery Switchover Threshold (VCC – V

Battery Switchover Hysteresis 20 mV BATT ON Output Voltage (Note 4) I BATT ON Output Short-Circuit Current (Note 4) BATT ON = V

Reset and Watchdog Timer

Reset Voltage Threshold ● 2.8 2.9 3.0 V Reset Threshold Hysteresis 40 mV Reset Active Time OSC SEL HIGH, VCC = 3V 160 200 240 ms

Watchdog Time-Out Period, Internal Oscillator Long Period, VCC = 3V 1.2 1.6 2.0 sec

Watchdog Time-Out Period, External Clock (Note 5) Long Period, VCC = 3V ● 4032 4097 Clock

Reset Active Time PSRR 4ms/V Watchdog Time-Out Period PSRR, Internal OSC Short Period 2 ms/V

Minimum WDI Input Pulse Width VIL = 0.4V, VIH = 3V ● 200 ns RESET Output Voltage at VCC = 1V I RESET and LOW LINE Output Voltage (Note 4) I

RESET and WDO Output Voltage (Note 4) I

RESET, RESET, WDO, LOW LINE Output Source Current ● 13 25µA Output Short-Circuit Current (Note 4) Output Sink Current 9 mA

OUT

) Power Up 70 mV

BATT

OUT

OUT OUT OUT

Power Down 50 mV

SINK

BATT ON = 0V, Source Current ● 0.5 1 25 µA

Short Period, VCC = 3V 80 100 120 ms

Short Period, V

Long Period 32 ms/V

SINK SINK

SOURCE SINK

SOURCE

The ● denotes specifications which apply over the operating temperature

= 2V, unless otherwise noted.

BATT

● 3.0 5.50 V

● 1.5 2.75 V

= 1mA V

● V

= 50mA ● VCC – 0.8 VCC – 0.4 V = 250µA, VCC < V ≤ 50mA, VCC = 3.6V 0.2 0.6 mA

BATT

= 800µA ● 0.3 V

OUT

= 10µA, VCC = 1V ● 4 200 mV = 400µA, VCC = 2.8V ● 0.3 V

= 0.1µA, VCC = 3V ● 2.3 V

= 400µA, VCC = 3V ● 0.3 V

= 0.1µA, VCC = 2.8V ● 2.3 V

BATT

= 2V 0.04 1 µA

+ 0.2V –0.02 0.02 µA

BATT

, Sink Current 25 mA

= 3V ● 960 1025 Cycles

● V

● 0.2 1.0 mA

● 0.04 5 µA

● –0.10 0.10 µA

● 140 200 280 ms

● 1.0 1.6 2.25 sec

● 70 100 140 ms

– 0.1 V

– 0.2 VCC – 0.01 V

– 0.1 V

BATT

– 0.01 V

– 0.02 V

BATT

Page 4

LTC694-3.3/LTC695-3.3

LECTRICAL C CHARA TERIST

ICS

range, otherwise specifications are at TA = 25°C. VCC = 3.3V, V

PARAMETER CONDITIONS MIN TYP MAX UNITS

WDI Input Threshold Logic Low ● 0.4 V

Logic High

WDI Input Current WDI = V

WDI = 0V

Power-Fail Detector

PFI Input Threshold ● 1.25 1.3 1.35 V PFI Input Threshold PSRR 0.3 mV/V PFI Input Current ● ±0.01 ±25 nA PFO Output Voltage (Note 4) I

PFO Short-Circuit Source Current (Note 4) PFI = HIGH, PFO = 0V ● 13 25µA

PFI Comparator Response Time (Falling) ∆VIN = –20mV, VOD = 15mV 2 µs PFI Comparator Response Time (Rising) (Note 4) ∆VIN = 20mV, VOD = 15mV 40 µs

Chip Enable Gating

CE IN Threshold V

CE IN Pull-Up Current (Note 6) 3 µA CE OUT Output Voltage I

CE IN Propagation Delay CL = 20pF ● 30 50 ns CE OUT Output Short-Circuit Current Output Source Current 15 mA

Oscillator

OSC IN Input Current (Note 6) ±2 µA OSC SEL Input Pull-Up Current (Note 6) 5 µA OSC IN Frequency Range OSC SEL = 0V ● 0 125 kHz

SINK

SOURCE

PFI = LOW, PFO = V

with 10kΩ Pull-Up 8 µs

SINK

SOURCE

Output Sink Current 20 mA

OSC SEL = 0V, C

The ● denotes specifications which apply over the operating temperature

= 2V, unless otherwise noted.

BATT

● 2.3 V

OUT

= 800µA ● 0.3 V

= 0.1µA ● 2.3 V

OUT

= 800µA ● 0.3 V

= 400µA ● V = 1µA, VCC = 0V ● V

= 47pF 4 kHz

OSC

● 4 50 µA

● –50 –8 µA

17 mA

0.45 V

1.9 V

– 0.50 V

OUT

– 0.05 V

OUT

Note 1: Absolute Maximum Ratings are those values beyond which the life of device may be impaired.

Note 2: All voltage values are with respect to GND. Note 3: For military temperature range parts, consult the factory. Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and

RESET have weak internal pullups of typically 3µA. However, external pull- up resistors may be used when higher speed is required.

Note 5: The external clock feeding into the circuit passes through the oscillator before clocking the watchdog timer. Variation in the time-out period is caused by phase errors which occur when the oscillator divides the external clock by 64. The resulting variation in the time-out period is 64 plus one clock of jitter.

Note 6: The input pins of CE IN, OSC IN and OSC SEL have weak internal pull-ups which pull to the supply when the input pins are floating.

Page 5

LPER

TEMPERATURE (°C)

–50

PFI INPUT THRESHOLD (V)

1.310

1.308

1.306

1.304

1.302

1.300

1.298

1.296

1.294 25 75

694/5-3.3 G03

–25 0

50 100 125

VCC = 3.3V

TIME (µs)

3.5

3.0

2.5

2.0

1.5

1.0

0.5 0

694/5-3.3 G06

1.315V

1.295V

108

PFI

= 20mV STEP

1816

PFO OUTPUT VOLTAGE (V)

VCC = 3.3V T

= 25°C

+ –

PFI

1.3V

30pF

10k

3.3V

PFO

SUPPLY VOLTAGE (V)

RESET OUTPUT VOLTAGE (V)

694/5-3.3 TA02

Output Voltage vs Load Current

3.30

3.25

VCC = 3.3V V

BATT

= 25°C

ATYPICA

= 2.4V

CCHARA TERIST

2.40

2.39

ICS

VCC = 0V V

BATT

= 25°C

LTC694-3.3/LTC695-3.3

Power Failure Input Threshold vs TemperatureOutput Voltage vs Load Current

= 2.4V

3.20 SLOPE = 4.6Ω

3.15

3.10

OUTPUT VOLTAGE (V)

3.05

3.00 10

LOAD CURRENT (mA)

Power-Fail Comparator Response Time

3.5

3.0

2.5

2.0

1.5

1.0

PFO OUTPUT VOLTAGE (V)

0.5 0

1.305V

1.285V

PFI

1.3V

= 20mV STEP

+ –

694/5-3.3 G01

VCC = 3.3V

= 25°C

PFO

30pF

1.315V

1.295V

2.38

SLOPE = 90Ω

100

200

LOAD CURRENT (µA)

2.37

OUTPUT VOLTAGE (V)

2.36

2.35

Power-Fail Comparator Response Time

3.5 VCC = 3.3V

3.0

= 25°C

2.5

2.0

1.5

1.0

0.5

PFO OUTPUT VOLTAGE (V)

PFI

300

PFI

–

1.3V

= 20mV STEP

400

694/5-3.3 G02

30pF

500

Power-Fail Comparator Response Time with Pull-Up Resistor

PFO

220

210

200

190

180

170

RESET ACTIVE TIME (ms)

160

150

–50

123

TIME (µs)

Reset Active Time vs Temperature

VCC = 3.3V

–25 0

TEMPERATURE (°C)

50 100 125

25 75

694/5-3.3 G04

694/5-3.3 G07

Reset Voltage Threshold vs Temperature

2.90 VCC = 3.3V

2.89

2.88

2.87

2.86

2.85

RESET VOLTAGE THRESHOLD (V)

2.84

–50

–25 0

TIME (µs)

25 75

TEMPERATURE (°C)

140

120

10080

50 100 125

180160

694/5-3.3 G05

694/5-3.3 G08

RESET Output Voltage vs Supply Voltage

Page 6

LTC694-3.3/LTC695-3.3

PI FU CTIO S

VCC: 3.3V Supply Input. The VCC pin should be bypassed with a 0.1µF capacitor.

: Voltage Output for Backed Up Memory. Bypass with

OUT

a capacitor of 0.1µF or greater. During normal operation, V

obtains power from VCC through an NMOS power

OUT

switch, M1, which can deliver up to 50mA and has a typical on resistance of 5Ω. When VCC is lower than V is internally switched to V used, connect V

: Back-Up Battery Input. When VCC falls below V

BATT

OUT

to VCC.

auxiliary power connected to V

BATT

. If V

BATT

and V

OUT

, is delivered to V

BATT

, V

OUT

are not

BATT

OUT

through PMOS switch, M2. If back-up battery or auxiliary power is not used, V

should be connected to GND.

BATT

GND: Ground Pin. BATT ON: Battery On Logic Output from Comparator C2.

BATT ON goes low when V

is internally connected to

OUT

VCC. The output typically sinks 25mA and can provide base drive for an external PNP transistor to increase the output current above the 50mA rating of V high when V

is internally switched to V

OUT

. BATT ON goes

OUT

BATT

PFI: Power Failure Input. PFI is the noninverting input to the power-fail comparator, C3. The inverting input is internally connected to a 1.3V reference. The power failure output remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. Connect PFI to GND or V

OUT

when

C3 is not used. PFO: Power Failure Output from C3. PFO remains high

when PFI is above 1.3V and goes low when PFI is below

1.3V. When VCC is lower than V

, C3 is shut down and

BATT

PFO is forced low. RESET: Logic Output for µ P Reset Control. Whenever V

falls below either the reset voltage threshold (2.90V, typically) or V

, RESET goes active low. After V

BATT

returns to 3.3V, the reset pulse generator forces RESET to remain active low for a minimum of 140ms. When the watchdog timer is enabled but not serviced prior to a preset time-out period, the reset pulse generator also forces RESET to active low for a minimum of 140ms for

every preset time-out period (see Figure 11). The reset active time is adjustable on the LTC695-3.3. An external push-button reset can be used in connection with the RESET output. See Push-Button Reset in Applications Information section.

RESET: Active High Logic Ouput. It is the inverse of RESET.

LOW LINE: Logic Output from Comparator C1. LOW LINE indicates a low line condition at the VCC input. When V

falls below the reset voltage threshold (2.90V typically), LOW LINE goes low. As soon as VCC rises above the reset voltage threshold, LOW LINE returns high (see Figure 1). LOW LINE goes low when V

drops below V

BATT

(see

Table 1). WDI: Watchdog Input. WDI is a three-level input. Driving

WDI either high or low for longer than the watchdog timeout period, forces both RESET and WDO low. Floating WDI disables the watchdog timer. The timer resets itself with each transition of the watchdog input (see Figure 11).

WDO: Watchdog Logic Output. When the watchdog input remains either high or low for longer than the watchdog time-out period, WDO goes low. WDO is set high whenever there is a transition on the WDI pin, or LOW LINE goes low. The watchdog timer can be disabled by floating WDI (see Figure 11).

CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN can be derived from microprocessor’s address line and/or decoder output. See Applications Information section and Figure 5 for additional information.

CE OUT: Logic Output on the Chip Enable Gating Circuit. When VCC is above the reset voltage threshold, CE OUT is a buffered replica of CE IN. When VCC is below the reset voltage threshold CE OUT is forced high (see Figure 5).

OSC SEL: Oscillator Selection Input. When OSC SEL is high or floating, the internal oscillator sets the reset active time and watchdog time-out period. Forcing OSC SEL low, allows OSC IN to be driven from an external clock signal or an external capacitor can be connected between OSC IN and GND.

Page 7

PI FU CTIO S

LTC694-3.3/LTC695-3.3

OSC IN: Oscillator Input. OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND when OSC SEL is forced low. In this configuration the nominal reset active time and watchdog time-out period are determined by the number of clocks or set by the formula (see Applications

BLOCK

IDAGRA

BATT

1.3V

–

Information section). When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 200ms typical for the LTC695-3.3. OSC IN selects between the 1.6 seconds and 100ms typical watchdog time-out periods. In both cases, the time-out period immediately after a reset is 1.6 seconds typical.

OUT

CHARGE

PUMP

BATT ON

LOW LINE

CE OUT

CE IN

OSC IN

OSC SEL

WDI

PFI

GND

OSC

TRANSITION

DETECTOR

–

RESET PULSE

GENERATOR

WATCHDOG

TIMER

PFO

RESET

WDO

694/5-3.3 BD

Page 8

LTC694-3.3/LTC695-3.3

PPLICATI

I FOR ATIO

Microprocessor Reset

The LTC694-3.3/LTC695-3.3 use a bandgap voltage reference and a precision voltage comparator C1 to monitor the

3.3V supply input on VCC (see Block Diagram). When V

falls below the reset voltage threshold, the RESET output is forced to active low state. The reset voltage threshold accounts for a 10% variation on VCC, so the RESET output becomes active low when VCC falls below 3.0V (2.9V typical). On power-up, the RESET signal is held active low for a minimum of 140ms after reset voltage threshold is reached to allow the power supply and microprocessor to stabilize. The reset active time is adjustable on the LTC695-

3.3. On power-down, the RESET signal remains active low even with VCC as low as 1V. This capability helps hold the microprocessor in stable shutdown condition. Figure 1 shows the timing diagram of the RESET signal.

The precision voltage comparator, C1, typically has 40mV of hysteresis which ensures that glitches at VCC pin do not activate the RESET output. Response time is typically 10µs. To help prevent mistriggering due to transient loads, the VCC pin should be bypassed with a 0.1µF capacitor with the leads trimmed as short as possible.

The LTC695-3.3 has two additional outputs: RESET and LOW LINE. RESET is an active high output and is the inverse of RESET. LOW LINE is the output of the precision voltage comparator C1. When VCC falls below the reset voltage threshold, LOW LINE goes low. LOW LINE returns high as soon as VCC rises above the reset voltage threshold.

Battery Switchover

The battery switchover circuit compares VCC to the V input, and connects V VCC rises to 70mV above V comparator, C2, connects V

to whichever is higher. When

OUT

, the battery switchover

BATT

to VCC through a charge-

OUT

BATT

pumped NMOS power switch, M1. When VCC falls to 50mV above V

, C2 connects V

BATT

OUT

to V

through a

BATT

PMOS switch, M2. C2 has typically 20mV of hysteresis to prevent spurious switching when VCC remains nearly equal to V

. The response time of C2 is approximately

BATT

20µ s. During normal operation, the LTC694-3.3/LTC695-3.3

use a charge-pumped NMOS power switch to achieve low dropout and low supply current. This power switch can deliver up to 50mA to V resistance of 5Ω. The V

from VCC and has a typical on

OUT

pin should be bypassed with

OUT

a capacitor of 0.1µF or greater to ensure stability. Use of a larger bypass capacitor is advantageous for supplying current to heavy transient loads.

When operating currents larger than 50mA are required from V

, or a lower dropout (VCC-V

OUT

voltage differen-

OUT

tial) is desired, the LTC695-3.3 should be used. This product provides BATT ON output to drive the base of an external PNP transistor (Figure 2). If higher currents are needed with the LTC694-3.3, a high current Schottky diode can be connected from the VCC pin to the V

OUT

to supply the extra current.

RESET

LOW LINE

Figure 1. Reset Active Time

V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS

t1 = RESET ACTIVE TIME

694/5-3.3 F01

Page 9

LTC694-3.3/LTC695-3.3

PPLICATI

3.3V

Figure 2. Using BATT ON to Drive External PNP Transistor

I FOR ATIO

ANY PNP POWER TRANSISTOR

BATT ON

0.1µF 1

2.4V

LTC695-3.3

BATT

GND

OUT

0.1µF

694/5-3.3 F02

The LTC694-3.3/LTC695-3.3 are protected for safe area operation with short-circuit limit. Output current is limited to approximately 200mA. If the device is overloaded for a long period of time, thermal shutdown turns the power switch off until the device cools down. The threshhold temperature for thermal shutdown is approximately 155°C with about 10°C of hysteresis which prevents the device from oscillating in and out of shutdown.

The PNP switch used in competitive devices was not chosen for the internal power switch because it injects unwanted current into the substrate. This current is collected by the V

pin in competitive devices and adds to

BATT

the charging current of the battery which can damage lithium batteries. The LTC694-3.3/LTC695-3.3 use a chargepumped NMOS power switch to eliminate unwanted charging current while achieving low dropout and low supply current. Since no current goes to the substrate, the current collected by V

A 125Ω PMOS switch connects the V

pin is strictly junction leakage.

BATT

input to V

OUT

in battery back-up mode. The switch is designed for very low dropout voltage (input-to-output differential). This feature is advantageous for low current applications such as battery back-up in CMOS RAM and other low power CMOS circuitry. The supply current in battery back-up mode is 1µA maximum.

The operating voltage at the V

pin ranges from 1.5V to

BATT

2.75V. The charging resistor for rechargeable batteries should be connected to V

since this eliminates the

OUT

discharge path that exists when the resistor is connected to VCC (Figure 3).

– V

OUT

LTC694-3.3 LTC695-3.3

GND

BATT

OUT

0.1µ

694/5-3.3 F03

OUT

I =

3.3V

0.1µF

2.4V

Figure 3. Charging External Battery Through V

BATT

Replacing the Back-Up Battery

When changing the back-up battery with system power on, spurious resets can occur while the battery is removed due to battery standby current. Although battery standby current is only a tiny leakage current, it can still charge up the stray capacitance on the V cycle is as follows: When V

BATT

pin. The oscillation

BATT

reaches within 50mV of VCC, the LTC694-3.3/LTC695-3.3 switch to battery backup. V

OUT

pulls V

low and the device goes back to

BATT

normal operation. The leakage current then charges up the V

pin again and the cycle repeats.

BATT

If spurious resets during battery replacement pose no problems, then no action is required. Otherwise, a resistor from V

to GND will hold the pin low while changing the

BATT

battery. For example, the battery standby current is 1µA maximum over temperature so the external resistor required to hold V

V – 50mV

≤

below VCC is:

BATT

With VCC = 3V, a 2.7M resistor will work. With a 2V battery, this resistor will draw only 0.7µA from the battery, which is negligible in most cases.

If battery connections are made through long wires, a 10Ω to 100Ω series resistor and a 0.1µF capacitor are recom- mended to prevent any overshoot beyond VCC due to the lead inductance (Figure 4).

Page 10

LTC694-3.3/LTC695-3.3

PPLICATI

Figure 4. 10Ω/0.1µF Combination Eliminates Inductive Overshoot and Prevents Spurious Resets During Battery Replacement. The 2.7M Pulls the V While the Battery is Removed, Eliminating Spurious Resets

Table 1. Input and Output Status in Battery Back-Up Mode

SIGNAL STATUS

OUT

BATT

BATT ON Logic high. The open-circuit output voltage is equal to V PFI Power failure input is ignored PFO Logic low RESET Logic low RESET Logic high. The open-circuit output voltage is equal to V LOW LINE Logic low WDI Watchdog input is ignored. WDO Logic high. The open-circuit output voltage is equal to V CE IN Chip Enable input is ignored. CE OUT Logic high. The open-circuit output voltage is equal to V OSC IN OSC IN is ignored OSC SEL OSC SEL is ignored

C2 monitors VCC for active switchover V

is connected to V

OUT

The supply current is 1µA maximum.

10Ω

I FOR ATIO

2.7M

0.1µF

through an internal PMOS switch

BATT

LTC694-3.3 LTC695-3.3

GND

694/5-3.3 F04

Pin to Ground

BATT

OUT

Table 1 shows the state of each pin during battery back-up. When the battery switchover section is not used, connect V

to GND and V

BATT

OUT

to VCC.

Memory Protection

The LTC695-3.3 includes memory protection circuitry which ensures the integrity of the data in memory by preventing write operations when VCC is at invalid level. Two additional pins, CE IN and CE OUT, control the Chip Enable or Write inputs of CMOS RAM. When VCC is 3.3V, CE OUT follows CE IN with a typical propagation delay of 30ns. When VCC falls below the reset voltage threshold or V

, CE OUT is forced high, independent of CE IN. CE

BATT

OUT is an alternative signal to drive the CE, CS, or Write input of battery backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NOVRAM to achieve similar protection. Figure 5 shows the timing diagram of CE IN and CE OUT.

CE IN can be derived from the microprocessor’s address decoder output. Figure 6 shows a typical nonvolatile CMOS RAM application.

Memory protection can also be achieved with the LTC694-

3.3 by using RESET as shown in Figure 7.

Power-Fail Warning

The LTC694-3.3/LTC695-3.3 generate a Power Failure Output (PFO) for early warning of failure in the microprocessor’s power supply. This is accomplished by

CE IN

CE OUT

= V

OUT

BATT

Figure 5. Timing Diagram for CE IN and CE OUT

V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS

OUT

= V

BATT

694/5-3.3 F05

Page 11

LTC694-3.3/LTC695-3.3

V =1.3V 1+

R1R2R1

 



 



PPLICATI

3.3V

0.1µF

2.4V

LTC695-3.3

BATT

GND

OUT

CE OUT

CE IN

RESET RESET

U S

I FOR ATIO

10µF

30ns PROPAGATION DELAY

FROM DECODER

TO µP

0.1µF

Figure 6. A Typical Nonvolatile CMOS RAM Application

3.3V

0.1µF

2.4V

LTC694-3.3

BATT

GND

OUT

RESET

10µF

0.1µF

Figure 7. Write Protect for RAM with LTC694-3.3

CS1

CS2

62128

RAM

GND

62512

RAM GND

694/5-3.3 F06

694/5-3.3 F07

comparing the power failure input (PFI) with an internal

1.3V reference. PFO goes low when the voltage at the PFI pin is less than

1.3V. Typically PFI is driven by an external voltage divider (R1 and R2 in Figures 8 and 9) which senses either an unregulated DC input or a regulated 3.3V output. The voltage divider ratio can be chosen such that the voltage at the PFI pin falls below 1.3V several milliseconds before the 3.3V supply falls below the maximum reset voltage threshold 3.0V. PFO is normally used to interrupt the microprocessor to execute shutdown procedure between PFO and RESET or RESET.

The power-fail comparator, C3, does not have hysteresis. Hysteresis can be added however, by connecting a resistor between the PFO output and the noninverting PFI input pin as shown in Figures 8 and 9. The upper and lower trip points in the comparator are established as follows:

When PFO output is low, R3 sinks current from the summing junction at the PFI pin.

10µF

LT1129-3.3

VINV

OUT SENSE

SHDN

ADJ

OUT

Unregulated

3.3V

100µF

0.1µF

10k

200k

DC Supply with the

≥ 5V

+ +

R1 51k

R2 16k

Figure 8. Monitoring LTC694-3.3/LTC695-3.3’s Power-Fail Comparator

10µF

LT1129-3.3 VINV

OUT

OUT SENSE

SHDN

ADJ

10µF

R1 27k

R2 16k

R5 5k

3.3V

2.7M

0.1µF

10k

≥ 6.5V

+ +

PFO PFI

TO µP

LTC694-3.3 LTC695-3.3

PFO PFI

TO µP

LTC694-3.3 LTC695-3.3

GND

694/5-3.3 F09

694/5-3.3 F08

When PFO output is high, the series combination of R3 and R4 source current into the PFI summing junction.



V 1.3V 1





Assuming R4 R3,V 3 V

(3.3V –1.3V)R1

–

1.3V(R3 R4)

<< = .3

HYSTERESIS

 



Example 1: The circuit in Figure 8 demonstrates the use of the power-fail comparator to monitor the unregulated power supply input. Assuming the the rate of decay of the supply input VIN is 100mV/ms and the total time to execute a shutdown procedure is 8ms. Also the noise of VIN is 200mV. With these assumptions in mind, we can reasonably set VL = 5V which is 1.6V greater than the sum of maximum reset voltage threshold and the dropout voltage of the LT1129-3.3 (3V + 0.4V) and V

HYSTERESIS

= 850mV.

Figure 9. Monitoring

Regulated

DC Supply with the

LTC694-3.3/LTC695-3.3’s Power-Fail Comparator

Page 12

LTC694-3.3/LTC695-3.3

PPLICATI

V3V

HYSTERESIS

==.3

I FOR ATIO

850mV

R3 ≈ 3.88 R1

Choose R3 = 200k and R1 = 51k. Also select R4 = 10k which is much smaller than R3.



5V=1.3V 1+R2–





(3.3V –1.3V)5151

1 3 210

Vk.( )

 



R2 = 15.8k, Choose nearest 5% resistor 16k and recalculate VL,



V1.3V1



16k





V1.3V1

=++



16k



(4.96V –3.4V)

(3.3V –1.3V)51

–

51k

200k

15.6ms

1.3V(210k



51k









)



496

100mV/ms

HYSTERESIS

= 5.77V – 4.96V = 810mV

The 15.6ms allows enough time to execute shutdown procedure for microprocessor and 810mV of hysteresis would prevent PFO from going low due to the noise of VIN.

Example 2: The circuit in Figure 9 can be used to measure the regulated 3.3V supply to provide early warning of power failure. Because of variations in the PFI threshold, this circuit requires adjustment to ensure the PFI comparator trips before the reset threshold is reached. Adjust R5 such that the PFO output goes low when the VCC supply reaches the desired level (e.g., 3.1V).

Monitoring the Status of the Battery

C3 can also monitor the status of the memory back-up battery (Figure 10). If desired, the CE OUT can be used to apply a test load to the battery. Since CE OUT is forced high in battery back-up mode, the test load will not be applied to the battery while it is in use, even if the microprocessor is not powered.

3.3V

BATT

R1 1M

2.4V

Figure 10. Back-Up Battery Monitor with Optional Test Load

1.6M

20k

OPTIONAL TEST LOAD

PFI

CE OUT

LTC695-3.3

PFO

CE IN

GND

LOW-BATTERY SIGNAL TO µP I/O PIN

I/O PIN

694/5-3.3 F10

Watchdog Timer

The LTC694-3.3/LTC695-3.3 provide a watchdog timer function to monitor the activity of the microprocessor. If the microprocessor does not toggle the watchdog input (WDI) within a seleced time-out period, RESET is forced to active low for a minimum of 140ms. The reset active time is adjustable on the LTC695-3.3. Since many systems can not service the watchdog timer immediately after a reset, the LTC695-3.3 has a longer time-out period (1.0 second minimum) right after a reset is issued. The normal timeout period (70ms minimum) becomes effective following the first transition of WDI after RESET is inactive. The watchdog time-out period is fixed at 1.0 second minimum on the LTC694-3.3. Figure 11 shows the timing diagram of watchdog time-out period and reset active time. The watchdog time-out period is restarted as soon as RESET is inactive. When either a high-to-low or low-to-high transition occurs at the WDI pin prior to time-out, the watchdog time is reset and begins to time out again. To ensure the watchdog time does not time out, either a highto-low or low-to-high transition on the WDI pin must occur at or less than the minimum time-out period. If the input to the WDI pin remains either high or low, reset pulses will be issued every 1.6 seconds typically. The watchdog time can be deactivated by floating the WDI pin. The timer is also disabled when VCC falls below the reset voltage threshold or V

BATT

Page 13

LTC694-3.3/LTC695-3.3

PPLICATI

WDI

WDO

RESET

= 3.3V

I FOR ATIO

Figure 11. Watchdog Time-Out Period and Reset Active Time

EXTERNAL CLOCK

3.3V

LTC695-3.3

OSC SEL

t1 = RESET ACTIVE TIME

= NORMAL WATCHDOG TIME-OUT PERIOD

= WATCHDOG TIME-OUT PERIOD IMMEDIATELY

AFTER A RESET

EXTERNAL OSCILLATOR

3.3V

OSC SEL

LTC695-3.3

694/5-3.3 F11

INTERNAL OSCILLATOR

1.6 SECOND WATCHDOG

3.3V

GND

LTC695-3.3

GND

OSC SEL

OSC IN

FLOATING OR HIGH

Figure 12. Oscillator Configurations

The LTC695-3.3 provides an additional output (Watchdog Output, WDO) which goes low if the watchdog timer is allowed to time out and remains low until set high by the next transition on the WDI pin. WDO is also set high when VCC falls below the reset voltage threshold or V

BATT

The LTC695-3.3 has two additonal pins, OSC SEL and OSC IN, which allow reset active time and watchdog time-out period to be adjusted per Table 2. Several configurations are shown in Figure 12.

INTERNAL OSCILLATOR

3.3V

GND

100ms WATCHDOG

LTC695-3.3

GND

OSC SEL

OSC IN

FLOATING OR HIGH

694/5-3.3 F12

OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND when OSC SEL is forced low. In these configurations, the nominal reset active time and watchdog time-out period are determined by the number of clocks or set by the formula in Table 2. When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 140ms minimum for the LTC695-3.3. OSC IN selects between the 1 second and 70ms minimum normal watchdog time-out periods. In both cases, the time-out period immediately after a reset is at least 1 second.

Page 14

LTC694-3.3/LTC695-3.3

PPLICATI

Table 2. LTC695-3.3 Reset Active Time and Watchdog Time-Out Selections

OSC SEL OSC IN (Short Period) (Long Period) LTC695-3.3

Low External Clock Input 1024 CLKs 4096 CLKs 2048 CLKs Low External Capacitor* Floating or High Low 100ms 1.6 sec 200ms

Floating or High Floating or High 1.6 sec 1.6 sec 200ms *The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is f

I FOR ATIO

Push-Button Reset

The LTC694-3.3/LTC695-3.3 do not provide a logic input for direct connection to a push-button. However, a pushbutton in series with a 100Ω resistor connected to the RESET output pin (Figure 13) provides an alternative for manual reset. Connecting a 0.1µ F capacitor to the RESET pin debounces the push-button input.

NORMAL AFTER RESET

400ms

70pF

WATCHDOG TIME-OUT PERIOD RESET ACTIVE TIME

IMMEDIATELY

• C

1.6 sec

• C

70pF

(Hz) =

OSC

3.3V

Figure 13. The External Push-Button Reset

LTC694-3.3 LTC695-3.3

GND

RESET

184,000

C(pF) • 1025

0.1µF

100Ω

800ms

• C

70pF

RESET

MPU

(e.g. 68HC05)

694/5-3.3 F13

The 100Ω resistor in series with the push-button is required to prevent the ringing, due to the capacitance and lead inductance, from pulling the RESET pins of the MPU and LTC69X below ground.

PPLICATITYPICAL

Capacitor Back-Up with 74HC4016 Switch

R1 10k

R2 30k

74HC4016

3.3V

0.1µF

14121110

100µF

LTC695-3.3

BATT

LOW LINE

GND

OUT

0.1µF

694/5-3.3 TA03

Page 15

PACKAGE DESCRIPTIO

N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)

0.300 – 0.325

(7.620 – 8.255)

LTC694-3.3/LTC695-3.3

Dimensions in inches (millimeters) unless otherwise noted.

0.400* (10.160)

0.045 – 0.065

(1.143 – 1.651)

0.130 ± 0.005

(3.302 ± 0.127)

MAX

876

0.065

(1.651)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015 +0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

TYP

0.100 ± 0.010

(2.540 ± 0.254)

S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610)

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0.016 – 0.050

0.406 – 1.270

0°– 8° TYP

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)

0.300 – 0.325

(7.620 – 8.255)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015

+0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

0.020

(0.508)

MIN

0.130 ± 0.005

(3.302 ± 0.127)

0.125

(3.175)

MIN

0.100 ± 0.010

(2.540 ± 0.254)

0.045 – 0.065

(1.143 – 1.651)

0.125

(3.175)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

(0.101 – 0.254)

0.050

(1.270)

0.018 ± 0.003

(0.457 ± 0.076)

0.020

(0.508)

MIN

0.004 – 0.010

TYP

0.065

(1.651)

TYP

0.255 ± 0.015* (6.477 ± 0.381)

0.228 – 0.244

(5.791 – 6.197)

0.255 ± 0.015* (6.477 ± 0.381)

1234

0.189 – 0.197* (4.801 – 5.004)

0.150 – 0.157**

0.770*

(19.558)

MAX

N8 1197

(3.810 – 3.988)

SO8 0996

910

N16 1197

SW Package 16-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620)

0.291 – 0.299** (7.391 – 7.595)

0° – 8° TYP

0.093 – 0.104

(2.362 – 2.642)

0.050

(1.270)

TYP

0.014 – 0.019

(0.356 – 0.482)

TYP

0.010 – 0.029

(0.254 – 0.737)

0.009 – 0.013

(0.229 – 0.330)

NOTE:

1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

NOTE 1

× 45°

0.016 – 0.050

(0.406 – 1.270)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

0.037 – 0.045

(0.940 – 1.143)

0.004 – 0.012

(0.102 – 0.305)

NOTE 1

0.398 – 0.413*

(10.109 – 10.490)

15 1413121110 9

2345678

0.394 – 0.419

(10.007 – 10.643)

S16 (WIDE) 0396

Page 16

LTC694-3.3/LTC695-3.3

PPLICATITYPICAL

Write Protect for Additional RAMs

3.3V

0.1µF

2.4V

BATT

LTC695-3.3

CE OUT

LOW LINE

GND

OUT

CE IN

10µF

30ns PROPAGATION DELAY CS A

0.1µF

CS B

0.1µF

CS C

OPTIONAL CONNECTION FOR ADDITIONAL RAMs

LH5168SH

RAM A

LH5116S

RAM B

CS1 CS2

LH5116S

RAM C

CS1 CS2

694/5-3.3 TA04

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1326 Micropower Precision Triple Supply Monitor 4.725V, 3.118V, 1V Thresholds (±0.75%) LTC1536 Micropower Triple Supply Monitor for PCI Applications Meets PCI t

Linear T echnolog y Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear-tech.com

Timing Specifications

FAIL

69453fa LT/TP 0399 2K REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1993