Datasheet LTC695, LTC691, LTC690, LTC694 Datasheet (Linear Technology)

SUPPLY VOLTAGE (V)

0

RESET OUTPUT VOLTAGE (V)

3

4

5

4

2

1

0

1

2

3

5

TA = 25°C
EXTERNAL PULL-UP = 10µA
V

BATT

= 0V

690 TA02

FEATURES

■

UL Recognized File # E145770

■

Guaranteed

■

1.5mA Maximum Supply Current

■

Fast (35ns Max) Onboard Gating of RAM Chip

®

Reset Assertion at VCC = 1V

Enable Signals

■

SO-8 and S16 Packaging

■

4.65V Precision Voltage Monitor

■

Power OK/Reset Time Delay: 50ms, 200ms
or Adjustable

■

Minimum External Component Count

■

1µA Maximum Standby Current

■

Voltage Monitor for Power-Fail
or Low-Battery Warning

■

Thermal Limiting

■

Performance Specified Over Temperature

■

Superior Upgrade for MAX690 Family

U

APPLICATIO S

■

Critical µ P Power Monitoring

■

Intelligent Instruments

■

Battery-Powered Computers and Controllers

■

Automotive Systems

LTC690/LTC691

LTC694/LTC695

Microprocessor

Supervisory Circuits

U

DESCRIPTIO

The LTC®690 family provides complete power supply
monitoring and battery control functions for microproces­sor reset, battery back-up, CMOS RAM write protection,
power failure warning and watchdog timing. A precise
internal voltage reference and comparator circuit monitor
the power supply line. When an out-of-tolerance condition
occurs, the reset outputs are forced to active states and the
chip enable output unconditionally write-protects external
memory. In addition, the RESET output is guaranteed to
remain logic low even with VCC as low as 1V.

The LTC690 family powers the active CMOS RAMs with a
charge pumped NMOS power switch to achieve low drop­out and low supply current. When primary power is lost,
auxiliary power, connected to the battery input pin, powers
the RAMs in standby through an efficient PMOS switch.

For an early warning of impending power failure, the
LTC690 family provides an internal comparator with a
user-defined threshold. An internal watchdog timer is also
available, which forces the reset pins to active states when
the watchdog input is not toggled prior to a preset time-out
period.

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO

≥ 7.5V

V

IN

10µF

51k

10k

MICROPROCESSOR RESET, BATTERY BACK-UP, POWER FAILURE
WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP
FOR MICROPROCESSOR SYSTEMS

LT®1086-5

V

IN

ADJ

U

RESET Output Voltage vs

Supply Voltage

5V

V

OUT

++

100µF

0.1µF

3V

V

CC

LTC690/LTC691
LTC694/LTC695

V

BATT

RESET

PFI

GND

V

OUT

PFO

WDI

0.1µF

0.1µF

POWER TO
CMOS RAM

µP RESET
µP NMI

I/O LINE

100Ω

µP

SYSTEM

µP

POWER

690 TA01

1

LTC690/LTC691
LTC694/LTC695

A

W

O

LUTEXI T

S

A

WUW

ARB

I

Terminal Voltage

VCC.................................................... –0.3V to 6.0V

V

................................................ –0.3V to 6.0V

BATT

All Other Inputs.................. –0.3V to (V

OUT

Input Current

VCC.............................................................. 200mA

V

............................................................ 50mA

BATT

GND .............................................................. 20mA

WU

/

PACKAGE

V

BATT

V

OUT

V

CC

GND

BATT ON

LOW LINE

OSC IN

OSC SEL

T

JMAX

O

RDER I FOR ATIO

TOP VIEW

1
2

3
4
5
6
7
8

N PACKAGE

16-LEAD PDIP

= 110°C, θJA = 130°C/W

16
15
14
13

12
11
10

9

RESET
RESET
WDO
CE IN
CE OUT

WDI
PFO
PFI

ORDER PART

NUMBER

LTC691CN
LTC691IN
LTC695CN
LTC695IN

U
G

S

(Notes 1 and 2)

+ 0.3V)

V

Output Current................. Short-Circuit Protected

OUT

Power Dissipation............................................. 500mW

Operating Temperature Range

LTC690/91/94/95C............................... 0°C to 70°C

LTC690/91/94/95I........................... –40°C to 85°C

LTC690M ...................................... –55°C to 125°C

Storage Temperature Range................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec.)................ 300°C

U

(Note 3)

TOP VIEW

1

V

BATT

2

V

OUT

3

V

CC

4

GND

5

BATT ON

LOW LINE

T

= 110°C, θJA = 130°C/W Conditions: PCB mount on

JMAX

FR4 Material, Still Air at 25°C, Copper Trace

6
7

OSC IN

8

OSC SEL

16-LEAD WIDE PLASTIC SO

SW PACKAGE

16
15
14
13
12
11
10

9

RESET
RESET
WDO
CE IN
CE OUT
WDI
PFO
PFI

ORDER PART

NUMBER

LTC691CSW
LTC691ISW
LTC695CSW
LTC695ISW

TOP VIEW

V

1

OUT

2

V

CC

3

GND

45

PFI

J8 PACKAGE

8-LEAD CERDIP

T

= 110°C, θJA = 100°C/W (J8)

JMAX

T

= 110°C, θJA = 130°C/W (N8)

JMAX

8
7
6

N8 PACKAGE
8-LEAD PDIP

V

BATT

RESET

WDI

PFO

LTC690CN8
LTC690IN8
LTC690MJ8
LTC694CN8
LTC694IN8

TOP VIEW

V

1

OUT

V

2

CC

GND

3
4

PFI

S8 PACKAGE

8-LEAD PLASTIC SO

T

= 110°C, θJA = 180°C/W Conditions: PCB Mount on

JMAX

FR4 Material, Still Air AT 25°C, Copper Trace

8

V

BATT

7

RESET

6

WDI

5

PFO

LTC690CS8
LTC690IS8
LTC694CS8
LTC694IS8

S8 PART

MARKING

690
690I

U

PRODUCT SELECTIO GUIDE

CONDITIONAL

PINS RESET TIMER BACK-UP WARNING PROTECT RESET BACK-UP
LTC690 8 X X X X
LTC691 16 X X X X X
LTC694 8 X X X X
LTC695 16 X X X X X

LTC699 8 X X
LTC1232 8 X X X
LTC1235 16 X X X X X X X

WATCHDOG BATTERY POWER-FAIL RAM WRITE PUSH-BUTTON BATTERY

694
694I

2

LTC690/LTC691

LTC694/LTC695

LECTRICAL C CHARA TERIST

E

range, otherwise specifications are at TA = 25°C. VCC = full operating range, V

PARAMETER CONDITONS MIN TYP MAX UNITS
Battery Back-Up Switching

Operating Voltage Range V

V

Output Voltage I

OUT

V

in Battery Back-Up Mode I

OUT

Supply Current (Exclude I

Supply Current in Battery Back-Up Mode VCC = 0V, V

Battery Standby Current (+ = Discharge, – = Charge) 5.5 > VCC > V

Battery Switchover Threshold, VCC – V

Battery Switchover Hysteresis 20 mV
BATT ON Output Voltage (Note 4) I
BATT ON Output Short-Circuit Current (Note 4) BATT ON = V

Reset and Watchdog Timer

Reset Voltage Threshold ● 4.5 4.65 4.75 V

Reset Threshold Hysteresis 40 mV
Reset Active Time (LTC690/91) (Note 5) OSC SEL HIGH, VCC = 5V 40 50 60 ms

Reset Active Time (LTC694/95) (Note 5) OSC SEL HIGH, VCC = 5V 160 200 240 ms

Watchdog Time-Out Period, Internal Oscillator Long Period, VCC = 5V 1.2 1.6 2.00 sec

Watchdog Time-Out Period, External Clock (Note 6) Long Period 4032 4097 Clock

Reset Active Time PSRR 1 ms/V
Watchdog Time-Out Period PSRR, Internal OSC 1 ms/V
Minimum WDI Input Pulse Width VIL = 0.4V, VIH = 3.5V ● 200 ns
RESET Output Voltage at VCC = 1V I
RESET and LOW LINE Output Voltage (Note 4) I

RESET and WDO Output Voltage (Note 4) I

)I

OUT

BATT

ICS

CC

V

BATT

OUT

I

OUT
OUT
OUT

Power Up 70 mV
Power Down 50 mV

SINK

BATT ON = 0V Source Current 0.5 1 25 µA

LTC690M ● 4.4 4.65 4.75 V

Short Period, VCC = 5V 80 100 120 ms

Short Period 960 1025 Cycles

SINK
SINK

I

SOURCE
SINK

I

SOURCE

The ● denotes specifications which apply over the operating temperature

= 2.8V, unless otherwise noted.

BATT

4.75 5.50 V

2.00 4.25 V

= 1mA V

● V

= 50mA VCC – 0.50 VCC – 0.250 V
= 250µA, VCC < V
≤ 50mA 0.6 1.5 mA

BATT

BATT

= 3.2mA 0.4 V

OUT

= 10µA, VCC = 1V 4 200 mV
= 1.6mA, VCC = 4.25V 0.4 V

= 1µA, VCC = 5V 3.5 V

= 1.6mA, VCC = 5V 0.4 V

= 1µA, VCC = 4.25V 3.5 V

BATT

● 0.6 2.5 mA

= 2.8V 0.04 1 µA

● 0.04 5 µA

+ 0.2V –0.1 +0.02 µA

● –1.0 +0.10 µA

Sink Current 35 m

● 35 50 70 ms

● 140 200 280 ms

● 1.0 1.6 2.25 sec

● 70 100 140 ms

– 0.05 V

CC

– 0.10 VCC – 0.005 V

CC

V

– 0.1 V

BATT

– 0.005 V

CC

– 0.02 V

BATT

3

LTC690/LTC691
LTC694/LTC695

LECTRICAL C CHARA TERIST

E

ICS

range, otherwise specifications are at TA = 25°C. VCC = full operating range, V

PARAMETER CONDITONS MIN TYP MAX UNITS

RESET, RESET, WDO, LOW LINE Output Source Current 1 3 25 µA
Output Short-Circuit Current (Note 4)

WDI Input Threshold Logic Low 0.8 V

WDI Input Current WDI = V

Power-Fail Detector

PFI Input Threshold VCC = 5V ● 1.25 1.3 1.35 V
PFI Input Threshold PSRR 0.3 mV/V
PFI Input Current ±0.01 ±25 nA
PFO Output Voltage (Note 4) I

PFO Short-Circuit Source Current (Note 4) PFI = HIGH, PFO = 0V 1 3 25 µA

PFI Comparator Response Time (Falling) ∆VIN = –20mV, VOD = 15mV 2 µs
PFI Comparator Response Time (Rising) (Note 4) ∆VIN = 20mV, VOD = 15mV 40 µs

Chip Enable Gating

CE IN Threshold V

CE IN Pull-Up Current (Note 7) 3 µA
CE OUT Output Voltage I

CE Propagation Delay VCC = 5V, CL = 20pF 20 35 ns

CE OUT Output Short-Circuit Current Output Source Current 30 mA

Oscillator

OSC IN Input Current (Note 7) ±2 µA
OSC SEL Input Pull-Up Current (Note 7) 5 µA
OSC IN Frequency Range OSC SEL = 0V ● 0 250 kHz
OSC IN Frequency with External Capacitor OSC SEL = 0V, C

Output Sink Current 25 mA

Logic High 3.5

WDI = 0V

SINK

I

SOURCE

PFI = LOW, PFO = V

with 10kΩ Pull-Up 8

IL

V

IH

SINK

I

SOURCE

I

SOURCE

Output Sink Current 35

The ● denotes specifications which apply over the operating temperature

= 2.8V, unless otherwise noted.

BATT

OUT

= 3.2mA 0.4 V

= 1µA 3.5

OUT

= 3.2mA 0.4 V

= 3.0mA V
= 1µA, VCC = 0V V

= 47pF 4 kHz

OSC

● 450µA

● –50 –8

25 mA

0.8 V

2.0

– 1.50

OUT

– 0.05

OUT

● 20 45

Note 1: Absolute Maximum Ratings are those values beyond which the life
of device may be impaired.

Note 2: All voltage values are with respect to GND.
Note 3: For military temperature range parts or for the LTC692 and

LTC693, consult the factory.
Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and

RESET have weak internal pull-ups of typically 3µA. However, external
pull-up resistors may be used when higher speed is required.

Note 5: The LTC690 and LTC691 have minimum reset active time of 35ms
(50ms typically) while the LTC694 and LTC695 have longer minimum

4

reset active time of 140ms (200ms typically). The reset active time of the
LTC691 and LTC695 can be adjusted (see Table 2 in Applications
Information section).

Note 6: The external clock feeding into the circuit passes through the
oscillator before clocking the watchdog timer (See Block Diagram).
Variation in the time-out period is caused by phase errors which occur
when the oscillator divides the external clock by 64. The resulting variation
in the time-out period is 64 clocks plus one clock of jitter.

Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal
pullups which pull to the supply when the input pins are floating.

BLOCK

LTC690/LTC691

LTC694/LTC695

W

IDAGRA

V

BATT

V

CE IN

PFI

OSC IN

OSC SEL

WDI

M2

CC

–

C2

+

+

C1

–

1.3V

GND

–

C3

+

OSC

TRANSITION

DETECTOR

RESET PULSE

GENERATOR

WATCHDOG

M1

CHARGE

PUMP

TIMER

V

OUT

BATT ON

LOW LINE

CE OUT

PFO

RESET

RESET

WDO

690 BD

UU

U

PI FU CTIO S

VCC: 5V Supply Input. The VCC pin should be bypassed
with a 0.1µF capacitor.

V

: Voltage Output for Backed Up Memory. Bypass with

OUT

a capacitor of 0.1µF or greater. During normal operation,
V

obtains power from VCC through an NMOS power

OUT

switch, M1, which can deliver up to 50mA and has a typical
on resistance of 5Ω. When VCC is lower than V
is internally switched to V
used, connect V

V

: Back-Up Battery Input. When VCC falls below V

BATT

OUT

to VCC.

auxiliary power, connected to V

BATT

. If V

BATT

and V

OUT

, is delivered to V
through PMOS switch, M2. If back-up battery or auxiliary
power is not used, V

should be connected to GND.

BATT

BATT

BATT

, V

OUT

are not

BATT

OUT

,

GND: Ground pin.
BATT ON: Battery On Logic Output from Comparator C2.

BATT ON goes low when V

is internally connected to

OUT

VCC. The output typically sinks 35mA and can provide base
drive for an external PNP transistor to increase the output
current above the 50mA rating of V
high when V

is internally switched to V

OUT

. BATT ON goes

OUT

.

BATT

PFI: Power Failure Input. PFI is the noninverting input to
the power-fail comparator, C3. The inverting input is
internally connected to a 1.3V reference. The power failure
output remains high when PFI is above 1.3V and goes low
when PFI is below 1.3V. Connect PFI to GND or V

OUT

when

C3 is not used.

5

LTC690/LTC691
LTC694/LTC695

UU

U

PI FU CTIO S

PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below

1.3V. When VCC is lower than V
PFO is forced low.

RESET: Logic Output for µ P Reset Control. Whenever V
falls below either the reset voltage threshold (4.65V,
typically) or V
returns to 5V, reset pulse generator forces RESET to
remain active low for a minimum of 35ms for the LTC690
/LTC691 (140ms for the LTC694/LTC695). When the
watchdog timer is enabled but not serviced prior to a
preset time-out period, reset pulse generator also forces
RESET to active low for a minimum of 35ms for the
LTC690/LTC691 (140ms for the LTC694/5) for every
preset time-out period (see Figure 11). The reset active
time is adjustable on the LTC691/LTC695. An external
push-button reset can be used in connection with the
RESET output. See Push-Button Reset in Applications
Information section.

RESET: RESET is an active high logic ouput. It is the
inverse of RESET.

LOW LINE: Logic Output from Comparator C1. LOW LINE
indicates a low line condition at the VCC input. When V
falls below the reset voltage threshold (4.65V typically),
LOW LINE goes low. As soon as VCC rises above the reset
voltage threshold, LOW LINE returns high (see Figure 1).
LOW LINE goes low when V
Table 1).

WDI: Watchdog Input, WDI, is a three level input. Driving
WDI either high or low for longer than the watchdog time­out period, forces both RESET and WDO low. Floating WDI
disables the watchdog timer. The timer resets itself with
each transition of the watchdog input (see Figure 11).

, RESET goes active low. After V

BATT

, C3 is shut down and

BATT

drops below V

CC

BATT

CC

CC

CC

(see

WDO: Watchdog Logic Output. When the watchdog input
remains either high or low for longer than the watchdog
time-out period, WDO goes low. WDO is set high whenever
there is a transition on the WDI pin, or LOW LINE goes low.
The watchdog timer can be disabled by floating WDI (see
Figure 11).

CE IN: Logic input to the Chip Enable gating circuit. CE IN
can be derived from microprocessor’s address line and/or
decoder output. See Applications Information section and
Figure 5 for additional information.

CE OUT: Logic Output on the Chip Enable Gating Circuit.
When VCC is above the reset voltage threshold, CE OUT is
a buffered replica of CE IN. When VCC is below the reset
voltage threshold CE OUT is forced high (see Figure 5).

OSC SEL: Oscillator Selection Input. When OSC SEL is
high or floating, the internal oscillator sets the reset active
time and watchdog time-out period. Forcing OSC SEL low,
allows OSC IN be driven from an external clock signal or
external capacitor be connected between OSC IN and
GND.

OSC IN: Oscillator Input. OSC IN can be driven by an
external clock signal or external capacitor can be connected
between OSC IN and GND when OSC SEL is forced low. In
this configuration the nominal reset active time and
watchdog time-out period are determined by the number
of clocks or set by the formula (see Applications Information
section). When OSC SEL is high or floating, the internal
oscillator is enabled and the reset active time is fixed at
50ms typical for the LTC691 and 200ms typical for the
LTC695. OSC IN selects between the 1.6 seconds and
100ms typical watchdog time-out periods. In both cases,
the time-out period immediately after a reset is 1.6 seconds
typical.

6

LPER

TEMPERATURE (°C)

–50

RESET VOLTAGE THRESHOLD (V)

4.64

4.65

4.66

25 75

690 G06

4.63

4.62

–25 0

50 100 125

4.61

4.60

V

vs I

OUT

5.00

4.95

4.90

4.85

OUTPUT VOLTAGE (V)

4.80

OUT

R

F

O

SLOPE = 5Ω

VCC = 5V

= 2.8V

V

BATT

= 25°C

T

A

ATYPICA

UW

CCH ARA TERIST

E

C

V

vs I

OUT

2.80

2.78

2.76

OUTPUT VOLTAGE (V)

2.74

OUT

ICS

VCC = 0V
V

BATT

= 25°C

T

A

SLOPE = 125Ω

= 2.8V

LTC690/LTC691

LTC694/LTC695

Power Failure Input Threshold
vs Temperature

1.308
VCC = 5V

1.306

1.304

1.302

1.300

1.298

PFI INPUT THRESHOLD (V)

1.296

4.75
10

0

20

LOAD CURRENT (mA)

Reset Active Time
vs Temperature LTC690-1

58

VCC = 5V

56

54

52

50

RESET ACTIVE TIME

48

46

–50

–25 0

25 75

TEMPERATURE (°C)

Power-Fail Comparator
Response Time

6
5
4
3
2

1

PFO OUTPUT VOLTAGE (V)

0

1.305V

1.285V

0

123

V

= 20mV STEP

PFI

30

50 100 125

V

+

PFI

PFO

–

1.3V

4

5

6

TIME (µs)

40

690 G01

690 G04

VCC = 5V

= 25°C

T

A

30pF

87

690 G07

50

2.72
100

0

200

LOAD CURRENT (µA)

Reset Active Time
vs Temperature LTC694-5

232

VCC = 5V

224

216

208

200

RESET ACTIVE TIME

192

184

–50

–25 0

TEMPERATURE (°C)

Power-Fail Comparator
Response Time

6

VCC = 5V

5

= 25°C

T

A

4
3
2

1

PFO OUTPUT VOLTAGE (V)

0

1.315V

1.295V

V

= 20mV STEP

PFI

0

40

20

300

50 100 125

25 75

V

+

PFI

PFO

–

1.3V

60

10080

TIME (µs)

120

400

140

690 G02

690 G05

30pF

690 G08

500

180160

1.294
–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

Reset Voltage Threshold
vs Temperature

Power-Fail Comparator Response
Time with Pull-Up Resistor

6

VCC = 5V

5

= 25˚C

T

A

4
3
2

1

PFO OUTPUT VOLTAGE (V)

0

1.315V

1.295V

0

2

V

= 20mV STEP

PFI

6

4

V

PFI

1.3V

TIME (µs)

+
–

108

PFO

690 G03

5V

10k

30pF

14

12

1816

690 G09

7

LTC690/LTC691
LTC694/LTC695

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

Microprocessor Reset

The LTC690 family uses a bandgap voltage reference and
a precision voltage comparator C1 to monitor the 5V
supply input on VCC (see Block Diagram). When VCC falls
below the reset voltage threshold, the RESET output is
forced to active low state. The reset voltage threshold
accounts for a 5% variation on VCC, so the RESET output
becomes active low when VCC falls below 4.75V (4.65V
typical). On power-up, the RESET signal is held active low
for a minimum of 35ms for the LTC690/LTC691 (140ms
for the LTC694/LTC695) after reset voltage threshold is
reached to allow the power supply and microprocessor to
stabilize. The reset active time is adjustable on the LTC691/
LTC695. On power-down, the RESET signal remains ac­tive low even with VCC as low as 1V. This capability helps
hold the microprocessor in stable shutdown condition.
Figure 1 shows the timing diagram of the RESET signal.

The precision voltage comparator, C1, typically has 40mV
of hysteresis which ensures that glitches at VCC pin do not
activate the RESET output. Response time is typically
10µs. To help prevent mistriggering due to transient loads,
VCC pin should be bypassed with a 0.1µ F capacitor with the
leads trimmed as short as possible.

The LTC691 and LTC695 have two additional outputs:
RESET and LOW LINE. RESET is an active high output and
is the inverse of RESET. LOW LINE is the output of the
precision voltage comparator C1. When VCC falls below

the reset voltage threshold, LOW LINE goes low. LOW
LINE returns high as soon as VCC rises above the reset
voltage threshold.

Battery Switchover

The battery switchover circuit compares VCC to the V
input, and connects V
VCC rises to 70mV above V
comparator, C2, connects V

to whichever is higher. When

OUT

, the battery switchover

BATT

to VCC through a charge

OUT

BATT

pumped NMOS power switch, M1. When VCC falls to
50mV above V

, C2 connects V

BATT

OUT

to V

through a

BATT

PMOS switch, M2. C2 has typically 20mV of hysteresis to
prevent spurious switching when VCC remains nearly
equal to V

. The response time of C2 is approximately

BATT

20µ s.
During normal operation, the LTC690 family uses a charge

pumped NMOS power switch to achieve low dropout and
low supply current. This power switch can deliver up to
50mA to V
5Ω. The V

from VCC and has a typical on resistance of

OUT

pin should be bypassed with a capacitor of

OUT

0.1µ F or greater to ensure stability. Use of a larger bypass
capacitor is advantageous for supplying current to heavy
transient loads.

When operating currents larger than 50mA are required
from V

, or a lower dropout (VCC-V

OUT

voltage differen-

OUT

tial) is desired, the LTC691 and LTC695 should be used.
These products provide BATT ON output to drive the base

8

V

RESET

LOW LINE

CC

V2

t

1

Figure 1. Reset Active Time

V1

V2

V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS

t

1

t1 = RESET ACTIVE TIME

V1

690 F01

LTC690/LTC691

F

F

LTC694/LTC695

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

of external PNP transistor (Figure 2). If higher currents are
needed with the LTC690 and LTC694, a high current
Schottky diode can be connected from the VCC pin to the
V

pin to supply the extra current.

OUT

ANY PNP POWER TRANSISTOR

5

BATT ON

5V

0.1µF

Figure 2. Using BATT ON to Drive External PNP Transistor

3

V

CC

LTC691
LTC695

1

V

BATT

3V

GND

2

V

OUT

0.1µ

4

690 F02

The LTC690 family is protected for safe area operation
with short-circuit limit. Output current is limited to ap­proximately 200mA. If the device is overloaded for long
period of time, thermal shutdown turns the power switch
off until the device cools down. The threshhold tempera­ture for thermal shutdown is approximately 155°C with
about 10°C of hysteresis which prevents the device from
oscillating in and out of shutdown.

The PNP switch used in competitive devices was not
chosen for the internal power switch because it injects
unwanted current into the substrate. This current is col­lected by the V

pin in competitive devices and adds to

BATT

the charging current of the battery which can damage
lithium batteries. The LTC690 family uses a charge pumped
NMOS power switch to eliminate unwanted charging
current while achieving low dropout and low supply cur­rent. Since no current goes to the substrate, the current
collected by V

A 125Ω PMOS switch connects the V

pin is strictly junction leakage.

BATT

BATT

input to V

OUT

in
battery back-up mode. The switch is designed for very low
dropout voltage (input-to-output differential). This feature
is advantageous for low current applications such as
battery back-up in CMOS RAM and other low power CMOS
circuitry. The supply current in battery back-up mode is
1µA maximum.

The operating voltage at the V

4.25V. High value capacitors, such as electrolytic or farad-

pin ranges from 2.0V to

BATT

size double layer capacitors, can be used for short term
memory back-up instead of a battery. The charging resis­tor for both capacitors and rechargeable batteries should
be connected to V
path that exists when the resistor is connected to V

since this eliminates the discharge

OUT

CC

(Figure 3).

V

– V

OUT

CC

BATT

R

R

LTC690
LTC691
LTC694
LTC695

GND

V

BATT

OUT

0.1µ

690 F03

OUT

I =

5V

0.1µF

3V

Figure 3. Charging External Battery Through V

V

V

Replacing the Back-Up Battery

When changing the back-up battery with system power
on, spurious resets can occur while battery is removed
due to battery standby current. Although battery standby
current is only a tiny leakage current, it can still charge up
the stray capacitance on the V
cycle is as follows: When V

BATT

VCC, the LTC690 switches to battery back-up. V
V

low and the device goes back to normal operation.

BATT

The leakage current then charges up the V

pin. The oscillation

BATT

reaches within 50mV of

pulls

OUT

pin again

BATT

and the cycle repeats.
If spurious resets during battery replacement pose no

problems, then no action is required. Otherwise, a resistor
from V

to GND will hold the pin low while changing the

BATT

battery. For example, the battery standby current is 1µA
maximum over temperature and the external resistor
required to hold V

V –50mV

CC

R

≤

1A

µ

below VCC is:

BATT

With VCC = 4.5V, a 4.3M resistor will work. With a 3V
battery, this resistor will draw only 0.7µA from the battery,
which is negligible in most cases.

9

LTC690/LTC691
LTC694/LTC695

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

If battery connections are made through long wires, a 10Ω
to 100Ω series resistor and a 0.1µ F capacitor are recom­mended to prevent any overshoot beyond VCC due to the
lead inductance (Figure 4).

10Ω

4.3M

Figure 4. 10Ω/0.1µF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement

0.1µF

V

BATT

LTC690
LTC691
LTC694
LTC695

GND

690 F04

Table 1 shows the state of each pin during battery back-up.
When the battery switchover section is not used, connect
V

to GND and V

BATT

OUT

to VCC.

Memory Protection

The LTC691 and LTC695 include memory protection
circuitry that ensures the integrity of the data in memory
by preventing write operations when VCC is at invalid level.
Two additional pins, CE IN and CE OUT, control the Chip
Enable or Write inputs of CMOS RAM. When VCC is 5V, CE
OUT follows CE IN with a typical propagation delay of
20ns. When VCC falls below the reset voltage threshold or
V

, CE OUT is forced high, independent of CE IN. CE

BATT

OUT is an alternative signal to drive the CE, CS, or Write
input of battery-backed up CMOS RAM. CE OUT can also
be used to drive the Store or Write input of an EEPROM,
EAROM or NOVRAM to achieve similar protection. Figure
5 shows the timing diagram of CE IN and CE OUT.

CE IN can be derived from the microprocessor’s address
decoder output. Figure 6 shows a typical nonvolatile
CMOS RAM application.

Memory protection can also be achieved with the LTC690
and LTC694 by using RESET as shown in Figure 7.

Table 1. Input and Output Status in Battery Back-Up Mode

SIGNAL STATUS

V

CC

V

OUT

V

BATT

BATT ON Logic high. The open-circuit output voltage is equal to V
PFI Power failure input is ignored.
PFO Logic low
RESET Logic low
RESET Logic high. The open-circuit output voltage is equal to V
LOW LINE Logic low
WDI Watchdog input is ignored.
WDO Logic high. The open-circuit output voltage is equal to V
CE IN Chip Enable Input is ignored.
CE OUT Logic high. The open-circuit output voltage is equal to V
OSC IN OSC IN is ignored.
OSC SEL OSC SEL is ignored.

C2 monitors VCC for active switchover.
V

is connected to V

OUT

The supply current is 1µA maximum.

through an internal PMOS switch.

BATT

OUT

OUT

OUT

OUT

.

.

.

.

10

V

CE IN

CE OUT

V2

CC

V

= V

OUT

BATT

Figure 5. Timing Diagram for CE IN and CE OUT

V1

V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS

= V

V

OUT

BATT

690 F05

LTC690/LTC691

V =1.3V 1+

R1R2R1

R3

H

+











LTC694/LTC695

PPLICATI

A

5V

0.1µF

3V

V

V

CC

BATT

GND

LTC691
LTC695

CE OUT

O

V

OUT

CE IN

RESET
RESET

U

S

I FOR ATIO

+

10µF

20ns PROPAGATION DELAY

FROM DECODER

TO µP

WU

0.1µF

Figure 6. A Typical Nonvolatile CMOS RAM Application

5V

0.1µF

3V

V

V

CC

LTC690
LTC694

BATT

GND

V

OUT

RESET

+

10µF

0.1µF

CS

Figure 7. Write Protect for RAM with LTC690 or LTC694

V

IN

≥ 7.5V

10µF
R1

51k

R2
10k

LT1086-5

V

INVOUT

ADJ

++

100µF

300k

Figure 8. Monitoring

5V

0.1µF

R4

R3

10k

Unregulated

V

LTC690/LTC691
LTC694/LTC695

PFO
PFI

TO µP

DC Supply

with the LTC690's Power-Fail Comparator

V

≥ 6.5V

IN

+ +

LT1086-5

V

V

OUT

IN

10µF

ADJ

Figure 9. Monitoring

10µF

5V

R4

R1

10k

27k

R3

2.7M

R2

8.2k
R5

3.3k

Regulated

V

0.1µF
LTC690/LTC691

LTC694/LTC695

PFO
PFI

TO µP

DC Supply

with the LTC690's Power-Fail Comparator

V

CC

62512

CS

V

CC

CS1
CS2

CC

GND

CC

U

RAM

GND

690 F06

62128

RAM

GND

690 F07

690 F08

GND

1690 F09

Power-Fail Warning

The LTC690 family generates a Power Failure Output
(PFO) for early warning of failure in the microprocessor's
power supply. This is accomplished by comparing the
Power Failure Input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than

1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 5V output. The voltage
divider ratio can be chosen such that the voltage at the PFI
pin falls below 1.3V several milliseconds before the 5V
supply falls below the maximum reset voltage threshold

4.75V. PFO is normally used to interrupt the microproces­sor to execute shutdown procedure between PFO and
RESET or RESET.

The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resis­tor between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:

When PFO output is low, R3 sinks current from the
summing junction at the PFI pin.

When PFO output is high, the series combination of R3 and
R4 source current into the PFI summing junction.



R1

V 1.3V 1

=+

L





Assuming R4 R3,V 5V

(5V –1.3V)R1

–

R2

1.3V(R3 R4)

<< =

HYSTERESIS




+



R1

R3

Example 1: The circuit in Figure 8 demonstrates the use of
the power-fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
supply input VIN is 100mV/ms and the total time to execute
a shutdown procedure is 8ms. Also the noise of VIN is
200mV. With these assumptions in mind, we can reason­ably set VL = 7.5V which 1.25V greater than the sum of
maximum reset voltage threshold and the dropout voltage

11

LTC690/LTC691

3V

5V

690 F10

R1
1M

R

L

20K

R2
1M

OPTIONAL TEST LOAD

LOW-BATTERY SIGNAL
TO µP I/O PIN

I/O PIN

V

CC

V

BATT

GND

PFI

LTC691
LTC695

CE IN

PFO

CE OUT

LTC694/LTC695

U

O

PPLICATI

A

S

I FOR ATIO

of LT1086-5 (4.75V + 1.5V) and V

V5V

HYSTERESIS

R1

==

850V

R3

WU

HYSTERESIS

R3 ≈ 5.88 R1

Choose R3 = 300k and R1 = 51k. Also select R4 = 10k
which is much smaller than R3.

7.5V =1.3V 1+







(5V –1.3V)5151

kk

–

1 3 310

R2

Vk.( )






R2 = 9.7kΩ, Choose nearest 5% resistor 10k and recalcu­late VL,

V1.3V1

=+

L









V1.3V1

=++

H





(7.32V – 6.25V)

(5V –1.3V)51

51

kk

–

10k

51k
10k

10.7ms=

1.3V(310k



51k



300k



=



=

732



)



8.151V

100mV/ms

V

HYSTERESIS

= 8.151V – 7.32V = 831mV

The 10.7ms allows enough time to execute shutdown
procedure for microprocessor and 831mV of hysteresis
would prevent PFO from going low due to the noise of VIN.

Example 2: The circuit in Figure 9 can be used to measure
the regulated 5V supply to provide early warning of power
failure. Because of variations in the PFI threshold, this
circuit requires adjustment to ensure the PFI comparator
trips before the reset threshold is reached. Adjust R5 such
that the PFO output goes low when the VCC supply reaches
the desired level (e.g., 4.85V).

Monitoring the Status of the Battery

C3 can also monitor the status of the memory back-up
battery (Figure 10). If desired, the CE OUT can be used to
apply a test load to the battery. Since CE OUT is forced high
in battery back-up mode, the test load will not be applied
to the battery while it is in use, even if the microprocessor
is not powered.

U

= 850mV.

.V

Figure 10. Back-Up Battery Monitor with Optional Test Load

Watchdog Timer

The LTC690 family provides a watchdog timer function to
monitor the activity of the microprocessor. If the micro­processor does not toggle the Watchdog Input (WDI)
within a seleced time-out period, RESET is forced to active
low for a minimum of 35ms for the LTC690/LTC691
(140ms for the LTC694/LTC695). The reset active time is
adjustable on the LTC691/LTC695. Since many systems
can not service the watchdog timer immediately after a
reset, the LTC691 and LTC695 have longer time-out
period (1.0 second minimum) right after a reset is issued.
The normal time-out period (70ms minimum) becomes
effective following the first transition of WDI after RESET
is inactive. The watchdog time-out period is fixed at 1.0
second minimum on the LTC690 and LTC694. Figure 11
shows the timing diagram of watchdog time-out period
and reset active time. The watchdog time-out period is
restarted as soon as RESET is inactive. When either a high­to-low or low-to-high transition occurs at the WDI pin
prior to time-out, the watchdog time is reset and begins to
time out again. To ensure the watchdog time does not time
out, either a high-to-low or low-to-high transition on the
WDI pin must occur at or less than the minimum time-out
period. If the input to the WDI pin remains either high or
low, reset pulses will be issued every 1.6 seconds typi­cally. The watchdog time can be deactivated by floating the
WDI pin. The timer is also disabled when VCC falls below
the reset voltage threshold or V

BATT

.

12

LTC690/LTC691

LTC694/LTC695

PPLICATI

A

U

O

S

I FOR ATIO

WU

U

The LTC691 and LTC695 provide an additional output
(Watchdog Output, WDO) which goes low if the watchdog
timer is allowed to time out and remains low until set high
by the next transition on the WDI pin. WDO is also set high
when VCC falls below the reset voltage threshold or V

BATT

.

The LTC691 and LTC695 have two additonal pins OSC SEL
and OSC IN, which allow reset active time and watchdog
time-out period to be adjusted per Table 2. Several con­figurations are shown in Figure 12.

OSC IN can be driven by an external clock signal or an
external capacitor can be connected between OSC IN and

V

= 5V

CC

WDI

t1 = RESET ACTIVE TIME

= NORMAL WATCHDOG TIME-OUT PERIOD

t

WDO

2

= WATCHDOG TIME-OUT PERIOD IMMEDIATELY

t

3

AFTER A RESET

GND when OSC SEL is forced low. In these configurations,
the nominal reset active time and watchdog time-out
period are determined by the number of clocks or set by
the formula in Table 2. When OSC SEL is high or floating,
the internal oscillator is enabled and the reset active time
is fixed at 35ms minimum for the LTC691 and 140ms
minimum for the LTC695. OSC IN selectes between the 1
second and 70ms minimum normal watchdog time-out
periods. In both cases, the time-out period immediately
after a reset is at least 1 second.

RESET

t

1

Figure 11. Watchdog Time-Out Period and Reset Active Time

EXTERNAL CLOCK

3

5V

5V

V

CC

4

GND

INTERNAL OSCILLATOR

1.6 SECOND WATCHDOG

3

V

CC

4

GND

LTC691
LTC695

LTC691
LTC695

OSC SEL

OSC IN

OSC SEL

OSC IN

t

2

8

7

8

7

FLOATING
OR HIGH

FLOATING
OR HIGH

t

3

t

1

EXTERNAL OSCILLATOR

OSC IN

OSC IN

8

7

8

7

FLOATING
OR HIGH

3

5V

V

CC

4

GND

INTERNAL OSCILLATOR

100ms WATCHDOG

3

5V

V

CC

4

GND

OSC SEL

LTC691
LTC695

OSC SEL

LTC691
LTC695

690 F11

Figure 12. Oscillator Configurations

690 F12

13

LTC690/LTC691
LTC694/LTC695

U

O

PPLICATI

A

Table 2. LTC691 and LTC695 Reset Active Time and Watchdog Time-Out Selections

Low External Clock Input 1024 clks 4096 clks 512 clks 2048 clks
Low External Capacitor*

Floating or High Low 100ms 1.6 sec 50ms 200ms
Floating or High Floating or High 1.6 sec 1.6 sec 50ms 200ms

*The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is f

S

I FOR ATIO

OSC INOSC SEL

WU

U

WATCHDOG TIME-OUT PERIOD

NORMAL

(Short Period)

400ms

70pF

• C

IMMEDIATELY

AFTER RESET
(Long Period)

1.6 sec

• C

70pF

OSC

200ms

(Hz) =

RESET ACTIVE TIME

LTC691

• C

70pF

184,000

C(pF) • 1025

Push-Button Reset

The LTC690 family does not provide a logic input for direct
connection to a pushbutton. However, a push-button in
series with a 100Ω resistor connected to the RESET output
pin (Figure 13) provides an alternative for manual reset.
Connecting a 0.1µ F capacitor to the RESET pin debounces

5V

V

RESET

CC

LTC690/LTC691
LTC694/LTC695

GND

0.1µF

the push-button input.

100Ω

LTC695

800ms

70pF

RESET

MPU

(e.g. 6805)

• C

690 F13

The 100Ω resistor in series with the push-button is
required to prevent the ringing, due to the capacitance and
lead inductance, from pulling the RESET pins of the MPU
and LTC69X below ground.

If a dedicated pushbutton reset input is desired, the
LTC1235 is a good choice (Figure 14). It has all the
functions of the LTC695 and provides push-button reset
as an extra feature. Its push-button is internally debounced
and invokes the normal 200ms reset sequence. This
eliminates the need for the 100Ω resistor and 0.1µF
capacitor. It also provides a more consistent reset pulse.

Figure 13. The External Push-Button Reset

V

5V

Figure 14. The External Push-Button Reset with the LTC1235

CC

LTC1235

PBRST

GND

RESET

RESET

MPU

(e.g. 6805)

690 F14

14

PACKAGE DESCRIPTIO

J8 Package 8-Lead CERDIP (Narrow 0.300, Hermetic) (LTC DWG # 05-08-1110)

0.300 BSC

(0.762 BSC)

0.008 – 0.018

(0.203 – 0.457)

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS

0° – 15°

0.300 – 0.325

(7.620 – 8.255)

CORNER LEADS OPTION

0.045 – 0.068

(1.143 – 1.727)

FULL LEAD

OPTION

N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)

LTC690/LTC691

LTC694/LTC695

U

Dimensions in inches (millimeters) unless otherwise noted.

0.005

0.200
(0.127)

0.015 – 0.060

(5.080)

MAX

0.125

3.175

MIN

MIN

0.025

(0.635)

RAD TYP

876

87

12

(4 PLCS)

0.023 – 0.045

(0.584 – 1.143)

HALF LEAD

OPTION

0.045 – 0.068

(1.143 – 1.727)

0.014 – 0.026

(0.360 – 0.660)

0.045 – 0.065

(1.143 – 1.651)

(0.381 – 1.524)

0.100 ± 0.010

(2.540 ± 0.254)

0.130 ± 0.005

(3.302 ± 0.127)

0.400*

(10.160)

MAX

0.405

(10.287)

MAX

65

3

4

5

0.220 – 0.310

(5.588 – 7.874)

J8 1197

0.065

(1.651)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015

+0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

TYP

0.100 ± 0.010

(2.540 ± 0.254)

S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610)

0.010 – 0.020

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

*

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

× 45°

0.016 – 0.050

0.406 – 1.270

0°– 8° TYP

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)

0.300 – 0.325

(7.620 – 8.255)

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.325

–0.015

+0.889

8.255

()

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

0.020

(0.508)

MIN

0.130 ± 0.005

(3.302 ± 0.127)

0.125

(3.175)

MIN

0.100 ± 0.010

(2.540 ± 0.254)

0.045 – 0.065

(1.143 – 1.651)

0.125

(3.175)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

TYP

0.018 ± 0.003

(0.457 ± 0.076)

0.065

(1.651)

TYP

0.020

(0.508)

MIN

0.228 – 0.244

(5.791 – 6.197)

0.255 ± 0.015*
(6.477 ± 0.381)

0.255 ± 0.015*
(6.477 ± 0.381)

8

1

1234

0.189 – 0.197*
(4.801 – 5.004)

7

6

3

2

14

15

16

2

1

3

5

0.150 – 0.157**
(3.810 – 3.988)

4

0.770*

(19.558)

MAX

12

13

4

5

N8 1197

SO8 0996

11

6

910

8

7

N16 1197

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of circuits as described herein will not infringe on existing patent rights.

15

LTC690/LTC691
LTC694/LTC695

PPLICATITYPICAL

O

U
SA

Capacitor Back-Up with 74HC4016 Switch

R1
10k

R2
30k

1

74HC4016

7

5V

0.1µF

14121110

2

13

100µF

V

CC

V

BATT

+

PACKAGE DESCRIPTIO

Write Protect for Additional RAMs

LTC691
LTC695

LOW LINE

GND

V

OUT

LTC690 TA03

0.1µF

5V

0.1µF

V

CC

V

BATT

3V

LTC691
LTC695

LOW LINE

GND

V

OUT

CE OUT

CE IN

U

Dimensions in inches (millimeters) unless otherwise noted.

+

10µF

20ns PROPAGATION
DELAY

CS A

CS B

CS C

OPTIONAL CONNECTION FOR
ADDITIONAL RAMs

0.1µF

0.1µF

0.1µF

V

CC

62512

RAM A

CS

V

CC

62128

RAM B

CS1
CS2

V

CC

62128

RAM C

CS1
CS2

690 TA04

S Package

16-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

0.291 – 0.299**
(7.391 – 7.595)

0.037 – 0.045

(0.940 – 1.143)

0.004 – 0.012

(0.102 – 0.305)

° – 8° TYP

0

0.093 – 0.104

(2.362 – 2.642)

0.050

(1.270)

TYP

0.014 – 0.019

(0.356 – 0.482)

TYP

0.010 – 0.029

(0.254 – 0.737)

0.009 – 0.013

(0.229 – 0.330)

NOTE:

1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

*

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

**

NOTE 1

× 45°

0.016 – 0.050

(0.406 – 1.270)

NOTE 1

0.398 – 0.413*

(10.109 – 10.490)

15 141312

16

2345678

1

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1326 Micropower Precision Triple Supply Monitor 4.725V, 3.118V, 1V Thresholds (±0.75%)
LTC1536 Micropower Triple Supply Monitor for PCI Applications Meets PCI t

Timing Specifications

FAIL

10 9

11

0.394 – 0.419

(10.007 – 10.643)

S16 (WIDE) 0396

16

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

690fc LT/TP 0399 2K REV C • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 1992