Datasheet LTC693IS, LTC693IN, LTC693CS, LTC693CN, LTC692IS8 Datasheet (Linear Technology)

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Page 1

LTC692/LTC693

Microprocessor

Supervisory Circuits

EATU

■

UL Recognized

■

Guaranteed

■

1.5mA Maximum Supply Current

■

Fast (35ns Max.) On-Board Gating of RAM Chip

Reset Assertion at VCC = 1V

Enable Signals

■

SO8 and SO16 Packaging

■

4.40V Precision Voltage Monitor

■

Power OK/Reset Time Delay: 200ms or Adjustable

■

Minimum External Component Count

■

1µA Maximum Standby Current

■

Voltage Monitor for Power Fail or Low Battery Warning

■

Thermal Limiting

■

Performance Specified Over Temperature

■

Superior Upgrade for MAX690 Family

PPLICATI

■

Critical µP Power Monitoring

■

Intelligent Instruments

■

Battery-Powered Computers and Controllers

■

Automotive Systems

DUESCRIPTIO

The LTC692/LTC693 provide complete power supply monitoring and battery control functions for microprocessor reset, battery backup, CMOS RAM write protection, power failure warning and watchdog timing. A precise internal voltage reference and comparator circuit monitor the power supply line. When an out-of-tolerance condition occurs, the reset outputs are forced to active states and the Chip Enable output unconditionally write-protects external memory. In addition, the RESET output is guaranteed to remain logic low even with VCC as low as 1V.

The LTC692/LTC693 power the active CMOS RAMs with a charge pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost, auxiliary power, connected to the battery input pin, powers the RAMs in standby through an efficient PMOS switch.

For an early warning of impending power failure, the LTC692/LTC963 provide an internal comparator with a user-defined threshold. An internal watchdog timer is also available, which forces the reset pins to active states when the watchdog input is not toggled prior to a preset time-out period.

PPLICATITYPICAL

≥ 7.5V

10µF

51k

10k

MICROPROCESSOR RESET, BATTERY BACKUP, POWER FAILURE WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP FOR MICROPROCESSOR SYSTEMS.

LT1086-5

ADJ

OUT

100µF

0.1µF

RESET Output Voltage vs

Supply Voltage

TA = 25°C EXTERNAL PULL-UP = 10µA

= 0V

BATT

RESET OUTPUT VOLTAGE (V)

SUPPLY VOLTAGE (V)

LTC692/3 • TA02

µP

SYSTEM

µP

POWER

LTC692/3 • TA01

0.1µF

POWER TO CMOS RAM

µP RESET µP NMI

I/O LINE

100Ω

BATT

PFI

LTC692 LTC693

GND

OUT

RESET

PFO

WDI

0.1µF

Page 2

LTC692/LTC693

LUTEXI T

WUW

ARB

Terminal Voltage

VCC.................................................... –0.3V to 6.0V

................................................. –0.3V to 6.0V

BATT

All Other Inputs .................. –0.3V to (V

OUT

Input Current

VCC.............................................................. 200mA

............................................................. 50mA

BATT

GND............................................................... 20mA

PACKAGE



OUT



GND

PFI

N8 PACKAGE

8-LEAD PLASTIC DIP

JMAX

S8 Package Conditions: PCB Mount on FR4 Material,

Still Air at 25°C, Copper Trace

RDER I FOR ATIO

TOP VIEW

1 2 3 4

= 110°C, θJA = 130°C/W (N) = 110°C, θJA = 180°C/W (S)

8 7 6 5



S8 PACKAGE

8-LEAD PLASTIC SOIC

BATT

RESET WDI PFO

ORDER PART

NUMBER



LTC692CN8 LTC692IN8 LTC692CS8 LTC692IS8

S8 PART MARKING

692 692I

(Notes 1 and 2)

+ 0.3V)

Output Current .................. Short Circuit Protected

OUT

Power Dissipation............................................. 500mW

Operating Temperature Range

LTC692C/LTC693C ............................... 0°C to 70°C

LTC692I/LTC693I ............................ –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

(Note 3)

TOP VIEW

1



BATT

2



OUT

3



4

GND

BATT ON

LOW LINE

OSC SEL

16-LEAD PLASTIC DIP

S16 Package Conditions: PCB Mount on FR4 Material,

5 6 7

OSC IN

8



N PACKAGE

= 110°C, θJA = 130°C/W (N, S)

JMAX

Still Air at 25°C, Copper Trace

16-LEAD PLASTIC SOL

RESET

16

RESET

15

WDO

14

CE IN

13

CE OUT

12

WDI

11

PFO

10

PFI

9



S PACKAGE

ORDER PART

NUMBER

LTC693CN LTC693IN LTC693CS LTC693IS

U

PRODUCT SELECTIO GUIDE

RESET CONDITIONAL

PINS (V) TIMER BACKUP WARNING PROTECT RESET BACKUP LTC692 8 4.40 X X X LTC693 16 4.40 X X X X

LTC690 8 4.65 X X X LTC691 16 4.65 X X X X LTC694 8 4.65 X X X LTC695 16 4.65 X X X X LTC699 8 4.65 X LTC1232 8 4.37/4.62 X X LTC1235 16 4.65 X X X X X X LTC694-3.3 8 2.90 X X X LTC695-3.3 16 2.90 X X X X

THRESHOLD WATCHDOG BATTERY POWER FAIL RAM WRITE PUSHBUTTON BATTERY

Page 3

LTC692/LTC693

LECTRICAL C CHARA TERIST

VCC = Full Operating Range, V

PARAMETER CONDITONS MIN TYP MAX UNITS Battery Backup Switching

Operating Voltage Range

BATT

Output Voltage I

OUT

in Battery Backup Mode I

OUT

Supply Current (Exclude I

Supply Current in Battery Backup Mode VCC = 0V, V

Battery Standby Current 5.5 > VCC > V

(+ = Discharge, – = Charge) ● –1.0 0.10 µA

Battery Switchover Threshold Power Up 70 mV

VCC – V

BATT

Battery Switchover Hysteresis 20 mV BATT ON Output Voltage (Note 4) I BATT ON Output Short-Circuit Current (Note 4) BATT ON = V

Reset and Watchdog Timer

Reset Voltage Threshold ● 4.25 4.40 4.50 V Reset Threshold Hysteresis 40 mV Reset Active Time OSC SEL HIGH, VCC = 5V 160 200 240 ms

(Note 5)

Watchdog Time-Out Period, Long Period, VCC = 5V 1.2 1.6 2.00 sec

Internal Oscillator

Watchdog Time-Out Period, External Clock Long Period 4032 4097 Clock

(Note 6) Short Period 960 1025 Cycles Reset Active Time PSRR 1 ms/V Watchdog Time-Out Period PSRR, Internal OSC 1 ms/V Minimum WDI Input Pulse Width VIL = 0.4V, VIH = 3.5V ● 200 ns RESET Output Voltage At VCC = 1V I RESET and LOW LINE Output Voltage I

(Note 4) I RESET and WDO Output Voltage I

(Note 4) I

OUT

= 2.8V, TA = 25°C, unless otherwise noted.

BATT

ICS

4.50 5.50 V

2.00 4.00 V

= 1mA V

OUT

= 50mA VCC – 0.50 VCC – 0.250 V

OUT

= 250µA, VCC < V

OUT

≤ 50mA 0.6 1.5 mA

OUT

BATT

Power Down 50 mV

= 3.2mA 0.4 V

SINK

BATT ON = 0V Source Current 0.5 1 25 µA

Short Period, VCC = 5V 80 100 120 ms

SINK

SINK SOURCE

OUT

= 10µA, VCC = 1V 4 200 mV = 1.6mA, VCC = 4.25V 0.4 V

= 1µA, VCC = 5V 3.5 V

= 1.6mA, VCC = 5V 0.4 V

= 1µA, VCC = 4.25V 3.5 V

BATT

= 2.8V 0.04 1 µA

+ 0.2V –0.1 0.02 µA

BATT

Sink Current 35 mA

● V

● 0.6 2.5 mA

● 0.04 5 µA

● 140 200 280 ms

● 1.0 1.6 2.25 sec

● 70 100 140 ms

– 0.05 V

– 0.10 VCC – 0.005 V

– 0.1 V

BATT

– 0.005 V

– 0.02 V

BATT

Page 4

LTC692/LTC693

LECTRICAL C CHARA TERIST

VCC = Full Operating Range, V

PARAMETER CONDITONS MIN TYP MAX UNITS

RESET, RESET, WDO, LOW LINE Output Source Current 1 3 25 µA Output Short-Circuit Current (Note 4) Output Sink Current 25 mA

WDI Input Threshold Logic Low 0.8 V

WDI Input Current WDI = V

Power Fail Detector

PFI Input Threshold VCC = 5V ● 1.25 1.3 1.35 V PFI Input Threshold PSRR 0.3 mV/V PFI Input Current ±0.01 ±25 nA PFO Output Voltage (Note 4) I

PFO Short Circuit Source Current PFI = HIGH, PFO = 0V 1 3 25 µA

(Note 4) PFI = LOW, PFO = V

PFI Comparator Response Time (falling) ∆VIN = –20mV, VOD = 15mV 2 µs PFI Comparator Response Time (rising) ∆VIN = 20mV, VOD = 15mV 40 µs

(Note 4) with 10kΩ Pull-Up 8 µs

Chip Enable Gating

CE IN Threshold V

CE IN Pullup Current (Note 7) 3 µA CE OUT Output Voltage I

CE Propagation Delay VCC = 5V, CL = 20pF 20 35 ns

CE OUT Output Short Circuit Current Output Source Current 30 mA

Oscillator

OSC IN Input Current (Note 7) ±2 µA OSC SEL Input Pull-Up Current (Note 7) 5 µA OSC IN Frequency Range OSC SEL = 0V ● 0 250 kHz OSC IN Frequency with External Capacitor OSC SEL = 0V, C

= 2.8V, TA = 25°C, unless otherwise noted.

BATT

ICS

Logic High 3.5 V

OUT

WDI = 0V

= 3.2mA 0.4 V

SINK

= 1µA 3.5 V

SOURCE

OUT

= 3.2mA 0.4 V

SINK

= 3.0mA V

SOURCE

= 1µA, VCC = 0V V

SOURCE

Output Sink Current 35 mA

= 47pF 4 kHz

OSC

● 450µA

● –50 –8 µA

25 mA

0.8 V

2.0 V

– 1.50 V

OUT

– 0.05 V

OUT

● 20 45 ns

The ● denotes specifications which apply over the full operating temperature range.

Note 1: Absolute maximum ratings are those values beyond which the life of the device may be impaired.

Note 2: All voltage values are with respect to GND. Note 3: For military temperature range, consult the factory. Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and

RESET have weak internal pull-ups of typically 3µA. However, external pull-up resistors may be used when higher speed is required.

Note 5: The LTC692/LTC693 have minimum reset active times of 140ms (200ms typically). The reset active time of the LTC693 can be adjusted (see Table 2 in Applications Information Section).

Note 6: The external clock feeding into the circuit passes through the oscillator before clocking the watchdog timer (See BLOCK DIAGRAM). Variation in the time-out period is caused by phase errors which occur when the oscillator divides the external clock by 64. The resulting variation in the time-out period is 64 clocks plus one clock of jitter.

Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal pull-ups which pull to the supply when the input pins are floating.

Page 5

LPER

TIME (µs)

LTC692/3 • TPC06

3 2

123

1.305V

1.285V

VCC = 5V T

= 25°C

–

PFI

1.3V

PFO

30pF

PFI

= 20mV STEP

PFO OUTPUT VOLTAGE (V)

vs I

OUT

5.00

4.95

4.90

4.85

OUTPUT VOLTAGE (V)

4.80

OUT

SLOPE = 5Ω

VCC = 5V V

BATT

= 25°C

ATYPICA

= 2.8V

CCHARA TERIST

vs I

OUT

2.80

2.78

SLOPE = 125Ω

2.76

OUTPUT VOLTAGE (V)

2.74

OUT

ICS

VCC = 0V V

BATT

= 25°C

= 2.8V

LTC692/LTC693

Power Failure Input Threshold vs Temperature

1.308 VCC = 5V

1.306

1.304

1.302

1.300

1.298

PFI INPUT THRESHOLD (V)

1.296

4.75

232

224

216

208

200

RESET ACTIVE TIME

192

184

–50

LOAD CURRENT (mA)

Reset Active Time vs Temperature

VCC = 5V

50 100 125

–25 0

25 75

TEMPERATURE (°C)

Power Fail Comparator Response Time

VCC = 5V

4 3 2

PFO OUTPUT VOLTAGE (V)

1.315V

1.295V

= 25°C

LTC692/3 • TPC01

LTC692/3 • TPC04

PFI

1.3V

= 20mV STEP

10080

TIME (µs)

2.72 100

Reset Voltage Threshold vs Temperature

4.41

4.40

4.39

4.38

4.37

RESET VOLTAGE THRESHOLD (V)

4.36

4.35

–50

–25 0

PFO

140

120

LTC692/3 • TPC07

30pF

180160

–

300

200

LOAD CURRENT (µA)

50 100 125

25 75

TEMPERATURE (°C)

1.315V

1.295V

1.294

400

LTC692/3 • TPC02

500

–50

–25 0

Power Fail Comparator Response Time

LTC692/3 • TPC05

Power Fail Comparator Response Time with Pull-Up Resistor

VCC = 5V

= 25°C

4 3 2

PFO OUTPUT VOLTAGE (V)

= 20mV STEP

PFI

1.3V

TIME (µs)

108

PFO

–

LTC692/3 • TPC08

25 75

TEMPERATURE (°C)

10k

30pF

1816

50 100 125

LTC692/3 • TPC03

Page 6

LTC692/LTC693

U

PI FU CTIO S

VCC: 5V Supply Input. The VCC pin should be bypassed with a 0.1µF capacitor.

: Voltage Output for Backed Up Memory. Bypass with

OUT

a capacitor of 0.1µF or greater. During normal operation, V

obtains power from VCC through an NMOS power

OUT

switch, M1, which can deliver up to 50mA and has a typical ON resistance of 5Ω. When VCC is lower than V is internally switched to V used, connect V

: Backup Battery Input. When VCC falls below V

BATT

OUT

to VCC.

auxiliary power connected to V

BATT

. If V

BATT

and V

OUT

, is delivered to V through PMOS switch, M2. If backup battery or auxiliary power is not used, V

should be connected to GND.

BATT

GND: Ground Pin. BATT ON: Battery On Logic Output from Comparator C2.

BATT ON goes low when V

is internally connected to

OUT

VCC. The output typically sinks 35mA and can provide base drive for an external PNP transistor to increase the output current above the 50mA rating of V high when V

is internally switched to V

OUT

. BATT ON goes

OUT

BATT

PFI: Power Failure Input. PFI is the noninverting input to the Power Fail Comparator, C3. The inverting input is internally connected to a 1.3V reference. The Power Failure Output remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. Connect PFI to GND or V C3 is not used.

PFO: Power Failure Output from C3. PFO remains high when PFI is above 1.3V and goes low when PFI is below

1.3V. When VCC is lower than V

, C3 is shut down and

BATT

PFO is forced low. RESET: Logic Output for µ P Reset Control. Whenever V

falls below either the reset voltage threshold (4.40V typically) or V

, RESET goes active low. After V

BATT

returns to 5V, reset pulse generator forces RESET to remain active low for a minimum of 140ms. When the watchdog timer is enabled but not serviced prior to a preset time-out period, reset pulse generator also forces RESET to active low for a minimum of 140ms for every preset

BATT

OUT

, V

OUT

are not

BATT

OUT

when

time-out period (see Figure 11). The reset active time is adjustable on the LTC693. An external pushbutton reset can be used in connection with the RESET output. See Pushbutton Reset in the Applications Information section.

RESET: RESET is an Active High Logic Ouput. It is the inverse of RESET.

LOW LINE: Logic Output from Comparator C1. LOW LINE indicates a low line condition at the VCC input. When V

falls below the reset voltage threshold (4.40V typically), LOW LINE goes low. As soon as VCC rises above the reset voltage threshold, LOW LINE returns high (see Figure 1). LOW LINE goes low when V

drops below V

BATT

(see

Table 1). WDI: Watchdog Input. WDI is a three level input. Driving

WDI either high or low for longer than the watchdog timeout period, forces both RESET and WDO low. Floating WDI disables the Watchdog Timer. The timer resets itself with each transition of the Watchdog Input (see Figure 11).

WDO: Watchdog Logic Output. When the watchdog input remains either high or low for longer than the watchdog time-out period, WDO goes low. WDO is set high whenever there is a transition on the WDI pin, or LOW LINE goes low. The watchdog timer can be disabled by floating WDI (see Figure 11).

CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN can be derived from microprocessor's address line and/or decoder output. See Applications Information Section and Figure 5 for additional information.

CE OUT: Logic Output on the Chip Enable Gating Circuit. When VCC is above the reset voltage threshold, CE OUT is a buffered replica of CE IN. When VCC is below the reset voltage threshold CE OUT is forced high (see Figure 5).

OSC SEL: Oscillator Selection Input. When OSC SEL is high or floating, the internal oscillator sets the reset active time and watchdog time-out period. Forcing OSC SEL low allows OSC IN to be driven from an external clock signal or an external capacitor to be connected between

OSC IN and

GND.

Page 7

LTC692/LTC693

U

PI FU CTIO S

OSC IN: Oscillator Input. OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND when OSC SEL is forced low. In this configuration the nominal reset active time and watchdog time-out period are determined by the number of clocks or set by the formula (see

BLOCK

IDAGRA

BATT

–

Applications Information section). When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 200ms typical. OSC IN selects between the 1.6 seconds and 100ms typical watchdog time-out periods. In both cases the time-out period immediately after a reset is 1.6 seconds typical.

OUT

CHARGE

PUMP

BATT ON

CE IN

PFI

OSC IN

OSC SEL

WDI



1.3V

GND

OSC

TRANSITION

DETECTOR

LOW LINE

–

RESET PULSE

GENERATOR

WATCHDOG

TIMER

CE OUT

PFO

RESET

WDO

LTC692/3 • BD

Page 8

LTC692/LTC693

PPLICATI

I FOR ATIO

Microprocessor Reset

The LTC692/LTC693 use a bandgap voltage reference and a precision voltage comparator C1 to monitor the 5V supply input on VCC (see BLOCK DIAGRAM). When V

falls below the reset voltage threshold, the RESET output is forced to active low state. The reset voltage threshold accounts for a 10% variation on VCC, so the RESET output becomes active low when VCC falls below 4.50V (4.40V typical). On power-up, the RESET signal is held active low for a minimum of 140ms after reset voltage threshold is reached to allow the power supply and microprocessor to stabilize. The reset active time is adjustable on the LTC693. On power-down, the RESET signal remains active low even with VCC as low as 1V. This capability helps hold the microprocessor in stable shutdown condition. Figure 1 shows the timing diagram of the RESET signal.

The precision voltage comparator, C1, typically has 40mV of hysteresis which ensures that glitches at the VCC pin do not activate the RESET output. Response time is typically 10µ s. To help prevent mistriggering due to transient loads, VCC pin should be bypassed with a 0.1µ F capacitor with the leads trimmed as short as possible.

The LTC693 has two additional outputs: RESET and LOW LINE. RESET is an active high output and is the inverse of RESET. LOW LINE is the output of the precision voltage comparator C1. When VCC falls below the reset voltage threshold, LOW LINE goes low. LOW LINE returns high as soon as VCC rises above the reset voltage threshold.

Battery Switchover

The battery switchover circuit compares VCC to the V

input, and connects V

BATT

When VCC rises to 70mV above V switchover comparator, C2, connects V a charge pumped NMOS power switch, M1. When V falls to 50mV above V

BATT

to whichever is higher.

OUT

, the battery

BATT

to VCC through

OUT

, C2 connects V

OUT

to V

BATT

through a PMOS switch, M2. C2 has typically 20mV of hysteresis to prevent spurious switching when V remains nearly equal to V

. The response time of C2

BATT

is approximately 20µs. During normal operation, the LTC692/LTC693 use a charge

pumped NMOS power switch to achieve low dropout and low supply current. This power switch can deliver up to 50mA to V of 5Ω. The V

from VCC and has a typical “on” resistance

OUT

pin should be bypassed with a capacitor

OUT

of 0.1µF or greater to ensure stability. Use of a larger bypass capacitor is advantageous for supplying current to heavy transient loads.

When operating currents larger than 50mA are required from V

, or a lower dropout (V

OUT

– V

voltage differ-

OUT

ential) is desired, the LTC693 should be used. This product provides BATT ON output to drive the base of the external PNP transistor (Figure 2). If higher currents are needed with the LTC692, a high current Schottky diode can be connected from the VCC pin to the V

OUT

pin to

supply the extra current.

RESET

LOW LINE

Figure 1. Reset Active Time

V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS

t1 = RESET ACTIVE TIME

LTC692/3 • F01

Page 9

LTC692/LTC693

V – 50mV

≤

PPLICATI

0.1µF

Figure 2. Using BATT ON to Drive External PNP Transistor

I FOR ATIO

ANY PNP POWER TRANSISTOR

BATT ON

LTC693

BATT

GND

OUT

0.1µF

LTC692/3 • F02

The LTC692/LTC693 are protected for safe area operation with a short circuit limit. Output current is limited to approximately 200mA. If the device is overloaded for long periods of time, thermal shutdown turns the power switch off until the device cools down. The threshhold temperature for thermal shutdown is approximately 155°C with about 10°C of hysteresis which prevents the device from oscillating in and out of shutdown.

The PNP switch used in competitive devices was not chosen for the internal power switch because it injects unwanted current into the substrate. This current is collected by the V

pin in competitive devices and adds to

BATT

the charging current of the battery which can damage lithium batteries. The LTC692/LTC693 use a charge pumped NMOS power switch to eliminate unwanted charging current while achieving low dropout and low supply current. Since no current goes to the substrate, the current collected by the V

A 125Ω PMOS switch connects the V

pin is strictly junction leakage.

BATT

input to V

BATT

OUT

in battery backup mode. The switch is designed for very low dropout voltage (input-to-output differential). This feature is advantageous for low current applications such as battery backup in CMOS RAM and other low power CMOS circuitry. The supply current in battery backup mode is 1µA maximum.

The operating voltage at the V

pin ranges from 2.0V to

BATT

4.0V. High value capacitors, such as electrolytic or faradsize double layer capacitors, can be used for short term

– V

OUT

I =

0.1µF

Figure 3. Charging External Battery Through V

LTC692 LTC693

BATT

GND



BATT

OUT

0.1µF



LTC692/3 • F03

OUT

memory backup instead of a battery. The charging resistor for the rechargeable batteries should be connected to V

since this eliminates the discharge path that exists

OUT

when the resistor is connected to VCC (Figure 3).

Replacing the Backup Battery

When changing the backup battery with system power on, spurious resets can occur while the battery is removed due to battery standby current. Although battery standby current is only a tiny leakage current, it can still charge up the stray capacitance on the V oscillation cycle is as follows: When V

BATT

pin. The

BATT

reaches within 50mV of VCC, the LTC692/LTC693 switch to battery backup. V

OUT

pulls V

low and the devices go back to

BATT

normal operation. The leakage current then charges up the V

pin again and the cycle repeats.

BATT

If spurious resets during battery replacement pose no problems, then no action is required. Otherwise, a resistor from V

to GND will hold the pin low while changing the

BATT

battery. For example, the battery standby current is 1µA maximum over temperature and the external resistor required to hold V

below VCC is:

BATT

With VCC = 4.25V, a 3.9M resistor will work. With a 3V battery, this resistor will draw only 0.77µA from the battery, which is negligible in most cases.

Page 10

LTC692/LTC693

PPLICATI

I FOR ATIO

If battery connections are made through long wires, a 10Ω to 100Ω series resistor and a 0.1µ F capacitor are recommended to prevent any overshoot beyond VCC due to the lead inductance (Figure 4).

10Ω

3.9M

Figure 4. 10Ω/0.1µF combination eliminates inductive overshoot and prevents spurious resets during battery replacement.

0.1µF

BATT

LTC692 LTC693

GND

LTC692/3 • F04

Table 1 shows the state of each pin during battery backup. When the battery switchover section is not used, connect V

to GND and V

BATT

OUT

to VCC.

Memory Protection

The LTC693 includes memory protection circuitry which ensures the integrity of the data in memory by preventing write operations when VCC is at an invalid level. Two additional pins, CE IN and CE OUT, control the Chip Enable or Write inputs of CMOS RAM. When VCC is 5V, CE OUT follows CE IN with a typical propagation delay of 20ns. When VCC falls below the reset voltage threshold or V

BATT

CE OUT is forced high, independent of CE IN. CE OUT is an

alternative signal to drive the CE, CS, or Write input of battery backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NOVRAM to achieve similar protection. Figure 5 shows the timing diagram of CE IN and CE OUT.

CE IN can be derived from the microprocessor's address decoder output. Figure 6 shows a typical nonvolatile CMOS RAM application.

Memory protection can also be achieved with the LTC692 by using RESET as shown in Figure 7.

Table 1. Input and Output Status in Battery Backup Mode

SIGNAL STATUS

OUT

BATT

BATT ON Logic high. The open-circuit output voltage is equal to V PFI Power Failure Input is ignored. PFO Logic low RESET Logic low RESET Logic high. The open-circuit output voltage is equal to V LOW LINE Logic low WDI Watchdog Input is ignored. WDO Logic high. The open-circuit output voltage is equal to V CE IN Chip Enable Input is ignored. CE OUT Logic high. The open-circuit output voltage is equal to V OSC IN OSC IN is ignored. OSC SEL OSC SEL is ignored.

C2 monitors VCC for active switchover. V

is connected to V

OUT

The supply current is 1µA maximum.

through an internal PMOS switch.

BATT

OUT

CE IN

CE OUT

= V

OUT

BATT

Figure 5. Timing Diagram for CE IN and CE OUT

V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS

OUT

= V

BATT

LTC692/3 • F05

Page 11

LTC692/LTC693

V =1.3V 1+

R1R2R1

 



 



V 1.3V 1

R1 R2

–

(5V –1.3V)R1

1.3V(R3 R4)

 



 



PPLICATI

0.1µF

BATT

GND

LTC693

CE OUT

I FOR ATIO

OUT

CE IN

RESET RESET

10µF

20ns PROPAGATION DELAY FROM DECODER

TO µP

0.1µF

Figure 6. A Typical Nonvolatile CMOS RAM Application

0.1µF

LTC692

BATT

GND

OUT

RESET

10µF

0.1µF

Figure 7. Write Protect for RAM with the LTC692

62512

RAM

GND

LTC692/3 • F06

62128

RAM

CS1

CS2

GND

LTC692/3 • F07

Power Fail Warning

The LTC692/LTC693 generate a Power Failure Output (PFO) for early warning of failure in the microprocessor's power supply. This is accomplished by comparing the Power Failure Input (PFI) with an internal 1.3V reference. PFO goes low when the voltage at the PFI pin is less than

1.3V. Typically PFI is driven by an external voltage divider (R1 and R2 in Figures 8 and 9) which senses either an unregulated DC input or a regulated 5V output. The voltage divider ratio can be chosen such that the voltage at the PFI pin falls below 1.3V, several milliseconds before the 5V supply falls below the maximum reset voltage threshold of

4.50V. PFO is normally used to interrupt the microprocessor to execute shutdown procedure between PFO and RESET or RESET.

The power fail comparator, C3, does not have hysteresis. Hysteresis can be added however, by connecting a resistor between the PFO output and the noninverting PFI input pin as shown in Figures 8 and 9. The upper and lower trip points in the comparator are established as follows:

≥ 7.5V

10µF

R1 51k

R2 10k

Figure 8. Monitoring

LT1086-5

INVOUT

ADJ

100µF

R3

300k

Unregulated

R4 10k

DC Supply with the

LTC692/LTC693 Power Fail Comparator

≥ 6.5V

LT1086-5

OUT

10µF

ADJ

Figure 9. Monitoring

10µF

Regulated

R1 27k

R2

8.2k

R5

3.3k

2.7M

R4

10k

R3

DC Supply

with the LTC692/LTC693 Power Fail Comparator

0.1µF

PFO PFI

TO µP

PFO

PFI

TO µP

LTC692 LTC693

GND

LTC692/3 • F08



LTC692 LTC693

GND

LTC692/3 • F09

When PFO output is low, R3 sinks current from the summing junction at the PFI pin.



When PFO output is high, the series combination of R3 and R4 source current into the PFI summing junction.

Assuming R4 R3,V 5V

<< =

HYSTERESIS

Example 1: The circuit in Figure 8 demonstrates the use of the power fail comparator to monitor the unregulated power supply input. Assuming the the rate of decay of the supply input VIN is 100mV/ms and the total time to execute a shutdown procedure is 8ms. Also, the noise of VIN is 200mV. With these assumptions in mind, we can reasonably set VL = 7.25V which is 1.25V greater than the sum of maximum reset voltage threshold and the dropout voltage of LT1086-5 (4.5V + 1.5V) and V

HYSTERESIS

= 850mV.

Page 12

LTC692/LTC693

PPLICATI

V5V

HYSTERESIS

I FOR ATIO

850mV

R3 ≈ 5.88 R1

Choose R3 = 300k and R1 = 51k. Also select R4 = 10k which is much smaller than R3.

7.25V =1.3V 1+







(5V –1.3V)5151

–

1 3 310

Vk.( )

 



R2 = 10.1k, Choose nearest 5% resistor 10k and recalculate VL,



V1.3V1







V1.3V1

=++





(7.32V – 6.25V)

–

10k

51k

10k

10.7ms=

(5V –1.3V)51

1.3V(310k



51k

300k







732



)



8.151V

100mV/ms

HYSTERESIS

= 8.151V – 7.32V = 831mV

The 10.7ms allows enough time to execute shutdown procedure for microprocessor and 831mV of hysteresis would prevent PFO from going low due to the noise of VIN.

Example 2: The circuit in Figure 9 can be used to measure the regulated 5V supply to provide early warning of power failure. Because of variations in the PFI threshold, this circuit requires adjustment to ensure the PFI comparator trips before the reset threshold is reached. Adjust R5 such that the PFO output goes low when the VCC supply reaches the desired level (e.g., 4.6V).

Monitoring the Status of the Battery

C3 can also monitor the status of the memory backup battery (Figure 10). If desired, the CE OUT can be used to apply a test load to the battery. Since CE OUT is forced high in battery backup mode, the test load will not be applied to the battery while it is in use, even if the microprocessor is not powered.

BATT

R1 1M

PFI

Figure 10. Backup Battery Monitor with Optional Test Load

R2 1M

CE OUT



20K

OPTIONAL TEST LOAD

PFO

LTC693

CE IN

GND

LOW BATTERY SIGNAL TO µP I/O PIN

I/O PIN

LTC692/3 • F10

Watchdog Timer

The LTC692/LTC693 provide a watchdog timer function to monitor the activity of the microprocessor. If the microprocessor does not toggle the Watchdog Input (WDI) within a seleced time-out period, RESET is forced to active low for a minimum of 140ms. The reset active time is adjustable on the LTC693. Since many systems cannot service the watchdog timer immediately after a reset, the LTC693 has longer time-out period (1.0 second minimum) right after a reset is issued. The normal time-out period (70ms minimum) becomes effective following the first transition of WDI after RESET is inactive. The watchdog time-out period is fixed at a 1.0 second minimum on the LTC692. Figure 11 shows the timing diagram of watchdog time-out period and reset active time. The watchdog time-out period is restarted as soon as RESET is inactive. When either a high-to-low or low-to-high transition occurs at the WDI pin prior to time-out, the watchdog timer is reset and begins to time-out again. To ensure the watchdog timer does not time-out, either a high-to-low or low-to-high transition on the WDI pin must occur at or less than the minimum time-out period. If the input to the WDI pin remains either high or low, reset pulses will be issued every 1.6 seconds typically. The watchdog timer can be deactivated by floating the WDI pin. The timer is also disabled when VCC falls below the reset voltage threshold or V

BATT

Page 13

LTC692/LTC693

PPLICATI

I FOR ATIO

The LTC693 provides an additional output (Watchdog Output, WDO) which goes low if the watchdog timer is allowed to time out and remains low until set high by the next transition on the WDI pin. WDO is also set high when VCC falls below the reset voltage threshold or V

BATT

The LTC693 has two additonal pins OSC SEL and OSC IN, which allow reset active time and watchdog time-out period to be adjusted per Table 2. Several configurations are shown in Figure 12.

OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and

= 5V

WDI

t1 = RESET ACTIVE TIME

WDO

t2 = NORMAL WATCHDOG TIME-OUT PERIOD t3 = WATCHDOG TIME-OUT PERIOD IMMEDIATELY AFTER A RESET

GND when OSC SEL is forced low. In these configurations, the nominal reset active time and watchdog time-out period are determined by the number of clocks or set by the formula in Table 2. When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 140ms minimum. OSC IN selects between the 1 second and 70ms minimum normal watchdog time-out periods. In both cases, the time-out period immediately after a reset is at least 1 second.

RESET

t2 t3

Figure 11. Watchdog Time-out Period and Reset Active Time

EXTERNAL CLOCK

OSC SEL

LTC693

GND

INTERNAL OSCILLATOR

1.6 SECOND WATCHDOG

OSC SEL

LTC693

GND GND

OSC IN

FLOATING OR HIGH

EXTERNAL OSCILLATOR

GND

INTERNAL OSCILLATOR

100ms WATCHDOG

OSC SEL

LTC693

OSC SEL

LTC693

OSC IN

FLOATING OR HIGH

LTC692/3 • F11

Figure 12. Oscillator Configurations

LTC692/3 • F12

Page 14

LTC692/LTC693

PPLICATI

I FOR ATIO

Table 2. LTC693 Reset Active Time and Watchdog Time-Out Selections

WATCHDOG TIME-OUT PERIOD

OSC SEL

Low External Clock Input 1024

Low External Capacitor*

Floating or High Low 100ms 1.6 sec 200ms Floating or High Floating or High 1.6 sec 1.6 sec 200ms

*The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is F

OSC IN

NORMAL

(Short Period) LTC693

clks

400ms

× C

47pF

IMMEDIATELY

AFTER RESET (Long Period)

4096

clks

1.6 sec

× C

47pF

(Hz) =

OSC

184,000

C(pF)

Pushbutton Reset

The LTC692/LTC693 do not provide a logic input for direct connection to a pushbutton. However, a pushbutton in series with a 100Ω resistor connected to the RESET output

LTC692 LTC693

RESET

0.1µF

pin (Figure 13) provides an alternative for manual reset. Connecting a 0.1µ F capacitor to the RESET pin debounces

GND

the pushbutton input.

RESET ACTIVE TIME

2048

clks

800ms

× C

47pF

RESET

100Ω

MPU

(e.g. 6805)

LTC692/3 • F13

The 100Ω resistor in series with the pushbutton is required to prevent the ringing, due to the capacitance and lead inductance, from pulling the RESET pins of the MPU and LTC692/LT693 below ground.

R1 10k

R2 30k

Capacitor Backup with 74HC4016 Switch

14121110

74HC4016

PPLICATITYPICAL

100µF

Figure 13. The External Pushbutton Reset

BATT

LTC693

LOW LINE

GND

OUT

0.1µF0.1µF

LTC692/3 • TA3

Page 15

LTC692/LTC693

PPLICATITYPICAL

Write Protect for Additional RAMs

0.1µF

PACKAGE DESCRIPTIO

0.1µF

CS CS

62512

RAM

62128

RAM

62128 RAM

LTC692/3 • TA04

BATT

LTC693

LOW LINE

GND

OUT

CE OUT

CE IN

10µF

20ns PROPAGATION  DELAY

OPTIONAL CONNECTION FOR ADDITIONAL RAMs

U

Dimensions in inches (millimeters) unless otherwise noted.

N8 Package

8-Lead Plastic DIP

S8 Package

8-Lead Plastic SOIC

0.300 – 0.320

(7.620 – 8.128)

0.065

(1.651)

0.009 – 0.015

(0.229 – 0.381)

+0.025

0.325

–0.015 +0.635

8.255

()

–0.381

0.008 – 0.010

(0.203 – 0.254)

0.010 – 0.020

(0.254 – 0.508)

× 45°

0.016 – 0.050

0.406 – 1.270

TYP

0.045 ± 0.015

(1.143 ± 0.381)

0°– 8° TYP

0.045 – 0.065

(1.143 – 1.651)

0.100 ± 0.010

(2.540 ± 0.254)

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

0.130 ± 0.005

(3.302 ± 0.127)

0.125

(3.175)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

0.050

(1.270)

BSC

0.020

(0.508)



MIN

0.004 – 0.010

(0.101 – 0.254)

0.228 – 0.244

(5.791 – 6.197)

0.400

(10.160)

MAX

876

1234

0.189 – 0.197

(4.801 – 5.004)

0.250 ± 0.010

(6.350 ± 0.254)



N8 0393

0.150 – 0.157

(3.810 – 3.988)

SO8 0393



Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.

Page 16

LTC692/LTC693

PACKAGE DESCRIPTIO

0.300 – 0.325

(7.620 – 8.255)

0.009 – 0.015

(0.229 – 0.381)

+0.025

0.325

–0.015

+0.635

8.255

()

–0.381

0.015

(0.381)

MIN

0.130 ± 0.005

(3.302 ± 0.127)

0.125

(3.175)

MIN

U

Dimensions in inches (millimeters) unless otherwise noted.

N Package

16-Lead Plastic DIP

0.045 – 0.065

(1.143 – 1.651)

0.260 ± 0.010

(6.604 ± 0.254)

0.045 ± 0.015

(1.143 ± 0.381)

0.100 ± 0.010

(2.540 ± 0.254)

0.018 ± 0.003

(0.457 ± 0.076)

S Package

16-Lead SOL

0.065

(1.651)

TYP

0.770

(19.558)

MAX

910

N16 0393

0.291 – 0.299

(7.391 – 7.595)

0.005

(0.127)

RAD MIN

0.009 – 0.013

(0.229 – 0.330)

NOTE:

1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.

2. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).

(NOTE 2)

0.010 – 0.029

(0.254 – 0.737)

NOTE 1

0.016 – 0.050

(0.406 – 1.270)

× 45°

0° – 8° TYP

0.093 – 0.104

(2.362 – 2.642)

0.050

(1.270)

TYP

0.014 – 0.019

(0.356 – 0.482)

TYP

0.037 – 0.045

(0.940 – 1.143)

0.004 – 0.012

(0.102 – 0.305)

NOTE 1

0.398 – 0.413

(10.109 – 10.490)

(NOTE 2)

15 1413121110 9

2345678

0.394 – 0.419

(10.007 – 10.643)

S16 0393

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7487

(408) 432-1900

●

FAX

: (408) 434-0507

●

TELEX

: 499-3977

LT/GP 0493 10K REV 0

 LINEAR TECHNOLOGY CORPORATION 1993

Datasheet LTC693IS, LTC693IN, LTC693CS, LTC693CN, LTC692IS8 Datasheet (Linear Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual