Datasheet LTC6605-10 Datasheet (Linear) [ru]

LTC6605-10

Dual Matched 10MHz Filter

with Low Noise, Low Distortion

Differential Amplifi er

FEATURES

n

Two Matched 10MHz 2nd Order Lowpass Filters

with Differential Amplifi ers

Gain Match: ±0.35dB Max, Passband
Phase Match: ±1.2° Max, Passband

Single-Ended or Differential Inputs

n

< –90dBc Distortion in Passband

n

2.1nV/√Hz Op Amp Noise Density

n

Pin-Selectable Gain (0dB/12dB/14dB)

n

Pin-Selectable Power Consumption (0.35mA/

16.2mA/33.1mA)

n

Rail-to-Rail Output Swing
Adjustable Output Common Mode Voltage Control
Buffered, Low Impedance Outputs

n

2.7V to 5.25V Supply Voltage

n

Small 22-Pin 6mm × 3mm × 0.75mm DFN Package

APPLICATIONS

n

Broadband Wireless ADC Driver/Filter

n

Antialiasing Filter

n

Single-Ended to Differential Conversion

n

DAC Smoothing Filter

n

Zero-IF Direct Conversion Receivers

DESCRIPTION

The LTC®6605-10 contains two independent, fully differ­ential amplifi ers confi gured as matched 2nd order 10MHz
lowpass fi lters. The f
range of 9.7MHz to 14MHz.

The internal op amps are fully differential, feature very
low noise and distortion, and are compatible with 16-bit
dynamic range systems. The inputs can accept single­ended or differential signals. An input pin is provided
for each amplifi er to set the common mode level of the
differential outputs.

Internal laser-trimmed resistors and capacitors determine
a precise, very well matched (in gain and phase) 10MHz
2nd order fi lter response. A single optional external re­sistor per channel can tailor the frequency response for
each amplifi er.

Three-state BIAS pins determine each amplifi er’s power
consumption, allowing a choice between shutdown, me­dium power or full power.

The LTC6605-10 is available in a compact 6mm × 3mm
22-pin leadless DFN package and operates over a –40°C
to 85°C temperature range.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.

of the fi lters is adjustable in the

–3dB

TYPICAL APPLICATION

Dual, Matched 9.7MHz Lowpass Filter

+

3V

V

INA

–

+

3V

V

INB

–

1

2

+

3

4

–

5

LTC6605-10

6

7

8

+

9

10

–

11

22

21

20

19

18

17

16

15

14

13

12

660510 TA01

0.1μF

0.1μF

0.1μF

0.1μF

Channel to Channel Phase Matching

120

352 TYPICAL UNITS

= 25°C

T

3V

V

–

OUTA

+

3V

V

–

OUTB

+

A

= 10MHz

f

100

IN

80

60

40

NUMBER OF UNITS

20

0

–1.0

–0.6 –0.2–0.4–0.8

0 0.6 0.80.40.2 1.0

PHASE MATCH (DEG)

660510 TA01b

660510f

1

LTC6605-10

(Note 1)

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

Total Supply Voltage (V+ to V–) ................................5.5V

Input Current (Note 2) ..........................................±10mA

Output Short-Circuit Duration (Note 3) ............ Indefi nite

Operating Temperature Range (Note 4).... –40°C to 85°C

Specifi ed Temperature Range (Note 5) ....–40°C to 85°C

Junction Temperature ........................................... 150°C

Storage Temperature Range ................... –65°C to 150°C

ORDER INFORMATION

TOP VIEW

+IN4 A

1

+IN1 A

2

BIAS A

3

–IN1 A

4

–IN4 A

5

–

V

6

+IN4 B

7

+IN1 B

8

BIAS B

9

–IN1 B

10

–IN4 B

11

22-LEAD (6mm × 3mm) PLASTIC DFN

EXPOSED PAD (PIN 23) IS V

DJC PACKAGE

T

= 150°C, θJA = 46.5°C/W

JMAX

22

–OUT A

+

A

21

V

–

V

20

V

19

OCMA

+OUT A

18

17

16

15

14

13

12

–

V

–OUT B

+

B

V

–

V

V

OCMB

+OUT B

23

–

, MUST BE SOLDERED TO PCB

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC6605CDJC-10#PBF LTC6605CDJC-10#TRPBF 660510 22-Lead (6mm × 3mm) Plastic DFN 0°C to 70°C
LTC6605IDJC-10#PBF LTC6605IDJC-10# TRPBF 660510 22-Lead (6mm × 3mm) Plastic DFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

DC ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. V+ = 3V, V– = 0V, V
R

= 10k. The fi lter is confi gured for a gain of 1, unless otherwise noted. VS is defi ned as (V+ – V–). V

BAL

V

–OUT

)/2. V

is defi ned as (V

INCM

INP

+ V

INM

)/2. V

is defi ned as (V

OUTDIFF

+OUT

– V

INCM

–OUT

). V

= V

= mid-supply, BIAS tied to V+, RL = Open,

OCM

is defi ned as (V

INDIFF

is defi ned as (V

OUTCM

– V

INP

). See Figure 1.

INM

+OUT

+

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

OS

Differential Offset Voltage (at Op Amp

VS = 2.7V to 5V

l

±0.25 ±1 mV

Inputs) (Note 6)

ΔVOS/ΔT Differential Offset Voltage Drift (at Op

Amp Inputs)

I

B

Input Bias Current (at Op Amp Inputs)
(Note 7)

I

OS

Input Offset Current

BIAS = V

+

BIAS = Floating
BIAS = V

+

BIAS = Floating

l
l

l

–60

l

–30

±1
±1

–25

–12.5

μV/°C
μV/°C

0
0

μA
μA

±1 μA

(at Op Amp Inputs) (Note 7)

2

660510f

LTC6605-10

DC ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
R

= 10k. The fi lter is confi gured for a gain of 1, unless otherwise noted. VS is defi ned as (V+ – V–). V

BAL

V

–OUT

)/2. V

is defi ned as (V

INCM

INP

+ V

INM

)/2. V

= 25°C. V+ = 3V, V– = 0V, V

A

is defi ned as (V

OUTDIFF

+OUT

– V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

INCM

Input Common Mode Voltage Range
(Note 8)

CMRR Common Mode Rejection Ratio

(ΔV

/ΔVOS) (Note 9)

INCM

PSRR Power Supply Rejection Ratio

(ΔV

/ΔVOS) (Note 10)

S

V

V

V
R
V

I

SC

V
I

S

OSCM

OCM

MID

VOCM

OUT

S

Common Mode Offset Voltage
(V

– V

OUTCM

OCM

)

Output Common Mode Range
(Valid Range for V

Self-Biased Voltage at the V
Input Resistance of V
Output Voltage Swing, High

(Measured Relative to V

Output Voltage Swing, Low
(Measured Relative to V

Pin) (Note 8)

OCM

OCM

+

)

–

)

OCM

Pin

Output Short-Circuit Current (Note 3) VS = 3V

Supply Voltage
Supply Current (per Channel) VS = 2.7V to 5V; BIAS = V

Pin VS = 3V

VS = 3V
V

= 5V

S

= 3V; ΔV

V

S

V

= 5V; ΔV

S

= 2.7V to 5V

V

S

= 3V

V

S

V

= 5V

S

= 3V

V

S

V

= 5V

S

= 3V; IL = 0mA

V

S

V

= 3V; IL = 5mA

S

V

= 3V; IL = 20mA

S

V

= 5V; IL = 0mA

S

V

= 5V; IL = 5mA

S

V

= 5V; IL = 20mA

S

= 3V; IL = 0mA

V

S

V

= 3V; IL = –5mA

S

V

= 3V; IL = –20mA

S

V

= 5V; IL = 0mA

S

V

= 5V; IL = –5mA

S

V

= 5V; IL = –20mA

S

V

= 5V

S

INCM
INCM

= 1.5V
= 2.5V

VS = 2.7V to 5V; BIAS = Floating
V

= 2.7V to 5V; BIAS = V

R
t
t

BIAS

ON

OFF

S

BIAS Pin Range for Shutdown Referenced to V
BIAS Pin Range for Medium Power Referenced to V
BIAS Pin Range for Full Power Referenced to V
BIAS Pin Self-Biased Voltage (Floating) Referenced to V
BIAS Pin Input Resistance
Turn-On Time VS = 3V, V
Turn- O f f Time VS = 3V, V

BIAS

BIAS

–

–

–

–

= V– to V
= V+ to V

+

–

–OUT

+

–

INCM

). V

= V

= mid-supply, BIAS tied to V+, RL = Open,

OCM

is defi ned as (V

INDIFF

l
l

l
l

l

l
l

l
l

l

l

l
l
l

l
l
l

l
l
l

l
l
l

l
l

l

l
l
l

l

l

l

l

l

–0.2
–0.2

1.1

1.1

1.475 1.5 1.525 V

12.5 18 23.5 kΩ

±40
±50

2.7 5.25 V

2.3 V

1.05 1.15 1.25 V
100 150 200 kΩ

is defi ned as (V

OUTCM

– V

INP

46
46

). See Figure 1.

INM

74
74

66 95 dB

±10
±10

245
285
415

350
390
550

120
135
195

175
200
270

±70
±95

33.1

16.2

0.35

00.4V

11.5V

400 ns
400 ns

1.7

4.7

±15
±15

2
4

450
525
750

625
700

1000

225
250
350

325
360
475

45

26.5

1.6

S

+OUT

+

V
V

dB
dB

mV
mV

V
V

mV
mV
mV

mV
mV
mV

mV
mV
mV

mV
mV
mV

mA
mA

mA
mA
mA

V

660510f

3

LTC6605-10

AC ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T

= 25°C. V+ = 3V, V– = 0V, V

A

otherwise noted. Filter confi gured as in Figure 2, unless otherwise noted. VS is defi ned as (V+ – V–). V
V

)/2. V

–OUT

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Gain Filter Gain ΔV

Phase Filter Phase ΔV

ΔGain Gain Match (Channel-to-Channel) ΔV

ΔPhase Phase Match (Channel-to-Channel) V

4V/V Gain Filter Gain in 4V/V Confi guration

TC Filter Cut-Off Frequency Temperature

f

O

Noise Integrated Output Noise

e

n

i

n

HD2 2nd Harmonic Distortion

HD3 3rd Harmonic Distortion

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: All pins are protected by steering diodes to either supply. If any
pin is driven beyond the LTC6605-10’s supply voltage, the excess input
current (current in excess of what it takes to drive that pin to the supply
rail) should be limited to less than 10mA.

Note 3: A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the output is shorted
indefi nitely. Long-term application of output currents in excess of the
Absolute Maximum Ratings may impair the life of the device.

Note 4: Both the LTC6605C and the LTC6605I are guaranteed functional
over the operating temperature range –40°C to 85°C.

is defi ned as (V

INCM

+IN

+ V

–IN

)/2. V

OUTDIFF

Inputs at ±IN1 Pins, ±IN4 Pins Floating
Channel Separation V

Coeffi cient

(BW = 10kHz to 20MHz)
Input Referred Noise Density (f = 1MHz) BIAS = V

Voltage Noise Density Referred to
Op Amp Inputs (f = 1MHz)

Current Noise Density Referred to
Op Amp Inputs (f = 1MHz)

f

= 5MHz; VIN = 2V

IN

f

= 5MHz; VIN = 2V

IN

Single-Ended

P-P

Single-Ended

P-P

is defi ned as (V

= ±0.125V, DC

IN

V

= 0.5V

INDIFF

V

INDIFF

V

INDIFF

V

INDIFF

V

INDIFF

= ±0.125V, DC

IN

V

INDIFF

V

INDIFF

V

INDIFF

= ±0.125V, DC

IN

V

INDIFF

V

INDIFF

V

INDIFF

INDIFF

V

INDIFF

V

INDIFF

ΔVIN = ±0.125V, DC

INDIFF

BIAS = V
BIAS = Floating

Figure 4, Gain = 1
Figure 4, Gain = 4
Figure 4, Gain = 5

BIAS = V
BIAS = Floating

BIAS = V
BIAS = Floating

BIAS = V
BIAS = Floating, R

BIAS = V
BIAS = Floating, R

= 0.5V
= 0.5V
= 0.5V
= 0.5V

= 0.5V
= 0.5V
= 0.5V

= 0.5V
= 0.5V
= 0.5V

= 0.5V
= 0.5V
= 0.5V

= 1V

+

+

+

+

+

+

P-P
P-P
P-P
P-P
P-P

P-P
P-P
P-P

P-P
P-P
P-P

P-P
P-P
P-P

P-P

– V

+OUT

, f = 5MHz
, f = 7.5MHz
, f = 10MHz
, f = 20MHz
, f = 50MHz

, f = 5MHz
, f = 7.5MHz
, f = 10MHz

, f = 5MHz
, f = 7.5MHz
, f = 10MHz

, f = 5MHz
, f = 7.5MHz
, f = 10MHz

, f = 5MHz –96 dB

= 400Ω

LOAD

= 400Ω

LOAD

Note 5: The LTC6605C is guaranteed to meet specifi ed performance
from 0°C to 70°C. The LTC6605C is designed, characterized and
expected to meet specifi ed performance from –40°C to 85°C, but is
not tested or QA sampled at these temperatures. The LTC6605I is
guaranteed to meet specifi ed performance from –40°C to 85°C.

Note 6: Output referred voltage offset is a function of gain. To determine
output referred voltage offset, or output voltage offset drift, multiply V
by the noise gain (1 + GAIN). See Figure 3.

Note 7: Input bias current is defi ned as the average of the currents
fl owing into the noninverting and inverting inputs of the internal amplifi er
and is calculated from measurements made at the pins of the IC. Input
offset current is defi ned as the difference of the currents fl owing into
the noninverting and inverting inputs of the internal amplifi er and is
calculated from measurements made at the pins of the IC.

INCM

–OUT

). V

= V

OCM

is defi ned as (V

INDIFF

= mid-supply, V

OUTCM

l

–0.25

l

–1.1

l

–2.35

l

–4.05

l

–11.75

l

–28

l

–0.2

l

–0.2

l

–0.3

l

–0.35

l

–1.1

l

–1.2

l

–1.2

l

11.85 12 12. 25 dB

= V+, unless

BIAS

is defi ned as (V

+ V

+IN

).

–IN

±0.05
–0.77

–1.89

–3.5
–11.1
–25.8

0.25
–0.4

–1.45

–3

–10.55

–24.8

0
–42.5
–63.2

–81.7

±0.05
±0.05
±0.05
±0.05

±0.2
±0.2
±0.2

0.2

0.2

0.3

0.35

1.1

1.2

1.2

–80

–260

69 μV

20

5

4

2.1

2.6
3

2.1

–90

–75

–106

–82

+OUT

+

dB
dB
dB
dB
dB
dB

Deg
Deg
Deg
Deg

dB
dB
dB
dB

Deg
Deg
Deg

ppm/°C
ppm/°C

RMS

nV/√Hz
nV/√Hz
nV/√Hz

nV/√Hz
nV/√Hz

pA/√Hz
pA/√Hz

dBc
dBc

dBc
dBc

OS

660510f

4

ELECTRICAL CHARACTERISTICS

LTC6605-10

Note 8: See the Applications Information section for a detailed
discussion of input and output common mode range. Input common
mode range is tested by measuring the differential DC gain with V
= mid-supply, and again with V

at the input common mode range

INCM

limits listed in the Electrical Characteristics table, with ΔV

= ±0.25V,

IN

INCM

verifying that the differential gain has not deviated from the mid-supply
common mode input case by more than 0.5%, and that the common
mode offset (V

) has not deviated from the mid-supply common

OSCM

mode offset by more than ±10mV.
Output common mode range is tested by measuring the differential

DC gain with V

pin at the output common range limits listed in the Electrical

V

OCM

= mid-supply, and again with voltage set on the

OCM

Characteristics table verifying that the differential gain has not
deviated from the mid-supply common mode input case by more than

0.5%, and that the common mode offset (V
more than ±10mV from the mid-supply case.

Note 9: CMRR is defi ned as the ratio of the change in the input common
mode voltage at the internal amplifi er inputs to the change in differential
input referred voltage offset (V

Note 10: Power supply rejection ratio (PSRR) is defi ned as the ratio of
the change in supply voltage to the change in differential input referred
voltage offset (V

TYPICAL PERFORMANCE CHARACTERISTICS

Supply Current vs Temperature Filter Gain vs Temperature

37.5

35.0

32.5

30.0

27.5

25.0

22.5

20.0

SUPPLY CURRENT (mA)

17.5

15.0

12.5
–60

–40 0

–20

TEMPERATURE (°C)

VS = 2.7V, BIAS = FLOAT

= 3V, BIAS = FLOAT

V

S

= 5V, BIAS = FLOAT

V

S

= 2.7V, BIAS = V

V

S

VS = 3V, BIAS = V
VS = 5V, BIAS = V

V

= V

OCM

20

= MID-SUPPLY

40

INCM

+
+
+

80

60

100

660510 G01

1.010

1.005

1.000

GAIN (V/V)

0.995

0.990
–60

).

OS

VS = 3V, BIAS = V
V

= V

INCM

5 RANDOM UNITS

–40 0

= MID-SUPPLY

OCM

–20

TEMPERATURE (°C)

) has not deviated by

OSCM

).

OS

+

80

20

60

40

100

660510 G02

–3dB Frequency vs Temperature

2.5

2.0

1.5

(%)

1.0

–3dB

0.5

0

–0.5

–1.0

–1.5

FREQUENCY SHIFT OF f

–2.0

–2.5

–60

–40 0

BIAS = FLOAT
BIAS = V

–20

TEMPERATURE (°C)

VS = 3V
V

INCM

+

20

Filter Frequency Response

0

= V

= 1.5V

OCM

80

60

40

100

660510 G03

–10

–20

–30

0.1

VS = 3V
V

INCM

BIAS = V
BIAS PIN FLOATING

= V

OCM

FREQUENCY (MHz)

GAIN MAGNITUDE (dB)

–40

–50

+

= MID SUPPLY

101.0 100 1000

660514 G04

660510f

5

LTC6605-10

TYPICAL PERFORMANCE CHARACTERISTICS

Harmonic Distortion
vs Frequency, BIAS High

–40

–50

–60

–70

–80

–90

DISTORTION (dBc)
–100

–110

–120

DIFFERENTIAL INPUTS, HD2
DIFFERENTIAL INPUTS, HD3
SINGLE-ENDED INPUTS, HD2
SINGLE-ENDED INPUTS, HD3

1

VIN = 2V

P-P,VS

= 400Ω DIFFERENTIAL, GAIN = 1V/ V

R

L

10 100

FREQUENCY (MHz)

= 3V

Harmonic Distortion vs Input
Common Mode Voltage (VS = 3V)

–40

–50

–60

–70

–80

–90

–100

DISTORTION (dBc)

–110

–120

–130

–0.5

01

INPUT COMMON MODE VOLTAGE (V)

VIN = 2V
BIAS = 3V, f = 3MHz

= 400Ω DIFFERENTIAL, GAIN = 1V/ V

R

L

DIFFERENTIAL INPUTS, HD2
DIFFERENTIAL INPUTS, HD3
SINGLE-ENDED INPUT, HD2
SINGLE-ENDED INPUT, HD3

0.5

= 1.5V

P-P,VOCM

1.5

2 2.5

660510 G05

660510 G08

–40

–50

–60

–70

–80

–90

DISTORTION (dBc)

–100

–110

–120

3

Harmonic Distortion
vs Frequency, BIAS Floating

–40

–50

–60

–70

–80

–90

DISTORTION (dBc)

–100

–110

–120

DIFFERENTIAL INPUTS, HD2
DIFFERENTIAL INPUTS, HD3
SINGLE-ENDED INPUTS, HD2
SINGLE-ENDED
INPUTS, HD3

1 10 100

VIN = 2V

= 400Ω DIFFERENTIAL, GAIN = 1V/ V

R

L

FREQUENCY (MHz)

= 3V

P-P,VS

Harmonic Distortion vs Input

3.53

= 5V)

S

Common Mode Voltage (V

DIFFERENTIAL
INPUTS, HD2
DIFFERENTIAL
INPUTS, HD3
SINGLE-ENDED
INPUT, HD2
SINGLE-ENDED
INPUT, HD3

0–0.5

0.5 2.52

P-P,VOCM

1.51

= 2.5V

INPUT COMMON MODE VOLTAGE (V)

VIN = 2V
BIAS = 5V, f = 3MHz

= 400Ω DIFFERENTIAL, GAIN = 1V/ V

R

L

4.5 54

660510 G09

660510 G06

Harmonic Distortion
vs Input Amplitude

–40

DIFFERENTIAL INPUTS, HD2
DIFFERENTIAL INPUTS, HD3

–50

SINGLE-ENDED
INPUTS, HD2

–60

SINGLE-ENDED
INPUTS, HD3

–70

–80

–90

DISTORTION (dBc)

–100

–110

–120

0

13

VS = 3V, BIAS TIED TO V+,V

= 400Ω, fIN = 3MHz, GAIN = 1V/ V

R

LOAD

Differential Output Noise
vs Frequency

1000

NOISE SPECTRAL DENSITY (nV/√Hz)

100

10

1

0.01

VS = 3V
BIAS TIED TO V

+

OUTPUT NOISE
SPECTRAL DENSITY
INTEGRATED OUTPUT
NOISE

0.1 1 10010
FREQUENCY (MHz)

OCM

5

660510 G07

= 1.5V

100

10

1

6

INTEGRATED NOISE (μV

RMS

)

2

V

IN

4

(V

)

P-P

= V

INCM

660510 G10

6

Channel Separation vs Frequency Overdrive Transient Response

–20

–30

–40

–50

–60

–70

–80

–90

CHANNEL SEPARATION (dB)

–100

–110

–120

0.1 10 100 1000

V

= 1V

IN

= 400Ω DIFFERENTIAL

R

L

+

BIAS = V
BIAS = FLOAT

1

FREQUENCY (MHz)

= 3V

P-P,VS

660510 G11

2.0

1.5

1.0

0.5

0

VOLTAGE (V)

–0.5

–1.0

–1.5

–2.0

VS = 3V, V
BIAS = 3V, R

OCM

= 1.5V

LOAD

50ns/DIV

= 400Ω

+OUT
–OUT
–IN4
+IN4

660510 G12

660510f

TEST CIRCUITS

LTC6605-10

LTC6605-10

400Ω

1

+

V

INP

100Ω

2

400Ω

125Ω

–

3

BIASBIAS

–

V

INM

+

100Ω

4

400Ω

5

125Ω

400Ω

81.5pF

48.2pF

+

–

48.2pF

81.5pF

25Ω

V

–OUT

22

21

0.1μF

–

20

+

+

V

36k

19

36k

–

V

18

660510 TC01

V

0.01μF

+OUT

+

V

0.1μF

–

V

0.1μF

V

OCM

25Ω

I

L

R

BAL

V

OUTCM

R

BAL

I

L

Figure 1. DC Test Circuit (Channel A Shown)

LTC6605-10

1μF

V

+IN

400Ω

1

100Ω

2

400Ω

125Ω

+

V

IN

3

BIASBIAS

–

1μF

100Ω

4

V

–IN

400Ω

5

125Ω

400Ω

81.5pF

48.2pF

+

–

48.2pF

81.5pF

V

–OUT

22

21

0.1μF

–

20

+

+

V

36k

19

36k

–

V

18

660510 TC02

V

0.01μF

+OUT

100Ω

V

OCM

100Ω

1μF

+

V

0.1μF

–

V

0.1μF

1μF

COILCRAFT
TTWB-4-B

50Ω

Figure 2. AC Test Circuit (Channel A Shown)

660510f

7

LTC6605-10

PIN FUNCTIONS

+IN4 A, –IN4 A, +IN4 B, –IN4 B (Pins 1, 5, 7, 11): Inputs
to Trimmed 400Ω Resistors. Can accept an input signal,
be fl oated, tied to an output pin, or connected to external
components.

+IN1 A, –IN1 A, +IN1 B, –IN1 B (Pins 2, 4, 8, 10): Inputs
to Trimmed 100Ω Resistors. Can accept an input signal,
be fl oated, tied to an output pin, or connected to external
components.

BIAS A, BIAS B (Pins 3, 9): Three-State Input to Select
Amplifi er Power Consumption. Drive low for shutdown,
drive high for full power, leave fl oating for medium power.
BIAS presents an input resistance of approximately 150k
to a voltage 1.15V above V

–

(Pins 6, 14, 17, 20): Negative Supply. All V– pins

V

should be connected to the same voltage, either a ground
plane or a negative supply rail.

–

.

V

pins sets the output common mode voltage of each fi lter
channel. If left fl oating, V
midway between V

V

A and B, Respectively. These are not connected to each
other internally.

–OUT A, +OUT A, –OUT B, +OUT B (Pins 22, 18, 16,

12): Differential Output Pins.
Exposed Pad (Pin 23): Always tie the underlying Exposed

Pad to V

to ground.

, V

OCMA

+

A, V+ B (Pins 21, 15): P os it i ve Su pp l y f or Fi l te r C ha nn e l

(Pins 19, 13): The voltage applied to these

OCMB

self-biases to a voltage

+

and V–.

–

. If split supplies are used, do not tie the pad

OCM

8

660510f

BLOCK DIAGRAM

+IN4 A

1

400Ω

400Ω

81.5pF

LTC6605-10

–OUT A

22

+IN1 A

BIAS A

–IN1 A

–IN4 A

+IN4 B

2

3

4

5

–

6

V

7

100Ω

BIAS

100Ω

400Ω

400Ω

125Ω

125Ω

400Ω

400Ω

48.2pF

–

+

48.2pF

81.5pF

81.5pF

+

V

A

21

+

–

V

20

–

V+ A

V

36k

V

19

18

17

16

OCMA

+OUT A

–

V

–OUT B

36k

–

+IN1 B

BIAS B

–IN1 B

–IN4 B

8

9

10

11

100Ω

BIAS

100Ω

400Ω

125Ω

125Ω

400Ω

48.2pF

–

+

48.2pF

81.5pF

+

15

V

B

+

–

14

V

–

V+ B

V

36k

V

OCMB

13

36k

–

+OUT B

12

660510 BD

660510f

9

LTC6605-10

APPLICATIONS INFORMATION

Functional Description

The LTC6605-10 is designed to make the implementation
of high frequency fully differential fi ltering functions very
easy. Two very low noise amplifi ers are surrounded by
precision matched resistors and precision matched capaci­tors enabling various fi lter functions to be implemented by
hard wiring pins. The amplifi ers are wide band, low noise
and low distortion fully dif ferential amplifi ers with accurate
output phase balancing. They are optimized for driving
low voltage, single-supply, differential input analog-to­digital converters (ADCs). The LTC6605-10 operates with
a supply voltage as low as 2.7V and accepts inputs up to
325mV below the V

–

power rail, which makes it ideal for
converting ground referenced, single-ended signals into
differential signals that are referenced to the user-supplied
common mode voltage. This is ideal for driving low volt­age, single-supply, differential input ADCs. The balanced
differential nature of the amplifi er and matched surround­ing components provide even-order harmonic distortion
cancellation, and low susceptibility to common mode
noise (like power supply noise). The LTC6605-10 can be
operated with a single-ended input and differential output,
or with a differential input and differential output.

The outputs of the LTC6605-10 can swing rail-to-rail.
They can source or sink a transient 70mA of current. Load

capacitances should be decoupled with at least 25Ω of
series resistance from each output.

Filter Frequency Response and Gain Adjustment

Figure 3 shows the fi lter architecture. The Laplace transfer
function can be expressed in the form of the following
generalized equation for a 2nd order lowpass fi lter:

V

OUT DIFF

()

V

IN DIFF

()

=

++

1

s

fQ

2

π

O

GAIN

•

2

π

()

2

s

f

,,

2

O

with GAIN, fO and Q as given in Figure 3.
Note that GAIN and Q of the fi lter are based on component

ratios, which both match and track extremely well over
temperature. The corner frequency f

of the fi lter is a

O

function of an RC product. This RC product is trimmed to
±1% and is not expected to drift by more than ±1% from
nominal over the entire temperature range –40°C to 85°C.
As a result, fully differential fi lters with tight magnitude,
phase tolerance and repeatability are achieved.

Various values for resistors R1 and R4 can be formed
by pin-strapping the internal 100Ω and 400Ω resis­tors, and optionally by including one or more external
resistors. Note that non-zero source resistance should be
combined with, and included in, R1.

+

–

10

V

IN(DIFF)

R2

400Ω

C2

81.5pF

R4A

R

R4B

R3

125Ω

+

EXT

–

R3

125Ω

R2

400Ω

R4 = R4A + R4B + R

R1

R1

C1

48.2pF

V

OUT(DIFF)

EXT

+

–

–

+

C1

48.2pF

C2

81.5pF

Figure 3. Filter Architecture and Equations

660510 F03

660510f

APPLICATIONS INFORMATION

LTC6605-10

Setting the passband gain (GAIN = R2/R1) only requires
choosing a value for R1, since R2 is a fi xed internal 400Ω.
Therefore, the following three gains can be easil y confi gured
without external components:

Table 1. Confi guring the Passband Gain Without External
Components

GAIN

(V/V)

GAIN (dB) R1 () INPUT PINS TO USE

1 0 400 Drive the 400Ω Resistors. Tie

the 100Ω Resisters Together.
4 12 100 Drive the 100Ω Resistors.
5 14 80 Drive the 400Ω and 100Ω

Resistors in Parallel.

The resonant frequency, fO, is independent of R1, and
therefore independent of the gain. For any LTC6605-10
fi lter confi guration that conforms to Figure 3, the f
fi xed at 11.36MHz. The f
combination of f

and Q. For any specifi c gain, Q is adjusted

O

frequency depends on the

–3dB

O

is

by the selection of R4.

Setting the f

Using an external resistor (R

Frequency

–3dB

EXT

), the f

frequency is ad-

–3dB

justable in the range of 9.7MHz to 14.0MHz (see Figure 3).
The minimum f
maximum f

–3dB

is set for R

–3dB

is arbitrarily set for a maximum passband

equal to 0Ω and the

EXT

gain peak less than 1dB.

Table 2. R
R1 = 400Ω, R4A = R4B = 100Ω

f

–3dB

Selection GAIN = 1,

EXT

(MHz) R

9.7 0
10 5.11

10.5 13.3
11 2 2.1

11.5 31. 6
12 41.2

12.5 52.3
13 64.9

13.5 80.6
14 97.6

EXT



Figure 4 shows three filter configurations with an

= 9.7MHz, without any external components. These

f

–3dB

fi lters have a Q = 0.61, which is an almost ideal Bessel
characteristic with linear phase.

Figure 5 shows three fi lter confi gurations that use some
external resistors, and are tailored for a very fl at ±0.7dB

11.2MHz passband.
Many other confi gurations are possible by using the equa-

tions in Figure 3. For example, external resistors can be
added to modify the value of R1 to confi gure GAIN ≠ 1. For
an even more fl exible fi lter IC with similar performance,
consider the LTC6601.

BIAS Pin

Each channel of the LTC6605-10 has a BIAS pin whose
function is to tailor both performance and power. The BIAS
pin can be modeled as a voltage source whose potential

–

is 1.15V above the V

supply and that has a Thevenin

equivalent resistance of 150k. This three-state pin has fi xed

–

logic levels relative to V

(see the Electrical Characteristics
table), and can be driven by any external source that can
drive the BIAS pin’s equivalent input impedance.

If the BIAS pin is tied to the positive supply, the part is
in a fully active state confi gured for highest performance
(lowest noise and lowest distortion).

If the BIAS pin is fl oated (left unconnected), the part is in a
fully active state, but with amplifi er currents reduced and
p e r f o r m a n c e s c a l e d b a c k t o p r e s e r v e p o w e r c o n s u m p t i o n .
Care should be taken to limit external leakage currents
to this pin to under 1μA to avoid putting the part in an
unexpected state.

–

If the BIAS pin is tied to the most negative supply (V

),
the part is in a low power shutdown mode with amplifi er
outputs disabled. In shutdown, all internal biasing current
sources are shut off, and the output pins each appear as
open colle ctor s with a non- linear capacitor in p arallel and
steering diodes to either supply. Because of the non-linear
capacitance, the outputs can still sink and source small
amounts of transient current if exposed to signifi cant
voltage transients. Using this function to wire-OR outputs
together is not recommended.

660510f

11

LTC6605-10

APPLICATIONS INFORMATION

–10

1

+

2

4

–

5

7

+

8

10

–

11

f

= 9.7MHz

–3dB

GAIN = 1V/V (0dB)
ZIN = 800Ω

660510 F04a

22

18

16

12

1

+

2

4

–

5

7

+

8

10

–

11

f

= 9.7MHz

–3dB

GAIN = 4V/V (12dB)
ZIN = 200Ω

22

18

16

12

660510 F04b

1

+

2

4

–

5

7

+

8

10

–

11

f

= 9.7MHz

–3dB

GAIN = 5V/V (14dB)
ZIN = 160Ω

22

18

16

12

660510 F04c

Gain Response Gain Response Gain Response

20

10

0

20

10

0

–10

20

10

0

–10

–20

–30

GAIN MAGNITUDE (dB)

–40

–50

0.1
FREQUENCY (MHz)

–20

–40

–60

–80

–100

–120

PHASE (DEG)

–140

–160

–180

–200

–20

–30

GAIN MAGNITUDE (dB)

–40

–50

0.1
FREQUENCY (MHz)

101 100 1000

660510 G04d

–20

–30

GAIN MAGNITUDE (dB)

–40

–50

0.1
FREQUENCY (MHz)

101 100 1000

660510 G04e

Phase and Group Delay Response Small Signal Step Response

025

20

GROUP DELAY (ns)

0.1

PHASE

101 100 1000

FREQUENCY (MHz)

Figure 4. f

GROUP DELAY

= 9.7MHz Filter Confi gurations without External Components

–3dB

15

100mV/DIV

10

5

0

660510 G04i

GAIN = 1V/ V

20ns/DIV

101 100 1000

660510 G04f

66057 G04j

660510f

12

APPLICATIONS INFORMATION

LTC6605-10

–10

20

10

0

88.7Ω

88.7Ω

660510 F05a

22

44.2Ω

44.2Ω

18

16

44.2Ω

44.2Ω

12

1

+

2

4

–

5

7

+

8

10

–

11

±0.7dB 11.2MHz PASSBAND
GAIN = 2.774V/V (8.9dB)
Z

= 288Ω

IN

660510 F05b

22

18

16

12

1

44.2Ω

44.2Ω

44.2Ω

44.2Ω

+

2

4

–

5

7

+

8

10

–

11

±0.7dB 11.2MHz PASSBAND
GAIN = 3.774V/V (11.5dB)
ZIN = 212Ω

1

+

2

4

–

5

7

+

8

10

–

11

±0.7dB 11.2MHz PASSBAND
GAIN = 1V/V (0dB)
Z

= 800Ω

IN

Gain Response Gain Response Gain Response

20

10

0

–10

20

10

0

–10

22

18

16

12

660510 F05c

–20

–30

GAIN MAGNITUDE (dB)

–40

–50

0.1
FREQUENCY (MHz)

–100

–150

PHASE (DEG)

–200

–250

–20

–30

GAIN MAGNITUDE (dB)

–40

–50

101 100 1000

660510 G05d

0.1

Phase and Group Delay Response

025

–50

0.1

GROUP DELAY

PHASE

101 100 1000

FREQUENCY (MHz)

20

GROUP DELAY (ns)

15

10

5

0

660510 G05i

101 100 1000

FREQUENCY (MHz)

660510 G05e

Small Signal Step Response

GAIN = 1V/ V

100mV/DIV

–20

–30

GAIN MAGNITUDE (dB)

–40

–50

0.1

20ns/DIV

FREQUENCY (MHz)

101 100 1000

660510 G05f

66057 G04j

Figure 5. Flat Passband 11.2MHz Filter Confi gurations with Some External Resistors

660510f

13

LTC6605-10

APPLICATIONS INFORMATION

Input Impedance

Calculating the low frequency input impedance depends
on how the inputs are driven.

Figure 6 shows a simplifi ed low frequency equivalent
circuit. For balanced input sources (V

INP

= –V

INM

), the

low frequency input impedance is given by the equation:
R

INP

= R

INM

= R1

Therefore, the differential input impedance is simply:

V

INP

V

INM

= 2 • R1

R

INP

R1

+

–
–

R1

+

R

INM

Figure 6. Input Impedance

R2

R3

R3

R2

–

V

OUT

0.1μF

660510 F06

–

V

OUTDIFF

+

V

OUT

V

OCM

+

+

–

R

IN(DIFF)

the ESD protection diodes on the input pins, neither input

–

should swing further than 325mV below the V

power
rail. Therefore, the input common mode voltage should
be constrained to:

V



INDIFF

2



R1



R2



 V

INCM



V



OCM



V 325mV +

+

•V

 1.4V

()



 1+




R1
R2






The specifi cations in the Electrical Characteristics table are
a special case of the general equation above. For a single
3V power supply, (V
ΔV

= ±0.25V and R1 = R2, the valid input common

INDIFF

= 3V, V– = 0V) with V

OCM

= 1.5V,

+

mode range is:
–200mV ≤ V
Likewise, for a single 5V power supply, (V

with V

= 2.5V, ΔV

OCM

INCM

≤ 1.7V

INDIFF

+

= 5V, V– = 0V )

= ±0.25V and R1 = R2, the

valid input common mode range is:
–200mV ≤ V

INCM

≤ 4.7V

For single-ended inputs (V

= 0), the input impedance

INM

increases over the balanced differential case due to the
fact that the summing node (at the junction of R1, R2
and R3) moves in phase with V
impedance. Referring to Figure 6 with V

to bootstrap the input

INP

= 0, the input

INM

impedance looking into either input is:

1

2

R1



•



R1+ R2



R2












R

= R

INP

INM






1

Input Common Mode Voltage Range

The input common mode voltage is defi ned as the average
of the two inputs into resistor R1:

VV

+

V

INCM

INP INM

=

2

The input common mode range is a function of the fi lter
confi guration (GAIN), V

INDIFF

and the V

potential.

OCM

Referring to Figure 6, the summing junction where R1, R2
and R3 merge together should not swing within 1.4V of

+

power supply. Additionally, to avoid forward biasing

the V

Output Common Mode and V

OCM

Pin

The output common mode voltage is defi ned as the aver­age of the two outputs:

+ −

VV

OUTCM OCM

==

VV

+

OUT OUT

2

As the equation shows, the output common mode voltage
is independent of the input common mode voltage, and
is instead determined by the voltage on the V

OCM

pin, by

means of an internal feedback loop.
If the V

develops a potential halfway between the V
ages. The V

pin is left open, an internal resistor divider

OCM

pin can be overdriven to another voltage

OCM

+

and V– volt-

if desired. For example, when driving an ADC, if the ADC
makes a reference available for setting the common mode
v o l t a g e , i t c a n b e d i r e c t l y t i e d t o t h e V

p i n , a s l o n g a s t h e

OCM

ADC is capable of driving the input impedance presented by
the V
(R
the valid range that can be applied to the V

pin as listed in the Electrical Characteristics table

OCM

). The Electrical Characteristics table also specifi es

VOCM

OCM

pin.

14

660510f

APPLICATIONS INFORMATION

LTC6605-10

Noise

When comparing the LTC6605-10’s noise to that of
other amplifi ers, be sure to compare similar specifi ­cations. Standalone op amps often specify noise re­ferred to the inputs of the op amp. The LTC6605-10’s
internal op amp has input referred voltage noise of
only 2.1nV/√Hz. In addition to the noise generated by

2

e

nR1

R1

2

e

nR1

R1

Figure 7a. Differential Noise Model

+

2

I

n

2

e

nR3

R3

2

e

nR3

R3

–

2

I

n

the amplifi er, the surrounding feedback resistors also
contribute noise. A noise model is shown in Figure 7a.
The output spot noise generated by both the amplifi er
and the feedback components is given in Figure 7b.
Substituting the equation for Johnson noise of a resistor

2

(e

= 4kTR) into the equation in Figure 7b and simplify-

nR

ing gives the result shown in Figure 7c.

2

e

nR2

R2

2

e

ni

+

2

e

no

–

2

e

nR2

R2

660510 F07a

⎡

eno= eni•1+

eno= eni•1+

⎛
⎜

⎢

⎝

⎣

⎡

⎛
⎜

⎢

⎝

⎣

2

R2
R1

R2
R1

⎤

⎞
⎟

⎥

⎠

⎦

⎤

⎞
⎟

⎥

⎠

⎦

⎡

+ 2• In•R2+ R3 • 1+

⎢
⎣

2

⎡

+ 2• In•R2+ R3 • 1+

⎢
⎣

2

⎛
⎜

⎝

⎛
⎜

⎝

⎡
⎢

⎣

⎡
⎢

⎣

⎤

R2

⎥
⎦

R1

Figure 7b

⎤

R2

⎥
⎦

R1

Figure 7c

⎤

⎞

⎥

⎟
⎠

⎦

⎤

⎞

⎥

⎟
⎠

⎦

⎡

+ 2• e

2

•

⎢

nR1

⎣

+ 8•k•T• R2• 1+

2

⎤

⎛

⎞

R2

⎜

⎟

⎥

R1

⎝

⎠

⎦

⎡

⎛

⎢

⎜

⎢

⎝

⎣

⎡

+ 2• e

⎢
⎣

⎞

R2

⎟

R1

⎠

⎛

•1+

⎜

nR3

⎝

⎛

+ R3 • 1+

⎜
⎝

R2
R1

R2

R1

⎤

⎞
⎟

⎥

⎠

⎦

⎞
⎟

⎠

2

+ 2•e

2

⎤
⎥
⎥

⎦

nR2

2

660510f

15

LTC6605-10

APPLICATIONS INFORMATION

Board Layout and Bypass Capacitors

For single-supply applications it is recommended that a
high quality X5R or X7R, 0.1μF bypass capacitor be placed
directly between V
including the Exposed Pad, should be tied directly to a low
impedance ground plane with minimal routing.

For split power supplies, it is recommended that addi­tional high quality X5R or X7R, 0.1μF capacitors be used
to bypass pin V
minimal routing.

For driving heavy differential loads (< 200Ω), additional
bypass capacitance may be needed between V
optimal performance. Keep in mind that small geometry
(e.g., 0603) surface mount ceramic c apacitors have a much
higher self-resonant frequency than do leaded capacitors,
and perform best in high speed applications.

The V
quality ceramic capacitor (at least 0.01μF). In split-sup­ply applications, the V
ground or directly hard wired to ground.

Stray parasitic capacitances to any unused input pins
s h o u l d b e k e p t t o a m i n i m u m t o p r e v e n t d e v i a t i o n s f r o m t h e
ideal frequency response. The best approach is to remove
the solder pads for the unused component pins and strip
away any ground plane underneath. Floating unused pins
does not reduce the reliability of the part.

pins should be bypassed to ground with a high

OCM

+

and the adjacent V– pin. The V– pins,

+

to ground and V– to ground, again with

+

and V– for

pin can be either bypassed to

OCM

At the output, always keep in mind the differential nature
of the LTC6605-10, because it is important that the load
impedances seen by both outputs (stray or intended) be
as balanced and symmetric as possible. This will help pre­serve the balanced operation that minimizes the generation
of even-order harmonics and maximizes the rejection of
common mode signals and noise.

Driving ADCs

The LTC6605-10’s rail-to-rail differential output and
adjustable output common mode voltage make it ideal
for interfacing to differential input ADCs. These ADCs
are typically supplied from a single-supply voltage
which can be as low as 3V (2.7V minimum), and have an
optimal common mode input range near mid-supply. The
LTC6605-10 makes interfacing to these ADCs easy, by
providing antialiasing, single-ended to differential conver­sion and common mode level shifting.

The sampling process of ADCs creates a transient that is
caused by the switching in of the ADC sampling capaci­tor. This momentarily “shorts” the output of the amplifi er
as charge is transferred between amplifi er and sampling
capacitor. The amplifi er must recover and settle from this
load transient before the acquisition period has ended, for a
valid representation of the input signal. The LTC6605-10 w ill
settle quickly from these periodic load impulses. The RC
network between the outputs of the driver decouples the

16

660510f

APPLICATIONS INFORMATION

LTC6605-10

sampling transient of the ADC (see Figure 8). The capaci­tance serves to provide the bulk of the charge during the
sampling process, while the two resistors at the outputs
of the LTC6605-10 are used to dampen and attenuate
any charge injected by the ADC. The RC fi lter gives the
additional benefi t of band limiting broadband output noise.
The selection of the RC time constant is trial and error
for a given ADC, but the following guidelines are recom­mended. Choose an RC time constant that is smaller than
the reciprocal of the fi lter cutoff frequency confi gured by the
LTC6605-10. Time constants on the order of 2ns do a good
job of fi ltering broadband noise. Longer time constants

1/2 LTC6605-10

BIAS

1

2

3

4

5

+

–

CHANNEL A

+

V

IN

–

22

21

0.1μF

20

19

18

10nF

3V

1μF

V

OCM

improve SNR at the expense of settling time. The resistors
in the decoupling network should be at least 25Ω. Too large
of a resistor will leave insuffi cient settling time. Too small
of a resistor will not properly dampen the load transient
of the sampling process, prolonging the time required for
settling. In 16-bit applications, this will typically require a
minimum of eleven RC time constants. The 10Ω resistors
at the inputs to the ADC minimize the sampling transients
that charge the RC fi lter capacitors. For lowest distortion,
choose capacitors with low dielectric absorption, such as
a C0G multilayer ceramic capacitor.

R

R

τ = R • (C1 + 2 • C2)

C1

C2

C1

10Ω

10Ω

+

A

IN

–

A

IN

CONTROL

D15

•

•

ADC

V

CM

GND

2.2μF

D0

3.3V

1μF

660510 F08

Figure 8. Driving an ADC

660510f

17

LTC6605-10

TYPICAL APPLICATIONS

V

INA

Dual, Matched, 4th Order 10MHz Lowpass Filter

LTC6605-10 LTC6605-10

22

18

182Ω

1

+

2

4

–

5

1

+

2

4

–

5

22

18

V

OUTA

7

V

INB

8

10

11

THREE GAINS ARE POSSIBLE,
AS SHOWN IN FIGURE 4

+

–

10

0

–10

–20

–30

GAIN (dB)

–40

–50

–60

–70

182Ω

7

+

8

10

–

11

16

12

Gain Magnitude vs Frequency

0.1

1 10 100

FREQUENCY (MHz)

660510 TA03

660510 TA02

16

V

OUTB

12

18

660510f

PACKAGE DESCRIPTION

0.889

3.60 ±0.05

2.20 ±0.05

1.65 ±0.05
(2 SIDES)

5.35 ± 0.05
(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

DJC Package

22-Lead Plastic DFN (6mm × 3mm)

(Reference LTC DWG # 05-08-1714)

0.70 ±0.05

R = 0.10

0.889

PACKAGE
OUTLINE

0.25 ± 0.05

0.50 BSC

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. APPLY SOLDER MASK TO AREAS THAT

3. DRAWING IS NOT TO SCALE

LTC6605-10

ARE NOT SOLDERED

6.00 ±0.10
(2 SIDES)

3.00 ±0.10

PIN 1

TOP MARK

(NOTE 6)

0.200 REF

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

(2 SIDES)

0.75 ±0.05

1.65 ± 0.10
(2 SIDES)

0.00 – 0.05

R = 0.115

5.35 ± 0.10
(2 SIDES)

TYP

0.889

0.25 ± 0.05

0.50 BSC

(DJC) DFN 0605

0.889

R = 0.10

TYP

11

BOTTOM VIEW—EXPOSED PAD

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE

0.40 ± 0.05

2212

1

PIN #1 NOTCH
R0.30 TYP OR

0.25mm × 45°
CHAMFER

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
Howev er, no resp onsi bilit y is a ssume d for it s use. L inea r Technol ogy Co rpor atio n make s no repr esen ta­t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r ib e d h e r e i n w i ll no t i n f r i ng e o n e x i s t i n g p a t e n t r i g h t s .

660510f

19

LTC6605-10

TYPICAL APPLICATION

Dual Matched, 3rd Order 7.5MHz Lowpass Filter

V

INA

V

INB

301Ω

301Ω

301Ω

301Ω

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

LTC6605-10

1

+

270pF
1%

270pF
1%

2

4

–

5

7

+

8

10

–

11

Gain Magnitude vs Frequency

10

0

0.1

1 10 100

FREQUENCY (MHz)

660510 TA04

660510 TA05

22

V

OUTA

18

16

V

OUTB

12

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1568 4th Order Filter Building Block Lowpass and Bandpass Responses Up to 10MHz
LTC6404 Rail-to-Rail Output Differential Op Amp 1.5nV/√Hz Noise, –95dBc Distortion at 10MHz
LTC6406 3GHz Rail-to-Rail Input Differential Op Amp 1.6nV/√Hz Noise, –72dBc Distortion at 50MHz, 18mA
LT6 600 -2.5/LT6 600-5/

LT6600-10/LT6600-15/
LT6600-20

LTC6601 Differential Pin-Confi gurable 2nd Order Filter

LT6604-2.5/LT6604-5 Dual Differential 4th Order Lowpass Filters Cut-Off Frequencies of 2.5MHz or 5MHz

Linear Technology Corporation

20

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

Differential 4th Order Lowpass Filters Cut-Off Frequencies of 2.5MHz/5MHz/10MHz/15MHz/20MHz

7MHz to 25MHz Pin-Confi gurable

Building Block

LT 1208 • PRINTED IN USA

●

www.linear.com

© LINEAR TECHNOLOGY CORPORATION 2008

660510f