Datasheet LTC6416 Datasheet (Linear) [ru]

LTC6416

2 GHz Low Noise Differential

16-Bit ADC Buffer

FEATURES

n

2GHz –3dB Small Signal Bandwidth

n

300MHz ±0.1dB Bandwidth

n

1.8nV/√Hz Output Noise

n

46.25dBm Equivalent OIP3 at 140MHz

n

40.25dBm Equivalent OIP3 Up to 300MHz

n

–81dBc/–72dBc HD2/HD3 at 140MHz, 2V

n

–84.5dBc IM3 at 140MHz, 2V

n

–74dBc/–67.5dBc HD2/HD3 at 300MHz, 2V

n

–72.5dBc IM3 at 300MHz, 2V

n

Programmable High Speed, Fast Recovery

Out Composite

P-P

Out Composite

P-P

P-P

Output Clamping

n

DC-Coupled Signal Path

n

Operates on Single 2.7V to 3.9V Supply

n

Low Power: 150mW on 3.6V

n

2mm × 3mm 10-Pin DFN Package

APPLICATIONS

n

Differential ADC Driver

n

IF Sampling Receivers

n

Impedance Transformer

n

SAW Filter Interface

n

CCD Buffer

Out

P-P

Out

DESCRIPTION

The LTC®6416 is a differential unity gain buffer designed
to drive 16-bit ADCs with extremely low output noise
and excellent linearity beyond 300MHz. Differential input
impedance is 12k, allowing 1:4 and 1:8 transformers to
be used at the input to achieve additional system gain.

With no external biasing or gain setting components and
a fl ow-through pinout, the LTC6416 is very easy to use.
It can be DC-coupled and has a common mode output
offset of –40mV. If the input signals are AC-coupled, the
LTC6416 input pins are internally biased to provide an
output common mode voltage that is set by the voltage
on the V

In addition the LTC6416 has high speed, fast recovery
clamping circuitry to limit output signal swing. Both the
high and low clamp voltages are internally biased to allow
maximum output swing but are also user programmable
via the CLLO and CLHI pins.

Supply current is nominally 42mA and the LTC6416 oper­ates on supply voltages ranging from 2.7V to 3.9V.

The LTC6416 is packaged in a 10-lead 3mm × 2mm DFN
package. Pinout is optimized for placement directly adjacent
to Linear’s high speed 12-, 14- and 16-bit ADCs.

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.

CM

pin.

TYPICAL APPLICATION

LTC6416 Driving LTC2208 ADC – 140MHz IF

3.6V

0.1µF

200

200

0.1µF

CLHI

+

IN

LTC6416

–

IN

CLLO

V

GND

+

V

GND

50

+
–

680pF

1:8

MINI-CIRCUITS

TCM8-1+

CM

OUT

OUT

LTC6416 Driving LTC2208 ADC

with 1:8 Transformer fIN =140MHz,

fS = 130MHz, –1dBFS, PGA = 1

0

–10

–20
–30

–40

2.2µF

25

+

–

25

1.5pF

1pF

1.5pF

AIN

AIN

+

–

LTC2208

PGA = 1

CLOCK

(130MHz)

3.3V

16

6416 TA01a

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110
–120

0

MEASURED USING DC1257B

WITH MINI-CIRCUIT TCM8-1+

10

3020

FREQUENCY (MHz)

V+ = 3.6V

HD2 = –94dBc

HD3 = –89.1dBc

SFDR = 89.1dB

SNR = 70.7dB

1:8 TRANSFORMER

40 50

6416 TA01b

60

6416f

1

LTC6416

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

(Note 1)

Total Supply Voltage (V+ to GND)................................4V

Input Current (CLLO, CLHI, V

+

Output Current (OUT

, OUT–) ...........................±22.5mA

, IN+, IN–) ...........±10mA

CM

Operating Temperature Range (Note 2).... –40°C to 85°C

Specifi ed Temperature Range (Note 3) .... –40°C to 85°C

Storage Temperature Range ...................–65°C to 150°C

Junction Temperature ........................................... 150°C

10-LEAD (3mm s 2mm) PLASTIC DFN

T

JMAX

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

TOP VIEW

+

1

V

CM

2

CLHI

+

3

IN

–

4

IN

5

CLLO

DDB PACKAGE

= 150°C, θJA = 76°C/W, θJC = 13.5°C/W

10

V

9

GND

11

+

8

OUT

–

7

OUT

6

GND

ORDER INFORMATION

Lead Free Finish

TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC6416CDDB#TRMPBF LTC6416CDDB#TRPBF LDDY
LTC6416IDDB#TRMPBF LTC6416IDDB#TRPBF LDDY

10-Lead (3mm × 2mm) Plastic DFN

10-Lead (3mm × 2mm) Plastic DFN
TRM = 500 pieces. *Temperature grades are identifi ed by a label on the shipping container.
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.

Consult LTC Marketing for information on lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

0°C to 70°C
–40°C to 85°C

3.6V ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full
operating temperature range, otherwise specifi cations are at TA = 25°C. V+ = 3.6V, GND = 0V, No R
CLHI = V+, CLLO = 0V unless otherwise noted. V
defi ned as (IN+ – IN–). V

is defi ned as (OUT+ – OUT–). See DC test circuit schematic.

OUTDIFF

is defi ned as (IN+ + IN–)/2. V

INCM

is defi ned as (OUT+ + OUT–)/2. V

OUTCM

LOAD

, C

= 6pF. VCM = 1.25V,

LOAD

INDIFF

is

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Input/Output Characteristics

G

DIFF

TCG

DIFF

V

SWINGDIFF

V

SWINGMIN

V

SWINGMAX

I

OUT

V

OS

Differential Input Offset Voltage Drift

TCV

OS

V

IOCM

Differential Gain V

Differential Gain Temperature Coeffi cient
Differential Output Voltage Swing V

Output Voltage Swing Low Single-Ended Measurement of OUT+,

Output Voltage Swing High Single-Ended Measurement of OUT+,

Output Current Drive Single-Ended Measurement of OUT+,

Differential Input Offset Voltage IN+ = IN– = 1.25V, VOS = V

Common Mode Offset Voltage, Input to
Output

= ±1.2V Differential

INDIFF

, V

OUTDIFF

OUT

OUT

OUT

G

DIFF

V

OUTCM

INDIFF

–

. V

INDIFF

–

. V

INDIFF

–

– V

INCM

= ±2.3V

= ±2.3V

= ±2.3V

OUTDIFF

–0.3

l

–0.4

l

3.7

l

3.3

–0.15 0

0

dB
dB

–0.00033 dB/°C

4.2 V

P-P

V

P-P

0.2 0.3

l

2.15

l

2

l

±20 mA

/

–5

l

–10

l

–65

l

–75

2.3 V

–0.5 5

1µV/°C

–47 –15

0.35

10

–5

mV
mV

mV
mV

6416f

V
V

V

2

LTC6416

3.6V ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full
operating temperature range, otherwise specifi cations are at T
CLHI = V+, CLLO = 0V unless otherwise noted. V
defi ned as (IN+ – IN–). V

is defi ned as (OUT+ – OUT–). See DC test circuit schematic.

OUTDIFF

is defi ned as (IN+ + IN–)/2. V

INCM

= 25°C. V+ = 3.6V, GND = 0V, No R

A

is defi ned as (OUT+ + OUT–)/2. V

OUTCM

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IVR

MIN

Input Voltage Range, IN+, IN–

Defi ned by Output Voltage Swing Test

l

(Minimum) (Single-Ended)

IVR

MAX

Input Voltage Range IN+, IN–

Defi ned by Output Voltage Swing Test

l

(Maximum) (Single-Ended)

I

B

R

INDIFF

C

INDIFF

R

INCM

Input Bias Current, IN+, IN
Differential Input Resistance V
Differential Input Capacitance 1 pF
Input Common Mode Resistance IN+ = IN– = 0.65V to 1.85V 6 k

–

IN+ = IN– = 1.25V

CMRR Common Mode Rejection Ratio IN

CMRR = (V

e

N

i

N

Input Noise Voltage Density f = 100kHz 1.8 nV/√Hz
Input Noise Current Density f = 100kHz 6.5 pA/√Hz

= ±1.2V

INDIFF

+

= IN– = 0.65V to 1.85V,

OUTDIFF/GDIFF

/1.2V)

l

l

l

Output Common Mode Voltage Control

G

CM

V

INCMDEFAULT

(VCM – V

V

OS

V

OUTCMDEFAULT

(VCM – V

V

OS

V

OUTCMMIN

V

OUTCMMAX

V

CMDEFAULT

R

VCM

C

VCM

I

BVCM

VCM Pin Common Mode Gain VCM = 0.65V to 1.85V
Default Input Common Mode Voltage V

) Offset Voltage, VCM to V

INCM

Default Output Common Mode Voltage Inputs Floating, VCM Pin Floating

) Offset Voltage, VCM to V

OUTCM

Output Common Mode Voltage Range
(Minimum)

Output Common Mode Voltage Range
(Maximum)

VCM Pin Default Voltage
VCM Pin Input Resistance
VCM Pin Input Capacitance 1 pF
VCM Pin Bias Current VCM = 1.25V

INCM

OUTCM

. IN+, IN–, VCM Pin Floating

INCM

VCM – V

VCM – V

, VCM = 1.25V

INCM

, VCM = 1.25V

OUTCM

VCM = 0.1V

VCM = 2.7V

l

l

l

l

l

l

l

l

l

l

DC Clamping Characteristics

V

CLHIDEFAULT

(CLHI – V

V

OS

V

CLLODEFAULT

(CLLO – V

V

OS

R

CLHI

IB

CLHI

R

CLLO

I

BCLLO

Default Output Clamp Voltage, High

) Offset Voltage, CLHI to V

OUTCM

Default Output Clamp Voltage, Low

) Offset Voltage, CLLO to V

OUTCM

CLHI Pin Input Resistance V
CLHI Pin Bias Current V
CLLO Pin Input Resistance V
CLLO Pin Bias Current V

OUTCM

OUTCM

CLHI

CLHI

CLLO

CLLO

= 2.45V
= 2.45V

= 0.275V
= 0.275V

l

l

l

l

l

l

l

l

Power Supply

V

S

I

S

Supply Voltage Range
Supply Current

PSRR Power Supply Rejection Ratio VS = 2.7V to 3.6V

l

l

l

, C

LOAD

= 6pF. VCM = 1.25V,

LOAD

INDIFF

is

0.1 V

2.4 V

–15 –5 15 µA

91215k

63.5

59.6

83 dB

dB

0.9 0.96 1.05 V/V

1.3 1.38 1.45 V

–70 –28 70 mV

1.25 1.34 1.45 V
–60 15 60 mV

0.37 0.5

0.55

2.3

2.46 V

2.25

1.325 1.36 1.425 V

2.5 3.8 5.1 k

–50 –32 50 µA

2.3 2.45 2.6 V

–55 13 55 mV

0.125 0.265 0.425 V
–120 –70 0 mV

3 4.1 5 k

–25 –1 25 µA

1.5 2.3 3.2 k

–25 4.5 25 µA

2.7 3.9 V
33 42 51

54

mA
mA

57.5 80 dB

V
V

V

6416f

3

LTC6416

3.3V ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full
operating temperature range, otherwise specifi cations are at T
CLHI = V+, CLLO = 0V unless otherwise noted. V
defi ned as (IN+ – IN–). V

is defi ned as (OUT+ – OUT–). See DC test circuit schematic.

OUTDIFF

is defi ned as (IN+ + IN–)/2. V

INCM

= 25°C. V+ = 3.3V, GND = 0V, No R

A

is defi ned as (OUT+ + OUT–)/2. V

OUTCM

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Input/Output Characteristics

G

DIFF

TCG
V

OUTDIFF

V

OUTMIN

V

OUTMAX

I

OUT

V

OS

DIFF

Differential Gain V

Differential Gain Temperature Coeffi cient
Differential Output Voltage Swing V

Output Voltage Swing Low Single-Ended Measurement of OUT+,

Output Voltage Swing High Single-Ended Measurement of OUT+,

Output Current Drive (Note 4) Single-Ended Measurement of OUT+,

Differential Input Offset Voltage IN+ = IN– = 1.25V, VOS = V

TCVOS Differential Input Offset Voltage Drift
V

IOCM

Common Mode Offset Voltage, Input to
Output

IVR

MIN

Input Voltage Range, IN+, IN–

= ±1.2V

INDIFF

= ±2.3V

INDIFF

–

OUT

. V

= ±2.3V

INDIFF

–

OUT

. V

= ±2.3V

INDIFF

–

OUT

/

G

DIFF

V

OUTCM

– V

INCM

OUTDIFF

Defi ned by Output Voltage Swing Test

l

l

l

l

l

l

l

l

l

l

(Minimum) (Single-Ended)

IVR

MAX

Input Voltage Range, IN+, IN–

Defi ned by Output Voltage Swing Test

l

(Maximum) (Single-Ended)

I

B

R

INDIFF

C

INDIFF

R

INCM

Input Bias Current, IN+, IN
Differential Input Resistance V
Differential Input Capacitance 1 pF
Input Common Mode Resistance IN+ = IN– = 0.65V to 1.85V 6 k

–

CMRR Common Mode Rejection Ratio IN

e

N

i

N

Input Noise Voltage Density f = 100kHz 1.8 nV/√Hz
Input Noise Current Density f = 100kHz 6.5 pA/√Hz

IN+ = IN– = 1.25V

= ±1.2V

INDIFF

+

= IN– = 0.65V to 1.85V = ∆V

CMRR = (V

OUTDIFF/GDIFF

/∆V

INCM

INCM

)

l

l

,

l

Output Common Mode Voltage Control

G

CM

V

INCMDEFAULT

VOS (VCM – V
V

OUTCMDEFAULT

(VCM – V

V

OS

V

OUTCMMIN

V

OUTCMMAX

V

CMDEFAULT

R

VCM

C

VCM

I

BVCM

VCM Pin Common Mode Gain VCM = 0.65V to 1.85V
Default Input Common Mode Voltage V

) Offset Voltage, VCM to V

INCM

Default Output Common Mode Voltage Inputs Floating, VCM Pin Floating

) Offset Voltage, VCM to V

OUTCM

Output Common Mode Voltage
(Minimum)

Output Common Mode Voltage
(Maximum)

VCM Pin Default Voltage
VCM Pin Input Resistance
VCM Pin Input Capacitance 1 pF
VCM Pin Bias Current VCM = 1.25V

INCM

OUTCM

. IN+, IN–, VCM Pin Floating

INCM

VCM – V

VCM – V

, VCM = 1.25V

INCM

, VCM = 1.25V

OUTCM

VCM = 0.1V

VCM = 2.4V

l

l

l

l

l

l

l

l

l

l

, C

LOAD

–0.3
–0.4

= 6pF. VCM = 1.25V,

LOAD

–0.15 0

INDIFF

0

is

dB
dB

–0.00033 dB/°C

3.5

3.2

4V

P-P

V

P-P

0.2 0.3

0.35

2.05

2.2 V

1.95

±20 mA

–5

–10

–0.1 5

10

mV
mV

1µV/°C

–65
–75

–40 –15

–5

mV
mV

0.1 V

2.4 V

–15 –4 15 µA

91215k

63.5

59.6

83 dB

dB

0.9 0.96 1.05 V/V

1.2 1.28 1.35 V

–70 –26 70 mV

1.15 1.24 1.35 V
–60 14 60 mV

0.34 0.5

0.55

2.05

2.16 V

2

1.2 1.25 1.3 V

2.5 3.8 5.1 k

–10 0.2 10 µA

V
V

V

V
V

V

4

6416f

LTC6416

3.3V ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full
operating temperature range, otherwise specifi cations are at T
CLHI = V+, CLLO = 0V unless otherwise noted. V
defi ned as (IN+ – IN–). V

is defi ned as (OUT+ – OUT–). See DC test circuit schematic.

OUTDIFF

is defi ned as (IN+ + IN–)/2. V

INCM

= 25°C. V+ = 3.3V, GND = 0V, No R

A

is defi ned as (OUT+ + OUT–)/2. V

OUTCM

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Clamping Characteristics

V

CLHIDEFAULT

(CLHI – V

V

OS

V

CLLODEFAULT

(CLLO – V

V

OS

R

CLHI

IB

CLHI

R

CLLO

I

BCLLO

Default Output Clamp Voltage, High

) Offset Voltage, CLHI to V

OUTCM

Default Output Clamp Voltage, Low

) Offset Voltage, CLLO to V

OUTCM

CLHI Pin Input Resistance V
CLHI Pin Bias Current V
CLLO Pin Input Resistance V
CLLO Pin Bias Current V

OUTCM

OUTCM

CLHI

CLHI

CLLO

CLLO

= 2.25V
= 2.25V

= 0.25V
= 0.25V

l

l

l

l

l

l

l

l

Power Supply

V

S

I

S

Supply Voltage Range
Supply Current

PSRR Power Supply Rejection Ratio VS = 2.7V to 3.6V

l

l

l

, C

LOAD

= 6pF. VCM = 1.25V,

LOAD

INDIFF

is

2.1 2.23 2.4 V

–55 4 55 mV

0.1 0.25 0.4 V

–120 –72 0 mV

3 4.1 5 k

–25 –1 25 µA

1.5 2.3 3.2 k

–25 3 25 µA

2.7 3.9 V
33 42 51

54

57.5 80 dB

mA
mA

AC ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. V+ = 3.3V and 3.6V unless otherwise noted, GND = 0V, No R
C

= 6pF. VCM = 1.25V, CLHI = VCC, CLLO = 0V unless otherwise noted. V

LOAD

(OUT+ + OUT–)/2. V

is defi ned as (IN+ – IN–). V

INDIFF

is defi ned as (OUT+ – OUT–). See DC test circuit schematic.

OUTDIFF

is defi ned as (IN+ + IN–)/2. V

INCM

is defi ned as

OUTCM

LOAD

,

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Differential AC Characteristics

–3dBBW –3dB Bandwidth 200mV

0.1dBBW ±0.1dB Bandwidth 200mV

0.5dBBW ±0.5dB Bandwidth 200mV

Differential 2 GHz

P-P,OUT

Differential 0.3 GHz

P-P,OUT

Differential 1.4 GHz

P-P,OUT

1/f 1/f Noise Corner 25 kHz
SR Slew Rate Differential 3.4 V/ns
t

S1%

1% Settling Time 2V

Common Mode AC Characteristics (V

–3dBBW

VCMVCM

Pin Small Signal –3dB BW VCM = 0.1V

CM

Pin)

P-P,OUT

, Measured Single-Ended

P-P

1.8 ns

9MHz

at Output

SR

CM

Common Mode Slew Rate Measured Single-Ended at Output 40 V/µs

AC Clamping Characteristics

t

OVDR

Overdrive Recovery Time 1.9V

P-P,OUT

5ns

AC Linearity
70MHz Signal

+

HD2 Second Harmonic Distortion V

= 3.3V, VCM = 1.05V, V
V+ = 3.3V, VCM = 1.25V, V
V+ = 3.6V, VCM = 1.05V, V
V+ = 3.6V, VCM = 1.25V, V

OUTDIFF
OUTDIFF
OUTDIFF
OUTDIFF

= 2V
= 2V
= 2V
= 2V

P-P
P-P
P-P
P-P

–83.5

–71
–78.5
–88.5

dBc
dBc
dBc
dBc

6416f

5

LTC6416

AC ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
C

= 6pF. VCM = 1.25V, CLHI = VCC, CLLO = 0V unless otherwise noted. V

LOAD

(OUT+ + OUT–)/2. V

is defi ned as (IN+ – IN–). V

INDIFF

= 25°C. V+ = 3.3V and 3.6V unless otherwise noted, GND = 0V, No R

A

is defi ned as (OUT+ – OUT–). See DC test circuit schematic.

OUTDIFF

is defi ned as (IN+ + IN–)/2. V

INCM

is defi ned as

OUTCM

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

HD3 Third Harmonic Distortion V

IM3 Output Third Order Intermodulation

Distortion

OIP3 Output Third Order Intercept (Equivalent)

(Note 5)

P1dB Output 1dB Compression Point (Equivalent)

= 3.3V, VCM = 1.05V, V
V+ = 3.3V, VCM = 1.25V, V
V+ = 3.6V, VCM = 1.05V, V
V+ = 3.6V, VCM = 1.25V, V

+

V

= 3.3V, VCM = 1.05V, V
V+ = 3.6V, VCM = 1.25V, V

V+ = 3.3V, VCM = 1.05V, V
V+ = 3.6V, VCM = 1.25V, V

V+ = 3.6V, VCM = 1.25V 14.1 dBm

OUTDIFF
OUTDIFF
OUTDIFF
OUTDIFF

OUTDIFF
OUTDIFF

OUTDIFF
OUTDIFF

= 2V
= 2V
= 2V
= 2V

= 2V
= 2V

= 2V
= 2V

P-P
P-P
P-P
P-P

P-P
P-P

P-P
P-P

–73
–60

–94.5

–83

–76.5

–86

42.25
47

+

(Note 5)

140MHz Signal

HD2 Second Harmonic Distortion V

HD3 Third Harmonic Distortion V

IM3 Output Third Order Intermodulation

Distortion

OIP3 Output Third Order Intercept (Equivalent)

(Note 5)

P1dB Output 1dB Compression Point (Equivalent)

= 3.3V, VCM = 1.05V, V
V+ = 3.3V, VCM = 1.25V, V
V+ = 3.6V, VCM = 1.05V, V
V+ = 3.6V, VCM = 1.25V, V

+

= 3.3V, VCM = 1.05V, V
V+ = 3.3V, VCM = 1.25V, V
V+ = 3.6V, VCM = 1.05V, V
V+ = 3.6V, VCM = 1.25V, V

+

V

= 3.3V, VCM = 1.05V, V
V+ = 3.6V, VCM = 1.25V, V

V+ = 3.3V, VCM = 1.05V, V
V+ = 3.6V, VCM = 1.25V, V

V+ = 3.6V, VCM = 1.25V 14.1 dBm

OUTDIFF
OUTDIFF
OUTDIFF
OUTDIFF

OUTDIFF
OUTDIFF
OUTDIFF
OUTDIFF

OUTDIFF
OUTDIFF

OUTDIFF
OUTDIFF

= 2V
= 2V
= 2V
= 2V

= 2V
= 2V
= 2V
= 2V

= 2V
= 2V

= 2V
= 2V

P-P
P-P
P-P
P-P

P-P
P-P
P-P
P-P

P-P
P-P

P-P
P-P

–79.5
–75.5

–73
–81

–64
–55
–70
–72

–75

–84.5

41.5

46.25

+

(Note 5)

300MHz Signal

HD2 Second Harmonic Distortion V

HD3 Third Harmonic Distortion V

IM3 Output Third Order Intermodulation

Distortion

OIP3 Output Third Order Intercept (Equivalent)

(Note 5)

P1dB Output 1dB Compression Point (Equivalent)

= 3.3V, VCM = 1.05V, V
V+ = 3.3V, VCM = 1.25V, V
V+ = 3.6V, VCM = 1.05V, V
V+ = 3.6V, VCM = 1.25V, V

+

= 3.3V, VCM = 1.05V, V
V+ = 3.3V, VCM = 1.25V, V
V+ = 3.6V, VCM = 1.05V, V
V+ = 3.6V, VCM = 1.25V, V

+

V

= 3.3V, VCM = 1.05V, V
V+ = 3.6V, VCM = 1.25V, V

V+ = 3.3V, VCM = 1.05V, V
V+ = 3.6V, VCM = 1.25V, V

+

= 3.6V, VCM = 1.25V 12.9 dBm

V

OUTDIFF
OUTDIFF
OUTDIFF
OUTDIFF

OUTDIFF
OUTDIFF
OUTDIFF
OUTDIFF

OUTDIFF
OUTDIFF

OUTDIFF
OUTDIFF

= 2V
= 2V
= 2V
= 2V

= 2V
= 2V
= 2V
= 2V

= 2V
= 2V

= 2V
= 2V

P-P
P-P
P-P
P-P

P-P
P-P
P-P
P-P

P-P
P-P

P-P
P-P

36

–75
–65

–69.5

–74
–59

–51.5

–63

–67.5
–68.5

–72.5 –64

38.25

40.25

+

(Note 5)

LOAD

,

dBc
dBc
dBc
dBc

dBc
dBc

dBm
dBm

dBc
dBc
dBc
dBc

dBc
dBc
dBc
dBc

dBc
dBc

dBm
dBm

dBc
dBc
dBc
dBc

dBc
dBc
dBc
dBc

dBc
dBc

dBm
dBm

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: The LTC6416C/LTC6416I is guaranteed functional over the
operating temperature range of –40°C to 85°C.

Note 3: The LTC6416C is guaranteed to meet specifi ed performance from
0°C to 70°C. It is designed, characterized and expected to meet specifi ed
performance from –40°C and 85°C but is not tested or QA sampled

6

at these temperatures. The LT6416I is guaranteed to meet specifi ed
performance from –40°C to 85°C.

Note 4: This parameter is pulse tested.
Note 5: Since the LTC6416 is a voltage-output buffer, a resistive load is not

required when driving an AD converter. Therefore, typical output power is very
small. In order to compare the LTC6416 with amplifi ers that require a 50
output load, the LTC6416 output voltage swing driving a given R

is converted

L

to OIP3 and P1dB as if it were driving a 50 load. Using this modifi ed
convention, 2V

is by defi nition equal to 10dBm, regardless of actual RL.

P-P

6416f

TYPICAL PERFORMANCE CHARACTERISTICS

LTC6416

Differential Forward Gain (S21)
vs Frequency

2

V+ = 3.3V

0

–2

–4

–6

–8

–10

DIFFERENTIAL GAIN (dB)

–12

–14

–16

10 1000 10000100

FREQUENCY (MHz)

Differential Reverse Isolation
(S12) vs Frequency

–20

V+ = 3.3V

–30

–40

–50

–60

–70

–80

–90

DIFFERENTIAL REVERSE ISOLATION (dB)

–100

10 1000100

FREQUENCY (MHz)

6416 G01

6416 G04

Differential Input Return Loss
(S11) vs Frequency

0

V+ = 3.3V

–5

–10

–15

–20

S11 (dB)

–25

–30

–35

10 1000100

FREQUENCY (MHz)

Second and Third Harmonic
Distortion vs Frequency

–50

–60

–70

–80

HD2, HD3 (dBc)

V+ = 3.3V

–90

= 1.25V

V

CM

= 400

R

LOAD

= 2V

–100

V

OUT

10

DIFFERENTIAL

P-P

FREQUENCY (MHz)

100

HD3

HD2

6416 G02

6416 G05

500

Differential Output Return Loss
(S22) vs Frequency

0

V+ = 3.3V

–1

–2

–3

–4

–5

–6

–7

–8

–9

DIFFERENTIAL OUTPUT RETURN LOSS (dB)

–10

10 1000100

FREQUENCY (MHz)

Second and Third Harmonic
Distortion vs Frequency

–50

V+ = 3.6V

= 1.25V

V

CM

= 400

R

LOAD

–60

–70

–80

HD2, HD3 (dBc)

–90

–100

= 2V

V

OUT

10 100 500

DIFFERENTIAL

P-P

FREQUENCY (MHz)

HD3

HD2

6416 G03

6416 G06

6416f

7

LTC6416

TYPICAL PERFORMANCE CHARACTERISTICS

Second and Third Harmonic
Distortion vs Output Common
Mode Voltage (75MHz)

–50

V+ = 3.6V

= 400

R

LOAD

= 2V

V

OUT

–60

–70

–80

HD2, HD3 (dBc)

–90

–100

1.05 1.15 1.251.10 1.20 1.35 1.451.30 1.40

DIFFERENTIAL

P-P

VCM (V)

HD3

Second and Third Harmonic
Distortion vs Output Common
Mode Voltage (300MHz)

–50

V+ = 3.6V

= 400

R

LOAD

= 2V

V

OUT

–60

–70

–80

HD2, HD3 (dBc)

–90

–100

1.05 1.15 1.251.10 1.20 1.35 1.451.30 1.40

DIFFERENTIAL

P-P

VCM (V)

HD2

HD3

HD2

6416 G07

6416 G10

Second and Third Harmonic
Distortion vs Output Common
Mode Voltage (140MHz)

–50

V+ = 3.6V

= 400

R

LOAD

= 2V

V

OUT

–60

–70

–80

HD2, HD3 (dBc)

–90

–100

1.05 1.15 1.251.10 1.20 1.35 1.451.30 1.40

DIFFERENTIAL

P-P

VCM (V)

HD3

Third Order Intermodulation
Distortion (IM3) vs Frequency and
Supply Voltage

–50

–60

–70

IM3 (dBc)

–80

V+ = 3.3V, 3.6V; VCM = 1.25V

–90

–100

R

LOAD

V

OUT

$f = 1MHz

0 250 450150 350 500200 400100 30050

= 400

= 2V

IM3 VCC = 3.3V

IM3 VCC = 3.6V

DIFFERENTIAL (COMPOSITE)

P-P

FREQUENCY (MHz)

HD2

6416 G08

6416 G11

Second and Third Harmonic
Distortion vs Output Common
Mode Voltage (250MHz)

–50

V+ = 3.6V

= 400

R

LOAD

= 2V

V

OUT

–60

–70

–80

HD2, HD3 (dBc)

–90

–100

1.05 1.15 1.251.10 1.20 1.35 1.451.30 1.40

DIFFERENTIAL

P-P

VCM (V)

Third Order Intermodulation
Distortion (IM3) vs Output
Common Mode Voltage (140MHz)

–50

–60

–70

IM3 (dBc)

–80

V+ = 3.3V, 3.6V

–90

–100

= 400

R

LOAD

= 2V

V

OUT

$f = 1MHz

1.05 1.15 1.251.10 1.20 1.35 1.451.30 1.40

IM3 V+ = 3.3V

IM3 V+ = 3.6V

DIFFERENTIAL (COMPOSITE)

P-P

VCM (V)

HD3

HD2

6416 G09

6416 G12

8

Output Third Order Intercept
(OIP3

) vs Frequency and

EQUIV

Supply Voltage

50

45

OIP3 VCC = 3.6V

40

(dB)

EQUIV

35

OIP3

30

25

0 250 450150 350 500200 400100 30050

OIP3 VCC = 3.3V

V+ = 3.3V, 3.6V

= 1.25V

V

CM

= 400

R

LOAD

= 2V

V

OUT

P-P

$f = 1MHz

DIFFERENTIAL (COMPOSITE)

FREQUENCY (MHz)

6416 G13

Output Third Order Intercept
(OIP3

) vs Output Common

EQUIV

Mode Voltage and Supply Voltage
(140MHz)

50

45

OIP3

V+ = 3.6V

EQUIV

40

(dBm)

EQUIV

35

OIP3

V+ = 3.3V

OIP3

30

25

1.05 1.15 1.251.10 1.20 1.35 1.451.30 1.40

EQUIV

V+ = 3.3V, 3.6V

= 400

R

LOAD

= 2V

V

OUT

P-P

$f = 1MHz

DIFFERENTIAL (COMPOSITE)

VCM (V)

6416 G14

Output 1dB Compression
(Equivalent) vs Frequency, VCM
and Supply Voltage

15.0

14.5

14.0

13.5

13.0

12.5

12.0

11.5

11.0
V+ = 3.3V, 3.6V

= 400

R

10.5

LOAD

P1dB COMPRESSION (EQUIVALENT) (dBm)

10.0

V

OUT

0 250150 350 400200100 30050

= 2V

DIFFERENTIAL

P-P

FREQUENCY (MHz)

V+ = 3.3V

+

= 3.6V

V

VCM = 1.25V

VCM = 1.05V

6416 G15

6416f

TYPICAL PERFORMANCE CHARACTERISTICS

√Hz

Noise Figure and Input Referred

Supply Current vs Supply Voltage

50

45

40

35

30

25

20

15

SUPPLY CURRENT (mA)

10

5

0

0 2.51.5 3.5 4.02.01.0 3.00.5

SUPPLY VOLTAGE (V)

6416 G16

Noise Voltage vs Frequency PSRR vs Frequency

14

)

12

10

8

6

4

2

INPUT REFERRED NOISE VOLTAGE (nV

0

1k 10k 100k 100M 1G10M1M

NF

eN

FREQUENCY (Hz)

6416 G17

14

12

NOISE FIGURE (dB)

10

8

6

4

2

0

PSRR (dB)

90

V+ = 3.6V

80

70

60

50

40

30

20

10

0

0.1 1

LTC6416

10 100

FREQUENCY (MHz)

1000

6416 G29

200mV/DIV

Positive Overdrive Recovery
(V

Pin)

CLHI

+

IN

+

OUT

20ns/DIV

200mV/DIV

6416 G18

Negative Overdrive Recovery
(V

Pin)

CLLO

+

OUT

+

IN

20ns/DIV

10mV/DIV

6416 G19

LTC6416 Driving LTC2208 16-Bit

Small Signal Transient Response,
Falling Edge

10mV/DIV

500ps/DIV

6416 G31

ADC, 64K Point FFT, fIN = 30MHz,
–1dBFS, PGA = 0

0

V+ = 3.6V

–10

HD2 = –104.9dBc

–20

HD3 = –86.1dBc

–30

SFDR = 86.05dB
SNR = 76.5dB

–40

SEE FIGURE 5/

–50

TABLE 1

–60

1:1 BALUN

–70
–80
–90

AMPLITUDE (dBFS)

–100
–110
–120
–130

0

10

20
FREQUENCY (MHz)

3

30

40 50

2

60

6416 G20

Small Signal Transient Response,
Rising Edge

500ps/DIV

LTC6416 Driving LTC2208 16-Bit
ADC, 64K Point FFT, fIN = 30MHz,
–1dBFS, PGA = 1

0

V+ = 3.6V

–10

HD2 = –101.9dBc

–20

HD3 = –96.2dBc

–30

SFDR = 96.2dBc
SNR = 74.2dB

–40

SEE FIGURE 5/

–50

TABLE 1

–60

1:1 BALUN

–70
–80

AMPLITUDE (dBFS)

–90
–100
–110
–120
–130

0

10

FREQUENCY (MHz)

3

3020

40 50

6416 G30

2

60

6416 G21

6416f

9

LTC6416

TYPICAL PERFORMANCE CHARACTERISTICS

LTC6416 Driving LTC2208 16-Bit
ADC, 64K Point FFT, fIN = 70MHz,
–1dBFS, PGA = 0

0

V+ = 3.6V

–10

HD2 = –95dBc

–20

HD3 = –86dBc
SFDR = 86dBc

–30

SNR = 74.6dBFS

–40

SEE FIGURE 5/TABLE 1

–50

1:1 BALUN

–60
–70
–80

AMPLITUDE (dBFS)

–90
–100
–110
–120
–130

2

3020

0

10

FREQUENCY (MHz)

40 50

LTC6416 Driving LTC2208
16-Bit ADC, 64K Point FFT,
fIN = 140MHz, –1dBFS, PGA = 1

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0

10

LTC6416 Driving LTC2208 16-Bit
ADC, 64K Point FFT, fIN = 70MHz
and 71MHz, –7dBFS/Tone, PGA = 0

0

V+ = 3.6V

–10

IM3 = 81.7dBc

–20

SEE FIGURE 5/TABLE 1
1:1 BALUN

–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0

10

3

60

6416 G22

HD2 = –91.8dBc
HD3 = –93.6dBc
SFDR = 91.8dBc

SNR = 70.9dBFS

SEE FIGURE 5/TABLE 1

32

3020

40 50

FREQUENCY (MHz)

3020

40 50

FREQUENCY (MHz)

LTC6416 Driving LTC2208 16-Bit
ADC, 64K Point FFT, fIN = 70MHz,
–1dBFS, PGA = 1

0

V+ = 3.6V

–10

HD2 = –99dBc

–20

HD3 = –91dBc
SFDR = 91dBc

–30

SNR = 73dBFS

–40

SEE FIGURE 5/TABLE 1

–50

1:1 BALUN

–60
–70
–80

AMPLITUDE (dBFS)

–90
–100
–110
–120
–130

V+ = 3.6V

1:1 BALUN

0

6416 G25

6416 G27

2

10

60

60

3020

FREQUENCY (MHz)

LTC6416 Driving LTC2208
16-Bit ADC, 64K Point FFT,
fIN = 140MHz, –1dBFS, PGA = 0

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0

10

40 50

3

60

6416 G23

LTC6416 Driving LTC2208 16-Bit
ADC, 64K Point FFT, fIN = 30MHz
and 31MHz, –7dBFS/Tone, PGA = 0

0

V+ = 3.6V

–10

IM3 = 86dBc

–20

SEE FIGURE 5/
TABLE 1

–30

1:1 BALUN

–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90
–100
–110
–120
–130

0

10

3020

40 50

FREQUENCY (MHz)

LTC6416 Driving LTC2208 16-Bit ADC,
64K Point FFT, fIN = 139.5MHz and

140.5MHz, –7dBFS/Tone, PGA = 0

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0

10

SEE FIGURE 5/TABLE 1

3020

FREQUENCY (MHz)

V+ = 3.6V

IM3 = 81.7dBc

1:1 BALUN

40 50

SEE FIGURE 5/TABLE 1

2

3

30

20
FREQUENCY (MHz)

60

6416 G26

60

6416 G28

V+ = 3.6V
HD2 = –85.6dBc
HD3 = –95.5dBc
SFDR = 85.6dBc

SNR = 72.6dBFS

1:1 BALUN

5

40 50

6416 G24

60

6416f

10

PIN FUNCTIONS

LTC6416

VCM (Pin 1): This pin sets the output common mode voltage

+

seen at OUT
internal buffer with a high output resistance of 6k. The V

and OUT– by driving IN+ and IN– through an

CM

pin has a Thevenin equivalent resistance of approximately

3.8k and can be overdriven by an external voltage. If no
voltage is applied to V

, it will fl oat to a default voltage

CM

of approximately 1.25V on a 3.3V supply or 1.36V on
a 3.6V supply. The V

pin should be bypassed with a

CM

high-quality ceramic bypass capacitor of at least 0.1µF.
CLHI (Pin 2): High Side Clamp Voltage. The voltage applied

+

to the CLHI pin defi nes the upper voltage limit of the OUT

–

and OUT

pins. This voltage should be set at least 300mV
above the upper voltage range of the driven ADC. On a 3.3V
supply, the CLHI pin will fl oat to a 2.23V default voltage.
On a 3.6V supply, the CLHI pin will fl oat to a 2.45V default
voltage. CLHI has a Thevenin equivalent of approximately

4.1k and can be overdriven by an external voltage. The
CLHI pin should be bypassed with a high-quality ceramic
bypass capacitor of at least 0.1µF.

+

,IN– (Pins 3, 4): Non-inverting and inverting input pins

IN

of the buffer, respectively. These pins are high impedance,
approximately 6k. If AC-coupled, these pins will self bias
to the voltage present at the V

CM

pin.

CLLO (Pin 5): Low Side Clamp Voltage. The voltage ap­plied to the CLLO pin defi nes the lower voltage limit of

+

the OUT

and OUT– pins. This voltage should be set at

least 300mV below the lower voltage range of the driven

ADC. On a 3.3V supply, the CLLO pin will fl oat to a 0.25V
default voltage. On a 3.6V supply, the CLLO pin will fl oat to
a 0.265V default voltage. CLLO has a Thevenin equivalent
resistance of approximately 2.3k and can be overdriven by
an external voltage. The CLLO pin should be bypassed with
a high quality ceramic bypass capacitor of at least 0.1µF.

GND (Pins 6, 9, 11): Negative power supply, normally
tied to ground. Both pins and the exposed paddle must
be tied to the same voltage. GND may be tied to a voltage

+

other than ground as long as the voltage between V

and
GND is 2.7V to 4V. If the GND pins are not tied to ground,
bypass them with 680pF and 0.1µF capacitors as close to
the package as possible.

–

, OUT+ (Pins 7, 8): Outputs. The LTC6416 outputs

OUT

are low impedance. Each output has an output impedance
of approximately 9 at DC.

+

(Pin 10): Positive Power Supply. Typically 3.3V to 3.6V.

V

Split supplies are possible as long as the voltage between

+

and GND is 2.7V to 4V. Bypass capacitors of 680pF

V
and 0.1µF as close to the part as possible should be used
between the supplies.

Exposed Pad (Pin 11): Ground. The exposed pad must
be soldered to the printed circuit board ground plane for
good heat transfer. If GND is a voltage other than ground,

the Exposed Pad must be connected to a plane with the
same potential as the GND pins – Not to the system
ground plane.

DC TEST CIRCUIT SCHEMATIC

+

V

10

+

V

1

V

INDIFF

V

INCM

= IN+– IN

IN++ IN

=

V

–

–

+

IN

2

–

IN

CM

V

CM

2

CLHICLHI

3

+

IN

4

–

IN

5

CLLOCLLO

6

LTC6416

9

8

+ OUT

OUT

–

OUT

7

11

C

LOAD

R

LOAD

6416 DC

OUT

–

V

= OUT+– OUT

OUTDIFF

OUTCM

OUT++ OUT

=

V

+

–

–

2

6416f

11

LTC6416

BLOCK DIAGRAM

V

CM

1

CLHI

2

+

IN

3

–

IN

4

CLLO

5

LTC6416 Simplifi ed Schematic

+

V

10

R5

13.5k

x1

R1
6k

R11
6k

R6

2.5k

R3
6k

R4
13k

I1 I11 I13

Q3

Q1

Q13

Q11

Q2

Q4

Q14

Q5

I2 I12

R2

9

Q12

R12

9

OUT

OUT

GND (6, 9)

+

8

–

7

6416 BD

12

6416f

APPLICATIONS INFORMATION

LTC6416

Circuit Operation

The LTC6416 is a low noise and low distortion fully dif­ferential unity-gain ADC driver with operation from DC to
2GHz (–3dB bandwidth), a differential input impedance of
12k, and a differential output impedance of 18. The
LTC6416 is composed of a fully differential buffer with
output common mode voltage control circuitry and high
speed voltage-limiting clamps at the output. Small output
resistors of 9 improve the circuit stability over various
load conditions. They also simplify possible external fi lter­ing options, which are often desirable when the load is an
ADC. Lowpass or bandpass fi lters are easily implemented
with just a few external components. The LTC6416 is very
fl exible in terms of I/O coupling. It can be AC- or DC­coupled at the inputs, the outputs or both. When using
the LTC6416 with DC-coupled inputs, best performance is
obtained with an input common mode voltage between 1V
and 1.5V. For AC-coupled operation, the LTC6416 will take
the voltage applied to the V

pin and use it to bias the

CM

inputs so that the output common mode voltage equals

, thus no external circuitry is needed. The VCM pin

V

CM

has been designed to directly interface with the V

CM

pin
found on Linear Technology’s 16-, 14- and 12-bit high
speed ADC families.

Input Impedance and Matching

The LTC6416 has a high differential input impedance of
12k. The differential inputs may need to be terminated
to a lower value impedance, e.g. 50, in order to provide
an impedance match for the source. Figure 1 shows input

matching using a 1:1 balun, while Figure 2 shows match­ing using a 1:4 balun. These circuits provide a wideband
impedance match. The balun and matching resistors must
be placed close to the input pins in order to minimize the
rejection due to input mismatch. In Figure 1, the capaci­tor center-tapping the two 24.9 resistors improves high
frequency common mode rejection. As an alternative to
this wideband approach, a narrowband impedance match
can be used at the inputs of the LTC6416 for frequency
selection and/or noise reduction.

The noise performance of the LTC6416 also depends upon
the source impedance and termination. For example, the
input 1:4 balun in Figure 2 improves SNR by adding 6dB
of voltage gain at the inputs. A trade-off between gain
and noise is obvious when constant noise fi gure circle
and constant gain circle are plotted within the same input
Smith Chart. This technique can be used to determine
the optimal source impedance for a given gain and noise
requirement.

Output Match and Filter

The LTC6416 provides a source resistance of 9 at each
output. For testing purposes, Figure 3 and Figure 4 show
the LTC6416 driving a differential 400 load impedance
using a 1:1 or 1:4 balun, respectively.

The LTC6416 can drive an ADC directly without external
output impedance matching, but improved performance
can usually be obtained with the addition of a few external
components. Figure 5 shows a typical topology used for
driving the LTC2208 16-bit ADC.

0.1µF

1:1

50

+

V

IN

–

Figure 1. Input Termination for Differential 50Ω Input Impedance Using a 1:1 Balun

•

0.1µF

24.9

•

0.1µF

24.9

3

4

+

IN

LTC6416

–

IN

OUT

OUT

6416 F01

8

+

7

–

6416f

13

LTC6416

APPLICATIONS INFORMATION

0.1µF

1:4

50

+

V

IN

–

•

0.1µF

0.1µF

•

100

100

3

4

+

IN

LTC6416

–

IN

OUT

OUT

6416 F02

8

+

7

–

Figure 2. Input Termination for Differential 50Ω Input Impedance Using a 1:4 Balun

1:1

0.1µF

50

•

0.1µF

6416 F03

3

4

+

IN

LTC6416

–

IN

OUT

OUT

165

8

+

0.1µF

•

165

7

–

Figure 3. Output Termination for Differential 400Ω Load Impedance Using a 1:1 Balun

4:1

0.1µF

50

•

0.1µF

6416 F04

3

4

+

IN

LTC6416

–

IN

OUT

OUT

90.9

8

+

0.1µF

•

90.9

7

–

Figure 4. Output Termination for Differential 400Ω Load Impedance Using a 4:1 Balun

3.6V

50

680pF

T1

TCM4-19+

4

+
–

3

2

16

R36
100

R15
100

0.1µF

C39

0.01µF

CLHI

+

IN

LTC6416

–

IN

CLLO

V

GND

2.2µF

+

V

CM

GND

OUT

OUT

25

+

–

25

1.5pF

1pF

1.5pF

AIN

AIN

V

+

–

CM

LTC2208

CLOCK

(130MHz)

3.3V

6416 F05

16

DATA

Figure 5. DC1257B Simplifi ed Schematic with Suggested Output Termination for Driving an LTC2208 16-Bit ADC at 140MHz

14

6416f

APPLICATIONS INFORMATION

LTC6416

As seen in Table 1, suggested component values for the
fi lter will change for differing IF frequencies.

Table 1.

INPUT

FREQUENCY

30MHz 50 5.6pF/6.8pF/5.6pF

70MHz 25 5.6pF/6.8pF/5.6pF
140MHz 25 1.5pF/1pF/1.5pF
250MHz 5 -/-/-

LTC6416 OUTPUT

RESISTORS

FILTERING

CAPACITORS

Output Common Mode Adjustment

The output common mode voltage is set by the V

CM

pin.
Because the input common mode voltage is approximately
the same as the output common mode voltage, both are
approximately equal to V

. The VCM pin has a Thevenin

CM

equivalent resistance of 3.8k and can be overdriven by an
external voltage. The V

pin fl oats to a default voltage of

CM

1.25V on a 3.3V supply and 1.36V on a 3.6V supply. The
output common mode voltage is capable of tracking V
in a range from 0.34V to 2.16V on a 3.3V supply. The V

CM
CM

pin can be fl oated, but it should always be bypassed close
to the LTC6416 with a 0.1µF bypass capacitor to ground.
When interfacing with A/D converters such as the LTC22xx
families, the V

pin can be connected to the VCM output

CM

pin of the ADC, as shown in Figure 5.

to 2.23V. On a 3.6V supply, CLLO self-biases to 0.265V
while CLHI self-biases to 2.45V. Both CLLO and CLHI pins
should be bypassed with a 0.1µF capacitor as close to the
LTC6416 as possible.

Interfacing the LTC6416 to A/D Converters

The LTC6416 has been specifi cally designed to interface
directly with high speed A/D converters. It is possible
to drive the ADC directly from the LTC6416. In practice,
however, better performance may be obtained by adding
a few external components at the output of the LTC6416.
Figure 5 shows the LTC6416 being driven by a 1:8 trans­former which provides 9dB of voltage gain while also
performing a single-ended to differential conversion. The
differential outputs of the LTC6416 are lowpass fi ltered,
then drive the differential inputs of the LTC2208 ADC. In
many applications, an anti-alias fi lter like this is desir­able to limit the wideband noise of the amplifi er. This is
especially true in high performance 16-bit designs. The
minimum recommended network between the LTC6416
and the ADC is simply two 5 series resistors, which are
used to help eliminate resonances associated with the
stray capacitance of PCB traces and the stray inductance
of the internal bond wires at the ADC input, and the driver
output pins.

Single-Ended Signals

CLLO and CLHI Pins

The CLLO and CLHI pins are used to set the clamping
voltage for high speed internal circuitry. This circuitry
limits the single-ended minimum and maximum voltage
excursion seen at each of the outputs. This feature is
extremely important in applications with input signals
having very large peak-to-average ratios such as cellular
basestation receivers. If a very large peak signal arrives
at the LTC6416, the voltages applied to the CLLO and
CLHI pins will determine the minimum and maximum
output swing respectively. Once the input signal returns
to the normal operating range, the LTC6416 returns to
linear operation within 5ns. Both CLLO and CLHI are high
impedance inputs. CLLO has an input impedance of 2.3k,
while CLHI has an input impedance of 4.1k. On a 3.3V
supply, CLLO self-biases to 0.25V while CLHI self-biases

The LTC6416 has not been designed to convert single­ended signals to differential signals. A single-ended input
signal can be converted to a differential signal via a balun
connected to the inputs of the LTC6416.

Power Supply Considerations

For best linearity, the LTC6416 should have a positive

+

supply of V

= 3.6V. The LTC6416 has an internal edge-trig­gered supply voltage clamp. The timing mechanism of the
clamp enables the LTC6416 to withstand ESD events. This
internal clamp is also activated by voltage overshoot and

+

rapid slew rate on the positive supply V

pin. The LTC6416

should not be hot-plugged into a powered socket. Bypass

+

capacitors of 680pF and 0.1µF should be placed to the V
pin, as close as possible to the LTC6416.

6416f

15

LTC6416

APPLICATIONS INFORMATION

Test Circuits

Due to the fully differential design of the LTC6416 and its
usefulness in applications both with and without ADCs,
two test circuits are used to generate the information in
this data sheet. Test circuit A is Demo Board DC1287A,
a two-port demonstration circuit for the LTC6416. The
board layout and the schematic are shown in Figures 6
and 7. This circuit includes input and output 1:1 baluns
for single-ended-to-differential conversion, allowing
direct analysis using a 2-port network analyzer. In this
circuit implementation, there are series resistors at the

output to present the LTC6416 with a 382 differential
load, thereby optimizing distortion performance. Including
the 1:1 input and output baluns, the –3dB bandwidth is
approximately 2GHz.

Test circuit B is Demo Circuit DC1257B. It consists of an
LTC6416 driving an LTC2208 ADC. It is intended for use in
conjunction with demo circuit DC890B (computer interface
board) and proprietary Linear Technology evaluation soft­ware to evaluate the performance of both parts together.
Both the DC1257B board layout and the schematic can
be seen in Figures 8 and 9.

16

Figure 6. Demo Board DC1287A Layout

+

V

CM

C1

0.1µF

CLHI

T1

C10

OPT

C7

MABA-007190-000000

C8

51

OPT

•

•

2

43

C12

0.1µF

24.9

24.9

CLLO

J1

+

IN

0.1µF

J2

–

IN

C4

0.1µF

R2

R6

C15

0.1µF

C13

0.1µF

1

V

CM

2

R4
0

R5
0

CLHI

3

LTC6416

+

IN

4

–

IN

5

CLLO

GND

10

+

V

9

GND

8

+

OUT

7

–

OUT

6

GND

11

R1

165

R3

165

C2
680pF

MABA-007190-000000

C14

0.1µF

V

2.7V TO 4V

C3

0.1µF
GND

T2

34

2

•

•

15

0.1µF

GND

OPT

C11

J3

+

C5

0.1µF

C9

OPT

6416 TA04

OUT

J4
OUT

–

C6

Figure 7. Demo Board DC1287A Schematic (Test Circuit A)

6416f

APPLICATIONS INFORMATION

LTC6416

Figure 8. Demo Board DC1257B Layout

6416f

17

LTC6416

LTC2208CUP

SENSE

GND

V

CM

GND

VDDVDDGND

A

IN

+

A

IN

−
GND

GND

ENC+ENC−GND

V

DDVDD

V

CM

DA6

DA5

DA4

DA3

DA2

DA1

DA0

CLKCOUTA

CLKCOUTB

OFB

DB15

DB14

DB13

DB12

DB11

DB10

123456789

10111213141516

484746454443424140393837363534

33

PGA

RAND

MODE

LVDS

OFA

DA15

DA14

DA13

DA12

DA11

DA10

DA9

DA8

DA7

OGND

OV

DD

17

18

19

20

21

22

23

24

25

26

27

27

29

30

31

32

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

V

DD

GND

SHDN

DITH

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

OGND

OV

DD

GND

C22

1pF

R13

24.9Ω

R15

24.9Ω

C24

1.5pF

C20

1.5pF

C16

2.2µF

C14

0.1µF

C17

680pF

65

R7, 100

R6

OPT

R5

OPT

31

OFF

V

DD

V

DD

JP2

RAND

R2

10

R3

10

JP1

PGA

2

R4

1k

31

LOW

E7

EXTREF

HI

2

E2

CLHI

E3

CLLO

V

DD

V

DD

OVP

OVP

C12

0.1µF

C11

0.1µF

6416 F09

R28

4.99k

R25

4.99k

C31

0.1µF

R24

4.99k

R29

OPT

R27

2k

24LC025

876

5

123

4

VCC

WP

SCL

SDA

A0A1A2

VSS

31

ON

OFF

SHDN

EN

JP3

SHDN ADC

JP4

DITH

2

31

2

V

DD

C10

0.1µF
C9

0.1µF

C8

0.1µF

••

C30

0.1µF

321

4

5

R19

51.1Ω

R26

51.1Ω

C28

0.1µF

T2

MABA-007159-000000

R21

100Ω

CLK

J4

C29

0.1µF

GND

V

S

3.6V TO 20V

3

2

1

LT1963AEST-3.3

GND

E5E4

E6

OPT

IN OUT

C32

10µF

25V

C33

10µF

6.3V

L1(opt.)

BLM18PG221SN1DL2BLM18PG221SN1DL3BLM18PG221SN1D

V

S

V

DD

V

CC

OVP

LTC6416CDDB

V

CC

V

CC

C26

0.1µF

TCM4

−

19

+

T1

C25

0.1µF

C27

0.1µF

C13

0.1µF

C21

OPT

J2

J3

R14A

100Ω

R14B

100Ω

V

+

GND

OUT+OUT

−
GND

V

CM

CLHI

IN+IN−CLLO

GND

C19

0.1µF

C23

OPT

R8

OPT

R10

OPT

V

CC

C18

0.1µF

1

1

234

5

109876

11

2

4

5

3

R11

OPT

R12

OPT

V

CC

R17

OPT

R18

OPT

R9

1k

E1

V

CM

••

246

8

1012141618202224262830323436384042444648505254

1357911131517192123252729313335373941434547495153

565860626466687072747678808284868890929496

98

100

5557596163656769717375777981838587899193959799

R16

5.1k

J1

EDGE-CON

(GOLD FINGER)

OVP

APPLICATIONS INFORMATION

18

Figure 9. Demo Board DC1257B Schematic (Test Circuit B)

6416f

PACKAGE DESCRIPTION

LTC6416

DDB Package

10-Lead Plastic DFN (3mm × 2mm)

(Reference LTC DWG # 05-08-1722 Rev Ø)

0.64 ±0.05
(2 SIDES)

0.70 ±0.05

2.55 ±0.05

1.15 ±0.05

PACKAGE
OUTLINE

0.25 ± 0.05

0.50 BSC

2.39 ±0.05
(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 BAR

TOP MARK

(SEE NOTE 6)

0.200 REF

3.00 ±0.10
(2 SIDES)

2.00 ±0.10
(2 SIDES)

0.75 ±0.05

R = 0.05

0 – 0.05

R = 0.115

TYP

TYP

0.64 ± 0.05
(2 SIDES)

0.25 ± 0.05

BOTTOM VIEW—EXPOSED PAD

2.39 ±0.05
(2 SIDES)

0.40 ± 0.10

106

15

0.50 BSC

PIN 1
R = 0.20 OR

0.25 × 45°
CHAMFER

(DDB10) DFN 0905 REV Ø

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

6416f

19

LTC6416

TYPICAL APPLICATION

DC1257B Simplifi ed Schematic with Suggested Output Termination for Driving an LTC2208 16-Bit ADC at 140MHz

3.6V

50

680pF

T1

TCM4-19+

4

+
–

3

2

16

R36
100

R15
100

0.1µF

C39

0.01µF

CLHI

+

IN

LTC6416

–

IN

CLLO

V

GND

2.2µF

+

V

CM

GND

OUT

OUT

25

+

–

25

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS
Fixed Gain IF Amplifi ers/ADC Drivers

LT1993-2/LT1993-4/
LT1993-10

LTC6400-8/LTC6400-14/
LTC6400-20/LTC6400-26

LTC6401-8/LTC6401-14/
LTC6401-20/LTC6401-26

LT6402-6/LT6402-12/
LT6402-20

LTC6420-XX Dual 1.8GHz Low Noise, Low Distortion Differential

LTC6421-XX Dual 1.3GHz Low Noise, Low Distortion Differential

IF Amplifi ers/ADC Drivers with Digitally Controlled Gain

LT5514 Ultra-Low Distortion IF Amplifi er/ADC Driver with

LT5524 Low Distortion IF Amplifi er/ADC Driver with Digitally

LT5554 High Dynamic Range 7-bit Digitally Controlled IF

Baseband Differential Amplifi ers

LT1994 Low Noise, Low Distortion Differential Amplifi er/

LTC6403-1 Low Noise Rail-to-Rail Output Differential Amplifi er/

LTC6404-1/LTC6404-2 Low Noise Rail-to-Rail Output Differential Amplifi er/

LTC6406 3GHz Rail-to-Rail Input Differential Amplifi er/

LT6411 Low Power Differential ADC Driver/Dual Selectable

Linear Technology Corporation

20

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

800MHz Differential Amplifi er/ADC Drivers –72dBc IM3 at 70MHz 2V

1.8GHz Low Noise, Low Distortion Differential
ADC Drivers

1.3GHz Low Noise, Low Distortion Differential
ADC Drivers

–71dBc IM3 at 240MHz 2V
14dB, 20dB, 26dB

–74dBc IM3 at 140MHz 2V
14dB, 20dB, 26dB

300MHz Differential Amplifi er/ADC Drivers –71dBc IM3 at 20MHz 2V

Dual Version of the LTC6400-XX, AV = 8dB, 14dB, 20dB, 26dB

ADC Drivers

Dual Version of the LTC6401-XX, AV = 8dB, 14dB, 20dB, 26dB

ADC Drivers

OIP3 = 47dBm at 100MHz, Gain Range 10.5dB to 33dB 1.5dB steps

Digitally Controlled Gain

OIP3 = 40dBm at 100MHz, Gain Range 4.5dB to 37dB 1.5dB steps

Controlled Gain

OIP3 = 46dBm at 200MHz, Gain Range 1.725 to 17.6dB 0.125dB

VGA/ADC Driver

steps

16-Bit SNR and SFDR at 1MHz, Rail-to-Rail Outputs

ADC Driver

16-Bit SNR and SFDR at 3MHz, Rail-to-Rail Outputs, e

ADC Driver

16-Bit SNR and SFDR at 10MHz, Rail-to-Rail Outputs, eN = 1.5nV/

ADC Driver

√Hz, LTC6404-1 is unity-gain stable, LTC6404-2 is Gain-of-2 Stable
–65dBc IM3 at 50MHz 2V

ADC Driver

e

= 1.6nV/√Hz, 18mA

N

–83dBc IM3 at 70MHz 2V

Gain Amplifi er

●

www.linear.com

Excellent for Single-Ended to Differential Conversion

1.5pF

1pF

1.5pF

3.3V

V

CM

+

AIN

LTC2208

–

AIN

CLOCK

(130MHz)

Composite, AV = 2V/V, 4V/V, 10V/V

P-P

Composite, IS = 90mA, AV = 8dB,

P-P

Composite, IS = 50mA, AV = 8dB,

P-P

Composite, AV = 6dB, 12dB, 20dB

P-P

Composite, Rail-to-Rail Inputs,

P-P

Composite, AV = 1, –1 or 2, 16mA,

P-P

16

DATA

6416 F05

© LINEAR TECHNOLOGY CORPORATION 2008

= 2.8nV/√Hz

N

6416f

LT 1108 • PRINTED IN USA