The LTC®6246/LTC6247/LTC6248 are single/dual/quad low
power, high speed unity gain stable rail-to-rail input/output
operational amplifiers. On only 1mA of supply current they
feature an impressive 180MHz gain-bandwidth product,
90V/µs slew rate and a low 4.2nV/√Hz of input-referred
noise. The combination of high bandwidth, high slew rate,
low power consumption and low broadband noise makes
these amplifiers unique among rail-to-rail input/output op
amps with similar supply currents. They are ideal for lower
supply voltage high speed signal conditioning systems.
The LTC6246 family maintains high efficiency performance
from supply voltage levels of 2.5V to 5.25V and is fully
specified at supplies of 2.7V and 5.0V.
For applications that require power-down, the LTC6246
and the LTC6247 in MS10 offer a shutdown pin which
disables the amplifier and reduces current consumption
to 42µA.
The LTC6246 family can be used as a plug-in replacement
for many commercially available op amps to reduce power
or to improve input/output range and performance.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
Low Noise Low Distortion Gain = 2 ADC Driver
350kHz FFT Driving ADC
624678fa
1
Page 2
LTC6246/LTC6247/LTC6248
TOP VIEW
9
KC PACKAGE
8-LEAD PLASTIC UTDFN (2mm s 2mm)
5
6
7
8
4
3
2
1OUT A
–IN A
+IN A
V
–
V
+
OUT B
–IN B
+IN B
+–+
–
1
2
3
4
OUT A
–IN A
+IN A
V
–
8
7
6
5
V
+
OUT B
–IN B
+IN B
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
+
–
+
–
1
2
3
4
5
OUT A
–IN A
+IN A
V
–
SHDNA
10
9
8
7
6
V
+
OUT B
–IN B
+IN B
SHDNB
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
+
–
+
–
1
2
3
4
5
6
7
8
OUT A
–IN A
+IN A
V
+
+IN B
–IN B
OUT B
16
15
14
13
12
11
10
9
OUT D
–IN D
+IN D
V
–
+IN C
–IN C
OUT C
TOP VIEW
MS PACKAGE
16-LEAD PLASTIC MSOP
+–+
–
+–+
–
OUT 1
V
–
2
+IN 3
6 V
+
5 SHDN
4 –IN
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
+
–
OUT A 1
–IN A 2
+IN A 3
V
–
4
8 V
+
7 OUT B
6 –IN B
5 +IN B
TOP VIEW
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
+
–
+
–
absoluTe MaxiMuM raTings
Total Supply Voltage (V+ to V–) ................................5.5V
Input Current (+IN, –IN, SHDN) (Note 2) ..............±10mA
Output Current (Note 3) ..................................... ±100mA
Operating Temperature Range (Note 4) . –40°C to 125°C
pin conFiguraTion
= 125°C, θJA = 102°C/W (NOTE 9)
T
JMAX
EXPOSED PAD (PIN 9) IS V
–
, MUST BE SOLDERED TO PCB
(Note 1)
Specified Temperature Range (Note 5) .. –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Junction Temperature ........................................... 150°C
LEAD FREE FINISHTAPE AND REELPART MARKING*PACKAGE DESCRIPTIONSPECIFIED TEMPERATURE RANGE
LTC6246CS6#TRMPBFLTC6246CS6#TRPBFLTDWF6-Lead Plastic TSOT-230°C to 70°C
LTC6246IS6#TRMPBFLTC6246IS6#TRPBFLTDWF6-Lead Plastic TSOT-23–40°C to 85°C
LTC6246HS6#TRMPBFLTC6246HS6#TRPBFLTDWF6-Lead Plastic TSOT-23–40°C to 125°C
LTC6247CKC#TRMPBFLTC6247CKC#TRPBFDWJT
LTC6247IKC#TRMPBFLTC6247IKC#TRPBFDWJT
LTC6247CMS8#PBFLTC6247CMS8#TRPBFLTDWH8-Lead Plastic MSOP0°C to 70°C
LTC6247IMS8#PBFLTC6247IMS8#TRPBFLTDWH8-Lead Plastic MSOP–40°C to 85°C
LTC6247CTS8#TRMPBFLTC6247CTS8#TRPBFLTDWK8-Lead Plastic TSOT-230°C to 70°C
LTC6247ITS8#TRMPBFLTC6247ITS8#TRPBFLTDWK8-Lead Plastic TSOT-23–40°C to 85°C
LTC6247HTS8#TRMPBFLTC6247HTS8#TRPBFLTDWK8-Lead Plastic TSOT-23–40°C to 125°C
2
= 150°C, θJA = 125°C/W (NOTE 9)
T
JMAX
= 150°C, θJA = 192°C/W (NOTE 9)
T
JMAX
8-Lead (2mm × 2mm) UTDFN
8-Lead (2mm × 2mm) UTDFN
= 150°C, θJA = 195°C/W (NOTE 9)
T
JMAX
0°C to 70°C
–40°C to 85°C
624678fa
Page 3
LTC6246/LTC6247/LTC6248
orDer inForMaTion
LEAD FREE FINISHTAPE AND REELPART MARKING*PACKAGE DESCRIPTIONSPECIFIED TEMPERATURE RANGE
LTC6247CMS#PBFLTC6247CMS#TRPBFLTDWM10-Lead Plastic MSOP0°C to 70°C
LTC6247IMS#PBFLTC6247IMS#TRPBFLTDWM10-Lead Plastic MSOP–40°C to 85°C
LTC6248CMS#PBFLTC6248CMS#TRPBF624816-Lead Plastic MSOP0°C to 70°C
LTC6248IMS#PBFLTC6248IMS#TRPBF624816-Lead Plastic MSOP–40°C to 85°C
LTC6248HMS#PBFLTC6248HMS#TRPBF624816-Lead Plastic MSOP–40°C to 125°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
(V
elecTrical characTerisTics
specified temperature range, otherwise specifications are at TA = 25°C. For each amplifier VS = 5V, 0V; V
= 5V) The l denotes the specifications which apply across the
S
= 2V; VCM = V
SHDN
OUT
= 2.5V,
unless otherwise noted.
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
V
OS
∆V
OS
V
OS TC
I
B
I
OS
e
n
i
n
C
IN
R
IN
A
VOL
CMRRCommon Mode Rejection RatioV
Input Offset VoltageVCM = Half Supply
Input Offset Voltage Match
(Channel-to-Channel) (Note 8)
Input Offset Voltage Drift
Input Bias Current (Note 7)VCM = Half Supply
Input Offset CurrentVCM = Half Supply
Input Noise Voltage Densityf = 100kHz4.2nV/√Hz
Input 1/f Noise Voltagef = 0.1Hz to 10Hz1.6µV
Input Noise Current Densityf = 100kHz2.0pA/√Hz
Input CapacitanceDifferential Mode
Input ResistanceDifferential Mode
Large Signal Voltage GainRL = 1k to Half Supply (Note 10)
= V+ – 0.5V, NPN Mode
V
CM
VCM = Half Supply
= V+ – 0.5V, NPN Mode
V
CM
= V+ – 0.5V, NPN Mode
V
CM
= V+ – 0.5V, NPN Mode
V
CM
Common Mode
Common Mode
= 100Ω to Half Supply (Note 10)
R
L
= 0V to 3.5V
CM
–500
l
–1000
–2.5
l
–3
–600
l
–1000
–3.5
l
–4
l
–350
l
–550
100
l
0
–250
l
–400
–250
l
–400
30
l
14
5
l
2.5
78
l
76
50500
1000
0.12.5
3
50600
1000
0.13.5
4
–2µV/°C
–30350
550
4001000
1500
–10250
400
–10250
400
2
0.8
32
14
45V/mV
15V/mV
110dB
µV
µV
mV
mV
µV
µV
mV
mV
nA
nA
nA
nA
nA
nA
nA
nA
P-P
pF
pF
kΩ
MΩ
V/mV
V/mV
dB
624678fa
3
Page 4
LTC6246/LTC6247/LTC6248
elecTrical characTerisTics
(V
specified temperature range, otherwise specifications are at TA = 25°C. For each amplifier VS = 5V, 0V; V
unless otherwise noted.
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
I
CMR
PSRRPower Supply Rejection RatioV
V
OL
V
OH
I
SC
I
S
I
SD
I
SHDNL
I
SHDNH
V
L
V
H
I
OSD
t
ON
t
OFF
BW–3dB Closed Loop BandwidthA
GBWGain-Bandwidth Productf = 2MHz, R
, 0.1%Settling Time to 0.1%AV = –1, VO = 2V Step RL = 1k74ns
t
S
, 0.01%Settling Time to 0.01%AV = –1, VO = 2V Step RL = 1k202ns
t
S
SRSlew RateA
FPBWFull Power BandwidthV
Input Common Mode Range
Supply Voltage Range (Note 6)
Output Swing Low (V
Output Swing High (V+ – V
– V–)No Load
OUT
)No Load
OUT
Output Short-Circuit CurrentSourcing
Supply Current per AmplifierVCM = Half Supply
Disable Supply Current per AmplifierV
SHDN Pin Current LowV
SHDN Pin Current HighV
SHDN Pin Input Voltage Low
SHDN Pin Input Voltage High
Output Leakage Current Magnitude in
Shutdown
Turn-On TimeV
Turn-Off TimeV
= 5V)The l denotes the specifications which apply across the
S
= 2.5V to 5.25V
S
V
= 1V
CM
= 5mA
I
SINK
= 25mA
I
SINK
= 5mA
I
SOURCE
= 25mA
I
SOURCE
Sinking
= V+ – 0.5V
V
CM
= 0.8V
SHDN
= 0.8V
SHDN
= 2V
SHDN
V
= 0.8V, Output Shorted to Either
SHDN
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
–300
l
–350
l
l
= 2V; VCM = V
SHDN
0V
69
73dB
OUT
S
= 2.5V,
65
2.55.25V
2540
55
70110
160
160250
450
70100
150
130175
225
300 500
750
–80–35
–30
60
100mA
40
0.951
1.4
1.251.4
1.8
4275
200
–3
–4
–1.60
0
35300
350
0.8V
2V
100nA
Supply
= 0.8V to 2V5µs
SHDN
= 2V to 0.8V2µs
SHDN
= 1, RL = 1k to Half Supply120MHz
V
= 1k to Half Supply
L
= –3.33, 4.6V Step (Note 11)
V
= 4V
OUT
(Note 13)4MHz
P-P
100
l
70
60
l
50
180MHz
90V/µs
dB
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
nA
nA
MHz
V/µs
V
4
624678fa
Page 5
LTC6246/LTC6247/LTC6248
(V
elecTrical characTerisTics
specified temperature range, otherwise specifications are at TA = 25°C. For each amplifier VS = 5V, 0V; V
= 5V)The l denotes the specifications which apply across the
S
= 2V; VCM = V
SHDN
OUT
= 2.5V,
unless otherwise noted.
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
= 100kHz, VO = 2V
HD2/HD3Harmonic Distortion
= 1k to Half Supply
R
L
R
= 100Ω to Half SupplyfC = 100kHz, VO = 2V
L
∆G
∆θ
Differential Gain (Note 14)A
Differential Phase (Note 14)A
CrosstalkA
(V
elecTrical characTerisTics
f
C
fC = 1MHz, VO = 2V
fC = 2MHz, VO = 2V
fC = 1MHz, VO = 2V
fC = 2MHz, VO = 2V
= 1, RL = 1k, VS = ±2.5V0.2%
V
= 1, RL = 1k, VS = ±2.5V0.08Deg
V
= –1, RL = 1k to Half Supply,
V
V
= 2V
OUT
P-P
= 2.7V) The l denotes the specifications which apply across the
S
P-P
P-P
P-P
P-P
P-P
P-P
, f = 1MHz
specified temperature range, otherwise specifications are at TA = 25°C. For each amplifier VS = 2.7V, 0V; V
110/90
88/80
78/62
90/79
66/60
59/51
–90dB
= 2V; VCM = V
SHDN
OUT
dBc
dBc
dBc
=
1.35V, unless otherwise noted.
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
V
OS
∆V
V
OS TC
I
B
I
OS
e
n
i
n
C
IN
R
IN
A
VOL
OS
Input Offset VoltageVCM = Half Supply
= V+ – 0.5V, NPN Mode
V
CM
Input Offset Voltage Match
VCM = Half Supply
(Channel-to-Channel) (Note 8)
= V+ – 0.5V, NPN Mode
V
CM
Input Offset Voltage Drift
Input Bias Current (Note 7)VCM = Half Supply
= V+ – 0.5V, NPN Mode
V
CM
Input Offset CurrentVCM = Half Supply
= V+ – 0.5V, NPN Mode
V
CM
Input Noise Voltage Densityf = 100kHz4.6nV/√Hz
Input 1/f Noise Voltagef = 0.1Hz to 10Hz1.7µV
Input Noise Current Densityf = 100kHz1.8pA/√Hz
Input CapacitanceDifferential Mode
Common Mode
Input ResistanceDifferential Mode
Common Mode
Large Signal Voltage GainRL = 1k to Half Supply
(Note 12)
= 100Ω to Half Supply
R
L
(Note 12)
–100
l
–300
–1.75
l
–2.25
–700
l
–1000
–3.5
l
–4
l
–450
l
–600
50
l
0
–250
l
–350
–250
l
–350
5001000
1400
0.753.25
3.75
–20700
1000
0.13.5
4
2µV/°C
–100 450
600
3501000
1500
–10250
350
–10250
350
mV
mV
mV
mV
nA
nA
nA
nA
nA
nA
nA
nA
P-P
2
0.8
32
12
15
l
7.5
2
l
1.3
25 V/mV
7.5V/mV
kΩ
MΩ
V/mV
V/mV
µV
µV
µV
µV
pF
pF
624678fa
5
Page 6
LTC6246/LTC6247/LTC6248
elecTrical characTerisTics
(V
specified temperature range, otherwise specifications are at TA = 25°C. For each amplifier VS = 2.7V, 0V; V
1.35V, unless otherwise noted.
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
CMRRCommon Mode Rejection RatioV
I
CMR
PSRRPower Supply Rejection RatioV
V
OL
V
OH
I
SC
I
S
I
SD
I
SHDNL
I
SHDNH
V
L
V
H
I
OSD
t
ON
t
OFF
BW–3dB Closed Loop BandwidthA
GBWGain-Bandwidth Productf = 2MHz, R
, 0.1Settling Time to 0.1%AV = –1, VO = 2V Step RL = 1k119ns
t
S
, 0.01Settling Time to 0.01%AV = –1, VO = 2V Step RL = 1k170ns
t
S
SRSlew RateA
Input Common Mode Range
Supply Voltage Range (Note 6)
Output Swing Low (V
Output Swing High (V+ – V
– V–)No Load
OUT
)No Load
OUT
Short Circuit CurrentSourcing
Supply Current per AmplifierVCM = Half Supply
Disable Supply Current per AmplifierV
SHDN Pin Current LowV
SHDN Pin Current HighV
SHDN Pin Input Voltage
SHDN Pin Input Voltage
Output Leakage Current Magnitude in Shutdown V
Turn-On TimeV
Turn-Off TimeV
= 2.7V) The l denotes the specifications which apply across the
S
= 0V to 1.2V
CM
= 2.5V to 5.25V
S
V
= 1V
CM
= 5mA
I
SINK
= 10mA
I
SINK
= 5mA
I
SOURCE
= 10mA
I
SOURCE
Sinking
= V+ – 0.5V
V
CM
= 0.8V
SHDN
= 0.8V
SHDN
= 2V
SHDN
= 0.8V, Output Shorted to Either
SHDN
80
l
78
l
0V
69
l
65
l
2.55.25V
l
l
l
l
l
l
l
25
l
20
l
l
l
–1
l
–1.5
–300
l
–350
l
l
2.0V
= 2V; VCM = V
SHDN
100dB
S
73dB
2040
55
80125
160
110175
225
6085
100
135190
225
180275
400
–35–20
–15
50mA
0.891
1.3
11.3
1.7
2250
90
–0.50
0
45300
350
0.8V
100nA
OUT
Supply
= 0.8V to 2V5µs
SHDN
= 2V to 0.8V2µs
SHDN
= 1, RL = 1k to Half Supply100MHz
V
= 1k to Half Supply
L
= –1, 2V Step55V/µs
V
80
l
50
150MHz
=
dB
dB
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
nA
nA
V
6
624678fa
Page 7
LTC6246/LTC6247/LTC6248
INPUT OFFSET VOLTAGE (µV)
PERCENT OF UNITS (%)
22
20
16
12
8
2
18
14
10
6
4
0
–50–150150
624678 G01
350250–250–37550
VS = 5V, 0V
V
CM
= 2.5V
INPUT OFFSET VOLTAGE (µV)
PERCENT OF UNITS (%)
25
15
5
20
10
0
–125–25–75
624678 G02
7512525175–175
VS = 5V, 0V
V
CM
= 2.5V
INPUT OFFSET VOLTAGE (µV)
PERCENT OF UNITS (%)
16
12
8
2
14
10
6
4
0
–1200400–400
624678 G03
12002000–2000
VS = 5V, 0V
V
CM
= 4.5V
elecTrical characTerisTics
(V
specified temperature range, otherwise specifications are at TA = 25°C. For each amplifier VS = 2.7V, 0V; V
1.35V, unless otherwise noted.
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
FPBWFull Power BandwidthV
CrosstalkA
= 2.7V) The l denotes the specifications which apply across the
S
= 2V
OUT
= –1, RL = 1k to Half Supply,
V
V
OUT
(Note 13)3.3MHz
P-P
= 2V
, f = 1MHz
P-P
= 2V; VCM = V
SHDN
–90dB
OUT
=
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs are protected by back-to-back diodes. If any of
the input or shutdown pins goes 300mV beyond either supply or the
differential input voltage exceeds 1.4V the input current should be limited
to less than 10mA. This parameter is guaranteed to meet specified
performance through design and/or characterization. It is not production
tested.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output current is high.
Note 4: The LTC6246C/LTC6247C/LTC6248C and LTC6246I/LTC6247I/
LTC6248I are guaranteed functional over the temperature range of –40°C
to 85°C. The LTC6246H/LTC6247H/LTC6248H are guaranteed functional
over the temperature range of –40°C to 125°C.
Note 5: The LTC6246C/LTC6247C/LTC6248C are guaranteed to meet
specified performance from 0°C to 70°C. The LTC6246C/LTC6247C/
LTC6248C are designed, characterized and expected to meet specified
performance from –40°C to 85°C but are not tested or QA sampled at
these temperatures. The LTC6246I/LTC6247I/LTC6248I are guaranteed
to meet specified performance from –40°C to 85°C. The LTC6246H/
LTC6247H/LTC6248H are guaranteed to meet specified performance from
–40°C to 125°C.
Note 6: Minimum supply voltage is guaranteed by power supply rejection
ratio test.
Note 7: The input bias current is the average of the average of the currents
through the positive and negative input pins.
Note 8: Matching parameters are the difference between amplifiers A and
D and between B and C on the LTC6248; between the two amplifiers on the
LTC6247.
Note 9: Thermal resistance varies with the amount of PC board metal
connected to the package. The specified values are with short traces
connected to the leads with minimal metal area.
Note 10: The output voltage is varied from 0.5V to 4.5V during
measurement.
Note 11: Middle 80% of the output waveform is observed. R
= 1k at half
L
supply.
Note 12: The output voltage is varied from 0.5V to 2.2V during
measurement.
Note 13: FPBW is determined from distortion performance in a gain of +2
configuration with HD2, HD3 < –40dBc as the criteria for a valid output.
Note 14: Differential gain and phase are measured using a Tektronix
TSG120YC/NTSC signal generator and a Tektronix 1780R video
measurement set.
Output Saturation Voltage
vs Load Current (Output High)
624678fa
9
Page 10
LTC6246/LTC6247/LTC6248
LOAD CURRENT (mA)
OUTPUT LOW SATURATION VOLTAGE (V)
624678 G22
10
1
0.1
0.01
0.011010010.1
VS = ±2.5V
TA = –55°C
TA = 125°C
TA = 25°C
OUTPUT VOLTAGE (V)
0
INPUT VOLTAGE (µV)
500
400
300
200
100
0
–100
–200
–300
–400
–500
2.53.5
624678 G24
5
RL = 1k TO MID SUPPLY
RL = 1k TO GROUND
RL = 100 TO MID SUPPLY
RL = 100 TO GROUND
TA = 25°C
V
S
= 5V, 0V
4 4.521.510.53
OUTPUT VOLTAGE (V)
0
INPUT VOLTAGE (µV)
1000
900
500
600
700
800
400
300
200
100
0
–100
–200
–300
2.5
624678 G25
2.7
RL = 1k TO MID SUPPLY
RL = 1k TO GROUND
RL = 100 TO MID SUPPLY
RL = 100 TO GROUND
TA = 25°C
V
S
= 2.7V, 0V
21.510.5
POWER SUPPLY VOLTAGE (±V)
1.25
OUTPUT SHORT-CIRCUIT CURRENT (mA)
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
1.651.452.05
624678 G23
2.65
TA = 125°C
TA = 125°C
SINK
SOURCE
TA = 25°C
TA = 25°C
TA = –55°C
TA = –55°C
2.25 2.451.85
FREQUENCY (MHz)
GAIN (dB)
624678 G26
6
0
–18
–12
–6
–24
0.011010010.1
VS = ±2.5V
T
A
= 25°C
R
L
= 1k
FREQUENCY (MHz)
GAIN (dB)
624678 G27
12
0
6
–12
–6
–18
0.011010010.1
VS = ±2.5V
T
A
= 25°C
R
F
= RG = 1k
R
L
= 1k
FREQUENCY (Hz)
GAIN (dB)
PHASE (DEG)
624678 G28
80
10
20
30
40
50
60
70
–10
0
–20
150
0
50
100
–50
–100
100k100M 300M10M1M
TA = 25°C
R
L
= 1k
VS = ±2.5V
PHASE
GAIN
VS = ±1.35V
VS = ±2.5V
VS = ±1.35V
TOTAL SUPPLY VOLTAGE (V)
2.5
GAIN BANDWIDTH (MHz)
PHASE MARGIN (DEG)
200
180
160
140
120
100
70
60
50
33.54.5
PHASE MARGIN
GAIN BANDWIDTH PRODUCT
624678 G29
TA = 25°C
R
L
= 1k
54
TEMPERATURE (°C)
–55
GAIN BANDWIDTH (MHz)
PHASE MARGIN (DEG)
300
250
200
150
100
60
70
50
40
–35 –154525
PHASE MARGIN
GAIN BANDWIDTH PRODUCT
624678 G30
125
TA = 25°C
R
L
= 1k
65 85 1055
VS = ±2.5V
VS = ±1.35V
VS = ±2.5V
VS = ±1.35V
Typical perForMance characTerisTics
Output Saturation Voltage
vs Load Current (Output Low)
Open Loop Gain
Output Short-Circuit Current
vs Power Supply VoltageOpen Loop Gain
Gain vs Frequency (A
= 1)
V
Gain vs Frequency (A
= 2)
V
Open Loop Gain and Phase
vs Frequency
10
Gain Bandwidth and Phase
Margin vs Supply Voltage
Gain Bandwidth and Phase
Margin vs Temperature
624678fa
Page 11
LTC6246/LTC6247/LTC6248
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
624678 G31
1000
10
100
1
0.1
0.01
0.001
100k100M1G10M1M
VS = ±2.5V
AV = 10
AV = 1
AV = 2
FREQUENCY (Hz)
COMMON MODE REJECTION RATIO (dB)
624678 G31
110
90
80
70
60
50
40
30
100
20
10
0
–10
10 100 1k 10k 100k100M 1G10M1M
TA = 25°C
V
S
= ±2.5V
FREQUENCY (Hz)
10
POWER SUPPLY REJECTION RATIO (dB)
50
40
30
20
10
70
80
60
0
–10
100 1k100k
NEGATIVE SUPPLY
POSITIVE SUPPLY
624678 G33
VS = ±2.5V
T
A
= 25°C
100M10M1M10k
TEMPERATURE (°C)
–55
SLEW RATE (V/µs)
140
FALLING, VS = ±2.5V
RISING, VS = ±2.5V
FALLING, VS = ±1.35V
RISING, VS = ±1.35V
120
100
80
60
40
–3545255–1585
624678 G34
125
AV = –1, RL = 1k, V
OUT
= 4V
P-P
(±2.5V),
2V
P-P
(±1.35V) SLEW RATE MEASURED
AT MIDDLE 2/3 OF OUTPUT
10565
FREQUENCY (MHz)
0.01
DISTORTION (dBc)
–40
–50
–60
–70
–80
–90
–100
–110
–120
0.1101
624678 G37
VS = ±2.5V
V
OUT
= 2V
P-P
AV = 1
RL = 100Ω, 2ND
RL = 1kΩ, 3RD
RL = 1kΩ, 2ND
RL = 100Ω, 3RD
FREQUENCY (MHz)
0.01
DISTORTION (dBc)
–40
–50
–60
–70
–80
–90
–100
–110
–120
0.1101
624678 G38
VS = ±1.35V
V
OUT
= 1V
P-P
AV = 1
RL = 100Ω, 2ND
RL = 1kΩ, 3RD
RL = 1kΩ, 2ND
RL = 100Ω, 3RD
FREQUENCY (MHz)
0.01
DISTORTION (dBc)
–40
–50
–60
–70
–80
–90
–100
–110
–120
0.1101
624678 G39
VS = ±2.5V
V
OUT
= 2V
P-P
AV = 2
RL = 100Ω, 2ND
RL = 1kΩ, 3RD
RL = 1kΩ, 2ND
RL = 100Ω, 3RD
CAPACITIVE LOAD (pF)
10
OVERSHOOT (%)
80
70
60
50
40
30
20
10
0
100100001000
624678 G35
VS = ±2.5V
V
OUT
= 100mV
P-P
AV = 1
RS = 20Ω
RS = 49.9Ω
RS = 10Ω
+
–
R
S
C
L
V
OUT
V
IN
AV = 1
CAPACITIVE LOAD (pF)
10
OVERSHOOT (%)
80
70
60
50
40
30
20
10
0
100100001000
624678 G36
VS = ±2.5V
V
OUT
= 200mV
P-P
RF = RG = 500Ω,
A
V
= 2
RS = 20Ω
RS = 49.9Ω
R
S
500Ω
500Ω
C
L
V
OUT
V
IN
AV = 2
RS = 10Ω
+
–
Typical perForMance characTerisTics
Output Impedance vs Frequency
Slew Rate vs Temperature
Common Mode Rejection Ratio
vs Frequency
Series Output Resistor
vs Capacitive Load (A
= 1)
V
Power Supply Rejection Ratio
vs Frequency
Series Output Resistor
vs Capacitive Load (AV = 2)
Distortion vs Frequency
(AV = 1, 5V)
Distortion vs Frequency
(AV = 1, 2.7V)
Distortion vs Frequency
(AV = 2, 5V)
624678fa
11
Page 12
LTC6246/LTC6247/LTC6248
OUTPUT STEP (V)
–4
SETTLING TIME (ns)
200
180
160
140
40
60
80
100
120
20
0
–3–1
624678 G42
4
1mV
1mV
10mV10mV
0132–2
VS = ±2.5V
A
V
= 1
T
A
= 25°C
1k
V
OUT
V
IN
+
–
OUTPUT STEP (V)
–4
SETTLING TIME (ns)
200
180
160
140
40
60
80
100
120
20
0
–3–1
624678 G43
4
10mV
0132–2
1k
1k
1k
V
OUT
V
IN
VS = ±2.5V
A
V
= –1
T
A
= 25°C
1mV
10mV
1mV
+
–
V
OUT
1.6V/DIV
A
V
= 1
V
S
= ±2.5V
R
L
= 1k
V
IN
= 1.6V
V
SHDN
2.5V/DIV
0V
0V
624678 G44
10µs/DIV
1V/DIV
0V
A
V
= 1
V
S
= ±2.5V
R
L
= 1k
624678 G45
200ns/DIV
25mV/DIV
0V
A
V
= 1
V
S
= ±2.5V
R
L
= 1k
624678 G46
50ns/DIV
V
OUT
2V/DIV
A
V
= ±2
V
S
= ±2.5V
R
L
= 1k
V
IN
= 3V
P-P
V
IN
1V/DIV
0V
0V
624678 G47
100ns/DIV
FREQUENCY (MHz)
0.01
DISTORTION (dBc)
–40
–50
–60
–70
–80
–90
–100
–110
–120
0.1101
624678 G40
VS = ±1.35V
V
OUT
= 1V
P-P
AV = 2
RL = 100Ω, 2ND
RL = 1kΩ, 3RD
RL = 1kΩ, 2ND
RL = 100Ω, 3RD
FREQUENCY (MHz)
0.01
OUTPUT VOLTAGE SWING (V
P-P
)
5
4
3
2
1
0
0.1101
624678 G41
VS = ±2.5V
T
A
= 25°C
R
L
= 1kΩ
HD2, HD3 < –40dBc
AV = 2
A
V
= –1
Typical perForMance characTerisTics
Distortion vs Frequency
= 2, 2.7V)
A
V
Maximum Undistorted Output
Signal vs Frequency
Settling Time vs Output Step
(Inverting)SHDN Pin Response Time
Settling Time vs Output Step
(Noninverting)
Large Signal Response
12
Small Signal ResponseOutput Overdriven Recovery
624678fa
Page 13
pin FuncTions
624678 F01
Q15
ESDD5
Q14
C2
C1
BUFFER
AND
OUTPUT BIAS
R5R4
Q13
Q12
I
3
V
–
+
C
C
Q8
R3
Q11
Q9
Q10
R2R1
Q2Q1Q3Q4
I
1
+
I
2
+
V
BIAS
Q5
Q6Q19
Q7
D8
D7
Q18
Q17
D6
D5
ESDD2
V
–
ESDD1
V
+
ESDD4
V
–
ESDD3
V
+
Q16
V
–
V
+
+IN
–IN
ESDD6
OUT
–IN: Inverting Input of Amplifier. Valid input range from V–
+
.
to V
LTC6246/LTC6247/LTC6248
–
: Negative Supply Voltage. Typically 0V. This can be made
V
a negative voltage as long as 2.5V ≤ (V
+
– V–) ≤ 5.25V.
+IN: Non-Inverting Input of Amplifier. Valid input range
–
from V
V
ranges from 2.5V to 5.25V when V
to V+.
+
: Positive Supply Voltage. Allowed applied voltage
–
= 0V.
applicaTions inForMaTion
Circuit Description
The LTC6246/LTC6247/LTC6248 have an input and output
signal range that extends from the negative power supply
to the positive power supply. Figure 1 depicts a simplified
schematic of the amplifier. The input stage is comprised
of two differential amplifiers, a PNP stage, Q1/Q2, and an
NPN stage, Q3/Q4 that are active over different common
mode input voltages. The PNP stage is active between
the negative supply to nominally 1.2V below the positive
supply. As the input voltage approaches the positive supply, the transistor Q5 will steer the tail current, I
current mirror, Q6/Q7, activating the NPN differential pair
, to the
1
SHDN: Active Low Shutdown. Threshold is typically 1.1V
–
referenced to V
. Floating this pin will turn the part on.
OUT: Amplifier Output. Swings rail-to-rail and can typically
source/sink over 50mA of current at a total supply of 5V.
and the PNP pair becomes inactive for the remaining input
common mode range. Also, at the input stage, devices Q17
to Q19 act to cancel the bias current of the PNP input pair.
When Q1/Q2 are active, the current in Q16 is controlled to
be the same as the current in Q1 and Q2. Thus, the base
current of Q16 is nominally equal to the base current of
the input devices. The base current of Q16 is then mirrored
by devices Q17 to Q19 to cancel the base current of the
input devices Q1/Q2. A pair of complementary common
emitter stages, Q14/Q15, enable the output to swing from
rail-to-rail.
The offset voltage will change depending upon which
input stage is active. The PNP input stage is active from
the negative supply rail to approximately 1.2V below the
positive supply rail, then the NPN input stage is activated
for the remaining input range up to the positive supply rail
with the PNP stage inactive. The offset voltage magnitude
for the PNP input stage is trimmed to less than 500µV with
5V total supply at room temperature, and is typically less
than 150μV. The offset voltage for the NPN input stage
is typically less than 1.7mV with 5V total supply at room
temperature.
Input Bias Current
The LTC6246 family uses a bias current cancellation circuit to compensate for the base current of the PNP input
pair. When the input common mode voltage is less than
200mV, the bias cancellation circuit is no longer effective
and the input bias current magnitude can reach a value
above 1µA. For common mode voltages ranging from
0.2V above the negative supply to 1.2V below the positive
supply, the low input bias current of the LTC6246 family
allows the amplifiers to be used in applications with high
source resistances where errors due to voltage drops
must be minimized.
Output
The LTC6246 family has excellent output drive capability.
The amplifiers can typically deliver over 50mA of output
drive current at a total supply of 5V. The maximum output current is a function of the total supply voltage. As
the supply voltage to the amplifier decreases, the output
current capability also decreases. Attention must be paid
to keep the junction temperature of the IC below 150°C
(refer to the Power Dissipation Section) when the output
is in continuous short circuit. The output of the amplifier
has reverse-biased diodes connected to each supply. If
the output is forced beyond either supply, extremely high
current will flow through these diodes which can result
in damage to the device. Forcing the output to even 1V
beyond either supply could result in several hundred milliamps of current through either diode.
Input Protection
The input stages are protected against a large differential
input voltage of 1.4V or higher by 2 pairs of back-to-back
diodes to prevent the emitter-base breakdown of the input
transistors. In addition, the input and shutdown pins have
reverse biased diodes connected to the supplies. The current in these diodes must be limited to less than 10mA.
The amplifiers should not be used as comparators or in
other open loop applications.
ESD
The LTC6246 family has reverse-biased ESD protection
diodes on all inputs and outputs as shown in Figure 1.
There is an additional clamp between the positive and negative supplies that further protects the device during ESD
strikes. Hot plugging of the device into a powered socket
must be avoided since this can trigger the clamp resulting
in larger currents flowing between the supply pins.
Capacitive Loads
The LTC6246/LTC6247/LTC6248 are optimized for high
bandwidth and low power applications. Consequently they
have not been designed to directly drive large capacitive
loads. Increased capacitance at the output creates an additional pole in the open loop frequency response, worsening the phase margin. When driving capacitive loads, a
resistor of 10Ω to 100Ω should be connected between the
amplifier output and the capacitive load to avoid ringing
or oscillation. The feedback should be taken directly from
the amplifier output. Higher voltage gain configurations
tend to have better capacitive drive capability than lower
gain configurations due to lower closed loop bandwidth
and hence higher phase margin. The graphs titled Series
Output Resistor vs Capacitive Load demonstrate the transient response of the amplifier when driving capacitive
loads with various series resistors.
14
624678fa
Page 15
applicaTions inForMaTion
624678 F02
C
PAR
5k
–
+
V
OUT
V
IN
5k
5pF
P
D(MAX)
=(VS•I
S(MAX)
)+
V
S
2
2
/ R
L
LTC6246/LTC6247/LTC6248
Feedback Components
When feedback resistors are used to set up gain, care
must be taken to ensure that the pole formed by the
feedback resistors and the parasitic capacitance at the
inverting input does not degrade stability. For example if
the amplifier is set up in a gain of +2 configuration with
gain and feedback resistors of 5k, a parasitic capacitance
of 5pF (device + PC board) at the amplifier’s inverting
input will cause the part to oscillate, due to a pole formed
at 12.7MHz. An additional capacitor of 5pF across the
feedback resistor as shown in Figure 2 will eliminate any
ringing or oscillation. In general, if the resistive feedback
network results in a pole whose frequency lies within the
closed loop bandwidth of the amplifier, a capacitor can be
added in parallel with the feedback resistor to introduce
a zero whose frequency is close to the frequency of the
pole, improving stability.
Power Dissipation
The LTC6246 and LTC6247 contain one and two amplifiers
respectively. Hence the maximum on-chip power dissipation for them will be less than the maximum on-chip
power dissipation for the LTC6248, which contains four
amplifiers.
The LTC6248 is housed in a small 16-lead MS package and
typically has a thermal resistance (θ
) of 125°C/ W. It is
JA
necessary to ensure that the die’s junction temperature
does not exceed 150°C. The junction temperature, T
JA
A
:
, power dis-
calculated from the ambient temperature, T
sipation, PD, and thermal resistance, θ
= TA + (PD • θJA)
T
J
J
, is
The power dissipation in the IC is a function of the supply
voltage, output voltage and load resistance. For a given
supply voltage with output connected to ground or supply,
the worst-case power dissipation P
D(MAX)
occurs when
the supply current is maximum and the output voltage at
half of either supply voltage for a given load resistance.
P
is approximately (since IS actually changes with
D(MAX)
output load current) given by:
Figure 2. 5pF Feedback Cancels Parasitic Pole
Shutdown
The LTC6246 and LTC6247MS have SHDN pins that can
shut down the amplifier to 42µA typical supply current.
The SHDN pin needs to be taken below 0.8V above the
negative supply for the amplifier to shut down. When left
floating, the SHDN pin is internally pulled up to the positive
supply and the amplifier remains on.
Example: For an LTC6248 in a 16-lead MS package operating
on ±2.5V supplies and driving a 100Ω load to ground, the
worst-case power dissipation is approximately given by
P
/Amp = (5 • 1.3mA) + (1.25)2/100 = 22mW
D(MAX)
If all four amplifiers are loaded simultaneously then the
total power dissipation is 88mW.
At the Absolute Maximum ambient operating temperature,
the junction temperature under these conditions will be:
= TA + PD • 125°C/W
T
J
= 125 + (0.088W • 125°C/W) = 136°C
which is less than the absolute maximum junction tem-
perature for the LTC6248 (150°C).
Refer to the Pin Configuration section for thermal resis-
tances of various packages.
624678fa
15
Page 16
LTC6246/LTC6247/LTC6248
LTC6246
+
–
624678 F03
LTC2366
V
REF
GND
V
DD
3.3V 2.5V
CS
SDO
SCK
OV
DD
3.3V
V
IN
A
IN
499Ω
1%
499Ω
1%
10pF
FREQUENCY (kHz)
0
MAGNITUDE (dB)
0
–10
–30
–50
–70
–20
–40
–60
–80
–90
–100
–110
400800200600
624678 F04
1000
fIN = 350.195kHz
f
SAMP
= 2.2Msps
SFDR = 82dB
SNR = 70dB
1024 POINT FFT
C3
0.1µF
LTC6246
–
+
624678 F05
3V
LT6003
–
+
3V
3V
3V
V
OUT
= VR + IPD • 1M
–3dB BW = 700kHz
I
CC
= 2.2mA
OUTPUT NOISE = 160µV
RMS
MEASURED ON A 1MHz BW
V
OUT
IS REFERRED TO V
R
AT ZERO PHOTOCURRENT, V
OUT
= V
R
V
R
R1
1M, 1%
R3
1k
R2
1k
C2
6.8nF
FILM
OR NPO
Q1
NXP
BF862
PD1
OSRAM
SFH213
I
PD
R5
20k
R4
10k
R6
10M
C1
0.1pF
R7
1k
C4
1µF
Typical applicaTions
12-Bit ADC Driver
Figure 3 shows the LTC6246 driving an LTC2366 12-bit A/D
converter. The low wideband noise of the LTC6246 maintains a 70dB SNR even without the use of an intermediate
antialiasing RC filter. On a single 3.3V supply with a 2.5V
reference, a full –1dBFS output can be obtained without
the amplifier transitioning between input regions, thus
minimizing crossover distortion. Figure 4 shows an FFT
obtained with a sampling rate of 2.2Msps and a 350kHz
input waveform. Spurious free dynamic range is a quite
handsome 82dB.
Low Noise Low Power DC-Accurate Single Supply
Photodiode Amplifier
Figure 5 shows the LTC6246 applied as a low power high
performance transimpedance amplifier for a photodiode.
A low noise JFET Q1 acts as a current buffer, with R2 and
R3 imposing a low frequency gain of approximately 1.
Transimpedance gain is set by feedback resistor R1 to
1MΩ. R4 and R5 set the LTC6246 inputs at 1V below
the 3V rail, with C3 reducing their noise contribution.
By feedback this 1V also appears across R2, setting the
JFET quiescent current at 1mA completely independent
of its pinchoff voltage and I
this by placing the JFETs 1mA V
characteristics. It does
DSS
at the gate referenced
GS
to the source, which is sitting 1V above ground. For this
JFET, that will typically be about 500mV, and this voltage
is imposed as a reverse voltage on the photodiode PD1.
At zero I
photocurrent, the output sits at the same volt-
PD
age and rises as photocurrent increases. As mentioned
before, R2 and R3 set the JFET gain to 1 at low frequency.
Figure 3. Single Supply 12-Bit ADC Driver
16
Figure 4. 350kHz FFT Showing 82dB SFDR
Figure 5. Low Noise Low Power DC Accurate
Single Supply Photodiode Amplifier
624678fa
Page 17
Typical applicaTions
624678 F06
–
+
1k
2.5V
–2.5V
2.5V
–2.5V
V
IN
1/2LTC6247
50Ω
1.5k
–
+
1/2LTC6247
660nF
V
OUT
30k
FREQUENCY (kHz)
10k
GAIN (dB)
65
60
50
40
30
55
45
35
25
20
1M100k10M
624678 F07
VS = ±2.5V
V
IN
= 4.5mV
P-P
RL = 1kΩ
DC GAIN = 30dB
(DUE TO 660nF DC BLOCKING CAP)
OUTPUT OFFSET = 4mV
624678 F08
56pF
–
+
V
IN
1.1k2.3k
1/2LTC6247
12pF
2.7k
2.7V
1.2V
910Ω
910Ω
–
+
1/2LTC6247
120pF
2.7V
V
OUT
5.6pF
1.1k
FREQUENCY (kHz)
10k
GAIN (dB)
10
–10
–30
–50
–70
–20
–40
–60
–80
–90
0
–100
100k10M1M
624678 F09
100M
VS = 2.7V, 0V
V
IN
= 2V
P-P
RL = 1kΩ to 0V
LTC6246/LTC6247/LTC6248
This is not the lowest noise configuration for a transistor, as
downstream noise sources appear at the input completely
unattenuated. At low frequency, this is not a concern for a
transimpedance amplifier because the noise gain is 1 and
the output noise is dominated by the 130nV/√Hz of the 1MΩ
R1. However, at increasing frequencies the capacitance
of the photodiode comes into play and the circuit noise
gain rises as the 1MΩ feedback looks back into lower and
lower impedance. But capacitor C2 comes to the rescue.
In addition to the obvious quenching of noise source R3,
capacitor C2 increases the JFET gain to about 30 at high
frequency effectively attenuating the downstream noise
contributions of R2 and the op amp input noise. Thus the
circuit achieves low input voltage noise at high frequency
where it is most needed. Amplifier LT6003 is used to
buffer the output voltage of the photodiode and R7 and
C4 are used to filter out the voltage noise of the LT6003.
Bandwidth to 700kHz was achieved with this circuit, with
integrated output noise being 160µV
up to 1MHz. Total
RMS
supply current was a very low 2.2mA.
60dB 5.5MHz Gain Block
Figure 6 shows the LTC6247 configured as a low power
high gain high bandwidth block. Two amplifiers each
configured with a gain of 31V/V, are cascaded in series. A
660nF capacitor is used to limit the DC gain of the block
to around 30dB to minimize output offset voltage. Figure 7
shows the frequency response of the block. Mid-band
voltage gain is approximately 60dB with a –3dB frequency
of 5.5MHz, thus resulting in a gain-bandwidth product of
5.5GHz with only 1.9mA of quiescent supply current.
Single 2.7V Supply 4MHz 4th Order Butterworth Filter
Benefitting from low voltage operation and rail-to-rail
output, a low power filter that is suitable for antialiasing
can be built as shown in Figure 8. On a 2.7V supply the
filter has a passband of approximately 4MHz with 2V
P-P
input signal and a stopband attenuation that is greater than
–75dB at 43MHz as shown in Figure 9. The resistor and
capacitor values can be scaled to reduce noise at the cost
of large signal power consumption and distortion.
Figure 6. 60dB 5.5MHz Gain Block
Figure 8. Single 2.7V Supply 4MHz
4th Order Butterworth Filter
Figure 7
Figure 9
624678fa
17
Page 18
LTC6246/LTC6247/LTC6248
2.00 p0.10
2.00 p0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
0.64 p 0.10
0.55 p0.05
R = 0.115
TYP
R = 0.05
TYP
1.35 REF
1.37 p 0.10
1
4
85
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.125 REF
0.00 – 0.05
(KC8) UTDFN 0107 REVØ
0.23 p 0.05
0.45 BSC
0.25 p 0.05
1.35 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.64 p0.05
1.37 p0.05
1.15 p0.05
0.70 p0.05
2.55 p0.05
PACKAGE
OUTLINE
0.45 BSC
PIN 1 NOTCH
R = 0.20 OR
0.25 s 45o
CHAMFER
MSOP (MS8) 0307 REV F
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 p 0.0508
(.004 p .002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2
3
4
4.90 p 0.152
(.193 p .006)
8
7
6
5
3.00 p 0.102
(.118 p .004)
(NOTE 3)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 p 0.038
(.0165 p .0015)
TYP
0.65
(.0256)
BSC
package DescripTion
8-Lead Plastic UTDFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1749 Rev Ø)
KC Package
18
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
624678fa
Page 19
package DescripTion
MSOP (MS) 0307 REV E
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
1 2
3
4 5
4.90 ± 0.152
(.193 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910
7
6
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010)
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
0.1016 ± 0.0508
(.004 ± .002)
LTC6246/LTC6247/LTC6248
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
624678fa
19
Page 20
LTC6246/LTC6247/LTC6248
MSOP (MS16) 1107 REV Ø
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
16151413121110
1 2 3 4 5 6 7 8
9
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010)
0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 p 0.038
(.0120 p .0015)
TYP
0.50
(.0197)
BSC
4.039 p 0.102
(.159 p .004)
(NOTE 3)
0.1016 p 0.0508
(.004 p .002)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0.280 p 0.076
(.011 p .003)
REF
4.90 p 0.152
(.193 p .006)
package DescripTion
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
MS Package
20
624678fa
Page 21
package DescripTion
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302 REV B
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX
0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
LTC6246/LTC6247/LTC6248
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
624678fa
21
Page 22
LTC6246/LTC6247/LTC6248
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.22 – 0.36
8 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3)
TS8 TSOT-23 0802
2.90 BSC
(NOTE 4)
0.65 BSC
1.95 BSC
0.80 – 0.90
1.00 MAX
0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.52
MAX
0.65
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
package DescripTion
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637)
TS8 Package
22
624678fa
Page 23
LTC6246/LTC6247/LTC6248
revision hisTory
REVDATEDESCRIPTIONPAGE NUMBER
A2/10Changes to Graph G159
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
624678fa
23
Page 24
LTC6246
+
–
624678 TA02a
V
OUT
≈ 0.5V + IPD • 1M
3V
R1
1M, 1%
3V
3V
R2
1k
I
PD
C3
0.1µF
C1
0.1pF
R5
20k
R4
10k
R3
1k
–3dB BW = 700kHz
I
CC
= 2.2mA
OUTPUT NOISE = 153µV
RMS
MEASURED ON A 1MHz BW
C2
6.8nF
FILM
OR NPO
PD1
OSRAM
SFH213
Q1
NXP
BF862
20nV/√Hz/DIV
200
0
624678 TA02b
100kHz
1MHz
10kHz
0V
5V/DIV
LED DRIVER
VOLTAGE
624678 TA02c
500ns/DIV
500mV/DIV
OUTPUT
WAVEFORM
LTC6246/LTC6247/LTC6248
Typical applicaTion
700kHz, 1MΩ Single Supply Photodiode AmplifierOutput Noise SpectrumTransient Response
relaTeD parTs
PART NUMBER DESCRIPTIONCOMMENTS
Operational Amplifiers
LT1818/LT1819 Single/Dual Wide Bandwidth, High Slew Rate Low Noise and
Distortion Op Amps
LT1806/LT1807 Single/Dual Low Noise Rail-to-Rail Input and Output Op Amps 325MHz, 13mA, 3.5nV/√Hz, 140V/µs, 550µV, 85mA Output Drive
LT6230/LT6231/
Single/Dual/Quad Low Power High Speed Rail-to-Rail Input
and Output Op Amps
LT6244Dual High Speed CMOS Op Amp50MHz, 7.4mA, 8nV/√Hz, 35V/µs, 100µV, Input Bias Current = 1pA
LT1632/LT1633 Dual/Quad Rail-to-Rail Input and Output Precision Op Amps45MHz, 4.3mA, 12nV/√Hz, 45V/µs, 1.35mV
LT1630/LT1631 Dual/Quad Rail-to-Rail Input and Output Op Amps30MHz, 3.5mA, 6nV/√Hz, 10V/µs, 525µV
LT1358/LT1359 Dual/Quad Low Power High Speed Op Amps25MHz, 2.5mA, 8nV/√Hz , 600V/µs, 800µV, Drives All Capacitive Loads
ADC’s
LTC23663Msps, 12-Bit ADC Serial I/O72dB SNR, 7.8mW No Data Latency TSOT-23 Package
LTC23651Msps, 12-Bit ADC Serial I/O73dB SNR, 7.8mW No Data Latency TSOT-23 Package
LTC1417Low Power 14-Bit 400ksps ADC Parallel I/OSingle 5V or ±5V Supplies, 0V to 4.096V or ±2.048V Input Range
LTC1274Low Power 12-Bit 400ksps ADC Parallel I/O10mW Single 5V or ±5V Supplies, 0V to 4.096V or ±2.048V Input Range
24
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
400MHz, 9mA, 6nV/√Hz, 2500V/µs, 1.5mV –85dBc at 5MHz
–96.5dB THD at 10V
, 100kHz
P-P
85MHz, 3mA, 21nV√Hz, 100V/µs, 2mV
80MHz, 2mA, 8.5nV√Hz, 25V/µs, 350µV
60MHz, 1mA, 10nV/√Hz, 20V/µs, 350µV
LT 0210 REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2009
624678fa
Page 25
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