Datasheet LTC485IN8, LTC485CS8, LTC485CN8, LTC485, LTC485MJ8 Datasheet (Linear Technology)

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LTC485

Low Power RS485

Interface Transceiver

EATU

■

Low Power: ICC = 300µA Typ

■

Designed for RS485 Interface Applications

■

Single 5V supply

■

–7V to 12V Bus Common-Mode Range Permits

±7V Ground Difference Between Devices on the Bus

■

Thermal Shutdown Protection

■

Power-Up/Down Glitch-Free Driver Outputs Permit Live Insertion or Removal of Transceiver

■

Driver Maintains High Impedance in Three-State or with the Power Off

■

Combined Impedance of a Driver Output and Receiver Allows Up to 32 Transceivers on the Bus

■

70mV Typical Input Hysteresis

■

30ns Typical Driver Propagation Delays with 5ns Skew

■

Pin Compatible with the SN75176A, DS75176A and µA96176

PPLICATI

DUESCRIPTIO

The LTC485 is a low power differential bus/line transceiver designed for multipoint data transmission standard RS485 applications with extended common-mode range (12V to –7V). It also meets the requirements of RS422.

The CMOS design offers significant power savings over its bipolar counterpart without sacrificing ruggedness against overload of ESD damage.

The driver and receiver feature three-state outputs, with the driver outputs maintaining high impedance over the entire common-mode range. Excessive power dissipation caused by bus contention or faults is prevented by a thermal shutdown circuit which forces the driver outputs into a high impedance state.

The receiver has a fail-safe feature which guarantees a high output state when the inputs are left open.

The LTC485 is fully specified over the commercial and extended industrial temperature range.

■

Low Power RS485/RS422 Transceiver

■

Level Translator

PPLICATITYPICAL

RO1

RE1 DE1

DI1

RO2

RE2 DE2

DI2

CC1

  GND1

CC2

  GND2



LTC485 • TA01

Driver Outputs

LTC485 • TA02

LTC485

LUTEXI T

WUW

ARB

U G

PACKAGE

RDER I FOR ATIO

(Note 1)

Supply Voltage ....................................................... 12V

Control Input Voltages ................... – 0.5V to VCC + 0.5V

Driver Input Voltage....................... – 0.5V to VCC + 0.5V

Driver Output Voltage ........................................... ±14V

RO

RE DE

Receiver Input Voltage.......................................... ±14V

Receiver Output Voltages .............. –0.5V to VCC + 0.5V

Operating Temperature Range

J8 PACKAGE

8-LEAD CERAMIC DIP

LTC485I...................................... –40°C ≤ TA ≤ 85°C

LTC485C.......................................... 0°C ≤ TA ≤ 70°C

LTC485M.................................. – 55°C ≤ TA ≤ 125°C

Lead Temperature (Soldering, 10 sec)................. 300°C

LECTRICAL C CHARA TERIST

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

OD1

OD2

∆V

∆V

IN1

IN2

∆V

OZR

OSD1

OSD2

OSR

Differential Driver Output Voltage (Unloaded) IO = 0 ● 5V Differential Driver Output Voltage (with Load) R = 50Ω (RS422) ● 2V

Change in Magnitude of Driver R = 27Ω or R = 50Ω, Figure 1 ● 0.2 V DifferentialOutput Voltage for Complementary States

Driver Common-Mode Output Voltage R = 27Ω or R = 50Ω, Figure 1 ● 3V

 Change in Magnitude of Driver R = 27Ω or R = 50Ω, Figure 1 ● 0.2 V

Common-Mode Output Voltage for Complementary States

Input High Voltage DE, DI, RE ● 2V Input Low Voltage DE, DI, RE ● 0.8 V Input Current DE, DI, RE ● ±2 µA Input Current (A, B) DE = 0, VCC = 0V VIN = 12V ● ±1mA

Differential Input Threshold Voltage –7V ≤ VCM ≤ 12V ● –0.2 0.2 V for Receiver

Receiver Input Hysteresis VCM = 0V ● 70 mV Receiver Output High Voltage IO = –4mA, VID = 200mV ● 3.5 V Receiver Outpu Low Voltage IO = 4mA, VID = –200mV ● 0.4 V Three-State (High Impedance) Output VCC = Max, 0.4V ≤ VO ≤ 2.4V ● ±1 µA

Current at Receiver Receiver Input Resistance –7V ≤ VCM ≤ 12V ● 12 kΩ Supply Current No Load, Pins 2, Outputs Enabled ● 500 900 µA

Driver Short-Circuit Current, V Driver Short-Circuit Current, V Receiver Short-Circuit Current 0V ≤ VO ≤ V

= HIGH VO = –7V ● 35 100 250 mA

OUT

= LOW VO = 10V ● 35 100 250 mA

OUT

ICS

= 5V ±5%, unless otherwise noted. (Notes 2 and 3)

R = 27Ω (RS485), Figure 1

or 5.25V

3, 4 = 0V or 5V

T T

= –7V ● –0.8 mA

Outputs Disabled

TOP VIEW

1 2 3

JMAX JMAX JMAX

S8 PACKAGE

8-LEAD PLASTIC SOIC

= 155°C, θ = 100°C, θ = 100°C, θ



8

8-LEAD PLASTIC DIP

= 100°C/ W (J)

= 130°C/ W (N)

= 170°C/ W (S)

B

7

A

6

GND

5



N8 PACKAGE

● 1.5 5 V

● 300 500 µA

● 785mA

ORDER PART

NUMBER

LTC485CJ8 LTC485CN8 LTC485CS8 LTC485IN8 LTC485IS8 LTC485MJ8

S8 PART MARKING

485 485I

LTC485

SWITCHI G CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PLH

PHL

SKEW

, t

tZHDriver Enable to Output High CL = 100pF (Figures 4 and 6) S2 Closed ● 40 70 ns t

PLH

PHL

SKD

Driver Input to Output R Driver Input to Output Driver Output to Output ● 510ns Driver Rise or Fall Time ● 31525ns

Driver Enable to Output Low CL = 100pF (Figures 4 and 6) S1 Closed ● 40 70 ns Driver Disable Time from Low CL = 15pF (Figures 4 and 6) S1 Closed ● 40 70 ns Driver Disable Time from High CL = 15pF (Figures 4 and 6) S2 Closed ● 40 70 ns Receiver Input to Output R

t

– t

PLH

 Differential Receiver Skew ● 13 ns

PHL

Receiver Enable to Output Low CRL = 15pF (Figures 2 and 8) S1 Closed ● 20 50 ns Receiver Enable to Output High CRL = 15pF (Figures 2 and 8) S2 Closed ● 20 50 ns Receiver Disable from Low CRL = 15pF (Figures 2 and 8) S1 Closed ● 20 50 ns Receiver Disable from High CRL = 15pF (Figures 2 and 8) S2 Closed ● 20 50 ns

VCC = 5V ±5%, unless otherwise noted. (Notes 2 and 3)

= 54Ω, CL1 = CL2 = 100pF, ● 10 30 50 ns

DIFF

(Figures 3 and 5)

= 54Ω, CL1 = CL2 = 100pF, ● 30 90 200 ns

DIFF

(Figures 3 and 7)

● 10 30 50 ns

● 30 90 200 ns

The ● denotes specifications which apply over the full operating temperature range.

Note 1: Absolute maximum ratings are those beyond which the safety of the device cannot be guaranteed.

Note 2: All currents into device pins are positive; all currents out ot device pins are negative. All voltages are referenced to device ground unless otherwise specified.

TEST CIRCUITS

Figure 1. Driver DC Test Load Figure 2. Receiver Timing Test Load

LTC485 • F01

DIFF

15pF

LTC485 • F03

Note 3: All typicals are given for V

= 5V and TA = 25°C.

Note 4: The LTC485 is guaranteed by design to be functional over a supply voltage range of 5V ±10%. Data sheet parameters are guaranteed over the tested supply voltage range of 5V ±5%.

RECEIVER

OUTPUT

OUTPUT

UNDER TEST

TEST POINT

15pF



500Ω

LTC485 • F02

Figure 3. Driver/Receiver Timing Test Circuit Figure 4. Driver Timing Test Load #2

LTC485

UW W

SWITCHI G TI E WAVEFOR S

A, B

–V

1/2 V

1.5V

10%

f = 1MHz, tr ≤ 10ns, tf ≤ 10ns

PLH

SKEW

80%

DIFF

= V(A) – V(B)

PLH

1.5V

1/2 V

SKEW

90%

20%

LTC485 • F05

Figure 5. Driver Propagation Delays

1.5V

f = 1MHz, tr ≤ 10ns, tf ≤ 10ns

2.3V

OUTPUT NORMALLY LOW

OUTPUT NORMALLY HIGH

1.5V

0.5V

LTC485 • F06

A, B

Figure 6. Driver Enable and Disable Times

–V

OD2

PHL

1.5V

f = 1MHz, tr ≤ 10ns, tf ≤ 10ns

OUTPUT

INPUT

1.5V

PLH

LTC485 • F07

Figure 7. Receiver Propagation Delays

1.5V

f = 1MHz, tr ≤ 10ns, tf ≤ 10ns

1.5V

OUTPUT NORMALLY LOW

OUTPUT NORMALLY HIGH

1.5V

0.5V

LTC485 • F08

Figure 8. Receiver Enable and Disable Times

LTC485

TEMPERATURE (°C)

–50

3.0

OUTPUT VOLTAGE (V)

3.2

3.6

3.8

4.0

4.8

LTC485 • TPC03

3.4

0 125

4.2

4.4

4.6

–25

25 50

100

I = 8mA

FU CTIO TABLES

LTC485 Transmitting

INPUTS OUTPUTS

RE DE DI B A

X 1 1 No Fault 0 1 X 1 0 No Fault 1 0 X0X X ZZ X 1 X Fault Z Z

LTC485 Receiving

INPUTS OUTPUTS

RE DE A – B R

00≥0.2V 1 00≤–0.2V 0 0 0 Inputs Open 1 10 X Z

LINE

CONDITION

UU U

PI FU CTIO S

PIN # NAME DESCRIPTION

1 RO Receiver Output. If the receiver output is enabled

(RE low), then if A > B by 200mV, RO will be high. If A < B by 200mV, then RO will be low.

2 RE Receiver Output Enable. A low enables the

receiver output, RO. A high input forces the receiver output into a high impedance state.

3 DE Driver Outputs Enable. A high on DE enables the

driver output. A and B, and the chip will function as a line driver. A low input will force the driver outputs into a high impedance state and the chip will function as a line receiver.

4 DI Driver Input. If the driver outputs are enabled

(DE high), then a low on DI forces the outputs A low and B high. A high on DI with the driver

outputs enabled will force A high and B low. 5 GND Ground Connection. 6 A Driver Output/Receiver Input. 7 B Driver Output/Receiver Input. 8V

Positive Supply; 4.75 < VCC < 5.25

OUTPUT CURRENT (mA)

LPER

Receiver Output Low Voltage vs Output Current

TA = 25°C

0.5 2.0

OUTPUT VOLTAGE (V)

1.0

1.5

ATYPICA

LTC485 • TPC01

CCHARA TERIST

Receiver Output High Voltage vs Output Current

–18

TA = 25°C

–16

–14

–12

–10

–8

–6

OUTPUT CURRENT (mA)

–4

–2

ICS

OUTPUT VOLTAGE (V)

Receiver Output High Voltage vs Temperature

LTC485 • TPC02

LTC485

TEMPERATURE (°C)

–50

1.5

DIFFERENTIAL VOLTAGE (V)

1.6

1.8

1.9

2.0

2.4

LTC485 • TPC06

1.7

0 125

2.1

2.2

2.3

–25

25 50

100

RI = 54Ω

TEMPERATURE (°C)

–50

1.55

INPUT THRESHOLD VOLTAGE (V)

1.56

1.58

1.59

1.60

1.64

LTC485 • TPC09

1.57

0 125

1.61

1.62

1.63

–25

25 50

100

TEMPERATURE (°C)

–50

100

SUPPLY CURRENT (µA)

160

280

340

400

640

LTC485 • TPC12

220

0 125

460

520

580

–25

25 50

100

DRIVER ENABLED

DRIVER DISABLED

LPER

ATYPICA

CCHARA TERIST

ICS

Receiver Output Low Voltage vs Temperature

0.9 I = 8mA

0.8

0.7

0.6

0.5

0.4

0.3

OUTPUT VOLTAGE (V)

0.2

0.1

–50

–25

25 50

0 125

TEMPERATURE (°C)

Driver Output Low Voltage vs Output Current

TA = 25°C

OUTPUT CURRENT (mA)

OUTPUT VOLTAGE (V)

LTC485 • TPC03

LTC485 • TPC07

100

Driver Differential Output Voltage vs Output Current

TA = 25°C

OUTPUT CURRENT (mA)

OUTPUT VOLTAGE (V)

LTC485 • TPC05

Driver Output High Voltage vs Output Current

–108

–96

–84

–72

–60

–48

–36

OUTPUT CURRENT (mA)

–24

–12

OUTPUT VOLTAGE (V)

TA = 25°C

LTC485 • TPC08

Driver Differential Output Voltage vs Temperature

TTL Input Threshold vs Temperature

Receiver t vs Temperature

7.5

7.0

6.5

6.0

5.5

5.0

TIME (ns)

4.5

4.0

3.5

3.0 –50

–25

– t

PHL

25 50



LTC485 • TPC10

100

PLH

0 125 TEMPERATURE (°C)

Driver Skew vs Temperature

5.4

4.8

4.2

3.6

3.0

2.4

TIME (ns)

1.8

1.2

0.6

–50

–25

25 50

0 125 TEMPERATURE (°C)

100

LTC485 • TPC11

Supply Current vs Temperature

UU W U

APPLICATIO S I FOR ATIO

LTC485

Basic Theory of Operation

Previous RS485 transceivers have been designed using bipolar technology because the common-mode range of the device must extend beyond the supplies and the device must be immune to ESD damage and latchup. Unfortunately, the bipolar devices draw a large amount of supply current, which is unacceptable for the numerous applications that require low power consumption. The LTC485 is the first CMOS RS485/RS422 transceiver which features ultra-low power consumption without sacrificing ESD and latchup immunity.

The LTC485 uses a proprietary driver output stage, which allows a common-mode range that extends beyond the power supplies while virtually eliminating latchup and providing excellent ESD protection. Figure 9 shows the LTC485 output stage while Figure 10 shows a conventional CMOS output stage.

When the conventional CMOS output stage of Figure 10 enters a high impedance state, both the P-channel (P1) and the N-channel (N1) are turned off. If the output is then driven above VCC or below ground, the P + /N-well diode

(D1) or the N + /P-substrate diode (D2) respectively will turn on and clamp the output to the supply. Thus, the output stage is no longer in a high impedance state and is not able to meet the RS485 common-mode range requirement. In addition, the large amount of current flowing through either diode will induce the well known CMOS latchup condition, which could destroy the device.

The LTC485 output stage of Figure 9 eliminates these problems by adding two Schottky diodes, SD3 and SD4. The Schottky diodes are fabricated by a proprietary modification to the standard N-well CMOS process. When the output stage is operating normally, the Schottky diodes are forward biased and have a small voltage drop across them. When the output is in the high impedance state and is driven above VCC or below ground, the parasitic diodes D1 or D2 still turn on, but SD3 or SD4 will reverse bias and prevent current from flowing into the N-well or the substrate. Thus, the high impedance state is maintained even with the output voltage beyond the supplies. With no minority carrier current flowing into the N-well or substrate, latchup is virtually eliminated under power-up or power-down conditions.

SD3

LOGIC

Figure 9. LTC485 Output Stage

OUTPUT

SD4

LTC485 • F09

LOGIC

Figure 10. Conventional CMOS Output Stage

OUTPUT

LTC485 • F10

LTC485

UU W U

APPLICATIO S I FOR ATIO

The LTC485 output stage will maintain a high impedance state until the breakdown of the N-channel or P-channel is reached when going positive or negative respectively. The output will be clamped to either VCC or ground by a Zener voltage plus a Schottky diode drop, but this voltage is way beyond the RS485 operating range. This clamp protects the MOS gates from ESD voltages well over 2000V. Because the ESD injected current in the N-well or substrate consists of majority carriers, latchup is prevented by careful layout techniques.

DRIVER

OUTPUTS

RECEIVER

OUTPUT

Propagation Delay

Many digital encoding schemes are dependent upon the difference in the propagation delay times of the driver and the receiver. Using the test circuit of Figure 13, Figures 11 and 12 show the typical LTC485 receiver propagation delay.

The receiver delay times are:

t

PLH

– t

 = 9ns Typ, V

PHL

= 5V

The driver skew times are:

Skew = 5ns Typ, VCC = 5V

10ns Max, VCC = 5V, TA = –40°C to 85°C

DRIVER

OUTPUTS

RECEIVER

OUTPUT

Figure 11. Receiver t

, tf < 6ns

LTC485 • F11

PHL

TTL IN

100pF

R 100Ω

100pF

LTC485 • F13

Figure 12. Receiver t

RECEIVER

OUT

Figure 13. Receiver Propagation Delay Test Circuit

LTC485 • F12

PLH

UU W U

MAXIMUM DATA RATE

10k

CABLE LENGTH (FT)

100

10k

100k 1M 10M

LTC485 • F19

2.5M

APPLICATIO S I FOR ATIO

LTC485

LTC485 Line Length vs Data Rate

The maximum line length allowable for the RS422/RS485 standard is 4000 feet.

100Ω

4000 FT 26AWG TWISTED PAIR

LTC485LTC485

TTL OUT

TTL IN

NOISE

GENERATOR

Figure 14. Line Length Test Circuit

Using the test circuit in Figure 14, Figures 15 and 16 show that with ~20V

common-mode noise injected on the

P-P

line, The LTC485 is able to reconstruct the data stream at the end of 4000 feet of twisted pair wire.

Figures 17 and 18 show that the LTC485 is able to comfortably drive 4000 feet of wire at 110kHz.

COMMON-MODE

VOLTAGE (A + B)/2

LTC485 • F17

Figure 17. System Common-Mode Voltage at 110kHz

COMMON-MODE

VOLTAGE (A – B)

COMMON-MODE

VOLTAGE (A + B)/2

LTC485 • F18

Figure 18. System Differential Voltage at 110kHz

When specifying line length vs maximum data rate the

LTC485 • F15

Figure 15. System Common-Mode Voltage at 19.2kHz

DIFFERENTIAL

VOLTAGE A – B

LTC485 • F16

curve in Figure 19 should be used:

Figure 16. System Differential Voltage at 19.2kHz

Figure 19. Cable Length vs Maximum Data Rate

LTC485

TYPICAL APPLICATIO S

Typical RS485 Network

PACKAGE DESCRIPTIO

LTC485 • TA03

Dimensions in inches (millimeters) unless otherwise noted.

J8 Package

8-Lead Ceramic DIP

0.005

(0.127)

MIN

0.405

(10.287)

MAX

CORNER LEADS OPTION 

(4 PLCS)

0.023 – 0.045

(0.584 – 1.143)

HALF LEAD

0.045 – 0.068

(1.143 – 1.727)

FULL LEAD

OPTION

NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP OR TIN PLATE LEADS.

OPTION

(7.366 – 8.128)

0.008 – 0.018

(0.203 – 0.457)

0.385 ± 0.025

(9.779 ± 0.635)

0.290 – 0.320

0° – 15°

0.025

(0.635)

RAD TYP

0.045 – 0.068

(1.143 – 1.727)



0.014 – 0.026

(0.360 – 0.660)

0.220 – 0.310

(5.588 – 7.874)

0.015 – 0.060

(0.381 – 1.524)

0.100 ± 0.010

(2.540 ± 0.254)

0.200

(5.080)

MAX

0.125

3.175 MIN

J8 0293

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

N8 Package

8-Lead Plastic DIP

0.400

(10.160)

MAX

876

LTC485

0.300 – 0.320

(7.620 – 8.128)

0.065

(1.651)

0.009 – 0.015

(0.229 – 0.381)

+0.025

0.325

–0.015

+0.635

8.255

()

–0.381

TYP

0.045 ± 0.015

(1.143 ± 0.381)

(2.540 ± 0.254)

0.045 – 0.065

(1.143 – 1.651)

0.100 ± 0.010

S8 Package

8-Lead Plastic SOIC

0.250 ± 0.010

(6.350 ± 0.254)

0.130 ± 0.005

(3.302 ± 0.127)

0.125

(3.175)

MIN

0.018 ± 0.003

(0.457 ± 0.076)



0.020

(0.508)



MIN

N8 0392

(0.254 – 0.508)

0.008 – 0.010

(0.203 – 0.254)

0.189 – 0.197

(4.801 – 5.004)

0.228 – 0.244

(5.791 – 6.197)

0.010 – 0.020

× 45°

0°– 8° TYP

0.016 – 0.050

0.406 – 1.270

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

0.150 – 0.157

(3.810 – 3.988)

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

BSC

SO8 0392

LTC485

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Linear Technology Corporation

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(408) 432-1900

●

FAX

: (408) 434-0507

●

TELEX

World Headquarters

Linear Technology Corporation

1630 McCarthy Blvd. Milpitas, CA 95035-7487 Phone: (408) 432-1900 FAX: (408) 434-0507

: 499-3977

06/24/93

LT/GP 0294 5K REV E • PRINTED IN THE USA

 LINEAR TECHNOLOGY CORPORATION 1994

Datasheet LTC485IN8, LTC485CS8, LTC485CN8, LTC485, LTC485MJ8 Datasheet (Linear Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual