Datasheet LTC4260 Datasheet (LINEAR TECHNOLOGY)

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Page 1

FEATURES

■

Allows Safe Insertion into Live Backplane

■

8-Bit ADC Monitors Current and Voltage

■

I2CTM/SMBus Interface

■

Wide Operating Voltage Range: 8.5V to 80V

■

High Side Drive for External N-Channel MOSFET

■

Input Overvoltage/Undervoltage Protection

■

Optional Latchoff or Autoretry After Faults

■

Alerts Host After Faults

■

Foldback Current Limiting

■

Available in 24-Lead SO, 24-Lead Narrow SSOP and 32-Lead (5mm × 5mm) QFN Packages

APPLICATIO S

■

Electronic Circuit Breakers

■

Live Board Insertion

■

Computers, Servers

LTC4260

Positive High Voltage

Hot Swap Controller with

C Compatible Monitoring

DESCRIPTIO

The LTC®4260 Hot SwapTM controller allows a board to be safely inserted and removed from a live backplane. Using an external N-channel pass transistor, the board supply voltage can be ramped up at an adjustable rate. An I2C interface and onboard ADC allow monitoring of board current, voltage and fault status.

The device features adjustable analog foldback current limit with latch off or automatic restart after the LTC4260 remains in current limit beyond an adjustable time-out delay.

The controller has additional features to interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a load card and power-up in either the on or off state.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATIO

3A, 48V Card Resident Application

48V

49.9k

0.1µF

1.74k

2.67k

SDA

SCL

ALERT

GND

*DIODES INC. SMBT70A

CONNECTOR 2

BACKPLANE PLUG-IN

CONNECTOR 1

CARD

UV OV SDAO SDAI SCL ALERT ON

INTV

0.010Ω

0.1µF

FDB3632

10Ω

6.8nF

GATE

SENSE

LTC4260

TIMER GND

68nF

100k

SOURCE

BD_PRST

ADIN

GPIO

4260 TA01

Power Up Waveforms

OUT

48V

43.5k

3.57k

24k

50V/DIV

2A/DIV

OUT

50V/DIV

GPIO

5V/DIV

CL = 1000µF

25ms/DIV

4260 TA02

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Page 2

LTC4260

WWWU

ABSOLUTE AXI U RATI GS

(Notes 1, 2)

Supply Voltages (V Input Voltages

SENSE ............................ V

SOURCE .......................... GATE – 5V to GATE + 0.3V

BD_PRST, FB, ON, OV, UV ................... – 0.3V to 12V

ADR0-ADR2, TIMER, ADIN ..... –0.3V to INTV

SCL, SDAI ........................................... –0.3V to 6.5V

Output Voltages

GPIO ................................................... –0.3V to 100V

GATE (Note 3) ..................................... –0.3V to 100V

) ............................ – 0.3V to 100V

– 10V or –0.3V to V

+ 0.3V

ALERT, SDAO ........................................... – 0.3V to 6.5V

Supply Voltage (INTV Operating Temperature Range

LTC4260C ............................................... 0°C to 70°C

LTC4260I............................................. –40°C to 85°C

Storage Temperature Range

GN, SW Packages............................. –65°C to 150°C

UH Package ...................................... –65°C to 125°C

Lead Temperature (Soldering, 10 sec)

GN, SW Packages Only..................................... 300°C

PACKAGE/ORDER I FOR ATIO

TOP VIEW

SENSE

GND

SCL

SDAI

SDAO

ALERT

TIMER

24-LEAD PLASTIC SSOP

= 125°C, θJA = 85°C/W

JMAX

GN PACKAGE

GATE

SOURCE

GPIO

INTV

ADR2

ADR1

ADR0

BD_PRST

ADIN

SENSE

GND

SCL

SDAI

SDAO

ALERT

TIMER

ORDER

PART NUMBER

LTC4260CGN LTC4260IGN

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

TOP VIEW

SW PACKAGE

24-LEAD PLASTIC SO

= 125°C, θJA = 75°C/W

JMAX

ORDER

PART NUMBER

LTC4260CSW LTC4260ISW

GATE

SOURCE

GPIO

INTV

ADR2

ADR1

ADR0

BD_PRST

ADIN

EXPOSED PAD (PIN 33) PCB ELECTRICAL CONNECTION OPTIONAL

PART NUMBER

) ......................... –0.3V to 6.2V

TOP VIEW

DDK

VDDV

SENSENCNC

32 31 30 29 28 27 26 25

1NC

GND

SCL

9 10 11 12

SDAI

SDAO

ALERT

32-LEAD (5mm × 5mm) PLASTIC QFN

UH PACKAGE

= 125°C, θJA = 34°C/W

JMAX

ORDER

13 14 15 16

ADIN

TIMER

BD_PRST

GATE

ADR0

UH PART

MARKING

LTC4260CUH LTC4260IUH

SOURCE

ADR1

4260

GPIO

INTV

ADR2

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

General

DD(UVL)

Input Supply Range

Input Supply Current

VDD Supply Undervoltage Lockout VDD Falling

●

8.5 80 V

●

7 7.45 7.9 V

25 mA

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Page 3

LTC4260

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. VDD = 48V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

INTV

CC(UVL)

VCC Supply Undervoltage Lockout INTVCC Falling

Internal Regulator Voltage

●

3.4 3.8 4.2 V

●

5 5.5 6 V

Gate Drive

∆V

GATE

GATE(UP)

GATE(FST)

GATE(DN)

SOURCE

Turn-On Delay

External N-Channel Gate Drive VDD = 20V to 80V (V

GATE

– V

SOURCE

= 8.5V to 20V

External N-Channel Pull-Up Current Gate Drive On, V

External N-Channel Fast Pull-Down Fast Turn Off, V

GATE

External N-Channel Pull-Down Current Gate Drive Off, V

SOURCE Pin Input Current SOURCE = 48V

GATE

= 48V, V

GATE

= 0V

= 58V, V

SOURCE

= 38V

= 48V

●

50 100 150 ms

●

10 14 18 V

●

4.5 6 18 V

●

–14 –18 –22 µA

●

400 600 1000 mA

●

0.7 1 1.4 mA

●

200 400 600 µA

Input Pins

ON(TH)

∆V

ON(HYST)

ON(IN)

OV(TH)

∆V

OV(HYST)

OV(IN)

UV(TH)

∆V

UV(HYST)

UV(IN)

UV(RTH)

∆V

UV(RHYST)

∆V

SENSE(TH)

SENSE(IN)

∆V

FB(HYST)

BD_PRST(TH)

∆V

BD_PRST(HYST)

BD_PRST

GPIO(TH)

∆V

GPIO(HYST)

GPIO(OL)

GPIO(IN)

ADIN

ON Pin Threshold Voltage VON Rising

ON Pin Hysteresis

ON Pin Input Current VON = 1.2V

OV Pin Threshold Voltage VOV Rising

OV Pin Hysteresis

OV Pin Input Current VOV = 3.5V

UV Pin Threshold Voltage VUV Rising

UV Pin Hysteresis

UV Pin Input Current VUV = 3.5V

UV Pin Reset Threshold Voltage VUV Falling

UV Pin Reset Threshold Hysteresis

Current Limit Sense Voltage Threshold VFB = 3.5V

– V

SENSE Pin Input Current V

SENSE

= 0V

SENSE

= 48V

Foldback Pin Power Good Threshold FB Rising

FB Pin Power Good Hysteresis

Foldback Pin Input Current FB = 3.5V

BD_PRST Input Threshold V

BD_PRST

Rising

BD_PRST Hysteresis

BD_PRST Pullup Current BD_PRST = 0V

GPIO Pin Input Threshold V

GPIO

Rising

●

1.19 1.235 1.27 V

●

60 130 200 mV

●

3.43 3.5 3.56 V

●

70 90 120 mV

●

3.43 3.5 3.56 V

●

310 380 440 mV

●

1.18 1.235 1.27 V

●

80 160 250 mV

●

45 50 55 mV

●

10 20 30 mV

●

70 100 130 µA

●

3.43 3.5 3.56 V

●

80 100 120 mV

●

1.2 1.235 1.27 V

●

70 130 190 mV

●

–7 –10 –16 µA

●

1.6 1.8 2 V

0 ±1 µA

0 ±2 µA

GPIO Pin Hysteresis 80 mV

GPIO Pin Output Low Voltage I

GPIO Pin Input Leakage Current V

ADIN Pin Input Resistance V

ADIN Pin Input Current V

GPIO

ADIN

= 2mA

= 80V

= 1.28V

= 2.56V

●

210 MΩ

●

0.25 0.5 V

0 ±10 µA

0 ±1 µA

Timer

TIMER(H)

TIMER(L)

TIMER(UP)

TIMER(DN)

TIMER(RATIO)

TIMER Pin High Threshold V

TIMER Pin Low Threshold V

TIMER Pin Pull-Up Current V

TIMER Pin Pull-Down Current V

TIMER Pin Current Ratio I

TIMER(DN)/ITIMER(UP)

TIMER

Rising

Falling

= 0V

= 1.3V

●

1.2 1.235 1.28 V

●

0.1 0.2 0.3 V

●

–80 –100 –120 µA

●

1.4 2 2.6 µA

●

1.6 2 2.7 %

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LTC4260

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. VDD = 48V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

AC Parameters

PLH(GATE)

Input High (ON) to GATE High C

GATE

= 1pF

●

13 µs

Propagation Delay

PHL(GATE)

Input High (OV, BD_PRST), Input Low C

GATE

= 1pF

●

0.5 3 µs

(ON, UV) to GATE Low Propagation Delay

PHL(SENSE)

(VDD – SENSE) High to GATE Low VDD – SENSE = 200mV, C

GATE

= 10nF

●

0.4 1 µs

ADC

Resolution (No Missing Codes) (Note 4)

Integral Nonlinearity VDD – SENSE (Note 5)

SOURCE ADIN

Offset Error VDD – SENSE

SOURCE ADIN

Full Scale Error (Note 6)

Total Unadjusted Error (Note 6)

Full Scale Voltage (Code 255) VDD – SENSE (Note 6)

SOURCE ADIN

●

8 Bits

●

75 76.5 78 mV

●

100 10.2 104 V

●

2.50 2.55 2.60 V

±0.5 ±2LSB ±0.2 ±1.25 LSB ±0.2 ±1.25 LSB

±1.5 LSB

±1LSB ±1LSB

±5LSB

Conversion Rate 10 Hz

I2C Interface

ADR(H)

ADR0 to ADR2 Input High Voltage

●

INTVCCINTVCCINTV

Threshold – 0.6 – 0.45 – 0.25

ADR(L)

ADR(IN)

SDAI,SCL(TH)

SDAI,SCL(IN)

SDAO(OL)

ALERT(OL)

SDAO,ALERT(IN)

ADR0 to ADR2 Input Low Voltage Threshold

ADR0 to ADR2 Input Current ADR0 to ADR2 = 0V, 5.5V

SDAI, SCL Input Threshold

SDAI, SCL Input Current SCL, SDAI = 5V

SDAO Output Low Voltage I

ALERT Output Low Voltage I

SDAO

ALERT

= 5mA

SDAO, ALERT Input Current SDAO, ALERT = 5V

●

0.25 0.45 0.65 V

●

–80 80 µA

●

1.6 1.8 2 V

●

0 ±1 µA

0.2 0.4 V

0 ±1 µA

I2C Interface Timing (Note 4)

SCL(MAX)

BUF(MIN)

Maximum SCL Clock Frequency Operates with f

SCL

≤ f

SCL(MAX)

400 kHz

Minimum Bus Free Time Between 0.12 1.3 µs Stop/Start Condition

SU,STA(MIN)

Minimum Repeated Start Condition 30 600 ns Set-Up Time

HD,STA(MIN)

Minimum Hold Time After (Repeated) Start 140 600 ns Condition

SU,STO(MIN)

SU,DAT(MIN)

HD,DATI(MIN)

HD,DATO(MIN)

SP(MAX)

Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired.

Minimum Stop Condition Set-Up Time 30 600 ns

Minimum Data Set-Up Time Input 30 100 ns

Minimum Data Hold Time Input –100 0 ns

Minimum Data Hold Time Output 300 500 900 ns

Maximum Suppressed Spike Pulse Width 50 110 250 ns

SCL, SDA Input Capacitance SDAI Tied to SDAO 5 10 pF

Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specified.

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ELECTRICAL CHARACTERISTICS

TEMPERATURE (°C)

–50

3.46

UV LOW-HIGH THRESHOLD (V)

3.48

3.50

3.52

3.54

–25 0 25 50

4260 G02

75 100

Note 3:

Limits on maximum rating is defined as whichever limit occurs first. An internal clamp limits the GATE pin to a minimum of 10V above source. Driving this pin to voltages beyond the clamp may damage the device.

Note 4: Guaranteed by design and not subject to test.

Note 6: For the V

above 200 may be discarded by offset cancellation. Full scale error and total unadjusted error are evaluated over the 0-200 code range. Full scale voltage corresponds to the theorectical code 255, and is extrapolated from a code 200 measurement.

Note 5: Integral nonlinearity is defined as the deviation of a code from a precise analog input voltage. Maximum specifications are limited by the LSB step size and the single shot measurement. Typical specificatons are measured from the 1/4, 1/2 and 3/4 areas of the quantization band.

TYPICAL PERFOR A CE CHARACTERISTICS

(mA)

IDD vs V

3.0

2.5

2.0

1.5

1.0 0

85°C

25°C

–40°C

VDD (V)

100

4260 G01

(V)

INTV

INT V

vs I

MAX I CAUTION: DRAWING CURRENT FROM INTV DISSIPATION AND T

= 4.5 mA

LOAD

–2 –6

LOAD

VDD = 48V

INCREASES POWER

–4 –8

(mA)

LOAD

VDD = 12V

LTC4260

-sense channel, full-scale is at code 255 but codes

TA = 25°C, VDD = 48V unless otherwise noted.

UV Low-High Threshold vs Temperature

–10

4260 G18

UV Hysteresis vs Temperature

0.39

0.38

0.37

0.36

UV HYSTERESIS (V)

0.35

0.34 –50

–25

02550

TEMPERATURE (°C)

75 100

4260 G03

ON, BD_PRST Low-High Threshold vs Temperature

1.245

1.240

1.235

1.230

1.225

ON, BD_PRST LOW-HIGH THRESHOLD (V)

1.220 –50

02550

–25

TEMPERATURE (°C)

75 100

4260 G04

ON, BD_PRST Hysteresis vs Temperature

0.16

0.15

0.14

0.13

0.12

ON, BD_PRST HYSTERESIS (V)

0.11

0.10 –50

02550

–25

TEMPERATURE (°C)

75 100

4260 G05

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LTC4260

VDD (V)

GATE DRIVE (V

GATE

– V

SOURCE

) (V)

20 30

4260 G11

10 15

25 35

85°C

25°C

–40°C

TYPICAL PERFOR A CE CHARACTERISTICS

= 25°C, VDD = 48V unless otherwise noted.

TIMER Pull-Up Current vs Temperature

–110

–105

–100

–95

TIMER PULL-UP CURRENT (µA)

–90

–50

–25 0 25 50

TEMPERATURE (°C)

Pull Up vs Temperature

GATE

–25

–20

PULL UP (µA)

–15

GATE

–10

–50

–25 0 25 50

TEMPERATURE (°C)

75 100

4260 G06

75 100

4260 G09

Current Limit Sense Voltage vs FB Voltage

) (mV)

SENSE

– V

0.5 1.5

CURRENT LIMIT SENSE VOLTAGE (V

Gate Drive vs I

) (V)

SOURCE

– V

GATE

GATE DRIVE (V

FB VOLTAGE (V)

GATE

VDD = 80V

VDD = 48V

VDD = 12V

GATE

–10

(µA)

–5

2.5

–15

3.5

4260 G07

4260 G10

–20

Current Limit Propagation Delay vs Sense Voltage

1000

100

CURRENT LIMIT PROPAGATION DELAY (µs)

0.1 0

50 100 150 200

CURRENT LIMIT SENSE VOLTAGE (VDD – V

Gate Drive vs V

250 300 350

SENSE

4260 G08

) (mV)

Gate Drive vs Temperature

) (V)

SOURCE

– V

GATE

GATE DRIVE (V

–50

–25

02550

TEMPERATURE (°C)

75 100

4260 G12

LOW (V)

OUT

GPIO V

10 20

Low vs I

OUT

LOAD

30 50

(mA)

LOAD

40 60

4260 G13

ADC Total Unadjusted Error vs Code (ADIN Pin)

–1

ADC TOTAL UNADJUSTED ERROR (LSB)

–2

128

CODE

192

256

4260 G14

4260fa

Page 7

CODE

ADC DNL (LSB)

0.25

256

4260 G17

–0.25

–0.50

128

192

0.50

TYPICAL PERFOR A CE CHARACTERISTICS

ADC Full-Scale Error vs Temperature (ADIN Pin)

ADC INL vs Code (ADIN Pin)

0.50

LTC4260

TA = 25°C, VDD = 48V unless otherwise noted.

ADC DNL vs Code (ADIN Pin)

–1

ADC FULL-SCALE ERROR (LSB)

–2

–50

–25 0 25 50

TEMPERATURE (°C)

75 100

3708 G15

0.25

ADC INL (LSB)

–0.25

–0.50

PI FU CTIO S

ADIN: ADC Input. A voltage between 0V and 2.56V applied to this pin can be measured by the onboard ADC. Tie to ground if unused.

ADR0 to ADR2: Serial Bus Address Inputs. Tying these pins to ground, open or INTV sible addresses. See Table 1 in Applications Information.

ALERT: Fault Alert Output. Open-drain logic output that can be pulled to ground when a fault occurs to alert the host controller. A fault alert is enabled by the ALERT register. This device is compatible with SMBus alert protocol. See Applications Information. Tie to ground if unused.

BD_PRST: Board Present Input. Ground this pin to enable the N-channel FET to turn on after 100ms debounce delay. When this pin is high, the FET is off. An internal 10µA current source pulls up this pin. Transitions on this pin will be recorded in the FAULT register. A high-to-low transition activates the logic to read the state of the ON pin and clear Faults. See Applications Information.

configures one of 27 pos-

128

CODE

192

256

4260 G16

Exposed Pad (Pin 33, UH Package): Exposed Pad may be left open or connected to device ground.

FB: Foldback and Power Good Input. A resistive divider from the output voltage is tied to this pin. When the voltage at this pin drops below 3.41V, the output power is considered bad and the current limit is reduced. The power bad condition can be indicated with the GPIO pin and a power bad fault can be logged in this condition. See Applications Information.

GATE: Gate Drive for External N-Channel FET. An internal 18µA current source charges the gate of the external N-channel MOSFET. A resistor and capacitor network from this pin to ground sets the turn-on rate and compensates the active current limit. During turn-off there is a 1mA pull-down current. During a short circuit or undervoltage lockout (V

or INTVCC), a 600mA pull-down

current source between GATE and SOURCE is activated.

GND: Device Ground.

4260fa

Page 8

LTC4260

PI FU CTIO S

GPIO: General Purpose Input/Output. Open-drain logic output and logic input. Defaults to pull low to indicate power is bad. Configure according to Table 3.

NC: No Connect. Unconnected pins. These pins provide extra distance between high and low voltage pins.

ON: On Control Input. A rising edge turns on the external N-channel FET and a falling edge turns it off. This pin is also used to configure the state of the FET ON bit (and hence the external FET) at power up. For example if the ON pin is tied high, then the FET ON control bit (A3) will go high 100ms after power-up. Likewise if the ON pin is tied low then the part will remain off after power-up until the FET ON control bit is set high using the I transition on this pin will clear faults.

OV (GN/UH Packages): Overvoltage Comparator Input. Connect this pin to an external resistive divider from VDD. If the voltage at this pin rises above 3.5V, an overvoltage fault is detected and the switch turns off. Tie to GND if unused.

SCL: Serial Bus Clock Input. Data at the SDA pin is shifted in or out on rising edges of SCL. This is a high impedance pin that is generally driven by an open-collector output from a master controller. An external pull-up resistor or current source is required.

SDAI: Serial Bus Data Input. A high impedance input used for shifting in address, command or data bits. Normally tied to SDAO to form the SDA line.

SDAO: Serial Bus Data Output. Open-drain output used for sending data back to the master controller or acknowledging a write operation. Normally tied to SDAI to form the SDA line. An external pull-up resistor or current source is required.

C bus. A high-to-low

SENSE: Current Sense Input. Connect this pin to the output of the current sense resistor. The current limit circuit controls the GATE pin to limit the sense voltage between the V ing on the voltage at the FB pin. This pin is used as an input to the 8-bit ADC.

SOURCE: N-Channel MOSFET Source Connection and ADC Input. Connect this pin to the source of the external N-channel MOSFET switch. This pin also serves as the ADC input to monitor output voltage. The pin provides a return for the gate pull-down circuit and as a supply for the charge pump circuit.

TIMER: Timer Input. Connect a capacitor between this pin and ground to set a 12ms/µF duration for current limit before the switch is turned off. The duration of the off time is 518ms/µF when autoretry during current limit is enabled. A minimum value of 0.1nF must be connected to this pin.

UV: Undervoltage Comparator Input. Connect this pin to an external resistive divider from V pin falls below 3.12V, an undervoltage fault is detected and the switch turns off. Pulling this pin below 1.2V resets all faults and allows the switch to turn back on. Tie to INTV if unused.

: Supply Voltage and Current Sense Input. This pin has

an undervoltage lockout threshold of 7.45V.

INTV

Connect a 0.1µF capacitor from this pin to ground. This pin can be used to drive the other pins to logic high and has an undervoltage lockout threshold of 3.8V.

: Internal Low Voltage Supply Decoupling Output.

(UH Package): Same as VDD. Connect this pin to

DDK

. V

DDK

and SENSE pins to 50mV or less depend-

. If the voltage at this

tied to VDD internally with 18Ω.

4260fa

Page 9

LTC4260

FU CTIO AL DIAGRA

3.5V

OV GN/UH ONLY

INTV

10µA

BD_PRST

3.5V

1.235V

7.45V

–

RST

–

UVLO1

UVS

OVS

RESET

BOARD

PRESENT

ONS

UVLO

3.5V

0.2V

1.235V

–

INTERNAL

POWER

FOLDBACK

–

TM1

TM2

UH ONLY

DDK

18Ω

20mV TO

50mV

PWRGD FET ON

LOGIC

UVLO

SENSE

–

CHARGE

PUMP

AND

GATE

DRIVER

1.8V

–

INTV

100µA

5.5V GEN

2µA

GATE

SOURCE

GPIO

TIMER

INTV

UVLO2

3.8V

–

SDAI

SDAO

SCL

ALERT

– SENSE

A/D CONVERTER

C ADDR

1 OF 27

ADR0 ADR1 ADR2

GND

UH ONLY

SOURCE

EXPOSED PAD

ADIN

4260 BD

4260fa

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LTC4260

UWW

TI I G DIAGRA

SDAI/SDAO

SCL

HD, STA

SU, DAT

HD, DATO,

HD, DATI

SU, STA

HD, STA

SU , STO

BUF

4260 TD01

START

CONDITION

REPEATED START

OPERATIO

The Functional Diagram displays the main functional areas of this device. The LTC4260 is designed to turn a board’s supply voltage on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. During normal operation, the charge pump and gate driver turn on the external N-channel pass FET’s gate to pass power to the load. The gate driver uses a charge pump that derives its power from the SOURCE pin. When the SOURCE pin is at ground, the charge pump is powered from an internal 12V supply derived from VDD. This results in a 200µA current load on the SOURCE pin when the gate is up. Also included in the gate driver is an internal 15V gate-to-source clamp.

The current sense (CS) amplifier monitors the load current using the difference between the V voltage. The CS amplifier limits the current in the load by reducing the GATE-to-SOURCE voltage in an active control loop. The CS amplifier requires 100µA input bias current from both the V

and the SENSE pins.

A short circuit on the output to ground causes significant power dissipation during active current limiting. To limit this power, the foldback amplifier reduces the current limit value from 50mV to 20mV (referred to the V SENSE voltage) in a linear manner as the FB pin drops below 2V (see Typical Performance curves).

If an overcurrent condition persists, the TIMER pin ramps up with a 100µA current source until the pin voltage exceeds 1.2V (comparator TM2). This indicates to the logic that it is time to turn off the pass FET to prevent overheating. At this point the TIMER pin ramps down using the 2µA current source until the voltage drops below

and SENSE pin

minus

CONDITION

STOP

CONDITION

START

CONDITION

0.2V (comparator TM1) which tells the logic that the pass transistor has cooled and it is safe to turn it on again.

The output voltage is monitored using the FB pin and the PG comparator to determine if the power is available for the load. The power good condition is signalled by the GPIO pin using an open-drain pull-down transistor. The GPIO pin can also be used as a general purpose input (GP comparator) or output pin.

The Functional Diagram shows the monitoring blocks of the LTC4260. The group of comparators on the left side includes the UV, OV, RST, BP and ON comparators. These comparators are used to determine if the external conditions are valid prior to turning on the FET. But first the two undervoltage lockout circuits UVLO1 and UVLO2 must validate the input supply and the internally generated 5.5V supply (INTV

) and generate the power up initialization to

the logic circuits.

Included in the LTC4260 is an 8-bit A/D converter. The converter has a 3-input mux to select between the ADIN pin, the SOURCE pin and the V

C interface is provided to read the A/D registers. It

An I

– SENSE voltage.

also allows the host to poll the device and determine if faults have occurred. If the ALERT line is used as an interrupt, the host can respond to a fault in real time. The typical SDA line is divided into an SDAI (input) and SDAO (output). This simplifies applications using an optoisolator driven directly from the SDAO output. The I2C device address is decoded using the ADR0, ADR1 and ADR2 pins. These inputs have three states each that decode into a total of 27 device addresses.

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LTC4260

The typical LTC4260 application is in a high availability system that uses a positive voltage supply to distribute power to individual cards. The device measures card voltages and currents and records past and present fault

conditions. The system queries each LTC4260 over the I

periodically and reads the stored information.

The basic LTC4260 application circuit is shown in Figure 1. External component selection is discussed in detail in the Design Example section.

Turn-On Sequence

The power supply on a board is controlled by placing an external N-channel pass transistor (Q1) in the power path. Note that sense resistor (R

) detects current and capacitor

C1 controls the GATE slew rate. Resistor R6 compensates the current control loop while R5 prevents high frequency oscillations in Q1. Resistors R1, R2 and R3 provide undervoltage and overvoltage sensing.

Several conditions must be present before the external switch can be turned on. First the external supply V

must exceed its undervoltage lockout level. Next the internally generated supply INTV

must cross its 4.5V

undervoltage threshold. This generates a 60µs to 120µs power-on-reset pulse. During reset the fault registers are

cleared and the control registers are set or cleared as described in the register section.

After the power-on-reset pulse, the LTC4260 will go through the following turn-on sequence. First, the UV and OV pins must indicate that the input power is within the acceptable range and the BD_PRST pin must be pulled low. All of these conditions must be satisfied for duration of 100ms to ensure that any contact bounce during insertion has ended.

When these initial conditions are satisfied, the ON pin is checked. If it is high, the external switch turns on. If it is low, the external switch turns on when the ON pin is brought high or if a serial bus turn-on command is received.

The switch is turned on by charging up the GATE with a 18µA current source (Figure 2). The voltage at the GATE pin rises with a slope equal to 18µA/C1 and the supply inrush current is set at:

INRUSH

=µ

18•

When the GATE voltage reaches the FET threshold voltage, the switch begins to turn on and the SOURCE voltage follows the GATE voltage as it increases.

48V

SDA

SCL

ALERT

GND

BACKPLANE PLUG-IN

CONNECTOR 2

CARD

Z1* SMBT70A

CONNECTOR 1

FDB3632

10Ω

6.8nF

GATE

SENSE

LTC4260GN

ADR0 ADR1NCADR2

0.1µF

100k

17 6

49.9k 1%

0.1µF

1.74k 1%

2.67k 1%

*DIODES, INC

0.010Ω

42 1 24 23

V OV ON SDAI SDA0 SCL ALERT

INTV

19 15

5 7 9

Figure 1. 5A, 48V Card Resident Application

SOURCE

ADIN

GPIO

BD_PRST

TIMER

GND

OUT

330µF

48V

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43.5k 1%

3.57k 1%

68nF

4260 F01

R4 100k

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VDD + 13V

SLOPE = 18µA/C1

Figure 2. Supply Turn-On

GATE

OUT

4260 F02

As the SOURCE voltage rises, so will the FB pin which is monitoring it. If the voltage across the current sense resistor R

gets too high, the inrush current will then be

limited by the internal current limit circuitry. Once the FB pin crosses its 3.5V threshold, the GPIO pin, in its default configuration, will cease to pull low and indicate that the power is now good.

Turn-Off Sequence

The switch can be turned off by a variety of conditions. A normal turn-off is initiated by the ON pin going low or a serial bus turn-off command. Additionally, several fault conditions will turn off the switch. These include an input overvoltage (OV pin), input undervoltage (UV pin), overcurrent circuit breaker (SENSE pin) or BD_PRST going high. Writing a logic one into the UV, OV or overcurrent fault bits will also turn off the switch if their autoretry bits are set to false.

Normally the switch is turned off with a 1mA current pulling down the GATE pin to ground. With the switch turned off, the SOURCE voltage drops and when the FB pin crosses below its threshold, GPIO pulls low to indicate that the output power is no longer good.

If the V INTV

pin falls below 7.5V for greater than 5µs or

drops below 3.8V for greater than 1µs, a fast

shutdown of the switch is initiated. The GATE pin is pulled down with a 600mA current to the SOURCE pin.

Overcurrent Fault

The LTC4260 features an adjustable current limit with foldback that protects against short circuits or excessive load current. To protect against excessive power dissipation in the switch during active current limit, the available current is reduced as a function of the output voltage sensed by the FB pin. The device also features a variable overcurrent response time. A graph in the Typical Performance curves shows the delay from a voltage step at the SENSE pin until the GATE voltage starts falling, as a function of overdrive.

An overcurrent fault occurs when the current limit circuitry has been engaged for longer than the time-out delay set by the TIMER pin. Current limiting begins when the current sense voltage between the V

and SENSE pins reaches

20mV to 50mV (depending on the foldback). The GATE pin is then brought down with a 600mA GATE-to-SOURCE current. The voltage on the GATE is regulated in order to limit the current sense voltage to less than 50mV. At this point, a circuit breaker time delay starts by charging the external timing capacitor from the TIMER pin with a 100µA pull-up current. If the TIMER pin reaches its 1.2V threshold, the external switch turns off (with a 1mA current from GATE to ground). The overcurrent present bit, C2, and the overcurrent fault bit, D2, are set at this time.

The circuit breaker time delay is given by:

tCB = CT • 12 [ms/µF]

After the switch is turned off, the TIMER pin begins discharging the timing capacitor with a 2µA pull-down current. When the TIMER pin reaches its 0.2V threshold, the overcurrent present bit, C2, is cleared, and the switch will be allowed to turn on again if the overcurrent fault has been cleared. However, if the overcurrent autoretry bit, A2, has been set then the switch turns on again automatically (without resetting the overcurrent fault). Use a minimum value of 0.1nF for CT.

The waveform in Figure 3 shows how the output latches off following a short circuit. The drop across the sense resistor is held at 20mV as the timer ramps up.

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OUT

50V/DIV

OUT

5A/DIV

∆V

GATE

10V/DIV

TIMER 2V/DIV

100µs/DIV

Figure 3. Short-Circuit Waveforms

During a short circuit, if the current limit sense voltage exceeds 150mV, the active current limit enters a high current protection mode that immediately turns off the output transistor by pulling the GATE-to-SOURCE voltage to zero. Current in the output transistor drops from tens of amps to zero in a few hundred nanoseconds. The input voltage will drop during the high current and then spike upwards due to parasitic inductances when the FET shuts off (see Supply Transients). Following this event, the part may turn on again after a delay (typically the 100ms normal turn-on delay if the input voltage drops below the UVLO threshold) and enters active current limit before shutting off.

Overvoltage Fault

An overvoltage fault occurs when the OV pin rises above its 3.5V threshold. This shuts off the switch immediately (with a 1mA current from GATE to ground) and sets the overvoltage present bit, C0, and the overvoltage fault bit D0. If the OV pin subsequently falls back below the threshold for 100ms, the switch will be allowed to turn on again unless the overvoltage autoretry has been disabled by clearing bit A0.

4260 F03

LTC4260

undervoltage autoretry has been disabled by clearing bit A1. When power is applied to the device, if UV is below its

3.12V threshold after INTV age lockout threshold, an undervoltage fault will be logged in the fault register.

Board Present Change of State

Whenever the BD_PRST pin toggles, bit D4 is set to indicate a change of state. When the BD_PRST pin goes high, indicating board removal, the switch turns off immediately (with a 1mA current from GATE to ground) and clears the board present bit, C4. If the BD_PRST pin is pulled low, indicating a board insertion, all fault bits except D4 will be cleared and the board present bit, C4, is set. If the BD_PRST pin remains low for 100ms the state of the ON pin will be captured in the FET On Control bit A3. This turns the switch on if the ON pin is tied high. There is an internal 10µA pull-up current source on the BD_PRST pin.

If the system shuts down due to a fault, it may be desirable to restart the system simply by removing and reinserting a load card. In cases where the LTC4260 and the switch reside on a backplane or midplane and the load resides on a plug-in card, the BD_PRST pin can be used to detect when the plug-in card is removed (see Figure 4). Once the plug-in card is reinserted the fault register is cleared (except for D4). After 100ms the state of the ON pin is latched into bit A3 of the control register. At this point the system will start up again.

If a connection sense on the plug-in card is driving the BD_PRST pin, the insertion or removal of the card may cause the pin voltage to bounce. This will result in clearing the fault register when the card is removed. The pin can be debounced using a filter capacitor, C on the BD_PRST pin as shown in Figure 4. The filter time is given by:

crosses its 4.5V undervolt-

BD_PRST

Undervoltage Fault

An undervoltage fault occurs when the UV pin falls below its 3.12V threshold. This turns off the switch immediately (with a 1mA current from GATE to ground) and sets the undervoltage present bit, C1, and the undervoltage fault bit D1. If the UV pin subsequently rises above the threshold for 100ms, the switch will turn on again unless the

FILTER

= C

BD_PRST

• 123 [ms/µF]

FET Short Fault

A FET short fault will be reported if the data converter measures a current sense voltage greater than or equal to 2mV while the FET is turned off. This condition sets the FET short present bit, C5, and the FET short fault bit D5.

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OUT

LTC4260

SOURCE

10µA

BD_PRST 14

1.235V

–

GND

MOTHERBOARD

Figure 4. Plug-In Card Insertion/Removal

BD_PRST

CONNECTOR PLUG-IN

LOAD

4260 F04

CARD

Power Bad Fault

A power bad fault will be reported if the FB pin drops below its 3.41V threshold while the FET is on. This pulls the GPIO pin low immediately, when configured as PWRGD, and sets the power bad present bit, C3, and the power bad fault bit D3. A circuit will prevent a power bad fault if the GATEto-SOURCE voltage is low, eliminating false power bad faults during power-up or power-down. If the FB pin subsequently rises back above the threshold, the GPIO pin will return to a high impedance state and bit C3 will be cleared.

Fault Alerts

Once the ALERT signal has been released for one fault, it will not be pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults will not generate alerts until the associated FAULT register bit has been cleared.

Resetting Faults

Faults are reset with any of the following conditions. First, a serial bus command writing zeros to the FAULT register D will clear the associated faults. Second, the entire FAULT register is cleared when the switch is turned off by either the ON pin or bit A3 going from high to low, or if the UV pin is brought below its 1.23V reset threshold, or if INTV

falls below its 3.8V undervoltage lockout threshold. Finally, when BD_PRST is brought from high to low, only FAULT bits D0-D3 and D5 are cleared, the bit D4 that indicates a BD_PRST change of state will be set. Faults that are still present (as indicated in the STATUS Register C) cannot be cleared.

The FAULT register will not be cleared when autoretrying. When autoretry is disabled the existence of a D0, D1 or D2 fault keeps the switch off. As soon as the fault is cleared, the switch will turn on. If autoretry is enabled, then a high value in C0, C1 or C2 will hold the switch off and the FAULT register is ignored. Subsequently, when the C0, C1 and C2 bits are cleared, the switch is allowed to turn on again

When any of the fault bits in FAULT register D are set, an

optional I

C bus alert can be generated by setting the appropriate bit in the ALERT register B. This allows only selected faults to generate alerts. At power-up the default state is to not alert on faults. If an alert is enabled, the corresponding fault will cause the ALERT pin to pull low. After the bus master controller broadcasts the Alert Response Address, the LTC4260 responds with its address on the SDA line and releases ALERT as shown in Figure 11. If there is a collision between two LTC4260s responding with their addresses simultaneously, then the device with the lower address wins arbitration and responds first. The ALERT line will also be released if the device is addressed by the bus master.

Data Converter

The LTC4260 incorporates an 8-bit data converter that continuously monitors three different voltages. The SOURCE pin uses a 1/40 resistive divider to monitor a fullscale voltage of 102.4V with 0.4V resolution (divider converts 102.4V to 2.56V). The ADIN pin is monitored with a 2.56V full scale and 10mV resolution, and the voltage between the V

and SENSE pins is monitored with a

76.8mV full scale and 300µV resolution.

The results from each conversion are stored in registers E, F and G and are updated 10 times per second. Setting CONTROL register bit A5 invokes a test mode that halts the data converter updates so that registers E, F and G can be written to and read from for software testing.

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LTC4260

Gate Pin Voltage

A curve of gate drive vs VDD is shown in the Typical Performance curves. At the minimum input supply voltage of 8.5V, the minimum gate drive voltage is 4.5V. When the input supply voltage is higher than 20V, the gate drive is at least 10V and a regular N-FET can be used. In applications over a 8.5V to 20V range, a logic level N-FET must be used to maintain adequate gate enhancement. The GATE pin is clamped at a typical value of 15V above the SOURCE pin.

Configuring the GPIO Pin

Table 3 describes the possible states of the GPIO pin using the control register bits A6 and A7. At power-up, the default state is for the GPIO pin to go high impedance when power is good (FB pin greater than 3.5V). Other uses for the GPIO pin are to pull down when power is good, a general purpose output and a general purpose input.

Compensating the Active Current Loop

The active current limit circuit is compensated using the resistor R6 and the slew rate capacitor C1. The value for C1 is calculated to limit the inrush current. The suggested value for R6 is 100k. This value should work for most pass FETs (Q1). If the gate capacitance of Q1 is very small then the best method to compensate the loop is to add a ≈10nF capacitor between the GATE and SOURCE terminals.The addition of 10Ω resistor (R5) prevents self-oscillation in Q1 by isolating trace capacitance from the FETs GATE Terminal. Locate the gate resistor at, or close to, the body of the MOSFET.

Supply Transients

The LTC4260 is designed to ride through supply transients caused by load steps. If there is a shorted load and the parasitic inductance back to the supply is greater than

0.5µH, there is a chance that the supply could collapse before the active current limit circuit brings down the GATE pin. In this case the undervoltage monitors turn off the pass FET. The undervoltage lockout circuit has a 5µs filter time after V

drops below 7.5V. The UV pin reacts

in 2µs to shut the GATE off, but it is recommended to add a filter capacitor C

to prevent unwanted shutdown caused

by short transient. Eventually either the UV pin or the

undervoltage lockout responds to bring the current under control before the supply completely collapses.

Supply Transient Protection

The LTC4260 is 100% tested and guaranteed to be safe from damage with supply voltages up to 100V. However, spikes above 100V may damage the part. During a shortcircuit condition, the large change in currents flowing through the power supply traces can cause inductive voltage spikes which could exceed 100V. To minimize the spikes, the power trace inductance should be minimized by using wider traces or heavier trace plating. Adding a snubber circuit will dampen the voltage spikes. It is built using a 100Ω resistor in series with a 0.1µF capacitor between V

and GND. A surge suppressor, Z1 in Figure 1,

at the input will clamp the voltage spikes.

Design Example

As a design example, take the following specifications: V = 48V, I V

UVOFF

= 45V and I2C sense resistor, R

= 5A, I

MAX

= 38.5V, V

ADDRESS

INRUSH

OVOFF

= 1A, CL= 330µF, V

= 70V, V

PWRGDUP

UVON

= 46V, V

PWRGDDN

= 1010011. The selection of the

, is set by the overcurrent threshold of

= 43V,

50mV:

50 50

===Ω

MAX

0 010.

The FET should be sized to handle the power dissipation during the inrush charging of the output capacitor C

OUT

The method used to determine the power is the principle:

= Energy in CL= Energy in Q1

Thus:

= 1/2 CV2 = 1/2(0.33mF)(48V)2 = 0.38J

Calculate the time it takes to charge up C

CHARGUP

••330 48

LIN

INRUSH

OUT

The average power dissipated in the FET:

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==≅

DISS

CHARGUP

038

The SOA (safe operating area) curves of candidate FETs must be evaluated to ensure that the heat capacity of the package can stand 24W for 16ms. The SOA curves of the Fairchild FDB3632 provide for 1A at 50V (50W) for 10ms, satisfying the requirement.

The inrush current is set to 1A using C1:

GATE UP

()

INRUSH

1033

59==µ=

Default values of R5 = 10Ω and R6 = 100k are chosen as discussed previously.

The power dissipated in the FET during overcurrent must be limited. The active current limit uses a timer to prevent excessive energy dissipation in the FET. The worst-case power occurs when the voltage versus current profile of the foldback current limit is at the maximum. This occurs when the current is 5A and the voltage is 1/2 of the 48V or 24V. See the Current Limit Sense Voltage vs FB Voltage in the Typical Performance curves to view this profile. In order to survive 120W, the FET SOA curve dictates the maximum time at this power level. This particular FET allows 300W at 1ms or less. Therefore, it is acceptable to set the current limit timeout using C

081

ms F

[]

to be 0.81ms:

Layout Considerations

To achieve accurate current sensing, a Kelvin connection is recommended. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. Using 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 530µΩ/



. Small resistances add up quickly in high current applications. To improve noise immunity, put the resistive divider to the UV, OV and FB pins close to the device and keep traces to VDD and GND short. It is also important to put C3, the bypass capacitor for the INTV

pin, as close as possible between INTV

and GND. A 0.1µF capacitor from the UV pin (and OV pin through resistor R2) to GND also helps reject supply noise. Figure 5 shows a layout that addresses these issues. Note that a surge suppressor, Z1, is placed between supply and ground using wide traces.

LOAD

SENSE RESISTOR R

SENSE

GND INTV

LTC4260

Note the minimum value for CT is 0.1nF.

Choose R1, R2, R3, R7 and R8 for the UV, OV and PG threshold voltages:

OVRISING

= 71.2V, V

OVFALLING

= 69.44V (using V

OV(TH)

3.5V rising and 3.41V falling)

UVRISING

= 43V, V

UVFALLING

= 38.5V, (using V

UV(TH)

3.5V rising and 3.12V falling)

PGRISING

= 46.14V, V

PGFALLING

= 45V, (using V

= 3.5V

rising and 3.411V falling)

In addition a 0.1µF ceramic bypass capacitor is placed on the INTVCC pin. The complete circuit is shown in Figure 1.

GND

LOAD

Figure 5. Recommended Layout for R1, R2, R3, R8, C

, C3, Z1 and R

4260 F05

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LTC4260

Digital Interface

The LTC4260 communicates with a bus master using a 2-wire interface compatible with the I SMBus, an I

The LTC4260 is a read-write slave device and supports SMBus bus Read Byte, Write Byte, Read Word and Write Word commands. The second word in a Read Word command will be identical to the first word. The second word in a Write Word command is ignored. The data formats for these commands are shown in Figures 6 to10.

Using Optoisolators with SDA

The LTC4260 separates the SDA line into SDAI and SDAO. If optoisolators are not used then tie SDAI and SDAO together to construct a normal SDA line. When using optoisolators connect the SDAI to the output of the incoming opto and connect the SDAO to the input of the outgoing opto (see Figure 13).

START and STOP Conditions

When the bus is idle, both SCL and SDA must be high (Figure 6). A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission.

I2C Device Addressing

Twenty-seven distinct bus address are configurable using the three-state ADR0-ADR2 pins. Table 1 shows the correspondence between pin states and addresses. Note that address bits B7 and B6 are internally configured to 10. In addition, the LTC4260 will respond to two special addresses. Address (1011 111)b is a mass write used to write to all LTC4260, regardless of their individual address settings. The mass write can be masked by setting register bit A4 to zero. Address (0001 100)b is the SMBus Alert Response Address. If the LTC4260 is pulling low on the ALERT pin, it will acknowledge this address using the SMBus Alert Response Protocol.

C extension for low power devices.

C bus and the

Acknowledge

The acknowledge signal is used for handshaking between the transmitter and the receiver to indicate that the last byte of data was received. The transmitter always releases the SDA line during the acknowledge clock pulse. When the slave is the receiver, it must pull down the SDA line so that it remains LOW during this pulse to acknowledge receipt of the data. If the slave fails to acknowledge by leaving SDA HIGH, then the master can abort the transmission by generating a STOP condition. When the master is receiving data from the slave, the master must pull down the SDA line during the clock pulse to indicate receipt of the data. After the last byte has been received the master will leave the SDA line HIGH (not acknowledge) and issue a STOP condition to terminate the transmission.

Write Protocol

The master begins communication with a START condition followed by the seven bit slave address and the R/W bit set to zero (Figure 7). The addressed LTC4260 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to write. The LTC4260 acknowledges this and then latches the lower three bits of the command byte into its internal Register Address pointer. The master then delivers the data byte and the LTC4260 acknowledges once more and latches the data into its internal register. The transmission is ended when the master sends a STOP condition. If the master continues sending a second data byte, as in a Write Word command, the second data byte will be acknowledged by the LTC4260 but ignored (Figure 8).

Read Protocol

The master begins a read operation with a START condition followed by the seven bit slave address and the R/W bit set to zero (Figure 9). The addressed LTC4260 acknowledges this and then the master sends a command byte that indicates which internal register the master wishes to read. The LTC4260 acknowledges this and then latches the lower three bits of the command byte into its internal Register Address pointer. The master then sends a repeated START condition followed by the same seven bit

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address with the R/W bit now set to one. The LTC4260 acknowledges and sends the contents of the requested register. The transmission is ended when the master sends a STOP condition. If the master acknowledges the transmitted data byte, as in a Read Word command (Figure 12), the LTC4260 will repeat the requested register as the second data byte.

Note that the Register Address pointer is not cleared at the end of the transaction. Thus the Receive Byte protocol can be used to repeatedly read a specific register.

Alert Response Protocol

The LTC4260 implements the SMBus Alert Response Protocol as shown in Figure 11. If enabled to do so through the ALERT register B, the LTC4260 will respond to faults by pulling the ALERT pin low. Multiple LTC4260s can share a common ALERT line and the protocol allows a master to determine which LTC4260s are pulling the line

low. The master begins by sending a START bit followed by the special Alert Response Address (0001 100)b with the R/W bit set to one. Any LTC4260 that is pulling its ALERT pin low will acknowledge and begin sending back its individual slave address.

An arbitration scheme ensures that the LTC4260 with the lowest address will have priority; all others will abort their response. The successful responder will then release its ALERT pin while any others will continue to hold their ALERT pins low. Polling may also be used to search for any LTC4260 that have detected faults. Any LTC4260 pulling its ALERT pin low will also release it if it is individually addressed during a read or write transaction.

The ALERT signal will not be pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults will not generate alerts until the associated FAULT register bit has been cleared.

SDA

SCL

START

CONDITION

a6 - a0 b7 - b0 b7 - b0

1 - 7 8 9

ADDRESS R/W ACK DATA ACK DATA ACK

Figure 6. Data Transfer Over I2C or SMBus

1 - 7 8 9 1 - 7 8 9

STOP

CONDITION

4260 F06

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LTC4260

S ADDRESS

1 0 a4:a0

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

COMMAND DATA

A A AP

X X X X X b2:b00

000b7:b0

A: ACKNOWLEDGE (LOW) A: NOT ACKNOWLEDGE (HIGH) R: READ BIT (HIGH) W: WRITE BIT (LOW) S: START CONDITION P: STOP CONDITION

4260 F07

Figure 7. LTC4260 Serial Bus SDA Write Byte Protocol

S ADDRESS

1 0 a4:a0

COMMAND DATA DATA

X X X X X b2:b00

000 0

X X X X X X X Xb7:b0

Figure 8. LTC4260 Serial Bus SDA Write Word Protocol

S ADDRESS

1 0 a4:a0 1 0 a4:a0 1 0

COMMAND S ADDRESS R A

X X X X X b2:b00

Figure 9. LTC4260 Serial Bus SDA Read Byte Protocol

DATA

b7:b0 1

4260 F08

4260 F09

S ADDRESS

1 0 a4:a0 1 0 a4:a0 1 0

COMMAND S ADDRESS R A

X X X X X b2:b00

Figure 10. LTC4260 Serial Bus SDA Read Word Protocol

ALERT

RESPONSE

ADDRESS

0 0 0 1 1 0 0

DEVICE

A A

ADDRESS

1 0 a4:a00 11

4260 F11

Figure 11. LTC4260 Serial Bus SDA Alert Response Protocol

DATA

b7:b0 1

DATA

0Ab7:b0

4260 F10

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Table 1. LTC4260 I2C Device Addressing

HEX DEVICE LTC4260

DESCRIPTION ADDRESS BINARY DEVICE ADDRESS ADDRESS PINS

h 6 5 4 3 2 1 0 R/W ADR2 ADR1 ADR0

Mass Write BE 1 0 1 1 1 1 1 0 X X X

Alert Response 19 0 0 0 1 1 0 0 1 X X X

0 80 1 00 0 0 00 X L NC L

1 82 1 00 0 0 01 X L H NC

2 84 1 00 0 0 10 X L NC NC

3 86 1 00 0 0 11 X L NC H

4 88 1 00 0 1 00 X L L L

5 8A 1 00 0 1 01 X L H H

6 8C 1 00 0 1 10 X L L NC

7 8E 1 00 0 1 11 X L L H

8 90 1 00 1 0 00 X NC NC L

9 92 1 00 1 0 01 X NC H NC

10 94 1 0 0 1 0 1 0 X NC NC NC

11 96 1 0 0 1 0 1 1 X NC NC H

12 98 1 0 0 1 1 0 0 X NC L L

13 9A 1001101X NC H H

14 9C 1001110X NC L NC

15 9E 1 0 0 1 1 1 1 X NC L H

16 A0 1010000X H NC L

17 A2 1010001X H H NC

18 A4 1010010X H NC NC

19 A6 1010011X H NC H

20 A8 1010100X H L L

21 AA 1010101X H H H

22 AC 1010110X H L NC

23 AE 1010111X H L H

24 B0 1011000X L H L

25 B2 1011001X NC H L

26 B4 1011010X H H L

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Table 2. LTC4260 Register Addresses and Contents

00h CONTROL (A) R/W Controls Whether the Part Retries After Faults, Set the Switch State

01h ALERT (B) R/W Controls Whether the ALERT Pin is Pulled Low After a Fault is Logged in the Fault Register

02h STATUS (C) R System Status Information

03h FAULT (D) R/W Fault Log

04h SENSE (E) R/W** ADC Current Sense Voltage Data

05h SOURCE (F) R/W** ADC SOURCE Voltage Data

06h, 07h ADIN (G) R/W** ADC ADIN Voltage Data

*Register address MSBs b7-b3 are ignored. **Writable if bit A5 set.

Table 3. CONTROL Register A (00h)—Read/Write

BIT NAME OPERATION

A7:6 GPIO Configure Configures Behavior of GPIO Pin

FUNCTION A6 A7 GPIO PIN

Power Good (Default) 0 0 GPIO = C3

Power Bad 0 1 GPIO = C3

General Purpose Output 1 0 GPIO = B6

General Purpose Input 1 1

GPIO = Hi-Z

A5 Test Mode Enable Test Mode Halts ADC Operation and Enables Writes to ADC Registers

1 = Enable Test Mode, 0 = Disable Test Mode (Default)

A4 Mass Write Enable Enables Mass Write Using Address (1011 111)b

1 = Enable Mass Write (Default), 0 = Disable Mass Write

A3 FET On Control Turns FET On and Off

1 = Turn FET On, 0 = Turn FET Off. Defaults to ON Pin State at End of Debounce Delay

A2 Overcurrent Autoretry Enables Autoretry After an Overcurrent Fault

1 = Retry Enabled, 0 = Retry Disabled (Default)

A1 Undervoltage Autoretry Enables Autoretry After an Undervoltage Fault

1 = Retry Enabled (Default), 0 = Retry Disabled

A0 Overvoltage Autoretry Enables Autoretry After an Overvoltage Fault

1 = Retry Enabled (Default), 0 = Retry Disabled

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Table 4. ALERT Register B (01h)—Read/Write

BIT NAME OPERATION

B7 Reserved Not Used

B6 GPIO Output Output Data Bit to GPIO Pin When Configured as Output. Defaults to 0

B5 FET Short Alert Enables Alert for FET Short Condition