Datasheet LTC4253, LTC4253A Datasheet (LINEAR TECHNOLOGY)

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Page 1

FEATURES

■

Allows Safe Board Insertion and Removal from a Live –48V Backplane

■

Floating Topology Permits Very High Voltage Operation

■

Adjustable Analog Current Limit with Breaker Timer Ideal for Two Battery Feeds

■

Fast Response Time Limits Peak Fault Current

■

Adjustable Undervoltage/Overvoltage Protection with ±1% Threshold Accuracy (LTC4253A)

■

Three Sequenced Power Good Outputs

■

Adjustable Soft-Start Current Limit

■

Adjustable Timer with Drain Voltage Accelerated Response

■

Latchoff After Fault

■

Available in a 16-Pin SSOP Package

APPLICATIO S

■

–48V Distributed Power Systems

■

Negative Power Supply Control

■

Central Office Switching

■

High Availability Servers

■

Disk Arrays

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.

LTC4253/LTC4253A

– 48V Hot Swap Controllers

with Sequencer

DESCRIPTIO

The LTC®4253/LTC4253A negative voltage Hot Swap controllers allow a board to be safely inserted and removed from a live backplane. Output current is controlled by three stages of current-limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. The LTC4253/LTC4253A latch off after a circuit fault.

Adjustable undervoltage and overvoltage detectors disconnect the load whenever the input supply exceeds the desired operating range. The LTC4253/LTC4253A’s supply input is shunt-regulated, allowing safe operation with very high supply voltages. A multifunction timer delays initial startup and controls the circuit breaker’s response time. The circuit breaker’s response time can be accelerated by sensing excessive MOSFET drain voltage, keeping the MOSFET within its safe operating area (SOA). An adjustable soft-start circuit controls MOSFET inrush current at start-up.

Three power good outputs are sequenced by an adjustable timer and two ENABLE inputs to enable external power modules at start-up or disable them if the circuit breaker trips. The LTC4253A features tight ±1% undervoltage/ overvoltage threshold accuracy. The LTC4253/LTC4253A are available in a 16-pin SSOP.

TYPICAL APPLICATIO

–48V/2.5A Hot Swap Controller

–48V RTN

10nF

68nF

0.1µF

0.33µF

1µF

EN2

LTC4253

RESET

SQTIMER

EN3

PWRGD1 PWRGD2 PWRGD3

DRAIN

GATE

SENSETIMER

–48V RTN

–48V A

–48V B

402k

32.4k 1%

B3100*

2.5k 15k(1/4W)/6

5.6k 5.6k 5.6k

†

IRF530S

10Ω

0.02Ω

18nF

100µF

†

*DIODES, INC.

†

MOC207

LOAD1

LOAD2

†

LOAD3

4253 TA01

GATE

10V

SENSE

50mV

OUT

50V

SS 1V

Start-Up Behavior

1ms/DIV

4253 TA01b

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LTC4253/LTC4253A

ABSOLUTE AXI U RATI GS

(Note 1), All voltages referred to V

Current into VIN (100µs Pulse) ........................... 100mA

Current into DRAIN (100µs Pulse)........................ 20mA

, DRAIN Minimum Voltage............................... –0.3V

Input/Output (Except SENSE

and DRAIN) Voltage...................................–0.3V to 16V

SENSE Voltage ..........................................–0.6V to 16V

Current Out of SENSE (20µs Pulse) .................. –200mA

Maximum Junction Temperature .......................... 125°C

Operating Temperature Range

LTC4253C/LTC4253AC ............................ 0°C to 70°C

LTC4253I/LTC4253AI ......................... – 40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

UUW

PACKAGE/ORDER I FOR ATIO

ORDER PART

TOP VIEW

EN2

PWRGD2

PWRGD1

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

RESET

SENSE

16-LEAD PLASTIC SSOP

= 125°C, θJA = 130°C/W

JMAX

GN PACKAGE

PWRGD3

EN3

SQTIMER

TIMER

DRAIN

GATE

NUMBER

LTC4253CGN LTC4253IGN LTC4253ACGN LTC4253AIGN

GN PART

MARKING

4253 4253I 4253A 4253AI

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

LKO

LKH

HYST

RESET

ACL

FCL

VIN – VEE Zener Voltage IIN = 2mA

VIN – VEE Zener Dynamic Impedance IIN = (2mA to 30mA) 5 5 Ω

VIN Supply Current UV = OV = 4V, V

Undervoltage Lockout Coming Out of UVLO (Rising VIN)

Undervoltage Lockout Hysteresis

TTL Input High Voltage

TTL Input Low Voltage

TTL Input Buffer Hysteresis 600 600 mV

RESET Input Current V

EN2, EN3 Input Current VEN = 4V

Circuit Breaker Current Limit Voltage VCB = (V

Analog Current Limit Voltage V

Analog Current Limit Voltage V Circuit Breaker Current Limit Voltage

Fast Current Limit Voltage V

SS Voltage After End of SS Timing Cycle

SS Pin Current UV = OV = 4V, V

≤ V

VEN = 0V

= (V

ACL

= (V

ACL

= (V

FCL

= 0V (Sourcing)

UV = OV = 0V, V V

= 1V (Sinking)

The ● denotes the specifications which apply over the full operating

= 25°C. (Note 2)

LTC4253 LTC4253A

●

11.5 13 14.5 11.5 13 14.5 V

= (VZ – 0.3V)

≤ V

RESET

– VEE)

SENSE

– VEE), SS = Open or 2.2V

SENSE

– VEE), SS = Open or 1.4V

SENSE

– VEE)

SENSE

= V

SENSE

= V

SENSE

EE,

●

0.8 2 1.1 2 mA

9.2 11.5 9 10 V

0.5 1 1.5 0.25 0.5 0.75 V

22 V

0.8 0.8 V

±0.1 ±10 ±0.1 ±10 µA

60 120 180 60 120 180 µA

±0.1 ±10 ±0.1 ±10 µA

40 50 60 45 50 55 mV

80 100 120 mV

1.05 1.20 1.38 V/V

150 200 300 150 200 300 mV

2 2.2 2.4 1.25 1.4 1.55 V

12 22 32 16 28 40 µA

28 28 mA

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LTC4253/LTC4253A

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. (Note 2)

LTC4253 LTC4253A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

+ VOSRatio (V

ACL

GATE

GATEL

GATEH

SS Output Impedance 100 50 kΩ

Analog Current Limit Offset Voltage 10 10 mV

+ VOS) to SS Voltage 0.05 0.05 V/V

ACL

GATE Pin Output Current UV = OV = 4V, V

= 0V (Sourcing)

GATE

UV = OV = 4V, V V

= 3V (Sinking)

GATE

UV = OV = 4V, V

= 1V (Sinking)

GATE

External MOSFET Gate Drive V

GATE

– V

EE, IIN

= VEE,

SENSE

– VEE = 0.15V, 17 17 mA

SENSE

– VEE = 0.3V, 190 190 mA

SENSE

= 2mA

●

30 50 70 30 50 70 µA

●

10 12 V

Gate Low Threshold Before Gate Ramp Up 0.5 0.5 V

Gate High Threshold V

GATEH

= VIN – V

, for PWRGD1, 2.8 2.8 V

GATE

PWRGD2, PWRGD3 Status

UVHI

UVLO

UVHST

OVHI

OVLO

OVHST

SENSE

UV Pin Threshold HIGH UV Low to High

UV Pin Threshold LOW UV High to Low

UV Pin Threshold UV Low to High

●

3.075 3.225 3.375 V

●

2.775 2.925 3.075 V

●

3.05 3.08 3.11 V

UV Pin Hysteresis 230 300 350 mV

OV Pin Threshold HIGH OV Low to High

OV Pin Threshold LOW OV High to Low

OV Pin Threshold OV Low to High

●

5.85 6.15 6.45 V

●

5.55 5.85 6.15 V

●

292 324 356 mV

5.04 5.09 5.14 V

OV Pin Hysteresis 230 300 350 mV

SENSE Pin Input Current UV = 0V = 4V, V

SENSE

= 50mV

●

15 30 15 30 µA

82 102 122 mV

(Sourcing)

INP

TMR

TMRH

TMRL

UV, OV Pin Input Current UV = OV = 4V

TIMER Pin Voltage High Threshold

TIMER Pin Voltage Low Threshold

TIMER Pin Current Timer On (Initial Cycle/Latchoff,

Sourcing), V

TMR

= 2V

●

±0.1 ± 1 ±0.1 ±1 µA

3.5 4 4.5 3.5 4 4.5 V

0.8 1 1.2 0.8 1 1.2 V

357 357 µA

Timer Off (Initial Cycle, Sinking), 28 28 mA V

= 2V

TMR

Timer On (Circuit Breaker, Sourcing, I

DRN

= 0µA), V

TMR

= 2V

●

120 200 280 120 200 280 µA

Timer On (Circuit Breaker, Sourcing, 600 600 µA I

∆I

TMRACCITMR

∆I

DRN

SQTMRH

SQTMRL

= 50µA), V

DRN

Timer Off (Circuit Breaker, Sinking),

= 2V

TMR

at I

= 50µA – I

DRN

50µAI

TMR

at I

= 0µA Timer On (Circuit Breaker with

DRN

= 50µA)

SQTIMER Pin Voltage High Threshold

SQTIMER Pin Voltage Low Threshold 0.33 0.33 V

TMR

= 2V

●

357 357 µA

●

789 789µA/µA

●

3.5 4 4.5 3.5 4 4.5 V

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LTC4253/LTC4253A

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. (Note 2)

LTC4253 LTC4253A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

SQTMR

SQTIMER Pin Current SQTIMER On (Power Good

Sequence, Sourcing), V

SQTMR

= 2V

●

357 357 µA

SQTIMER Off (Power Good 28 28 mA

DRNL

DRNCL

PGL

PGH

Sequence, Sinking), V

DRAIN Pin Voltage Low Threshold For PWRGD1, PWRGD2, PWRGD3 Status

DRAIN Leakage Current V

DRAIN Pin Clamp Voltage I

= 5V ±0.1 ±1 µA

DRAIN

= 4V ±0.1 ± 1 µA

DRAIN

= 50µA

DRN

PWRGD1, PWRGD2, PWRGD3 IPG = 1.6mA Output Low Voltage I

= 5mA

PWRGD1, PWRGD2, PWRGD3 VPG = 0V (Sourcing)

SQTMR

= 2V

●

2 2.39 3 2 2.39 3 V

●

6 7 8.5 5 6 7.5 V

●

0.25 0.4 0.25 0.4 V

1.2 1.2 V

30 50 70 30 50 70 µA

Output High Current

PLLUG

PHLOG

SQTIMER Default Ramp Period SQTIMER Pin Floating, 250 250 µs

Ramps from 0.5V to 3.5V

SQTMR

SS Default Ramp Period SS Pin Floating, VSS Ramps from 0.2V to 2V 250 µs

SS Pin Floating, V

UV Low to GATE Low

OV High to GATE Low

Ramps from 0.2V to 1.25V 140 µs

●

0.4 5 0.4 5 µs

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device

Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to V specified.

reliability and lifetime.

TYPICAL PERFOR A CE CHARACTERISTICS

1000

100

(mA)

0.1

vs V

TA = –40°C

TA = 25°C

5 10 15 20

VIN (V)

TA = 85°C

TA = 125°C

VZ vs Temperature

14.5 IIN = 2mA

14.0

13.5

(V)

13.0

12.5

12.0

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

4253 G01

4253 G02

unless otherwise

vs Temperature

1000

VIN = VZ – 0.3V

950

900

850

800

750

(µA)

700

650

600

550

500

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

4253 G03

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TYPICAL PERFOR A CE CHARACTERISTICS

LTC4253/LTC4253A

vs V

180

IIN = 2mA

= 25°C

160

140

120

100

(µA)

4 6 8 10 12 14 16

VEN (V)

Fast Current Limit Voltage V Temperature

300

280

260

240

220

(mV)

200

FCL

180

160

140

120

100

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

FCL

4253 G04

4253 G07

Circuit Breaker Current Limit Voltage V

(mV)

–55 –35 –15 5 25 45 65 85 105 125

GATE

UV/OV = 4V

TIMER = 0V V

SENSE

GATE

(µA)

GATE

–55 –35 –15 5 25 45 65 85 105 125

vs TemperatureI

TEMPERATURE (°C)

(Source) vs Temperature I

= V

= 0V

TEMPERATURE (°C)

4253 G05

4253 G08

Analog Current Limit Voltage V vs Temperature

150

140

130

120

110

(mV)

100

ACL

–55 –35 –15 5 25 45 65 85 105 125

GATE

(mA)

GATE

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

(ACL, Sink) vs Temperature

UV/OV = 4V TIMER = 0V

– VEE = 0.15V

SENSE

= 3V

GATE

TEMPERATURE (°C)

ACL

4253 G06

4253 G09

(FCL, Sink) vs Temperature V

GATE

400

350

300

250

(mA)

200

GATE

150

100

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

UV/OV = 4V TIMER = 0V

– VEE = 0.3V

SENSE

= 1V

GATE

4253 G10

vs Temperature V

GATE

14.5 UV/OV = 4V

TIMER = 0V

(V)

GATE

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

10.0

= V

SENSE

IIN = 2mA

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

4253 G11

vs Temperature

GATEL

1.0 UV/OV = 4V

0.9

TIMER = 0V GATE THRESHOLD

0.8 BEFORE RAMP UP

0.7

0.6

(V)

0.5

GATEL

0.4

0.3

0.2

0.1

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

4253 G12

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LTC4253/LTC4253A

TYPICAL PERFOR A CE CHARACTERISTICS

vs Temperature

GATEH

3.6 UV/OV = 4V

= VIN – V

GATEH

3.4 IIN = 2mA

3.2

3.0

(V)

2.8

GATEH

2.6

2.4

2.2

2.0

–55 –35 –15 5 25 45 65 85 105 125

SENSE

0.01

0.1

(mA)

SENSE

–I

100

1000

–1.5

–1 –0.5 0 0.5 1 1.5

GATE

TEMPERATURE (°C)

vs (V

SENSE

– VEE)

– VEE (V)

UV/OV = 4V TIMER = 0V GATE = HIGH

= 25°C

4253 G13

4253 G16

3.375 IIN = 2mA

3.275

3.175

3.075

2.975

UV THRESHOLD (V)

2.875

2.775

–55 –35 –15 5 25 45 65 85 105 125

SENSE

UV/OV = 4V TIMER = 0V V

–5

–10

(µA)

–15

SENSE

–20

–25

–30

–55 –35 –15 5 25 45 65 85 105 125

SENSE GATE

= HIGH

vs TemperatureI

– VEE = 50mV

TEMPERATURE (°C)

UVH

UVL

4253 G14

4253 G17

Threshold vs TemperatureUV Threshold vs TemperatureV

6.4 IIN = 2mA

6.2

6.0

5.8

5.6

OV THRESHOLD (V)

5.4

5.2

5.0

–55 –35

–15

OVH

OVL

45 125

525

TEMPERATURE (°C)

65 85 105

TIMER Threshold vs TemperatureI

5.0

IIN = 2mA

4.5

4.0

3.5

3.0

2.5

2.0

1.5

TIMER THRESHOLD (V)

1.0

0.5

–55 –35 –15 5 25 45 65 85 105 125

TMRH

TMRL

TEMPERATURE (°C)

4352 G15

4253 G18

(Initial Cycle, Sourcing)

TMR

vs Temperature

IIN = 2mA

= 2V

TMR

(µA)

TMR

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

4253 G19

(Circuit Breaker, Sourcing)

TMR

vs Temperature

240

IIN = 2mA

= 0µA

DRN

230

220

210

(µA)

200

TMR

190

180

170

160

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

4253 G20

(mA)

TMR

0.1

0.001

vs I

TMR

IIN = 2mA T

DRN

= 25°C

0.01 0.1 110 I

(mA)

DRN

4253 G21

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TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

PGL

(V)

4253 G27

3.0

2.5

2.0

1.5

1.0

0.5

IIN = 2mA

IPG = 10mA

IPG = 5mA

IPG = 1.6mA

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

(µs)

4253 G30

500

450

400

350

300

250

200

150

100

IIN = 2mA V

SQTMR

RAMPS FROM 0.5V TO 3.5V

TYPICAL PERFOR A CE CHARACTERISTICS

SQTIMER Threshold

∆I

9.0 IIN = 2mA

8.8

8.6

8.4

(µA/µA)

8.2

DRN

8.0

∆I

7.8

7.6

TMRACC/

∆I

7.4

7.2

7.0

–55 –35 –15 5 25 45 65 85 105 125

8.0 IIN = 2mA

7.8

DRN

7.6

7.4

7.2

(V)

7.0

DRNCL

6.8

6.6

6.4

6.2

6.0

–55 –35 –15 5 25 45 65 85 105 125

/∆I

TMRACC

TEMPERATURE (°C)

vs Temperature

DRNCL

= 50µA

TEMPERATURE (°C)

vs Temperature

DRN

4253 G22

4253 G25

vs Temperature

5.0 IIN = 2mA

4.5

4.0

3.5

3.0

(V)

2.5

SQTMR

2.0

1.5

1.0

0.5

–55 –35 –15 5 25 45 65 85 105 125

DRN

100

IIN = 2mA

0.1

(mA)

0.01

DRN

TA = 125°C

0.001

0.0001

0.00001 0

TEMPERATURE (°C)

vs V

DRAIN

TA = 85°C

TA = –40°C

2 4 6 8 10 12 14 16

DRAIN

SQTMRH

SQTMRL

TA = 25°C

(V)

LTC4253/LTC4253A

vs Temperature

DRNL

2.60 IIN = 2mA

2.55

2.50

2.45

(V)

2.40

DRNL

2.35

2.30

2.25

2.20

4253 G23

4253 G26

–55 –35 –15 5 25 45 65 85 105 125

PGL

TEMPERATURE (°C)

vs Temperature

4253 G24

vs Temperature

PGH

IIN = 2mA

(µA)

PGH

–55 –35 –15 5 25 45 65 85 105 125

= 0V

PWRGD

TEMPERATURE (°C)

4253 G28

vs Temperature

300

IIN = 2mA

290

SS PIN FLOATING

RAMPS FROM 0.2V TO 2V

280

270

260

(µs)

250

240

230

220

210

200

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

4253 G29

vs Temperature

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Page 8

LTC4253/LTC4253A

UUU

PI FU CTIO S

EN2 (Pin 1): Power Good Status Output Two Enable. This is a TTL compatible input that is used to control PWRGD2 and PWRGD3 outputs. When EN2 is driven low, both PWRGD2 and PWRGD3 will go high. When EN2 is driven high, PWRGD2 will go low provided PWRGD1 has been active for more than one power good sequence delay

) provided by the sequencing timer. EN2 can be used

SQT

to control the power good sequence. This pin is internally pulled low by a 120µA current source.

PWRGD2 (Pin 2): Power Good Status Output Two. Power good sequence starts with PWRGD1 latching active low. PWRGD2 will latch active low after EN2 goes high and after one power good sequence delay t

provided by the

SQT

sequencing timer from the time PWRGD1 goes low, whichever comes later. PWRGD2 is reset by PWRGD1 going high or EN2 going low. This pin is internally pulled high by a 50µA current source.

PWRGD1 (Pin 3): Power Good Status Output One. At start-up, PWRGD1 latches active low and starts the power good sequence when the DRAIN pin is below 2.39V and GATE is within 2.8V of VIN. PWRGD1 status is reset by UV, VIN (UVLO), RESET going high or circuit breaker fault time-out. This pin is internally pulled high by a 50µA current source.

(Pin 4): Positive Supply Input. Connect this pin to the

positive side of the supply through a dropping resistor. A shunt regulator clamps VIN at 13V above VEE. An internal undervoltage lockout (UVLO) circuit holds GATE low until the V

pin is greater than V

UV is high, OV is low and V

, overriding UV and OV. If

LKO

comes out of UVLO, TIMER

starts an initial timing cycle before initiating GATE ramp up. If V

drops below approximately 8.2V (8.5V for the

LTC4253A), GATE pulls low immediately.

RESET (Pin 5): Circuit Breaker Reset Pin. This is an asynchronous TTL compatible input. RESET going high will pull GATE, SS, TIMER, SQTIMER low and the PWRGD outputs high. The RESET pulse must be wide enough to discharge any voltage on the TIMER pin below V

TMRL

. After the reset of a latched fault, the chip waits for the interlock conditions before recovering as described in Interlock Conditions in the Operation section.

SS (Pin 6): Soft-Start Pin. This pin is used to ramp inrush current during start up, thereby effecting control over di/dt. A 20X attenuated version of the SS pin voltage is presented to the current limit amplifier. This attenuated voltage limits the MOSFET’s drain current through the sense resistor during the soft-start current limiting. At the beginning of the start-up cycle, the SS capacitor (C

) is ramped by a 22µA (28µA for the LTC4253A) current source. The GATE pin is held low until SS exceeds 20 • V = 0.2V. SS is internally shunted by a 100k R

which limits

the SS pin voltage to 2.2V (50k resistor and 1.4V for the LTC4253A). This corresponds to an analog current limit SENSE voltage of 100mV (60mV for the LTC4253A). If the SS capacitor is omitted, the SS pin ramps up in about 250µs (140µs for the LTC4253A). The SS pin is pulled low under any of the following conditions: UVLO at V

, UV,

OV, during the initial timing cycle, a circuit breaker fault time-out or the RESET pin going high.

SENSE (Pin 7): Circuit Breaker/Current Limit Sense Pin. Load current is monitored by a sense resistor R nected between

SENSE and VEE, and controlled in three

con-

steps. If SENSE exceeds VCB (50mV), the circuit breaker comparator activates a (200µA+8•I current. If SENSE exceeds V

, the analog current-limit

ACL

) TIMER pull-up

DRN

amplifier pulls GATE down to regulate the MOSFET current at V SENSE may overshoot V

. In the event of a catastrophic short-circuit,

ACL/RS

. If SENSE reaches V

ACL

FCL

(200mV), the fast current-limit comparator pulls GATE low with a strong pull-down. To disable the circuit breaker and current limit functions, connect SENSE to VEE.

VEE (Pin 8): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply.

GATE (Pin 9): N-channel MOSFET Gate Drive Output. This pin is pulled high by a 50µA current source. GATE is pulled low by invalid conditions at VIN (UVLO), UV, OV, during the initial timing cycle, a circuit breaker fault time-out or the RESET pin going high. GATE is actively servoed to control the fault current as measured at SENSE. Compensation capacitor, CC, at GATE stabilizes this loop. A comparator monitors GATE to ensure that it is low before allowing an initial timing cycle, then the GATE ramps up after an overvoltage event or restart after a current limit fault.

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UUU

PI FU CTIO S

LTC4253/LTC4253A

During GATE start-up, a second comparator detects GATE within 2.8V of V

before PWRGD1 can be set and power

good sequencing starts.

DRAIN (Pin 10): Drain Sense Input. Connecting an external resistor, RD between this pin and the MOSFET’s drain

) allows voltage sensing below 6.15V (5V for

OUT

LTC4253A) and current feedback to TIMER. A comparator detects if DRAIN is below 2.39V and together with the GATE high comparator, sets the PWRGD1 flag. If V above V V

DRNCL

, the DRAIN pin is clamped at approximately

DRNCL

. RD current is internally multiplied by 8 and added

OUT

to TIMER’s 200µA during a circuit breaker fault cycle. This reduces the fault time and MOSFET heating.

OV (Pin 11): Overvoltage Input. For the LTC4253, the threshold at the OV pin is set at 6.15V with 0.3V hysteresis. If OV > 6.15V, GATE pulls low. When OV returns below

5.85V, GATE start-up begins without an initial timing cycle. The LTC4253A OV threshold is set at 5.09V with 102mV hysteresis. If OV > 5.09V, GATE pulls low. When OV returns below 4.988V, GATE start-up begins without an initial timing cycle. If OV occurs in the middle of an initial timing cycle, the initial timing cycle is restarted after OV goes away. OV does not reset the latched fault or PWRGD1 flag. The internal UVLO at V

always overrides

OV. A 1nF to 10nF capacitor at OV prevents transients and switching noise from affecting the OV thresholds and prevents glitches at the GATE.

starts an initial timing cycle when the following conditions are met: RESET is low, UV is high, OV is low, V UVLO, TIMER pin is low, GATE pin is lower than V < 0.2V, and V then charges C

(4V), the timing cycle terminates. TIMER quickly

TMRH

– VEE < VCB. A pull-up current of 5µA

SENSE

, generating a time delay. If CT charges to

clears

GATEL

, SS

pulls low and GATE is activated.

If SENSE exceeds 50mV while GATE is high, a circuit breaker cycle begins with a 200µA pull-up current charg- ing C

. If DRAIN is approximately 7V (6V for the LTC4253A)

during this cycle, the timer pull-up has an additional current of 8 • I

. If SENSE drops below 50mV before

DRN

TIMER reaches 4V, a 5µA pull-down current slowly dis- charges the C up to the V

. In the event that CT eventually integrates

(4V) threshold, the circuit breaker trips,

TMRH

GATE quickly pulls low and PWRGD1 pulls high. TIMER latches high with a 5µA pull-up source. This latched fault may be cleared by driving RESET high until TIMER is pulled low. Other ways of clearing the fault include pulling the V

pin momentarily below (V

LKO

– V

), pulling

LKH

TIMER low with an external device or pulling UV below

2.925V (2.756V for the LTC4253A).

SQTIMER (Pin 14): Sequencing Timer Input. The sequencing timer provides a delay t

for the power good sequenc-

SQT

ing. This delay is adjusted by connecting an appropriate capacitor to this pin. If the SQTIMER capacitor is omitted, the SQTIMER pin ramps from 0V to 4V in about 300µs.

UV (Pin 12): Undervoltage Input. For the LTC4253, the threshold at the UV pin is set at 3.225V with 0.3V hysteresis. If UV < 2.925V, PWRGD1 pulls high, both GATE and TIMER pull low. If UV rises above 3.225V, this initiates an initial timing cycle followed by GATE start-up. The LTC4253A UV threshold is set at 3.08V with 324mV hysteresis. If UV < 2.756V, PWRGD1 pulls high, both GATE and TIMER pull low. If UV rises above 3.08V, this initiates an initial timing cycle followed by GATE start-up. The internal UVLO at V

always overrides UV. A low at UV

resets an internal fault latch. A 1nF to 10nF capacitor at UV prevents transients and switching noise from affecting the UV thresholds and prevents glitches at the GATE pin.

TIMER (Pin 13): Timer Input. Timer is used to generate an initial timing delay at start-up, and to delay shutdown in the event of an output overload (circuit breaker fault). Timer

EN3 (Pin 15): Power Good Status Output Three Enable. This is a TTL compatible input that is used to control the PWRGD3 output. When EN3 is driven low, PWRGD3 will go high. When EN3 is driven high, PWRGD3 will go low provided PWRGD2 has been active for for more than one power good sequence delay (t

). EN3 can be used to

SQT

control the power good sequence. This pin is internally pulled low by a 120µA current source.

PWRGD3 (Pin 16): Power Good Status Output Three. Power good sequence starts with PWRGD1 latching active low. PWRGD3 will latch active low after EN3 goes high and after one power good sequence delay t

provided by the

SQT

sequencing timer from the time PWRGD2 goes low, whichever comes later. PWRGD3 is reset by PWRGD1 going high or EN3 going low. This pin is internally pulled high by a 50µA current source.

425353afc

Page 10

LTC4253/LTC4253A

BLOCK DIAGRA

50µA

120µA

SQTIMER

DELAY

SQTIMER

DELAY

6.15V

(5.09V)

PWRGD1

EN2

PWRGD2

EN3

PWRGD3

–

5µA

SQTIMER

–

0.33V

DRAIN

–

2.39V

–

8× 1×

50µA

6.15V (5V)

1×

–

1×

2.8V

–

GATE

UV 12

(2.756V)

200µA

5µA

2.925V

–

TIMER 13

–

22µA (28µA)

SS 6

95k (47.5k)

5k (2.5k)

FOR COMPONENTS, CURRENTS AND VOLTAGES WITH TWO VALUES, VALUES WITHOUT PARENTHESES REFER TO THE LTC4253, VALUES WITH PARENTHESES REFER TO THE LTC4253A

5µA

LOGIC

RESET

–

0.5V

FCL

–

200mV

–

ACL

–

10mV

–

SENSE7

–

50mV

–

4253 BD

425353afc

Page 11

OPERATIO

LTC4253/LTC4253A

Hot Circuit Insertion

When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. The LTC4253/LTC4253A are designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage.

Initial Start-Up

The LTC4253/LTC4253A reside on a removable circuit board and control the path between the connector and

PLUG-IN BOARD

–48RTN

LTC4253

LTC4253A

–48V

BACKPLANE

load or power conversion circuitry with an external MOSFET switch (see Figure 1). Both inrush control and shortcircuit protection are provided by the MOSFET.

A detailed schematic is shown in Figure 2. –48V and –48RTN receive power through the longest connector pins and are the first to connect when the board is inserted. The GATE pin holds the MOSFET off during this time. UV/OV determines whether or not the MOSFET should be turned on based upon internal high accuracy thresholds and an external divider. UV/OV does double duty by also monitoring whether or not the connector is seated. The top of the divider detects – 48RTN by way of a short connector pin that is the last to mate during the insertion sequence.

ISOLATED

DC/DC

MODULE

–

LOW VOLTAGE CIRCUITRY

4253 F01

LOAD

CONVERTER

–

–48RTN (LONG PIN)

–48RTN (SHORT PIN)

432k

4.75k

38.3k

–48V (LONG PIN)

Figure 1. Basic LTC4253/LTC4253A Hot Swap Topology

2.5k 15k(1/4W)/6

5.6k

EN3 EN2

1µF

†††

Q1 IRF530S

C 18nF

0.02Ω

10Ω

PUSH

RESET

UV OV RESET

0.33µF

LTC4253

PWRGD1 PWRGD2 PWRGD3

DRAINSS

GATESQTIMER

SENSETIMER

C1 10nF

68nF

47k

0.1µF

EN2

5.6k

†

5.6k

100µF

POWER MODULE 1 OUTPUT

POWER

MODULE 1

EN3

†

POWER

MODULE 2

POWER

MODULE 2

OUTPUT

MOC207

POWER

MODULE 3

4253 F02

Figure 2. –48V/2.5A Application with a Wider Operating Range

425353afc

Page 12

LTC4253/LTC4253A

OPERATIO

Interlock Conditions

A start-up sequence commences once these “interlock” conditions are met:

1. The input voltage VIN exceeds V

2. The voltage at UV > V

3. The voltage at OV < V

(VUV for the LTC4253A).

UVHI

OVLO

(UVLO).

LKO

(VOV – V

OVHST

for the

LTC4253A).

4. The input voltage at RESET < 0.8V.

5. The (SENSE – V

) voltage < 50mV (VCB)

6. The voltage at SS is < 0.2V (20 • VOS)

7. The voltage on the TIMER capacitor (C is < 1V (V

8. The voltage at GATE is < 0.5V (V

TMRL

GATEL

)

The first four conditions are continuously monitored and the latter four are checked prior to initial timing or GATE ramp-up. Upon exiting an OV condition, the TIMER pin voltage requirement is inhibited. Details are described in the Applications Information, Timing Waveforms section.

If RESET < 0.8V occurs after the LTC4253/LTC4253A come out of UVLO (interlock condition 1) and undervoltage (interlock condition 2), GATE and SS are released without an initial TIMER cycle once the other interlock conditions are met (see Figure 13a). If not, TIMER begins the start-up sequence by sourcing 5µA into C

. If VIN, UV or OV falls out

of range or RESET asserts, the start-up cycle stops and TIMER discharges C aforementioned conditions are once again met. If C

to less than 1V, then waits until the

successfully charges to 4V, TIMER pulls low and both SS and GATE pins are released. GATE sources 50µA (I

GATE

), charging the MOSFET gate and associated capacitance. The SS voltage ramp limits V

to control the inrush

SENSE

current. PWRGD1 pulls active low when GATE is within

2.8V of V

and DRAIN is lower than V

. This sets off

DRNL

the power good sequence in which PWRGD2 and then PWRGD3 is subsequently pulled low after a delay, adjustable through the SQTIMER capacitor CSQ or by external control inputs EN2 and EN3. In this way, external loads or power modules controlled by the three PWRGD signals are turned on in a controlled manner without overloading the power bus.

Two modes of operation are possible during the time the MOSFET is first turned on, depending on the values of external components, MOSFET characteristics and nominal design current. One possibility is that the MOSFET will turn on gradually so that the inrush into the load capacitance remains a low value. The output will simply ramp to –48V and the LTC4253/LTC4253A will fully enhance the MOSFET. A second possibility is that the load current exceeds the soft-start current limit threshold of [V 20 – V

]/RS. In this case the LTC4253/LTC4253A ramp

(t)/

the output by sourcing soft-start limited current into the load capacitance. If the soft-start voltage is below 1.2V, the circuit breaker TIMER is held low. Above 1.2V, TIMER ramps up. It is important to set the timer delay so that, regardless of which start-up mode is used, the TIMER ramp is less than one circuit breaker delay time. If this condition is not met, the LTC4253/LTC4253A may shut down after one circuit breaker delay time.

Board Removal

When the board is withdrawn from the card cage, the UV/OV divider is the first to lose connection. This shuts off the MOSFET and commutates the flow of current in the connector. When the power pins subsequently separate there is no arcing.

Current Control

Three levels of protection handle short-circuit and overload conditions. Load current is monitored by SENSE and resistor R

. There are three distinct thresholds at SENSE:

50mV for a timed circuit breaker function; 100mV for an analog current limit loop (60mV for the LTC4253A); and 200mV for a fast, feedforward comparator which limits peak current in the event of a catastrophic short-circuit.

If, due to an output overload, the voltage drop across R

exceeds 50mV, TIMER sources 200µA into CT. CT eventually charges to a 4V threshold and the LTC4253/LTC4253A shut off. If the overload goes away before C and SENSE measures less than 50mV, C

reaches 4V

slowly dis-

charges (5µA). In this way the LTC4253/LTC4253A’s circuit breaker function responds to low duty cycle overloads, and accounts for the fast heating and slow cooling characteristic of the MOSFET.

425353afc

Page 13

OPERATIO

LTC4253/LTC4253A

Higher overloads are handled by an analog current limit loop. If the drop across R

reaches V

, the current

ACL

limiting loop servos the MOSFET gate and maintains a constant output current of V

(MOSFET drain-source voltage drop) typically rises

OUT

and this increases MOSFET heating. If V connecting an external resistor, R

. In current limit mode,

ACL/RS

OUT

between V

> V

OUT

DRNCL

and

DRAIN allows the fault timing cycle to be shortened by accelerating the charging of the TIMER capacitor. The TIMER pull-up current is increased by 8 • I because SENSE > 50mV, TIMER charges C

. Note that

DRN

during this

time, and the LTC4253/LTC4253A eventually shut down.

Low impedance failures on the load side of the LTC4253/ LTC4253A, coupled with 48V or more driving potential, can produce current slew rates well in excess of 50A/µs. Under these conditions, overshoot is inevitable. A fast SENSE comparator with a threshold of 200mV detects overshoot and pulls GATE low much harder and hence much faster than the weaker current limit loop. The V R

current limit loop then takes over and servos the cur-

ACL

rent as previously described. As before, TIMER runs and shuts down the LTC4253/LTC4253A when C

reaches 4V.

reaches 4V, the LTC4253/LTC4253A latch off with a

If C

5µA pull-up current source. The LTC4253/LTC4253A cir- cuit breaker latch is reset by either pulling the RESET pin active high until TIMER goes low, pulling UV momentarily low, dropping the input voltage V

below the internal

UVLO threshold or pulsing TIMER momentarily low with a switch.

Although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. Noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus or the insertion of non-hot swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. The action of TIMER and C

rejects these events allowing the LTC4253/

LTC4253A to “ride out” temporary overloads and disturbances that could trip a simple current comparator and, in some cases, blow a fuse.

425353afc

Page 14

LTC4253/LTC4253A

APPLICATIO S I FOR ATIO

WUU

(Refer to Block Diagram)

SHUNT REGULATOR

A fast responding regulator shunts the LTC4253/LTC4253A

pin. Power is derived from –48RTN by an external

current limiting resistor. The shunt regulator clamps V

to 13V (VZ). A 1µF decoupling capacitor at VIN filters supply transients and contributes a short delay at start-up. R

should be chosen to accommodate both VIN supply

current and the drive required for three optocouplers used by the PWRGD signals. Higher current through R in higher dissipation for R well as higher V

noise. Alternative circuits are VIN with an

NPN buffer as in Figure 3, V

and LTC4253/LTC4253A as

driving base resistors of NPN

results

cascodes as in Figure 17 or VIN driving the gates of MOSFET cascodes replacing the NPNs in Figure 17. Multiple 1/4W resistors can replace a single higher power R

resistor.

INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)

A hysteretic comparator, UVLO, monitors V undervoltage. The thresholds are defined by V hysteresis V enabled; below (V pulled low. The UVLO function at V

. When VIN rises above V

LKH

LKO

– V

), it is disabled and GATE is

LKH

, the chip is

LKO

should not be

LKO

for

and its

confused with the UV and OV pins. These are completely separate functions.

UV/OV COMPARATORS (LTC4253)

A UV hysteretic comparator detects undervoltage conditions at the UV pin, with the following thresholds:

UV low-to-high (V

UV high-to-low (V

) = 3.225V

UVHI

) = 2.925V

UVLO

An OV hysteretic comparator detects overvoltage conditions at the OV pin, with the following thresholds:

OV low-to-high (V

OV high-to-low (V

) = 6.150V

OVHI

) = 5.850V

OVLO

The UV and OV trip point ratio is designed to match the standard telecom operating range of 43V to 82V when connected together as in the Typical Application. A resistive divider is used to scale the supply voltage. Using 402k and 32.4k gives a typical operating range of 43.2V to 82.5V. The undervoltage shutdown and overvoltage recovery thresholds are then 39.2V and 78.4V. 1% divider resistors are recommended to preserve threshold accuracy.

–48V RTN (LONG PIN)

–48V RTN (SHORT PIN)

392k

30.1k 1%

–48V (LONG PIN)

47k

EN3 EN2

1µF

R3 22k

Q2 FZT857

2.2k

†††

Q1 IRF530S

R 10Ω

10nF

0.02Ω

EN2

2.2k

IN1

†

2.2k

100µF

POWER MODULE 1 OUTPUT

POWER

MODULE 1

EN3

IN1

†

MOC207

POWER

MODULE 2

POWER

MODULE 2

OUTPUT

POWER

MODULE 3

4253 F03

425353afc

10k

20k(1/4W)/2

PUSH

RESET

LTC4253A

PWRGD1

PWRGD2

PWRGD3

0.1µF

33nF

RESET

0.68µF

DRAINSS

GATESQTIMER

SENSETIMER

C1 10nF

Figure 3. –48V/2.5A Application for the LTC4253A

Page 15

LTC4253/LTC4253A

WUU

APPLICATIO S I FOR ATIO

The resistive divider values shown set a standing current of slightly more than 100µA and define an impedance at UV/OV of 30kΩ. In most applications, 30kΩ impedance coupled with 300mV UV hysteresis make the LTC4253 insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to V

The separate UV and OV pins can be used for wider operating range such as 35.6V to 76.3V range as shown in Figure 2. Other combinations are possible with different resistors arrangement.

UV/OV COMPARATORS (LTC4253A)

A UV hysteretic comparator detects undervoltage conditions at the UV pin, with the following thresholds:

UV low-to-high (VUV) = 3.08V

UV high-to-low (V

– V

UVHST

) = 2.756V

An OV hysteretic comparator detects overvoltage conditions at the OV pin, with the following thresholds:

OV low-to-high (VOV) = 5.09V

OV high-to-low (V

– V

OVHST

) = 4.988V

The UV and OV trip point ratio is designed to match the standard telecom operating range of 43V to 71V when connected together as in Figure 3. A divider (R1, R2) is used to scale the supply voltage. Using R1 = 392k and R2 = 30.1k gives a typical operating range of 43.2V to 71.4V. The undervoltage shutdown and overvoltage recovery thresholds are then 38.6V and 69.9V. 1% divider resistors are recommended to preserve threshold accuracy.

The R1-R2 divider values shown in Figure 3 set a standing current of slightly more than 100µA and define an impedance at UV/OV of 28kΩ. In most applications, 28kΩ impedance coupled with 324mV UV hysteresis makes the LTC4253A insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to VEE.

The UV and OV pins can also be used for a wider operating range by adding a resistor between UV and OV as shown in Figure 2 for the LTC4253. Other combinations are possible with different resistor arrangements.

UV/OV OPERATION

A low input to the UV comparator will reset the chip and pull the GATE and TIMER pins low. A low-to-high UV transition will initiate an initial timing sequence if the other interlock conditions are met. A high-to-low transition in the UV comparator immediately shuts down the LTC4253/ LTC4253A, pulls the MOSFET gate low and resets the three latched PWRGD signals high.

An overvoltage condition is detected by the OV comparator and pulls GATE low, thereby shutting down the load, but it will not reset the circuit breaker TIMER and PWRGD flags. Returning from the overvoltage condition will restart the GATE pin if all the interlock conditions except TIMER are met. Only during the initial timing cycle does OV condition have an effect of resetting TIMER.

DRAIN

Connecting an external resistor, R DRAIN pin allows V

(MOSFET drain-source voltage

OUT

, to this dual function

drop) sensing without it being damaged by large voltage transients. Below 5V, negligible pin leakage allows a DRAIN low comparator to detect V (V

). This, together with the GATE low comparator,

DRNL

less than 2.39V

OUT

sets the PWRGD flag.

When V

OUT

> V

, the DRAIN pin is clamped at V

DRNCL

and the current flowing in RD is given by:

−

DRN

OUT DRNCL

≈

(1)

This current is scaled up 8 times during a circuit breaker fault before being added to the nominal 200µA. This accelerates the fault TIMER pull-up when the MOSFET’s drain-source voltage exceeds V

and effectively short-

DRNCL

ens the MOSFET heating duration.

425353afc

Page 16

LTC4253/LTC4253A

WUU

APPLICATIO S I FOR ATIO

TIMER

The operation of the TIMER pin is somewhat complex as it handles several key functions. A capacitor C TIMER to provide timing for the LTC4253/LTC4253A. Four different charging and discharging modes are available at TIMER:

1. 5µA slow charge; initial timing delay.

2. (200µA+8•I

) fast charge; circuit breaker delay.

DRN

3. 5µA slow discharge; circuit breaker “cool-off.”

4. Low impedance switch; resets the TIMER capacitor after an initial timing delay, in UVLO, in UV and in OV during initial timing and when RESET is high.

For initial timing delay, the 5µA pull-up is used. The low impedance switch is turned off and the 5µA current source is enabled when the interlock conditions are met. C charges to 4V in a time period given by:

•

µ45

is used at

(2)

If V current and this makes I above V charging of C

< 5V, an internal PMOS isolates DRAIN pin leakage

OUT

= 0 in Equation (3). If V

DRN

during the circuit breaker fault period, the

DRNCL

is accelerated by 8 • I

of Equation (1).

DRN

OUT

Intermittent overloads may exceed the 50mV threshold at SENSE but, if their duration is sufficiently short, TIMER will not reach 4V and the LTC4253/LTC4253A will not shut the external MOSFET off. To handle this situation, the TIMER discharges C

slowly with a 5µA pull-down when-

ever the SENSE voltage is less than 50mV. Therefore, any intermittent overload with V

< 5V and an aggregate

OUT

duty cycle of more than 2.5% will eventually trip the circuit breaker and shut down the LTC4253/LTC4253A. Figure 4 shows the circuit breaker response time in seconds normalized to 1µF. The asymmetric charging and discharging of C

is a fair gauge of MOSFET heating.

The normalized circuit response time is estimated by:

()

205 8 5

()

[]

••

DRN

for D

(4)

−

When C turns on and discharges C

reaches V

( 4V), the low impedance switch

TMRH

. A GATE start-up cycle begins

and both SS and GATE outputs are released.

CIRCUIT BREAKER TIMER OPERATION

If the SENSE pin detects more than 50mV drop across RS, the TIMER pin charges C

with (200µA+8•I

DRN

). If C

charges to 4V, the GATE pin pulls low and the LTC4253/ LTC4253A latch off. The LTC4253/LTC4253A remain latched off until the RESET pin is momentarily pulsed high, the UV pin is momentarily pulsed low, the TIMER pin is momentarily discharged low by an external switch or V

dips below UVLO and is then restored. The circuit breaker timeout period is given by:

200 8••

µ+

DRN

(3)

0.1

NORMALIZED RESPONSE TIME (s/µF)

0.01

Figure 4. Circuit Breaker Response Time

(µF)4(205 + 8 • I

20 40 60 800

FAULT DUTY CYCLE, D (%)

DRN

) • D – 5

= 0µA

100

4253 F04

425353afc

Page 17

LTC4253/LTC4253A

VtV e

SS SS

()–≈−

⎛

⎝

⎜ ⎜

⎞

⎠

⎟ ⎟

WUU

APPLICATIO S I FOR ATIO

POWER GOOD SEQUENCING

After the initial TIMER cycle, GATE ramps up to turn on the external MOSFET which in turn pulls DRAIN low. When GATE is within 2.8V of VIN and DRAIN is lower than V the power good sequence starts with PWRGD1 pulling active low. This starts off a 5µA pull-up on the SQTIMER pin which ramps up until it reaches the 4V threshold then pulls low. When the SQTIMER pin floats, this delay t about 300µs. Connecting an external capacitor C SQTIMER to V

SQT

modifies the delay to:

•

µ45

PWRGD2 asserts when EN2 goes high and PWRGD1 has asserted for more than one t

. When PWRGD2 success-

SQT

fully pulls low, SQTIMER ramps up on another delay cycle. PWRGD3 asserts when EN2 and EN3 go high and PWRGD2 has asserted for more than one t

SQT

All three PWRGD signals are reset in UVLO, in UV condition, if RESET is high or when C

charges up to 4V. In

addition, PWRGD2 is reset by EN2 going low. PWRGD3 is reset by EN2 or EN3 going low. An overvoltage condition has no effect on the PWRGD flags. A 50µA current pulls each PWRGD pin high when reset. As power modules signal common are different from PWRGD, optoisolation is recommended. These three pins can sink an optodiode current. Figure 17 shows an NPN configuration for the PWRGD interface. A limiting base resistor should be used for each NPN and the module enable input should have protection from negative bias current.

SOFT-START

Soft-start is effective in limiting the inrush current during GATE start-up. Unduly long soft-start intervals can exceed the MOSFET’s SOA duration if powering-up into an active load. When the SS pin floats, an internal current source ramps SS from 0V to 2.2V in about 300µs (0V to 1.4V in about 200µs for the LTC4253A). Connecting an external capacitor, CSS, from SS to ground modifies the ramp to approximate an RC response of:

DRNL

SQT

from

(5)

(6)

An internal resistor divider (95k/5k for the LTC4253 and

47.5k/2.5k for the LTC4253A) scales V

(t) down by 20

times to give the analog current limit threshold:

()

ACL

This allows the inrush current to be limited to V The offset voltage, V

–=

(t)/RS.

ACL

(10mV), ensures CSS is sufficiently

(7)

discharged and the ACL amplifier is in current limit mode before GATE start-up. SS is discharged low during UVLO at VIN , UV, OV, during the initial timing cycle, a latched circuit breaker fault or the RESET pin going high.

GATE

GATE is pulled low to VEE under any of the following conditions: in UVLO, when RESET pulls high, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or a latched circuit breaker fault. When GATE turns on, a 50µA current source charges the MOSFET gate and any associated external capacitance. VIN limits the gate drive to no more than 14.5V.

Gate-drain capacitance (C

) feedthrough at the first

abrupt application of power can cause a gate-source voltage sufficient to turn on the MOSFET. A unique circuit pulls GATE low with practically no usable voltage at V

and eliminates current spikes at insertion. A large external gate-source capacitor is thus unnecessary for the purpose of compensating C capacitor C

is adequate. CC also provides compensation

. Instead, a smaller value (≥10nF)

for the analog current limit loop.

GATE has two comparators: the GATE low comparator looks for <0.5V threshold prior to initial timing; the GATE high comparator looks for <2.8V relative to VIN and, together with DRAIN low comparator, sets PWRGD1 output during GATE start-up.

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APPLICATIO S I FOR ATIO

SENSE

The SENSE pin is monitored by the circuit breaker (CB) comparator, the analog current limit (ACL) amplifier, and the fast current limit (FCL) comparator. Each of these three measures the potential of SENSE relative to V SENSE exceeds 50mV, the CB comparator activates the 200µA TIMER pull-up. At 100mV (60mV for the LTC4253A) the ACL amplifier servos the MOSFET current, and at 200mV the FCL comparator abruptly pulls GATE low in an attempt to bring the MOSFET current under control. If any of these conditions persists long enough for TIMER to charge C

to 4V (see Equation 3), the LTC4253/LTC4253A

shut down and pull GATE low.

If the SENSE pin encounters a voltage greater than V the ACL amplifier will servo GATE downwards in an attempt to control the MOSFET current. Since GATE overdrives the MOSFET in normal operation, the ACL amplifier needs time to discharge GATE to the threshold of the MOSFET. For a mild overload the ACL amplifier can control the MOSFET current, but in the event of a severe overload the current may overshoot. At SENSE = 200mV the FCL comparator takes over, quickly discharging the GATE pin to near VEE potential. FCL then releases, and the ACL amplifier takes over. All the while TIMER is running. The effect of FCL is to add a nonlinear response to the control loop in favor of reducing MOSFET current.

Owing to inductive effects in the system, FCL typically overcorrects the current limit loop, and GATE undershoots. A zero in the loop (resistor RC in series with the gate capacitor) helps the ACL amplifier to recover.

SHORT-CIRCUIT OPERATION

Circuit behavior arising from a load side low impedance short is shown in Figure 5. Initially the current overshoots the analog current limit level of V as the GATE pin works to bring V

= 200mV (trace 2)

SENSE

under control (trace 3). The overshoot glitches the backplane in the negative direction and when the current is reduced to 100mV/R backplane responds by glitching in the positive direction.

. When

ACL

, the

TIMER commences charging CT (trace 4) while the analog current limit loop maintains the fault current at 100mV/R

which in this case is 5A (trace 2). Note that the backplane voltage (trace 1) sags under load. Timer pull-up is accelerated by V

. When CT reaches 4V, GATE turns off, the

OUT

PWRGD signals pull high, the load current drops to zero and the backplane rings up to over 100V. The transient associated with the GATE turn-off can be controlled with a snubber to reduce ringing and a transient voltage suppressor (such as Diodes Inc. SMAT70A) to clip off large spikes. The choice of RC for the snubber is usually done experimentally. The value of the snubber capacitor is usually chosen between 10 to 100 times the MOSFET C

. The value of the snubber resistor is typically be-

OSS

tween 3Ω to 100Ω.

A low impedance short on one card may influence the behavior of others sharing the same backplane. The initial glitch and backplane sag as seen in Figure 5 trace 1, can rob charge from output capacitors on the adjacent card. When the faulty card shuts down, current flows in to refresh the capacitors. If LTC4253/LTC4253A are used by the other cards, they respond by limiting the inrush current to a value of V capacitors will recharge long before C

SUPPLY RING OWING

TO CURRENT OVERSHOOT

–48RTN

0.5ms 50V

SENSE

0.5ms

200mV

GATE

0.5ms 10V

TIMER

0.5ms

Figure 5. Output Short-Circuit Behavior of LTC4253

. If CT is sized correctly, the

ACL/RS

times out.

SUPPLY RING OWING TO MOSFET TURN-OFF

ONSET OF OUTPUT SHORT-CIRCUIT

FAST CURRENT LIMIT

ANALOG CURRENT LIMIT

RAMP

LATCH OFF

4253 F05

TIMER

TRACE 1

TRACE 2

TRACE 3

TRACE 4

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APPLICATIO S I FOR ATIO

MOSFET SELECTION

The external MOSFET switch must have adequate safe operating area (SOA) to handle short-circuit conditions until TIMER times out. These considerations take precedence over DC current ratings. A MOSFET with adequate SOA for a given application can always handle the required current but the opposite may not be true. Consult the manufacturer’s MOSFET data sheet for safe operating area and effective transient thermal impedance curves.

MOSFET selection is a 3-step process by assuming the absence of soft-start capacitor. First, R then the time required to charge the load capacitance is determined. This timing, along with the maximum short-circuit current and maximum input voltage, defines an operating point that is checked against the MOSFET’s SOA curve.

To begin a design, first specify the required load current and Ioad capacitance, I current trip point (V

CB/RS

and CL. The circuit breaker

) should be set to accommodate the maximum load current. Note that maximum input current to a DC/DC converter is expected at V R

is given by:

CB MIN

LMAX

CB(MIN)

()

= 40mV (45mV for the LTC4253A) repre-

where V sents the guaranteed minimum circuit breaker threshold.

During the initial charging process, the LTC4253/LTC4253A may operate the MOSFET in current limit, forcing (V between 80mV to 120mV (V LTC4253A) across R

. The minimum inrush current is

is 54mV to 66mV for the

ACL

given by:

()

INRUSH MIN

()

ACL MIN

Maximum short-circuit current limit is calculated using the maximum V

SHORTCIRCUIT MAX

. This gives

SENSE

()

ACL MAX

is calculated and

SUPPLY(MIN)

ACL

(10)

(8)

)

(9)

The TIMER capacitor C

must be selected based on the

slowest expected charging rate; otherwise TIMER might time out before the load capacitor is fully charged. A value for CT is calculated based on the maximum time it takes the load capacitor to charge. That time is given by:

()

CL CHARGE

L SUPPLY MAX

INRUSH MIN

()

(11)

()

•

The maximum current flowing in the DRAIN pin is given by:

()

DRN MAX

SUPPLY MAX DRNCL

Approximating a linear charging rate, I I

DRN(MAX)

to zero, the I

DRN

be approximated with 0.5 • I equation, TIMER capacitor C

tAI

CL CHARGE DRN MAX

() ()

•( • )200 4

−

()

drops from

DRN

(12)

component in Equation (3) can

DRN(MAX)

is given by:

. Rearranging the

µ+

(13)

Returning to Equation (3), the TIMER period is calculated and used in conjunction with V I

SHORTCIRCUIT(MAX)

to check the SOA curves of a prospec-

SUPPLY(MAX)

and

tive MOSFET.

As a numerical design example for the LTC4253, consider a 30W load, which requires 1A input current at 36V. If V

SUPPLY(MAX)

= 72V and CL = 100µF, RD = 1MΩ, Equation (8) gives RS= 40mΩ; Equation (13) gives CT = 414nF. To account for errors in R TIMER threshold (4V), R DRAIN voltage clamp (V

, CT, TIMER current (200µA),

, DRAIN current multiplier and

), the calculated value should

DRNCL

be multiplied by 1.5, giving the nearest standard value of C

= 680nF.

If a short-circuit occurs, a current of up to 120mV/40mΩ = 3A will flow in the MOSFET for 6.3ms as dictated by CT = 680nF in Equation (3). The MOSFET must be selected based on this criterion. The IRF530S can handle 100V and 3A for 10ms and is safe to use in this application.

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APPLICATIO S I FOR ATIO

Computing the maximum soft-start capacitor value during soft-start to a load short is complicated by the nonlinear MOSFET’s SOA characteristics and the R An overconservative but simple approach begins with the maximum circuit breaker current, given by:

()

CB MAX

where V

CB(MAX)

CB MAX

is 60mV (55mV for the LTC4253A).

From the SOA curves of a prospective MOSFET, determine the time allowed, t

SOA MAX

()

.•

0 916

SOA MAX

()

.•

248

SOA(MAX)

. CSS is given by:

for the LTC4253

for the LTC4253A

In the above example, 60mV/40mΩ gives 1.5A. t the IRF530S is 40ms. From Equation (15), C Actual board evaluation showed that C appropriate. The ratio ( R

SS • CSS

) to t

CL(CHARGE)

gauge as large ratios may result in the time-out period expiring prematurely. This gauge is determined empirically with board level evaluation.

SUMMARY OF DESIGN FLOW

To summarize the design flow, consider the application shown in Figure 3 for the LTC4253A. It was designed for 80W and C

= 100µF.

Calculate maximum load current: 80W/43V = 1.86A; allowing for 83% converter efficiency, I

Calculate R

Calculate I I

SHORTCIRCUIT(MAX)

: from Equation (8) RS = 20mΩ.

SHORT-CIRCUIT(MAX)

: from Equation (10)

= 3.3A.

IN(MAX)

Select a MOSFET that can handle 3.3A at 71V: IRF530S.

Calculate C

= 680nF, which gives the circuit breaker time-out

period t

: from Equation (13) CT = 302nF. Select

= 5.9ms.

MAX

response.

SSCSS

SOA

= 437nF.

= 100nF was

is a good

= 2.2A.

(14)

(15)

for

Consult MOSFET SOA curves: the IRF530S can handle

3.3A at 100V for 8.3ms, so it is safe to use in this application.

Calculate C

= 33nF.

: using Equations (14) and (15) select

FREQUENCY COMPENSATION

The LTC4253 typical frequency compensation network for the analog current limit loop is a series RC (10Ω) and C

connected from GATE to VEE. Figure 6 depicts the relationship between the compensation capacitor C MOSFET’s C starting value for C

. The line in Figure 6 is used to select a

ISS

based upon the MOSFET’s C

and the

ISS

specification. Optimized values for CC are shown for several popular MOSFETs. Differences in the optimized value of C

versus the starting value are small. Neverthe-

less, compensation values should be verified by board level short-circuit testing.

As seen in Figure 5, at the onset of a short-circuit event, the input supply voltage can ring dramatically due to series inductance. If this voltage avalanches the MOSFET, current continues to flow through the MOSFET to the output. The analog current limit loop cannot control this current flow and therefore the loop undershoots. This effect cannot be eliminated by frequency compensation. A zener diode is required to clamp the input supply voltage and prevent MOSFET avalanche.

(nF)

IRF530

COMPENSATION CAPACITOR C

Figure 6. Recommended Compensation Capacitor C

IRF3710

IRF540

IRF740

2000

MOSFET C

vs MOSFET C

4000

NTY100N10

6000

(pF)

ISS

for the LTC4253

ISS

8000

4253 F06

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APPLICATIO S I FOR ATIO

SENSE RESISTOR CONSIDERATIONS

For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the LTC4253/ LTC4253A’s VEE and SENSE pins are strongly recommended. The drawing in Figure 7 illustrates the correct way of making connections between the LTC4253/ LTC4253A and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation.

CURRENT FLOW

FROM LOAD

TRACK WIDTH W:

0.03" PER AMP

ON 1 OZ COPPER

Figure 7. Making PCB Connections to the Sense Resistor

SENSE RESISTOR

SENSE

TIMING WAVEFORMS

System Power-Up

Figure 8 details the timing waveforms for a typical powerup sequence in the case where a board is already installed in the backplane and system power is applied abruptly. At time point 1, the supply ramps up, together with UV/OV,

and DRAIN. VIN and the PWRGD signals follow at a

OUT

slower rate as set by the V point 2, V UV > V V

OVHST

SENSE < V

exceeds V

(VUV for the LTC4253A), OV < V

UVHI

LKO

for the LTC4253A), RESET < 0.8V, GATE < V

, SS < 20 • VOS, and TIMER < V

bypass capacitor. At time

and the internal logic checks for

all conditions are met, initial timing starts and the TIMER

CURRENT FLOW

TO –48V BACKPLANE

OVLO

TMRL

4253 F07

(VOV –

GATEL

. When

capacitor is charged by a 5µA current source pull-up. At time point 3, TIMER reaches the V

threshold and the

TMRH

initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the V reached and the conditions of GATE < V

GATEL

threshold is

TMRL

, SENSE < V

and SS < 20 • VOS must be satisfied before the GATE startup cycle begins. SS ramps up as dictated by R

• CSS (as

in Equation 6); GATE is held low by the analog current limit (ACL) amplifier until SS crosses 20 • V

. Upon releasing

GATE, 50µA sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET’s threshold, current flows into the load capacitor at time point 5. At time point 6, load current reaches SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed, the SENSE voltage is regulated at V

ACL

(t) (Equation 7) and soft-start limits the slew rate of the load current. If the SENSE voltage (V

threshold at time point 7, circuit breaker TIMER

activates. The TIMER capacitor, C (200µA+8•I

) current pull-up. As the load capacitor

DRN

– VEE) reaches the

SENSE

, is charged by a

nears full charge, load current begins to decline. At time point 8, the load current falls and the SENSE voltage drops below V

(t). The analog current limit loop shuts off and

ACL

the GATE pin ramps further. At time point 9, the SENSE voltage drops below V

, the fault TIMER ends, followed

by a 5µA discharge cycle (cool-off). The duration between time points 7 and 9 must be shorter than one circuit breaker delay to avoid fault time-out during GATE rampup. When GATE ramps past the V

threshold at time

GATEH

point A, PWRGD1 pulls low. At time point B, GATE reaches its maximum voltage as determined by V

. At time point

A, SQTIMER starts its ramp-up to 4V. Having satisfied the requirement that PWRGD1 is low for more than one t PWRGD2 pulls low after EN2 pulls high above the V

SQT

threshold at time point C. This sets off the second SQTIMER ramp-up. Having satisfied the requirement that PWRGD2 is low for more than one t

, PWRGD3 pulls low after EN3

SQT

pulls high at time point D.

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APPLICATIO S I FOR ATIO

GND – VEE OR

(–48RTN) – (–48V)

UV/OV

TIMER

GATE

SENSE

OUT

VIN CLEARS V RESET < 0.8V, GATE < V

12 3456 789

LKO

GATEL

, CHECK UV > V

LKO

5µA

, SENSE < VCB, SS < 20 • VOS AND TIMER < V

GATEL

20 • (V

(VUV FOR THE LTC4253A), OV < V

UVHI

TIMER CLEARS V

TMRH

+ VOS)

ACL

20 • (VCB + VOS)

20 • V

200µA + 8 • I

TMRL

50µA

OVLO (VOV

TMRL

, CHECK GATE < V

TMRL

DRN

VIN – V

GATEH

ACL

– V

5µA

OVHST

FOR THE LTC4253A),

, SENSE < VCB AND SS < 20 • V

GATEL

5µA

DRAIN

PWRGD1

PWRGD2

PWRGD3

SQTIMER

EN2

EN3

DRNCL

SQTMRH

5µA

DRNL

5µA

SQTMRH

50µA

INITIAL TIMING

GATE

START-UP

Figure 8. System Power-Up Timing (All Waveforms are Referenced to VEE)

4253 F08

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APPLICATIO S I FOR ATIO

Live Insertion with Short Pin Control of UV/OV

In the example shown in Figure 9, power is delivered through long connector pins whereas the UV/OV divider makes contact through a short pin. This ensures the power con-

GND – VEE OR

(–48RTN) – (–48V)

UV/OV

TIMER

GATE

SENSE

UV CLEARS V SENSE < V

12 3456789

UVHI

GATEL

LKO

FOR THE LTC4253A), CHECK OV < V

UVHI (VUV

, SS < 20 • VOS AND TIMER < V

5µA

TMRH

20 • (V

+ VOS)

ACL

20 • (VCB + VOS)

20 • V

TMRL

nections are firmly established before the LTC4253/ LTC4253A are activated. At time point 1, the power pins make contact and V

ramps through V

. At time point 2,

LKO

the UV/OV divider makes contact and its voltage exceeds

TMRL

TIMER CLEARS V

200µA + 8 • I

50µA

(VOV FOR THE LTC4253A), RESET < 0.8V, GATE < V

OVHI

50µA

, CHECK GATE < V

TMRL

A B

DRN

VIN – V

ACL

C D

5µA

GATEH

, SENSE < VCB AND SS < 20 • V

GATEL

5µA

GATEL

OUT

DRAIN

PWRGD1

PWRGD2

PWRGD3

SQTIMER

EN2

EN3

DRNCL

SQTMRH

5µA

DRNL

SQTMRL

5µA

SQTMRH

SQTMRL

50µA

INITIAL TIMING

GATE

START-UP

Figure 9. Power-Up Timing with a Short Pin (All Waveforms are Referenced to VEE)

4253 F09

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APPLICATIO S I FOR ATIO

(VUV for the LTC4253A). In addition, the internal logic

UVHI

checks for OV < V

0.8V, GATE < V TIMER < V

TMRL

starts and the TIMER capacitor is charged by a 5µA current source pull-up. At time point 3, TIMER reaches the V threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the V threshold is reached and the conditions of GATE < V SENSE < V

and SS < 20 • VOS must be satisfied before

the GATE start-up cycle begins. SS ramps up as dictated by R

• CSS; GATE is held low by the analog current limit

amplifier until SS crosses 20 • V 50µA sources into the external MOSFET gate and compen- sation network. When the GATE voltage reaches the MOSFET’s threshold, current begins flowing into the load capacitor at time point 5. At time point 6, load current reaches SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed and the SENSE voltage is regulated at V and soft-start limits the slew rate of the load current. If the SENSE voltage (V at time point 7, the circuit breaker TIMER activates. The TIMER capacitor, C current pull-up. As the load capacitor nears full charge, load current begins to decline. At point 8, the load current falls and the SENSE voltage drops below V current limit loop shuts off and the GATE pin ramps further. At time point 9, the SENSE voltage drops below V and the fault TIMER ends, followed by a 5µA discharge current source (cool-off). When GATE ramps past V threshold at time point A, PWRGD1 pulls low, starting off the PWRGD sequence. PWRGD2 pulls low at time point C when EN2 is high and PWRGD1 is low for more than one t

. PWRGD3 pulls low at time point D when EN2 and EN3

SQT

is high and PWRGD2 is low for more than one t point B, GATE reaches its maximum voltage as determined

by V

(VOV for the LTC4253A), RESET <

OVHI

SENSE < VCB, SS < 20 • VOS and

GATEL,

. When all conditions are met, initial timing

TMRH

TMRL

GATEL

. Upon releasing GATE,

(t)

ACL

– VEE) reaches the VCB threshold

SENSE

is charged by a (200µA+8•I

(t). The analog

ACL

. At time

SQT

DRN

GATEH

)

Undervoltage Timing

In Figure 10 when the UV pin drops below V V

for the LTC4253A) at time point 1, the LTC4253/

UVHST

UVLO

(VUV –

LTC4253A shut down with TIMER, SS and GATE pulled low. If current has been flowing, the SENSE pin voltage decreases to zero as GATE collapses. When UV recovers and clears V

(VUV for the LTC4253A) at time point 2,

UVHI

an initial time cycle begins followed by a start-up cycle.

Undervoltage Lockout Timing

undervoltage lockout comparator, UVLO has a similar

timing behavior as the UV pin timing except it looks at V < (V

LKO–VLKH

) to shut down and VIN > V

to start. In an

LKO

undervoltage lockout condition, both UV and OV comparators are held off. When V

exits undervoltage lockout,

the UV and OV comparators are enabled.

Overvoltage Timing

During normal operation, if the OV pin exceeds V

OVHI

for the LTC4253A) as shown at time point 1 of Figure 11, the TIMER and PWRGD status are unaffected; SS and GATE pull down; load disconnects. At time point 2, OV recovers and drops below the V

OVLO

(VOV – V

OVHST

for the LTC4253A) threshold; GATE start-up begins. If the overvoltage glitch is long enough to deplete the load capacitor, time points 4 through 7 may occur.

Circuit Breaker Timing

In Figure 12a, the TIMER capacitor charges at 200µA if the SENSE pin exceeds VCB but V SENSE pin returns below V

threshold, TIMER is discharged by 5µA. In

TMRH

Figure 12b, when TIMER exceeds V

is less than 5V. If the

DRN

before TIMER reaches the

, GATE pulls

TMRH

down immediately and the chip shuts down. In Figure 12c, multiple momentary faults cause the TIMER capacitor to integrate and reach V

followed by GATE pull down

TMRH

and the chip shuts down. During chip shutdown, the LTC4253/LTC4253A latch TIMER high with a 5µA pull-up current source.

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LTC4253/LTC4253A

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APPLICATIO S I FOR ATIO

TIMER

GATE

SENSE

DRAIN

UV DROPS BELOW V

UV CLEARS V

12 3456789ABCD

UVLO

GATEL

UVHI

UVLO

(VUV – V

UVHI (VUV

5µA

FOR THE LTC4253A). GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES

UVHST

FOR THE LTC4253A), CHECK OV CONDITION, RESET < 0.8V, GATE < V

20 • (V

ACL

20 • (VCB + VOS)

50µA

TMRH

20 • V

TMRL

+ VOS)

TIMER CLEARS V

200µA + 8 • I

50µA

TMRL

DRN

, CHECK GATE < V

5µA

VIN – V

GATEH

ACL

DRNCL

DRNL

, SENSE < VCB, SS < 20 • VOS AND TIMER < V

GATEL

, SENSE < VCB AND SS < 20 • V

GATEL

5µA

TMRL

PWRGD1

PWRGD2

PWRGD3

SQTIMER

EN2

EN3

INITIAL TIMING

GATE

START-UP

SQTMRH

5µA

SQTMRL

5µA

SQTMRH

SQTMRL

Figure 10. Undervoltage Timing (All Waveforms are Referenced to VEE)

4253 F10

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APPLICATIO S I FOR ATIO

TIMER

GATE

SENSE

OV OVERSHOOTS V

123456789

OVHI

GATEL

20 • (V

ACL

20 • (VCB + VOS)

20 • V

(VOV FOR THE LTC4253A). GATE AND SS ARE PULLED DOWN, PWRGD SIGNALS AND TIMER ARE UNAFFECTED

OVHI

OV DROPS BELOW V

OVLO

TMRH

200µA + 8 • I

50µA

+ VOS)

DRN

50µA

GATE

START-UP

OVLO

– V

VIN – V

ACL

FOR THE LTC4253A), CHECK GATE < V

OVHST

5µA

GATEH

5µA

, SENSE < VCB AND SS < 20 • V

GATEL

4253 F11

200µA + 8 • I

TIMER

GATE

SENSE

OUT

DRAIN

PWRGD1

Figure 11. Overvoltage Timing (All Waveforms are Referenced to VEE)

12 1 2 12 34

TMRH

DRN

CB FAULT CB FAULT CB FAULT CB FAULT

5µA

ACL

200µA + 8 • I

TIMER

GATE

SENSE

OUT

DRAIN

PWRGD1

TMRH

DRN

ACL

DRNCL

200µA + 8 • I

TIMER

GATE

SENSE

OUT

DRAIN

PWRGD1

TMRH

DRN

CB TIMES-OUTCB TIMES-OUT

5µA

DRNCL

ACL

4253 F12

(12a) Momentary Circuit Breaker Fault (12b) Circuit Breaker Time-Out (12c) Multiple Circuit Breaker Fault

Figure 12. Circuit Breaker Timing Behavior (All Waveforms are Referenced to VEE)

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APPLICATIO S I FOR ATIO

Resetting a Fault Latch

A latched circuit breaker fault of the LTC4253/LTC4253A has the benefit of a long cooling time. The latched fault can be reset by pulsing the RESET pin high until the TIMER pin is pulled below V the RESET pulse, SS and GATE ramp up without an initial timing cycle provided the interlock conditions are satisfied.

Alternative methods of reset include using an external switch to pulse the UV pin below V the LTC4253A) or the V the TIMER pin below V simultaneously releasing them also achieves a reset. An initial timing cycle is generated for reset by pulsing the UV pin or V

pin, while no initial timing cycle is generated for

reset by pulsing of the TIMER and SS pins.

Using Reset as an ON/OFF switch

The asynchronous RESET pin can be used as an ON/OFF function to cut off supply to the external power modules or loads controlled by the LTC4253/LTC4253A. Pulling RESET high will pull GATE, SS, TIMER and SQTIMER low and the PWRGD signal high. The supply is fully cut off if the RESET pulse is maintained wide enough to fully discharge the GATE and SS pins. As long as RESET is high, GATE, SS, TIMER and SQTIMER are strapped to V When RESET is released, if the LTC4253/LTC4253A are in UVLO, UV, OV or V interlock conditions are met before recovering as described in the Operation, Interlock Conditions section. If not, the GATE pin will ramp up in a soft start cycle without going through an initial cycle as in Figure 13c.

Analog Current Limit and Fast Current Limit

In Figure 14a, when SENSE exceeds V lated by the analog current limit amplifier loop. When SENSE drops below V Figure 14b, when a severe fault occurs, SENSE exceeds

and GATE immediately pulls down until the analog

FCL

current amplifier establishes control. If the severe fault causes V at V

DRNCL

to exceed V

OUT

. I

flows into the DRAIN pin and is multiplied

DRN

by 8. This extra current is added to the TIMER pull-up

(1V) as shown in Figure 13b. After

TMRL

(VUV – V

UVLO

pin below (V

and the SS pin to 0V then

TMRL

and the supply is cut off.

> VCB, turn-on is delayed until the

SENSE

, GATE is allowed to pull up. In

ACL

, the DRAIN pin is clamped

DRNCL

– V

LKO

LKH

, GATE is regu-

ACL

for

UVHST

). Pulling

current of 200µA. This accelerated TIMER current of (200µA+8•I delay. Careful selection of C

) produces a shorter circuit breaker fault

DRN

, RD and MOSFET helps

prevent SOA damage in a low impedance fault condition.

Soft-Start

f the SS pin is not connected, this pin defaults to a linear voltage ramp, from 0V to 2.2V in about 300µs (0V to 1.4V in about 200µs for the LTC4253A) at GATE start-up, as shown in Figure 15a. If a soft-start capacitor, CSS, is connected to this SS pin, the soft-start response is modified from a linear ramp to an RC response (Equation 6), as shown in Figure 15b. This feature allows load current to slowly ramp-up at GATE start-up. Soft-start is initiated at time point 3 by a TIMER transition from V (time points 1 and 2), by the OV pin falling below the V (VOV – V

for the LTC4253A) threshold after an OV

OVHST

TMRH

to V

TMRL OVLO

condition or by the RESET pin falling < 0.8V after a Reset condition. When the SS pin is below 0.2V, the analog current limit amplifier keeps GATE low. Above 0.2V, GATE is released and 50µA ramps up the compensation network and GATE capacitance at time point 4. Meanwhile, the SS pin voltage continues to ramp up. When GATE reaches the MOSFET’s threshold, the MOSFET begins to conduct. Due to the MOSFET’s high g reaches the soft-start control value of V

, the MOSFET current quickly

(t) (Equa-

ACL

tion 7). At time point 6, the GATE voltage is controlled by the current limit amplifier. The soft-start control voltage reaches the circuit breaker voltage, VCB at time point 7 and the circuit breaker TIMER activates. As the load capacitor nears full charge, load current begins to decline below V

(t). The current limit loop shuts off and GATE releases

ACL

at time point 8. At time point 9, SENSE voltage falls below V

and TIMER deactivates.

Large values of C time-out as V

ACL

can cause premature circuit breaker

(t) may marginally exceed the VCB potential during the circuit breaker delay. The load capacitor is unable to achieve full charge in one GATE start-up cycle. A more serious side effect of a large CSS value is that SOA duration may be exceeded during soft-start into a low impedance load. A soft-start voltage below V

will not

activate the circuit breaker TIMER.

425353afc

Page 28

LTC4253/LTC4253A

RESET PULSE

WIDTH MUST FULLY

DISCHARGE TIMER

123456789

LATCHED TIMER RESET BY

RESET PULLING HIGH

RESET < V

, CHECK UVLO, UV, OV CONDITION, GATE < V

GATEL

SENSE < V

, SS < 20 • V

AND TIMER < V

TMRL

TIMER

GATE

SENSE

RESET

DRAIN

PWRGD1

UV/OV

TMRH

ACL

TMRL

GATEL

LKO

UVHI

20 • (V

ACL

+ V

)

20 • (V

+ V

)

20 • V

5µA

50µA

5µA

50µA

DRNCL

DRNL

– V

GATEH

200µA + 8 • I

DRN

RESET PULSE

WIDTH MUST FULLY

DISCHARGE GATE AND SS

123456789

4253 F13

RESET < V

, CHECK UVLO, UV, OV CONDITION, V

SENSE

< V

TIMER

GATE

SENSE

RESET

DRAIN

PWRGD1

UV/OV

ACL

TMRL

GATEL

LKO

UVHI

20 • (V

ACL

+ V

)

20 • (V

+ V

)

20 • V

5µA

50µA

5µA

50µA

DRNCL

DRNL

– V

GATEH

200µA + 8 • I

DRN

123 4 5678

RESET < V

, CHECK UVLO, UV, OV CONDITION, GATE < V

GATEL

SENSE < V

, SS < 20 • V

AND TIMER < V

TMRL

TIMER

GATE

SENSE

RESET

DRAIN

PWRGD1

UV/OV

ACL

TMRL

GATEL

LKO

20 • (V

ACL

+ V

)

20 • (V

+ V

)

20 • V

5µA

50µA

5µA

50µA

DRNCL

DRNL

– V

GATEH

200µA + 8 • I

DRN

UVHI

WUU

APPLICATIO S I FOR ATIO

(13c) Reset as an ON/OFF Switch

)

(13b) Reset of the LTC4253/LTC4253A’s Latched Fault

Figure 13. Reset Functions (All Waveforms are Referenced to V

(13a) Reset Forcing Start-Up Without

Initial TIMER Cycle

425353afc

Page 29

LTC4253/LTC4253A

WUU

APPLICATIO S I FOR ATIO

TMRH

200µA + 8 • I

TIMER

GATE

SENSE

OUT

DRAIN

PWRGD1

DRN

5µA

ACL

200µA + 8 • I

TIMER

GATE

SENSE

OUT

DRNCL

DRAIN

PWRGD1

TMRH

1212 34

DRN

CB TIMES-OUT

FCL

ACL

4253 F14

(14a) Analog Current Limit Fault (14b) Fast Current Limit Fault

Figure 14. Current Limit Behavior (All Waveforms are Referenced to VEE)

END OF INITIAL TIMING CYCLE

12 34 5 6 7 7a 8 9 10 11

TMRH

TIMER

GATE

SENSE

DRAIN

GS(th)

20 • (V

ACL

TMRL

50µA

+ VOS)

20 • V

200µA + 8 • I

20 • (VCB + VOS)

DRN

50µA

ACL

DRNCL

5µA

DRNL

VIN – V

GATEH

END OF INITIAL TIMING CYCLE

12 3 4 5 6 7 8 9 10 11

TMRH

TIMER

GATE

SENSE

DRAIN

200µA + 8 • I

TMRL

GS(th)

50µA

20 • (V

20 • V

ACL

DRN

+ VOS)

50µA

5µA

50µA

20 • (VCB + VOS)

ACL

DRNCL

DRNL

VIN – V

GATEH

PWRGD1

(15a) Without External C

Figure 15. Soft-Start Timing (All Waveforms are Referenced to VEE)

PWRGD1

(15b) With External C

4253 F15

425353afc

Page 30

LTC4253/LTC4253A

WUU

APPLICATIO S I FOR ATIO

Power Limit Circuit Breaker

Figure 16 shows the LTC4253A in a power limit circuit breaking application. The SENSE pin is modulated by board voltage V

SUPPLY

to be the same as the lowest operating voltage, V

SUPPLY(MIN)

= 43V. If the goal is to have the high supply operating voltage, V power as available at V R4 are selected by:

RVV

SUPPLY MAX

–48V RTN (LONG PIN)

–48V RTN (SHORT PIN)

392k

RESET (LONG PIN)

30.1k 1%

–48V (LONG PIN)

. The zener voltage, VZ of D1, is set

SUPPLY(MAX)

()

C1 10nF

0.1µF

SUPPLY(MIN)

15k(1/4W)/6

33nF

= 71V give the same

, then resistors R3 and

OV UV RESET

0.68µF

2.5k

LTC4253A

BZV85C43

PWRGD1 PWRGD2 PWRGD3

EN3 EN2

DRAINSS

GATESQTIMER

SENSETIMER

1µF

31.6k

10nF

(16)

5.6k

††

22Ω

10Ω

If R4 is 22Ω, then R3 is 31.6k. The peak circuit breaker power limit is:

()

POWER MAX

when V

()

SUPPLY

()

SUPPLY MIN SUPPLY MAX

••

SUPPLY MIN SUPPLY MAX

POWER AT V

•

1 064

= 0.5 • (V

POWER AT V

.•

SUPPLY(MIN)

() ( )

SUPPLY MIN

()

SUPPLY MIN

+ V

SUPPLY(MAX)

= 57V

5.6k

Q1 IRF530S

0.02Ω

EN2

100µF

5.6k

†

0.1µF

†

POWER MODULE 1 OUTPUT

POWER

MODULE 1

EN3

†

MOC207

POWER

MODULE 2

POWER

MODULE 2

OUTPUT

4253 F16

POWER

MODULE 3

(17)

)

Figure 16. Power Limit Circuit Breaker Application

425353afc

Page 31

LTC4253/LTC4253A

WUU

APPLICATIO S I FOR ATIO

The peak power at the fault current limit occurs at the supply overvoltage threshold. The fault current limited power is:

POWER FAULT

()

SUPPLY

⎡

−−

VV V

•( )•

ACL SUPPLY Z

⎢ ⎣

⎤ ⎥

⎦

(18)

PACKAGE DESCRIPTIO

Circuit Breaker with Foldback Current Limit

Figure 17 shows the LTC4253A in a foldback current limit application. When V

is shorted to the –48V RTN

OUT

supply, current flows through resistors R3 and R4. This results in a voltage drop across R4 and a corresponding reduction in voltage drop across the sense resistor, R

, as the ACL amplifier servos the sense voltage between the SENSE and V current through R

pins to about 60mV. The short-circuit

reduces as the V

voltage increases

OUT

during an output short-circuit condition. Without foldback current limiting resistor R4, the current is limited to 3A during analog current limit. With R4, the short-circuit current is limited to 0.5A when V

is shorted to 71V.

OUT

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.045 ±.005

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.007 – .0098

(0.178 – 0.249)

.016 – .050

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

(0.406 – 1.270)

INCHES

(MILLIMETERS)

.150 – .165

.0250 BSC.0165 ± .0015

.015 ± .004

(0.38

0° – 8° TYP

± 0.10)

GN Package

(5.817 – 6.198)

× 45°

(0.203 – 0.305)

.229 – .244

.0532 – .0688

(1.35 – 1.75)

.008 – .012

TYP

.189 – .196*

(4.801 – 4.978)

12 11 10

678

.0250

(0.635)

BSC

.009

(0.229)

.150 – .157** (3.810 – 3.988)

.004 – .0098

(0.102 – 0.249)

GN16 (SSOP) 0204

REF

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

425353afc

Page 32

LTC4253/LTC4253A

TYPICAL APPLICATIO

10k

OV UV RESET

33nF

1µF

–48V RTN (LONG PIN)

–48V RTN (SHORT PIN)

392k

RESET (LONG PIN)

30.1k 1%

–48V (LONG PIN)

R8 47k

C1 10nF

0.1µF

20k(1/4W)/2

EN2 EN3

PWRGD1 PWRGD2 PWRGD3

LTC4253A

DRAIN

GATESQTIMER

SENSETIMER

†

Q1 IRF530S

0.02Ω

C2 100µF

0.1µF

POWER

MODULE 1

OUT

†

FMMT493

POWER

MODULE 2

POWER

MODULE 3

4253 F18

C 1µF

3.3M

R5 100k

†

38.3k

22Ω

10nF

100k

R7 100k

†

10Ω

Figure 17. –48V/2.5A Application with Foldback Current Limiting and Transistor Enabled Sequencing Without Feedback

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PART NUMBER DESCRIPTION COMMENTS

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Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

425353afc

LT 0506 REV C • PRINTED IN USA