Datasheet LTC4218 Datasheet (LINEAR TECHNOLOGY)

LTC4218

Hot Swap Controller

FEATURES

■

Wide Operating Voltage Range: 2.9V to 26.5V

■

Adjustable, 5% Accurate (15mV) Current Limit

■

Current Monitor Output

■

Adjustable Current Limit Timer Before Fault

■

Powergood and Fault Outputs

■

Adjustable Inrush Current Control

■

2% Accurate Undervoltage and Overvoltage

Protection

■

Available in 16-Lead SSOP and 16-Pin 5mm × 3mm

DFN Packages

APPLICATIONS

■

RAID Systems

■

ATCA, AMC, μTCA Systems

■

Server I/O Cards

■

Industrial

DESCRIPTION

The LTC®4218 is a Hot Swap™ controller that allows a board
to be safely inserted and removed from a live backplane.
An internal high side switch driver controls the gate of an
external N-channel MOSFET for supply voltages from 2.9V
to 26.5V. A dedicated 12V version (LTC4218-12) contains
preset 12V specifi c thresholds, while the standard LTC4218
allows adjustable thresholds.

The LTC4218 provides an accurate (5%) current limit with
current foldback limiting. The current limit threshold can
be adjusted dynamically using an external pin. Additional
features include a current monitor output that amplifi es
the sense voltage for ground referenced current sensing.
Overvoltage, undervoltage and powergood monitoring
are also provided.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.

TYPICAL APPLICATION

12V, 6A Card Resident Application

12V

2mΩ

AUTO

RETRY

0.1μF

0.1μF

Si7108DN

10Ω

SENSE–GATE

+

SENSE

V

DD

UV

LTC4218DHC-12

FLT

TIMER

INTV

CC

GND

SOURCE

I

MON

PG

12V

10k

20k

1k

0.01μF

Power-Up Waveform

V

OUT

12V
6A

+

330μF

ADC

4218 TA01a

V

10V/DIV

1A/DIV

V

OUT

10V/DIV

PG

10V/DIV

IN

I

IN

25ms/DIV

4218 TA01b

4218f

1

LTC4218

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

Supply Voltage (VDD) ................................. –0.3V to 35V

Input Voltages

FB, OV, UV ............................................. –0.3V to 12V

TIMER ................................................... –0.3V to 3.5V

–

SENSE

SENSE+ ............................. VDD – 10V or –0.3V to V

............................. VDD – 10V or –0.3V to V

DD
DD

SOURCE ........................................ – 5V to VDD + 0.3V

Output Voltages

, I

I

SET

PG,

................................................. –0.3V to 3V

MON

⎯F⎯L⎯

T .................................................. –0.3V to 35V

PIN CONFIGURATION

TOP VIEW

SENSE

SENSE

I

SET

I

MON

FB

FLT

PG

GATE

+

–

1

NC

2

V

DD

3

UV

4

OV

5

TIMER

6

INTV

CC

7

GND

SOURCE

8

16-LEAD (5mm × 3mm) PLASTIC DFN

EXPOSED PAD (PIN 17) IS SUBSTRATE GND

DHC PACKAGE

T

= 125°C, θJA = 43°C/W

JMAX

16

15

14

13

17

12

11

10

9

INTVCC .................................................. –0.3V to 3.5V

GATE (Note 3) ........................................ –0.3V to 35V

Operating Temperature Range

LTC4218C ................................................ 0°C to 70°C

LTC4218I ............................................. –40°C to 85°C

Storage Temperature Range

DHC Package ..................................... –65°C to 125°C

GN Package .......................................–65°C to 150°C

Lead Temperature (Soldering, 10 sec)

GN Package Only .............................................. 300°C

TOP VIEW

NC

V

DD

UV

OV

TIMER

INTV

CC

GND

SOURCE

16-LEAD PLASTIC SSOP

T

JMAX

1

2

3

4

5

6

7

8

GN PACKAGE

= 150°C, θJA = 135°C/W

16

15

14

13

12

11

10

9

SENSE

SENSE

I

SET

I

MON

FB

FLT

PG

GATE

+

–

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4218CDHC-12#PBF LTC4218CDHC-12#TRPBF 421812 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C

LTC4218IDHC-12#PBF LTC4218IDHC-12#TRPBF 421812 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C

LTC4218CGN#PBF LTC4218CGN#TRPBF 4218 16-Lead Plastic SSOP 0°C to 70°C

LTC4218IGN#PBF LTC4218IGN#TRPBF 4218 16-Lead Plastic SSOP –40°C to 85°C

Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

4218f

2

LTC4218

ELECTRICAL CHARACTERISTICS

The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DC Characteristics

V

DD

I

DD

V

DD(UVL)

V

DD(UVTH)

ΔV

DD(UVHYST)

V

DD(OVTH)

ΔV

DD(OVHYST)

V

SOURCE(PGTH)

ΔV

SOURCE(PGHYST)

ΔV

SNS(TH)

I

SENSE–(IN)

I

SENSE+(IN)

ΔV

GATE

ΔV

GATE-HIGH(TH)

I

GATE(UP)

I

GATE(FST)

I

GATE(DN)

Inputs

I

(IN)

R

(IN)

V

(TH)

ΔV

OV(HYST)

ΔV

UV(HYST)

V

UV(RTH)

ΔV

FB(HYST)

R

ISET

I

SOURCE

Outputs

V

(OL)

I

(OH)

V

TIMER(H)

V

TIMER(L)

I

TIMER(UP)

I

TIMER(DN)

Input Supply Range

Input Supply Current FET On

Input Supply Undervoltage Lockout VDD Rising

Input Supply Undervoltage Threshold LTC4218-12 Only VDD Rising

Input Supply Undervoltage Hysteresis LTC4218-12 Only

Input Supply Overvoltage Threshold LTC4218-12 Only VDD Rising

Input Supply Overvoltage Hysteresis LTC4218-12 Only

SOURCE Powergood Threshold LTC4218-12 Only V

SOURCE Powergood Hysteresis LTC4218-12 Only

Current Limit Sense Voltage Threshold
(V

SENSE+

– V

SENSE–

)

SENSE– Pin Input Current V

SENSE+ Pin Input Current V

External N-Channel Gate Drive
(V

– V

GATE

Gate High Threshold (V

SOURCE

)

– V

GATE

SOURCE

External N-Channel Gate Pull-Up Current Gate Drive On, V

External N-Channel Gate Fast Pulldown
Current

External N-Channel Gate Pulldown Current Gate Drive Off, V

OV, UV, FB Pin Input Current VIN = 1.2V, LTC4218 Only

OV, UV, FB Pin Input Resistance LTC4218-12 Only

OV, UV, FB Pin Threshold Voltage VIN Rising

OV Pin Hysteresis

UV Pin Hysteresis

UV Pin Reset Threshold Voltage VUV Falling

FB Pin Power Good Hysteresis

I

Pin Output Resistor

SET

SOURCE Pin Input Current V

PG, ⎯F⎯L⎯T Pin Output Low Voltage I

PG, ⎯F⎯L⎯T Pin Input Leakage Current V

TIMER Pin High Threshold V

TIMER Pin Low Threshold V

TIMER Pin Pull Up Current V

TIMER Pin Pulldown Current V

= 25°C. VDD = 12V unless otherwise noted.

A

Rising

SOURCE

= 1.23V

V

FB

V

= 0V

FB

V

= 1.23V, R

FB

= 12V

SENSE–

= 12V

SENSE+

= 2.9V to 26.5V (Note 3)

V

DD

I

= 0, –1μA

GATE

SET

= 20kΩ

)

Fast Turn Off, V
V

=12V

SOURCE

V

=12V

SOURCE

= V

SOURCE

V

SOURCE

V

SOURCE

OUT

OUT

TIMER

TIMER

TIMER

TIMER

= V
= V

= 2mA

= 30V

Rising

Falling

= 0V

= 1.2V

GATE
GATE
GATE

= V

GATE

= 18V,

GATE

= 18V,

GATE

= 12V, LTC4218-12 Only
= 12V, LTC4218 Only
= 0V

SOURCE

= 12V

●

2.9 26.5 V

●

●

2.65 2.73 2.85 V

●

9.6 9.88 10.2 V

●

580 650 700 mV

●

14.7 15.05 15.4 V

●

230 270 300 mV

●

10.2 10.5 10.8 V

●

150 175 200 mV

●

14.25

●

2.8

●

6.7

●

●

●

5 6.15 6.5 V

●

3.5 4.2 4.8 V

●

–19 –24 –29 μA

●

120 170 220 mA

●

200 250 340 μA

●

●

13 18 23 kΩ

●

1.21 1.235 1.26 V

●

10 20 30 mV

●

50 80 110 mV

●

0.55 0.62 0.7 V

●

10 20 30 mV

●

19.5 20 20.5 kΩ

●

50

●

1

●

●

●

●

1.2 1.235 1.28 V

●

0.1 0.21 0.3 V

●

–80 –100 –120 μA

●

1.4 2 2.6 μA

1.6 5 mA

15

15.75

3.75

7.5

8.325

4 ±10 μA

5.5 ±20 μA

0±1 μA

70

2
0

0.4 0.8 V

0 ±10 μA

4.7

90

4

±1

mV
mV
mV

μA
μA
μA

4218f

3

LTC4218

ELECTRICAL CHARACTERISTICS

The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

TIMER(RATIO)

I

MON(FS)

I

MON(OFF)

G

IMON

AC Characteristics

t

PHL(GATE)

t

PHL(SENSE)

t

D(ON)

TIMER Pin Current Ratio I
I

TIMER(UP)

I

Fullscale Output Current V

MON

I

Pin Offset Current V

MON

I

Pin Gain V

MON

TIMER(DN)

Input High (OV), Input Low (UV) to GATE
Low Propagation Delay

V

SENSE

+

– V

–

High to GATE Low

SENSE

Propagation Delay

Turn-On Delay Step VUV to 2V, V

= 25°C. VDD = 12V unless otherwise noted.

A

/

+

– V

SENSE

+

– V

SENSE

+

– V

SENSE

V

< 16.5V Falling

GATE

VFB = 0, Step (V
60mV, C

GATE

–

= 15mV

SENSE

–

= 1mV

SENSE

–

= 15mV and 1mV

SENSE

+

SENSE

= 1.5nF, V

– V

GATE

SENSE

< 16.5V

Falling

> 13V

GATE

–

) to

●

1.6 2 2.7 %

●

94 100 106 μA

●

●

6.47 6.67 6.87 μA/mV

●

●

●

50 100 150 ms

±0 ±6 μA

35 μs

0.2 1 μs

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specifi ed.

Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V above
the SOURCE pin. Driving either GATE or SOURCE pin to voltages beyond
the clamp may damage the device.

4

4218f

LTC4218

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

1.8

1.6

(mA)

DD

I

1.4

1.2

1.0

IDD vs V

0

DD

85°C

25°C

–40°C

5101520

VDD (V)

UV Hysteresis vs Temperature

0.10

25 30

4218 G01

INTVCC Load Regulation

3.5

3.0

2.5

2.0

(V)

CC

1.5

INTV

1.0

0.5

0

0

I

LOAD

VDD = 3.3V

(mA)

Timer Pull-Up Current vs
Temperature Current Limit Delay

–110

T

= 25°C, VDD = 12V unless otherwise noted.

A

UV Low-High Threshold vs
Temperature

1.234

VDD = 5V

1.232

1.230

1.228

UV LOW-HIGH HRESHOLD (V)

–14–12–10–8–6–4–2

4218 G02

1.226

1000

–50

–25 0 25

C

= 10nF

GATE

TEMPERATURE (°C)

50 75 100

4218 G03

–105

0.08

–100

0.06

UV HYSTERESIS (V)

0.04
–50

–25 0 25

TEMPERATURE (°C)

50 75 100

4218 G04

–95

TIMER PULL-UP CURRENT (μA)

–90

–25 0 25

–50

TEMPERATURE (°C)

50 75 100

4218 G05

Current Limit Threshold Foldback Current Limit Adjustment I

16

14

12

) (mV)

–

10

SENSE

8

– V

+

6

SENSE

4

(V

CURRENT LIMIT SENSE VOLTAGE

2

0

0.2 0.4 0.6 0.8

0

FB VOLTAGE (V)

1.0 1.2

4218 G07

16

14

12

10

) (mV)

8

SENSE

– V

6

DD

(V

4

CURRENT LIMIT SENSE VOLTAGE

2

0

1k

10k 100k 1M

R

SET

(Ω)

4218 G08

10M

100

10

1

CURRENT LIMIT PROPAGATION DELAY (μs)

(kΩ)

ISET

R

0.1

22

21

20

19

18

15 30 45 60

075

CURRENT LIMIT SENSE VOLTAGE

Resistor vs Temperature

SET

–50

–25 0 25

+

– V

(V

SENSE

SENSE

TEMPERATURE (°C)

–

) (mV)

50 75 100

4218 G06

4218 G09

4218f

5

LTC4218

TYPICAL PERFORMANCE CHARACTERISTICS

GATE Pull-Up Current vs
Temperature

–26.0

–25.5

–25.0

PULL-UP (μA)

GATE

I

–24.5

–24.0

–50

–25 0 25

TEMPERATURE (°C)

50 75 100

4218 G10

Gate Drive vs Temperature PG, ⎯F⎯L⎯T V

6.15

) (V)

6.14

SOURCE

6.13

– V

GATE

6.12

6.11

GATE DRIVE (V

Gate Pull-Up Current vs
Gate Drive Gate Drive vs V

7

6

) (V)

5

SOURCE

4

– V

GATE

3

2

1

GATE DRIVE (V

0

0

14

12

10

8

LOW (V)

OUT

6

4

PG, FLT V

2

–5 –10 –15 –20

OUT

VDD = 12V

VDD = 3.3V

I

(μA)

GATE

Low vs I

PG

LOAD

FLT

TA = 25°C, VDD = 12V unless otherwise noted.

SENSE

DD

VDD (V)

–

= 15mV

20 25 30

–25 –30

4218 G11

6.2

) (V)

6.0

SOURCE

5.8

– V

GATE

5.6

5.4

GATE DRIVE (V

5.2
0

vs Temperature and V

I

MON

105

VDD = 3.3V, 12V, 24V
V

SENSE

100

95

(μA)

MON

I

90

85

51015

+

– V

4218 G12

DD

6

6.10
–50

–25 0 25

TEMPERATURE (°C)

100

75

(μA)

50

MON

I

25

0

50 75 100

I

vs Sense V

MON

0

4218 G13

510

SENSE VOLTAGE (mV)

0

0

2468

15

4218 G16

I

LOAD

(mA)

10 12

4218 G14

4

3

(V)

2

IMON

V

1

0

0

IMON

vs Sense

80

–50

–25 0 25

TEMPERATURE (°C)

R

IMON

R

IMON

R

= 20k

IMON

R

IMON

510

SENSE VOLTAGE (mV)

50 75 100

4218 G15

= 100k

= 40k

= 10k

15

4218 G17

4218f

PIN FUNCTIONS

LTC4218

Exposed Pad: Exposed pad may be left open or connected
to device ground.

FB: Foldback and Power Good Comparator Input. Connect
this pin to an external resistive divider from SOURCE for
the LTC4218 (adjustable version). The LTC4218-12 ver­sion uses a fi xed internal divider with optional external
adjustment. Open the pin if the LTC4218-12 thresholds
for 12V operation are desired. If the voltage falls below

0.6V, the output power is considered bad and the current
limit is reduced. If the voltage falls below 1.21V the PG
pin will pull low to indicate the power is bad.

⎯F⎯L⎯

T: Overcurrent Fault Indicator. Open drain output pulls

low when an overcurrent fault has occurred and the circuit
breaker trips. For overcurrent auto-retry tie to UV pin (see
Applications Information for details).

GATE: Gate Drive for External N-Channel FET. An internal
24μA current source charges the gate of the external
N-channel MOSFET. A resistor and capacitor network
from this pin to ground sets the turn-on rate. During an
undervoltage or overvoltage generated turn-off a 250μA
pulldown current turns the MOSFET off. During a short
circuit or undervoltage lockout, a 170mA pulldown current
source between GATE and SOURCE is activated.

GND: Device Ground.

OV: Overvoltage Comparator Input. Connect this pin to

an external resistive divider from VDD for the LTC4218
(adjustable version). The LTC4218-12 version uses a fi xed
internal divider with optional external adjustment for 12V
operation. Open the pin if the LTC4218-12 thresholds are
desired. If the voltage at this pin rises above 1.235V, an
overvoltage is detected and the switch turns off. Tie to
GND if unused.

PG: Power Good Indicator. Open drain output pulls low
when the FB pin drops below 1.21V indicating the power
is bad.

SENSE–: Current Sense Minus Input. Connect this pin to
the opposite of VDD current sense resistor side. The cur­rent limit circuit controls the GATE pin to limit the sense
voltage between the SENSE+ and SENSE– pins to 15mV
or less depending on the voltage at the FB pin.

SENSE+: Current Sense Plus Input. Connect this pin to
the VDD side of the current sense resistor.

SOURCE: N-Channel MOSFET Source Connection. Connect
this pin to the source of the external N-channel MOSFET
switch. This pin provides a return for the gate pulldown
circuit. In the LTC4218-12 version, the powergood com­parator monitors an internal resistive divider between the
SOURCE pin and GND.

I

: Current Monitor Output. The current sourced from

MON

this pin is defi ned as the current sense voltage (between
the SENSE+ and SENSE– pins) multiplied by 6.67μA/mV.
Placing a 20k resistor from this pin to GND creates a 0V to
2V voltage swing when the current sense voltage ranges
from 0mV to 15mV.

INTVCC: Internal 3V Supply Decoupling Output. This pin
must have a 0.1μF or larger capacitor.

I

: Current Limit Adjustment Pin. For 15mV current limit

SET

threshold, open this pin. This pin is driven by a 20k resis­tor in series with a voltage source. The pin voltage is used
to generate the current limit threshold. The internal 20k
resistor and an external resistor between I
create an attenuator that lowers the current limit value.

NC: No Connection

and ground

SET

TIMER: Timer Input. Connect a capacitor between this pin
and ground to set a 12ms/μF duration for current limit
before the switch is turned off. If the UV pin is toggled
low while the MOSFET switch is off, the switch will turn on
again following a cool down time of 518ms/μF duration.

UV: Undervoltage Comparator Input. Tie high if unused.
Connect this pin to an external resistive divider from VDD
for the LTC4218 (adjustable version). The LTC4218-12
version drives the UV pin with an internal resistive divider
from VDD. Open the pin if the preset LTC4218-12 thresh­olds for 12V operation are desired. If the UV pin voltage
falls below 1.15V, an undervoltage is detected and the
switch turns off. Pulling this pin below 0.62V resets the
overcurrent fault and allows the switch to turn back on
(see Applications Information for details). If overcurrent
auto-retry is desired then tie this pin to the ⎯F⎯L⎯T pin.

VDD: Supply Voltage. This pin has an undervoltage lockout
threshold of 2.73V.

4218f

7

LTC4218

FUNCTIONAL DIAGRAM

+

SENSE

V

DD

+–

V

DD

UV

OV

140k

20k

224k

20k

1.235V

*

*

0.62V

V

DD

*

*

1.235V

+

–

+

–

+

–

SENSE

UV

RST

OV

–

–

CS

+

CM

0.2V

GATE SOURCE

CHARGE

PUMP

AND GATE

DRIVER

+

TM1

–

LOGIC

100μA

2μA

INTV

CC

REFERENCE

FOLDBACK

PG

CLAMP

0.6V

I

MON

I

SET

20k

X1

FB

0.6V

SOURCE

150k

20k

*

*

PG

FLT

+

–

1.235V

+

V

DD

3.1V
GEN

INTV

CC

–

V

2.73V

TM2

–

DD

UVLO1

1.235V

–

+

8

TIMER

* DFN ONLY

GND

EXPOSED PAD*

UVLO2

+

2.65V

4218 BD

4218f

OPERATION

LTC4218

The Functional Diagram displays the main circuits of the
device. The LTC4218 is designed to turn a board’s sup­ply voltage on and off in a controlled manner, allowing
the board to be safely inserted and removed from a live
backplane. During normal operation, the charge pump and
gate driver turn on the external N-channel pass FET’s gate
to provide power to the load.

The current sense (CS) amplifi er monitors the load current
using the voltage sensed across the current sense resistor.
The CS amplifi er limits the current in the load by reducing
the GATE-to-SOURCE voltage in an active control loop. It
is simple to adjust the current limit threshold using the
current setting (I
during other times such as startup.

A short circuit on the output to ground causes signifi cant
power dissipation during active current limiting. To limit
this power, the foldback amplifi er reduces the current limit
value from 15mV to 3.75mV (referred to the SENSE
SENSE
below 0.6V (see Typical Performance Characteristics).

If an overcurrent condition persists, the TIMER pin ramps
up with a 100μA current source until the pin voltage exceeds

1.2V (comparator TM2). This indicates to the logic that it
is time to turn off the MOSFET to prevent overheating. At
this point the TIMER pin ramps down using the 2μA current
source until the voltage drops below 0.2V (Comparator
TM1) which tells the logic to start an internal 100ms timer.

–

voltage) in a linear manner as the FB pin drops

) pin. This allows a different threshold

SET

+

minus

At this point, the pass transistor has cooled and it is safe
to turn it on again.

The fi xed 12V version, LTC4218-12, uses two separate
internal dividers from V
This version also features a divider from the SOURCE pin
to drive the FB pin. The LTC4218-12 is available in a DFN
package while the LTC4218 (adjustable version) is in a
SSOP package.

The output voltage is monitored using the FB pin and the
PG comparator to determine if the power is available for
the load. The power good condition is signaled by the PG
pin using an open-drain pulldown transistor.

The Functional Diagram shows the monitoring blocks of
the LTC4218. The comparators on the left side include
the UV and OV comparators. These comparators are used
to determine if the external conditions are valid prior to
turning on the MOSFET. But fi rst, the undervoltage lockout
circuits (UVLO1 and UVLO2) must validate the input supply
and internally generated 3.1V supply (INTV
ate the power up initialization to the logic circuits. If the
external conditions remain valid for 100ms the MOSFET
is allowed to turn on.

Other monitoring features include the I
The current monitor (CM) outputs a current proportional to
the sense resistor current. This current can drive an external
resistor or other circuits for monitoring purposes.

to drive the UV and OV pins.

DD

) and gener-

CC

current monitor.

MON

4218f

9

LTC4218

APPLICATIONS INFORMATION

The typical LTC4218 application is in a high availability
system that uses a positive voltage supply to distribute
power to individual cards. The basic application circuit
is shown in Figure 1. External component selection is
discussed in detail in the following sections.

R

Q1

S

2mΩ

12V

0.1μF

Si7108DN

R1

10Ω

R

I

I

MON

GATE

1k

C

GATE

0.01μF

R6

12V

R8

10k

R

20k

R

20k

SET

MON

150k

20k

R7

FB

PG

SET

–

GATE SOURCESENSE

+

SENSE

V

DD

R4
140k

R2

224k

R3

20k

C

T

0.1μF

UV

FLT

LTC4218GN

OV

R5
20k

TIMER

INTV

CC

C1

GND

V

OUT

12V
3A

+

C

L

330μF

ADC

4218 F01

Figure 1. 3A, 12V Card Resident Application

Turn-On Sequence

The power supply on a board is controlled by placing
an external N-channel pass transistor (Q1) in the power
path. Note the sense resistor (R
the capacitor (C

) controls gate slew rate. Resistor R1

GATE

) detects current and

S

prevents high frequency oscillations in Q1 and resistor
R

GATE

isolates C

during fast turn-off.

GATE

Several conditions must be present before the external
pass transistor can be turned on. First, the supply V

DD

must exceed its undervoltage lockout level. Next, the
internally generated supply INTV

must cross its 2.65V

CC

undervoltage threshold. This generates a 25μs power­on-reset pulse which clears the logic’s fault register and
initializes internal latches.

After the power-on-reset pulse, the LTC4218 will go through
the following sequence. First, the UV and OV pins must
indicate that the input power is within the acceptable range.
All of these conditions must be satisfi ed for a duration
of 100ms to ensure that any contact bounce during the
insertion has ended.

The pass transistor is turned on by charging up the GATE
with a 24μA charge pump generated current source
(Figure 2).

VDD + 6.15

V

SLOPE = 24μA/C

DD

Figure 2. Supply Turn-On

GATE

t1 t2

GATE

SOURCE

4218 F02

The voltage at the GATE pin rises with a slope equal to
24μA/C

I

INRUSH

and the supply inrush current is set at:

GATE

C

L

= •24

C

GATE

µA

When the GATE voltage reaches the MOSFET threshold
voltage, the switch begins to turn on and the SOURCE
voltage follows the GATE voltage as it increases. Once
SOURCE reaches V

, the GATE will ramp up until clamped

DD

by the 6.15V zener between GATE and SOURCE.

As the SOURCE pin voltage rises, so will the FB pin which
is monitoring it. If the voltage across the current sense
resistor (R

) gets too high, the inrush current will be limited

S

by the internal current limiting circuitry. Once the FB pin
crosses its 1.235V threshold and the GATE to SOURCE
voltage exceeds 4.2V, the PG pin will cease to pull low and
indicate that the power is good.

Turn-Off Sequence

The switch can be turned off by a variety of conditions. A
normal turn-off is initiated by the UV pin going below its

1.235V threshold. Additionally, several fault conditions will
turn off the switch. These include an input overvoltage (OV
pin) and overcurrent circuit breaker (SENSE pin). Normally,
the switch is turned off with a 250μA current pulling down
the GATE pin to ground. With the switch turned off, the
SOURCE pin voltage drops which pulls the FB pin below

10

4218f

APPLICATIONS INFORMATION

LTC4218

its threshold. The PG then pulls low to indicate output
power is no longer good.

drops below 2.65V for greater than 5μs or INTVCC

If V

DD

drops below 2.5V for greater than 1μs, a fast shutdown
of the switch is initiated. The GATE is pulled down with a
170mA current to the SOURCE pin.

Overcurrent Fault

The LTC4218 features an adjustable current limit with
foldback that protects the MOSFET when excessive load
current happens. To protect the switch during active cur­rent limit, the available current is reduced as a function
of the output voltage sensed by the FB pin. A graph in the
Typical Performance Characteristics shows the current
limit versus FB voltage.

An overcurrent fault occurs when the current limit circuitry
has been engaged for longer than the time-out delay set by
the TIMER. Current limiting begins when the current sense

+

voltage between the SENSE

and SENSE– pins reaches

3.75mV to 15mV (depending on the foldback). The GATE
pin is then brought down with a 170mA GATE-to-SOURCE
current. The voltage on the GATE is regulated in order to
limit the current sense voltage to less than 15mV. At this
point, a circuit breaker time delay starts by charging the
external timing capacitor from the TIMER pin with a 100μA
pull-up current. If the TIMER pin reaches its 1.2V thresh­old, the external switch turns off (with a 250μA current

⎯F⎯L⎯

from GATE to ground). Next, the

T pin is pulled low to
indicate an overcurrent fault has turned off the MOSFET.
For a given the circuit breaker time delay, the equation for
setting the timing capacitor’s value is as follows:

= TCB • 0.083[μF/ms]

C

T

After the switch is turned off, the TIMER pin begins dis­charging the timing capacitor with a 2μA pulldown current.
When the TIMER pin reaches its 0.2V threshold, the switch
is allowed to turn on again if the overcurrent fault has been
cleared. Bringing the UV pin below 0.6V and then high will
clear the fault. If the TIMER pin is tied to INTV

, then the

CC

switch is allowed to turn on again (after an internal 100ms
delay) if the overcurrent fault is cleared.

⎯F⎯L⎯

Tying the

T pin to the UV pin allows the part to self-clear
the fault and turn the MOSFET on as soon as TIMER pin has
ramped below 0.2V. In this auto retry mode, the LTC4218
repeatedly tries to turn on after an overcurrent at a period
determined by the capacitor on the TIMER pin.

The waveform in Figure 3 shows how the output latches
off following a short circuit. The drop across the sense
resistor is 3.75mV as the timer ramps up.

V

OUT

10V/DIV

I

OUT

2A/DIV

ΔV

GATE

10V/DIV

TIMER
2V/DIV

1ms/DIV

Figure 3. Short-Circuit Waveform

4218 F03

Current Limit Adjustment

The default value of the active current limiting signal
threshold is 15mV. The current limit threshold can be
adjusted lower by placing a resistor on the I
shown in the Functional Diagram the voltage at the I

pin. As

SET

SET

pin (via the clamp circuit) sets the CS amplifi er’s built-in
offset voltage. This offset voltage directly determines the
active current limit value. With the I
age at the I

pin is determined by the buffered reference

SET

pin open, the volt-

SET

voltage. This voltage is set to 0.618V which corresponds
to a 15mV current limit threshold.

An external resistor placed between the I

pin and ground

SET

forms a resistive divider with the internal 20k sourcing
resistor. The divider acts to lower the voltage at the I

SET

pin and therefore lower the current limit threshold. The
overall current limit threshold precision is reduced to ±11%
when using a 20k resistor to half the threshold.

4218f

11

LTC4218

APPLICATIONS INFORMATION

Using a switch (connected to ground) in series with the
external resistor allows the active current limit to change
only when the switch is closed. This feature can be used
when the startup current exceeds the typical maximum
load current.

Monitor MOSFET Current

The current in the MOSFET passes through the sense
resistor. The voltage on the sense resistor is converted to
a current that is sourced out of the I
the I

amplifi er is 100μA from I

SENSE

pin. The gain of

MON

for 15mV on the

MON

sense resistor. This output current can be converted to a
voltage using an external resistor to drive a comparator
or ADC. The voltage compliance for the I
0V to INTV

– 0.7V.

CC

pin is from

MON

A microcontroller with a built-in comparator can build a
simple integrating single-slope ADC by resetting a capaci­tor that is charged with this current. When the capacitor
voltage trips the comparator and the capacitor is reset, a
timer is started. The time between resets will indicate the
MOSFET current.

Monitor OV and UV Faults

Protecting the load from an overvoltage condition is the
main function of the OV pin. In the LTC4218-12 an internal
resistive divider (driving the OV pin) connects to a compara­tor to turn off the MOSFET when the V

15.05V. If the V

pin subsequently falls back below 14.8V,

DD

voltage exceeds

DD

the switch will be allowed to turn on immediately. In the
LTC4218, the OV pin threshold is 1.23V when rising and

1.21V when falling out of overvoltage.

The UV pin functions as an undervoltage protection pin or
as an “on” pin. In the LTC4218-12 the MOSFET turns off
when V

falls below 9.23V. If the VDD pin subsequently

DD

rises above 9.88V for 100ms, the switch will be allowed
to turn on again. The LTC4218 UV turn on/off threshold
is 1.23V (rising) and 1.15V (falling).

In the case of an undervoltage or overvoltage, the MOSFET
turns off and there is indication on the PG status pin. When
the overvoltage is removed, the MOSFET’s gate ramps up
immediately.

Powergood Indication

In addition to setting the foldback current limit threshold,
the FB pin is used to determine a powergood condition.
The LTC4218-12 uses an internal resistive divider on
the SOURCE pin to drive the FB pin. The PG comparator
indicates logic high when SOURCE pin rises above 10.5V.
If the V

pin subsequently falls below 10.3V, the com-

DD

parator toggles low. On the LTC4218 the PG comparator
drives high when the FB pin rises above 1.23V and low
when falls below 1.21V.

Once the PG comparator is high, the GATE pin voltage
is monitored with respect to the SOURCE pin. Once the
GATE minus SOURCE voltage exceeds 4.2V, the PG pin
goes high. This indicates to the system that it is safe to
load the Output while the MOSFET is completely turned
“on”. The PG pin goes low when the GATE is commanded

+

off (using the UV, OV or SENSE

/SENSE– pins) or when

the PG comparator drives low.

12V Fixed Version

In the LTC4218-12, the UV, OV and FB pins are driven by
internal dividers which may need to be fi ltered to prevent
false faults. By placing a bypass capacitor on these pins
the faults are delayed by the RC time constant. Use the R

IN

value from the electrical table for this calculation.

In cases where the fi xed thresholds need a slight adjust­ment, placing a resistor from the UV or OV pins to V

DD

or GND will adjust the threshold up or down. Likewise,
placing a resistor between FB pin to OUT or GND adjusts
the threshold. Again, use the R

value from the electrical

IN

table for this calculation.

An example in Figure 4 raises the UV turn-on voltage from

9.88V to 10.5V. Increasing the UV level requires adding a
resistor between UV and ground. The resistor, (R

SHUNT1

),
can be calculated using electrical table parameters as
follows:

RV

•

OLD

IN

()

R

SHUNT

=

1

VV

()

–

NEW OLD

18 9 88

k

=

•.

10 5

()

.–

9988

.

287

= k

12

4218f

APPLICATIONS INFORMATION

LTC4218-12

Figure 4. Adjusting LTC4218-12 Thresholds

In this same fi gure the OV threshold is lowered from

15.05V to 13.5V. Decreasing the OV threshold requires
adding a resistor between V
be calculated as follows:

V

DD

R

SHUNT2

OV

UV

R

SHUNT1

4218 F04

and OV. This resistor can

DD

12V

LTC4218

R

S

2mΩQ1Si7108DN

R1

10Ω

R

R2
10k

R3
20k

GATE

1k

SENSE–GATE

SENSE

V

DD

UV

LTC4218DHC-12

FLT

C

0.1μF

0.1μF

Figure 5. 6A, 12V Card Resident Application

TIMER

T

INTV

CC

C1

SOURCE

+

12V

PG

I

MON

GND

+

C

GATE

0.01μF

ADC

V

12V
6A

C

L

330μF

4218 F05

OUT

RV

•

IN

R

SHUNT

k

18 15 05

1 235

•.

.

()

=

2

V

TH

()

⎛

13 5 1 235

.–.

()

⎜

115 05 13 5

.–.

()

⎝

Use the equation for R

⎛

()

OLD

⎜
⎜

⎜

⎝

SHUNT1

–

VV

NEW

VV

()

OLD

–

OV TH

NNEW

⎞

1 736

.

= M

⎟
⎠

for increasing the OV and

FB thresholds. Likewise, use the equation for R

⎞

()

⎟

=
⎟
⎟

⎠

SHUNT2

for

decreasing the UV and FB thresholds.

Design Example

Consider the following design example (Figure 5): V
12V, I
V

OVOFF

= 7.5A. I

MAX

= 15.05V, V

INRUSH

= 1A, CL = 330μF, V

= 10.5V. A current limit fault

PWRGD

UVON

=

IN

= 9.88V,

triggers an automatic restart of the power up sequence.

The selection of the sense resistor, (R

), is set by the

S

overcurrent threshold of 15mV:

R

S

= 15mV/I

= 15mV/7.5A = 0.002Ω

MAX

The MOSFET should be sized to handle the power dissi­pation during the inrush charging of the output capacitor

. The method used to determine the power in Q1 is

C

OUT

the principal:

= Energy in CL = Energy in Q1

E

C

Thus:

= ½ CV2 = ½ (330μF)(12)2 = 0.048J

E

C

Calculate the time it takes to charge up C

CV

t

CHARGUP

•

LIN

== =

I

INRUSH

•330 12

µF V

1

A

The inrush current is set to 1A using C

CC

==≅

GATE L

I

GATE UP

I

INRUSH

()

µF

24

1

µA
A

OUT

4

GATE

001

ms

:

.330

:

µF

The average power dissipated in the MOSFET:

P

DISS

= EC/t

CHARGUP

= 0.048J/4ms = 12W

The SOA (safe operating area) curves of candidate MOSFETs
must be evaluated to ensure that the heat capacity of the
package can stand 12W for 4ms. The SOA curves of the
Vishay Siliconix Si7108DN provide 1.5A at 10V (15W) for
100ms, satisfying the requirement.

Next, the power dissipated in the MOSFET during overcurrent
must be limited. The active current limit uses a timer to
prevent excessive energy dissipation in the MOSFET. The
worst-case power occurs when the voltage versus current
profi le of the foldback current limit is at the maximum. This
occurs when the current is 6A and the voltage is one half
of 12V or (6V). See the Current Limit Sense Voltage vs
FB Voltage in the Typical Performance curves to view this
profi le. In order to survive 36W, the MOSFET SOA dictates
a maximum time at this power level. The Si7108DN allows
60W for 10ms or less. Therefore, it is acceptable to set the
current limit timeout using C

to be 1.2ms:

T

= 1.2ms/12[ms/μF] = 0.1μF

C

T

4218f

13

LTC4218

APPLICATIONS INFORMATION

After the 1.2ms timeout the ⎯F⎯L⎯T pin needs to pull down
on the UV pin to restart the power-up sequence.

Since the default values for overvoltage, undervoltage and
powergood thresholds for the 12V fi xed version match
the requirements, no external components are required
for the UV, OV and FB pins.

The fi nal schematic results in very few external com­ponents. Resistor R1 (10Ω) prevents high frequency
oscillations in Q1 while R

of 1k isolates C

GATE

GATE

during
fast turn-off. The pull-up resistor, (R2), connects to the
PG pin while the 20k (R3) converts the I

current to a

MON

voltage at a ratio:

µAmVmV

V

IMON

667 2

==

••

20

k

A

V

0 267.

.

A

In addition, there is a 0.1μF bypass (C1) on the INTVCC
pin.

Layout Considerations

To achieve accurate current sensing, a Kelvin connection
for the sense resistor is recommended. The PCB layout
should be balanced and symmetrical to minimize wiring
errors. In addition, the PCB layout for the sense resistors
and the power MOSFETs should include good thermal
management techniques for optimal device power dissipa­tion. A recommended PCB layout for the sense resistor
and power MOSFET is illustrated in Figure 6.

In Hot Swap applications where load currents can be 6A,
narrow PCB tracks exhibit more resistances than wider
tracks and operate at elevated temperatures. The minimum
trace width for 1oz copper foil is 0.02” per amp to make sure
the trace stays at a reasonable temperature. Using 0.03”
per amp or wider is recommended. Note that 1oz copper
exhibits a sheet resistance of about 0.5mΩ/square. Small
resistances add up quickly in high current applications

It is also important to put C1, the bypass capacitor for the
INTV

pin, as close as possible between the INTVCC and

CC

GND. Place the 10Ω resistor as close as possible to Q1.
This will limit the parasitic trace capacitance that leads to
Q1 self-oscillation.

Additional Applications

The LTC4218 has a wide operating range from 2.9V to

26.5V. The UV, OV and PG thresholds are set with a few
resistors. All other functions are independent of supply
voltage.

The last page includes a 24V application with a UV threshold
of 19.8V, an OV threshold of 28.3V and a PG threshold
of 20.75V. Figure 7 shows a 3.3V application with a UV
threshold of 2.87V, an OV threshold of 3.77V and a PG
threshold of 3.05V.

14

R

S

LTC4218

C

Q1

R1

Figure 6. Recommended Layout

4218 F06

3.3V

R

Q1

S

2mΩ

Si7104DN

3.3V

R7
10k

R
20k

R
1k

MON

14.7k

GATE

C

GATE

0.01μF

R5

17.4k

3.16k

10k

R1

10Ω

+

LTC4218GN

CC

GND

SOURCE

I

FB

PG

OUT

SENSE–GATE

C

T

0.1μF

C1

SENSE

V

DD

UV

FLT

OV

TIMER

INTV

R2

R3

R4

0.1μF

Figure 7. 3.3V, 6A Card Resident Application

R6
10k

ADC

V

OUT

3.3V
6A

+

C

L

330μF

4218 F07

4218f

PACKAGE DESCRIPTION

LTC4218

DHC Package

16-Lead Plastic DFN (5mm × 3mm)

(Reference LTC DWG # 05-08-1706)

3.50 ±0.05

2.20 ±0.05

0.65 ±0.05

1.65 ±0.05

(2 SIDES)

0.25 ± 0.05

0.50 BSC

4.40 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

PACKAGE
OUTLINE

TOP MARK

(SEE NOTE 6)

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.045 ±.005

5.00 ±0.10

(2 SIDES)

PIN 1

0.200 REF

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

3.00 ±0.10

(2 SIDES)

0.75 ±0.05

R = 0.20

1.65 ± 0.10

(2 SIDES)

0.00 – 0.05

TYP

GN Package

.189 – .196*

(4.801 – 4.978)

16

15

14

13

12 11 10

9

4.40 ±0.10

(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

.009

(0.229)

REF

R = 0.115

TYP

0.25 ± 0.05

0.50 BSC

169

18

0.40 ± 0.10

PIN 1
NOTCH

(DHC16) DFN 1103

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.007 – .0098

(0.178 – 0.249)

.016 – .050

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

(0.406 – 1.270)

(MILLIMETERS)

INCHES

.150 – .165

.0250 BSC.0165 ±.0015

.015

(0.38 ± 0.10)

0° – 8° TYP

± .004

× 45°

.229 – .244

(5.817 – 6.198)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

12

.150 – .157**

(3.810 – 3.988)

5

4

678

3

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

GN16 (SSOP) 0204

BSC

4218f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LTC4218

TYPICAL APPLICATION

24V, 6A Card Resident Application

+

ADC

V

OUT

24V
6A

330μF

4218 TA02

24V

*DIODES INC., SMAJ24A

215k

4.32k

10k

*

0.1μF

0.1μF

2mΩ

SENSE–GATE

SENSE

V

DD

UV

FLT

OV

TIMER

INTV

CC

Si7880ADP

10Ω

+

LTC4218GN

GND

SOURCE

I

MON

PG

158k

1k

0.01μF

FB

10k

24V

10k

20k

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I

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16

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

4218f

LT 0108 • PRINTED IN USA

© LINEAR TECHNOLOGY CORPORATION 2007