Datasheet LTC4210-2IS6, LTC4210-2CS6, LTC4210-1IS6, LTC4210-1CS6 Datasheet (Linear Technology)
Page 1
FEATURES
LTC4210-1/LTC4210-2
Hot Swap Controller in
6-Lead SOT-23 Package
U
DESCRIPTIO
■
Allows Safe Board Insertion and Removal
from a Live Backplane
■
Adjustable Analog Current Limit
with Circuit Breaker
■
Fast Response Limits Peak Fault Current
■
Automatic Retry or Latch Off On Current Fault
■
Adjustable Supply Voltage Power-Up Rate
■
High Side Drive for External MOSFET Switch
■
Controls Supply Voltages from 2.7V to 16.5V
■
Undervoltage Lockout
■
Adjustable Overvoltage Protection
■
Low Profile (1mm) SOT-23 (ThinSOTTM) Package
U
APPLICATIO S
■
Hot Board Insertion
■
Electronic Circuit Breaker
■
Industrial High Side Switch/Circuit Breaker
U
TYPICAL APPLICATIO
The LTC®4210 is a 6-pin SOT-23 Hot SwapTM controller
that allows a board to be safely inserted and removed from
a live backplane. An internal high side switch driver
controls the GATE of an external N-channel MOSFET for a
supply voltage ranging from 2.7V to 16.5V. The LTC4210
provides the initial timing cycle and allows the GATE to be
ramped up at an adjustable rate.
The LTC4210 features a fast current limit loop providing
active current limiting together with a circuit breaker
timer. The signal at the ON pin turns the part on and off and
is also used for the reset function.
This part is available in two options: the LTC4210-1 for
automatic retry on overcurrent fault and the LTC4210-2
for latch off on an overcurrent fault.
, LTC and LT are registered trademarks of Linear Technology Corporation.
ThinSOT and Hot Swap are trademarks of Linear Technology Corporation.
V
GND
IN
5V
BACKPLANE
CONNECTOR
(FEMALE)
Single Channel 5V Hot Swap Controller
PCB EDGE
CONNECTOR
(MALE)
LONG
R
R
10k
ON2
10Ω
X
C
X
0.1µF
Z1
OPTIONAL
R
ON1
SHORT
LONG
Z1: ISMA10A OR SMAJ10A
20k
R
0.01Ω
VCCSENSE
LTC4210
ON
TIMER
C
TIMER
0.22µF
SENSE
GND
GATE
Q1
Si4410DY
R
100Ω
R
100Ω
+
G
C
C
C
0.01µF
470µF
C
LOAD
4210 TA01
V
OUT
5V
4A
GND
Power-Up Sequence
C
= 470µF
LOAD
10ms/DIV
4210 TA02
V
ON
(2V/DIV)
V
TIMER
(1V/DIV)
V
OUT
(5V/DIV)
I
OUT
(0.5A/DIV)
421012f
1
Page 2
LTC4210-1/LTC4210-2
PACKAGE/ORDER I FOR ATIO
UU
W
WWWU
ABSOLUTE AXI U RATI GS
(Note 1)
Supply Voltage (VCC) ............................................... 17V
Input Voltage (SENSE, TIMER) .. –0.3V to (VCC + 0.3V)
Input Voltage (ON)..................................... –0.3V to 17V
Output Voltage (GATE) ........ Internally Limited (Note 3)
Operating Temperature Range
LTC4210-1C/LTC4210-2C ....................... 0°C to 70°C
LTC4210-1I/LTC4210-2I .................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
ORDER PART
NUMBER
TOP VIEW
TIMER 1
GND 2
ON 3
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
T
= 125°C, θJA = 230°C/ W
JMAX
6 V
CC
5 SENSE
4 GATE
LTC4210-1CS6
LTC4210-2CS6
LTC4210-1IS6
LTC4210-2IS6
S6 PART MARKING
LTYW
LTYX
LTF5
LTF6
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
I
CC
V
LKOR
V
LKOHYST
I
INON
I
INSENSE
V
CB
I
GATEUP
I
GATEDN
∆V
GATE
I
TIMERUP
I
TIMERDN
V
TIMER
V
TMRHYST
V
ON
V
ONHYST
Supply Voltage ● 2.7 16.5 V
VCC Supply Current ● 0.65 3.5 mA
VCC Undervoltage Lockout Release VCC Rising ● 2.2 2.5 2.65 V
VCC Undervoltage Lockout Hysteresis 100 mV
ON Pin Input Current ● –10 0 10 µA
SENSE Pin Input Current V
Circuit Breaker Trip Voltage VCB = (VCC – V
GATE Pin Pull-Up Current V
GATE Pin Pull-Down Current V
External N-Channel Gate Drive V
TIMER Pin Pull-Up Current Initial Cycle, V
TIMER Pin Pull-Down Current After Current Fault Disappears, V
TIMER Pin Threshold High Threshold, TIMER Rising ● 1.22 1.3 1.38 V
TIMER Low Threshold Hysteresis 100 mV
ON Pin Threshold ON Threshold, ON Rising ● 1.22 1.3 1.38 V
ON Pin Threshold Hysteresis 80 mV
= V
SENSE
GATE
TIMER
V
ON
VCC – V
GATE
V
GATE
V
GATE
V
GATE
V
GATE
V
GATE
During Current Fault Condition, V
Under Normal Conditions, V
Low Threshold, TIMER Falling
CC
) ● 44 50 56 mV
SENSE
= 0V ● –5 –10 –15 µA
= 1.5V, V
= 0V, V
GATE
SENSE
– VCC, VCC = 2.7V ● 4.0 6.5 8 V
– VCC, VCC = 3V ● 4.5 7.5 10 V
– VCC, VCC = 3.3V ● 5.0 8.5 12 V
– VCC, VCC = 5V ● 10 12 16 V
– VCC, VCC = 12V ● 9.0 12 16 V
– VCC, VCC = 15V ● 6.0 11 18 V
= 3V or 25 mA
GATE
= 3V or
= 100mV, V
= 1V ● –2 –5 –8.5 µA
TIMER
= 3V
GATE
TIMER
TIMER
= 1V 100 µA
TIMER
● –10 5 10 µA
= 1V ● –25 –60 –100 µA
= 1V ● 2 3.5 µA
● 0.15 0.2 0.25 V
2
421012f
Page 3
LTC4210-1/LTC4210-2
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
OFF(TMRHIGH)
t
OFF(ONLOW)
t
OFF(VCCLOW)
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Turn-Off Time (TIMER Rise to GATE Fall) V
= 0V to 2V Step, VCC = VON = 5V 1 µs
TIMER
Turn-Off Time (ON Fall to GATE Fall) VON = 5V to 0V Step, VCC = 5V 30 µs
Turn-Off Time (VCC Fall to IC Reset) VCC = 5V to 2V Step, VON = 5V 30 µs
Note 3: An internal Zener on the GATE pin clamps the charge pump
voltage to a typical maximum voltage of 26V. External overdrive of the
GATE pin beyond the internal Zener voltage may damage the device.
Without a limiting resistor, the GATE capacitance must be <0.15µF at
maximum V
. If a lower GATE pin clamp voltage is desired, an external
CC
Zener diode may be used.
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Undervoltage Lockout Threshold
Supply Current vs Supply Voltage Supply Current vs Temperature
4.0
TA = 25°C
3.5
3.0
2.5
2.0
1.5
SUPPLY CURRENT (mA)
1.0
0.5
0
42 6 10 14 18
0
SUPPLY VOLTAGE (V)
12
16
8
20
4210 G01 4210 G02 4210 G03
4.0
3.5
3.0
2.5
2.0
1.5
SUPPLY CURRENT (mA)
1.0
0.5
0
–75
0 25 50 75 100 125
–25–50
TEMPERATURE (°C)
VCC = 15V
VCC = 12V
VCC = 5V
VCC = 3V
150
vs Temperature
2.65
2.60
2.55
2.50
2.45
2.40
2.35
2.30
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
2.25
–75
VCC RISING
VCC FALLING
0 25 50 75 100 125
–25–50
TEMPERATURE (°C)
150
(V)
GATE
V
40
35
30
25
20
15
10
5
0
V
vs Supply Voltage V
GATE
TA = 25°C
42 6 10 14 18
0
SUPPLY VOLTAGE (V)
12
16
8
20
4210 G04 4210 G05 4210 G06
(V)
GATE
V
vs Temperature
GATE
40
35
30
25
20
15
10
5
0
–75
0 25 50 75 100 125
–25–50
TEMPERATURE (°C)
VCC = 15V
VCC = 12V
VCC = 5V
VCC = 3V
150
–8.0
–8.5
–9.0
–9.5
(µA)
–10.0
GATEUP
I
–10.5
–11.0
–11.5
–12.0
I
vs Supply Voltage
GATEUP
TA = 25°C
42 6 10 14 18
0
8
SUPPLY VOLTAGE (V)
12
16
20
421012f
3
Page 4
LTC4210-1/LTC4210-2
UW
TYPICAL PERFOR A CE CHARACTERISTICS
∆V
vs Supply Voltage
GATE
TA = 25°C
42 6 10 14 18
0
8
SUPPLY VOLTAGE (V)
12
16
–8.0
–8.5
–9.0
–9.5
(µA)
–10.0
GATEUP
I
–10.5
–11.0
–11.5
–12.0
I
GATEUP
–75
vs Temperature
VCC = 3V
VCC = 15V
0 25 50 75 100 125
–25–50
TEMPERATURE (°C)
VCC = 12V
VCC = 5V
4210 G07
150
(V)
GATE
∆V
18
16
14
12
10
8
6
4
2
4210 G08
∆V
vs Temperature
GATE
18
16
14
12
(V)
10
GATE
∆V
8
6
4
2
20
–75 150
0 25 50 75 100 125
–25–50
TEMPERATURE (°C)
VCC = 5V
VCC = 12V
VCC = 15V
VCC = 3V
4210 G09
I
(In Initial Cycle)
TIMERUP
vs Supply Voltage
0
TA = 25°C
–1
–2
–3
–4
(µA)
–5
–6
TIMERUP
I
–7
–8
–9
–10
42 6 10 14 18
0
I
TIMERUP
8
SUPPLY VOLTAGE (V)
(During Circuit Breaker
12
16
Delay) vs Temperature
–20
VCC = 5V
–30
–40
–50
(µA)
–60
TIMERUP
I
–70
–80
–90
–100
–75 150
0 25 50 75 100 125
–25–50
TEMPERATURE (°C)
I
vs Temperature
0
–1
–2
–3
–4
(µA)
–5
–6
TIMERUP
I
–7
–8
–9
–10
20
4210 G10 4210 G11 4210 G12
–75 150
I
vs Supply Voltage
3.0
2.8
2.6
2.4
2.2
(µA)
2.0
1.8
TIMERDN
I
1.6
1.4
1.2
1.0
0
4210 G13
(In Initial Cycle)
TIMERUP
VCC = 5V
0 25 50 75 100 125
–25–50
TEMPERATURE (°C)
(In Cool-Off Cycle)
TIMERDN
TA = 25°C
42 6 10 14 18
8
SUPPLY VOLTAGE (V)
I
(During Circuit Breaker
TIMERUP
Delay) vs Supply Voltage
–20
TA = 25°C
–30
–40
–50
(µA)
–60
TIMERUP
I
–70
–80
–90
–100
42 6 10 14 18
0
I
TIMERDN
8
SUPPLY VOLTAGE (V)
(In Cool-Off Cycle)
12
16
vs Temperature
3.0
VCC = 5V
2.8
2.6
2.4
2.2
(µA)
2.0
1.8
TIMERDN
I
1.6
1.4
1.2
1.0
12
16
20
4210 G14
–75 150
0 25 50 75 100 125
–25–50
TEMPERATURE (°C)
4210 G15
20
4
421012f
Page 5
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC4210-1/LTC4210-2
TIMER High Threshold
vs Supply Voltage
1.38
TA = 25°C
1.36
1.34
1.32
1.30
1.28
1.26
TIMER HIGH THRESHOLD (V)
1.24
1.22
42 6 10 14 18
0
8
SUPPLY VOLTAGE (V)
12
16
20
4210 G16
TIMER Low Threshold
vs Temperature
0.24
VCC = 5V VCC = 5V
0.23
0.22
0.21
0.20
0.19
0.18
TIMER LOW THRESHOLD (V)
0.17
0.16
–75 150
0 25 50 75 100 125
–25–50
TEMPERATURE (°C)
4210 G19
TIMER High Threshold
vs Temperature
1.38
VCC = 5V
1.36
1.34
1.32
1.30
1.28
1.26
TIMER HIGH THRESHOLD (V)
1.24
1.22
–75 150
0 25 50 75 100 125
–25–50
TEMPERATURE (°C)
ON Pin Threshold
vs Supply Voltage
1.45
TA = 25°C
1.40
1.35
1.30
1.25
1.20
ON PIN THRESHOLD (V)
1.15
1.10
1.05
0
HIGH THRESHOLD
LOW THRESHOLD
42 6 10 14 18
SUPPLY VOLTAGE (V)
12
8
4210 G17
16
20
4210 G20
TIMER Low Threshold
vs Supply Voltage
0.24
TA = 25°C
0.23
0.22
0.21
0.20
0.19
0.18
TIMER LOW THRESHOLD (V)
0.17
0.16
42 6 10 14 18
0
8
SUPPLY VOLTAGE (V)
12
ON Pin Threshold
vs Temperature
1.45
1.40
1.35
1.30
1.25
1.20
ON PIN THRESHOLD (V)
1.15
1.10
1.05
–75 150
HIGH THRESHOLD
LOW THRESHOLD
0 25 50 75 100 125
–25–50
TEMPERATURE (°C)
16
20
4210 G18
4210 G21
t
OFF(ONLOW)
80
TA = 25°C
70
60
50
(µs)
40
30
OFF,ONLOW
t
20
10
0
016
vs Supply Voltage
42 6 10 14 18
SUPPLY VOLTAGE (V)
12
8
20
4210 G22
t
OFF(ONLOW)
80
70
60
50
(µs)
40
30
OFF,ONLOW
t
20
10
0
–75 150
vs Temperature
0 25 50 75 100 125
–25–50
TEMPERATURE (°C)
VCC = 15V
VCC = 12V
VCC = 5V
VCC = 3V
4210 G23
421012f
5
Page 6
LTC4210-1/LTC4210-2
UW
TYPICAL PERFOR A CE CHARACTERISTICS
VCB vs Supply Voltage
58
TA = 25°C
56
54
52
(mV)
50
CB
V
48
46
44
42
U
42 6 10 14 18
0
8
SUPPLY VOLTAGE (V)
UU
12
16
20
4210 G24
PI FU CTIO S
TIMER (Pin 1): Timer Input Pin. An external capacitor
C
µF circuit breaker delay. The GATE pin turns off whenever
the TIMER pin is pulled beyond the COMP2 threshold,
such as for overvoltage detection with an external zener.
GND (Pin 2): Ground Pin.
ON (Pin 3): ON Input Pin. The ON pin comparator has a
low-to-high threshold of 1.3V with 80mV hysteresis and a
glitch filter. When the ON pin is low, the LTC4210 is reset.
When the ON pin goes high, the GATE turns on after the
initial timing cycle.
GATE (Pin 4): GATE Output Pin. This pin is the high side
gate drive of an external N-channel MOSFET. An internal
charge pump provides a 10µA pull-up current with Zener
clamps to VCC and ground. In overload, the error amplifier
sets a 272.9ms/µF initial timing delay and a 21.7ms/
TIMER
VCB vs Temperature
58
VCC = 5V
56
54
52
(mV)
50
CB
V
48
46
44
42
–75 150
0 25 50 75 100 125
–25–50
TEMPERATURE (°C)
4210 G25
(EA) controls the external MOSFET to maintain a constant
load current. An external R-C compensation network
should be connected to this pin for current limit loop
stability.
SENSE (Pin 5): Current Limit Sense Input Pin. A sense
resistor between the VCC and SENSE pins sets the analog
current limit. In overload, the EA controls the external
MOSFET gate to maintain the SENSE pin voltage at 50mV
below VCC. When the EA is maintaining current limit, the
TIMER circuit breaker mode is activated. The current limit
loop/circuit breaker mode can be disabled by connecting
the SENSE pin to the VCC pin.
VCC (Pin 6): Positive Supply Input Pin. The operating
supply voltage range is between 2.7V to 16.5V. An undervoltage lockout (UVLO) circuit with a glitch filter resets the
LTC4210 when a low supply voltage is detected.
6
421012f
Page 7
BLOCK DIAGRA
LTC4210-1/LTC4210-2
W
1
2
TIMER
GND
5µA
INITIAL UP/LATCH OFF
60µA
0.2V
+
–
+
1.3V
–
INITIAL DOWN/NORMAL
100µA2µA
CURRENT LIMIT
COMP1
COMP2
LOGIC
6
V
UVLO
GLITCH
FILTER
GLITCH
FILTER
5
+
50mV
–
+
EA
SHUTDOWN
SENSE
CHARGE
PUMP
M5
10µA
Z2
26V
Z1
12V
GATE
4
CC
–
COOL OFF
–
1.3V
COMP3
+
ON
3
4210 BD
421012f
7
Page 8
LTC4210-1/LTC4210-2
WUUU
APPLICATIO S I FOR ATIO
Hot Circuit Insertion
When circuit boards are inserted into live backplanes, the
supply bypass capacitors can draw large transient currents from the backplane power bus as they charge. Such
transient currents can cause permanent damage to connector pins, glitches on the system supply or reset other
boards in the system.
The LTC4210 is designed to turn a printed circuit board’s
supply voltage ON and OFF in a controlled manner, allowing the circuit board to be safely inserted into or removed
from a live backplane. The LTC4210 can reside either on
the backplane or on the daughter board for hot circuit
insertion applications.
Overview
The LTC4210 is designed to operate over a range of
supplies from 2.7V to 16.5V. Upon insertion, an undervoltage lockout circuit determines if sufficient supply voltage
is present. When the ON pin goes high an initial timing
cycle assures that the board is fully seated in the backplane
before the MOSFET is turned on. A single timer capacitor
sets the periods for all of the timer functions. After the
initial timing cycle the LTC4210 can either start up in
current limit or with a lower load current. Once the external
MOSFET is fully enhanced and the supply has ramped up,
the LTC4210 monitors the load current through an external sense resistor. Overcurrent faults are actively limited
to 50mV/R
The LTC4210-1 will automatically retry after a current limit
fault while the LTC4210-2 latches off. The LTC4210-1
timer function limits the retry duty cycle to 3.8% for
MOSFET cooling.
Undervoltage Lockout
An internal undervoltage lockout (UVLO) circuit resets the
LTC4210 if the VCC supply is too low for normal operation.
for a specified circuit breaker timer limit.
SENSE
The UVLO has a low-to-high threshold of 2.5V, a 100mV
hysteresis and a high-to-low glitch filter of 30µs. Above
2.5V supply voltage, the LTC4210 will start if the ON pin
conditions are met. A short supply dip below 2.4V for less
than 30µs is ignored to allow for bus supply transients.
ON Function
The ON pin is the input to a comparator which has a lowto-high threshold of 1.3V, an 80mV hysteresis and a highto-low glitch filter of 30µs. A low input on the ON pin resets
the LTC4210 TIMER status and turns off the external
MOSFET by pulling the GATE pin to ground. A low-to-high
transition on the ON pin starts an initial cycle followed by
a start-up cycle. A 10k pull-up resistor connecting the ON
pin to the supply is recommended. The 10k resistor shunts
any potential static charge on the backplane and reduces
the overvoltage stress at the ON pin during live insertion.
Alternatively, an external resistor divider at the ON pin can
be used to program an undervoltage lockout value higher
than the internal UVLO circuit. An RC filter can be added at
the ON pin to increase the delay time at card insertion if the
internal glitch filter delay is insufficient.
GATE Function
During hot insertion of the PCB, an abrupt application of
supply voltage charges the external MOSFET drain/gate
capacitance. This can cause an unwanted gate voltage
spike. An internal proprietary circuit holds GATE low
before the internal circuitry wakes up. This reduces the
MOSFET current surges substantially at insertion. The
GATE pin is held low in reset mode and during the initial
timing cycle. In the start-up cycle the GATE pin is pulled up
by a 10µA current source. During an overcurrent fault
condition, the error amplifier servoes the GATE pin to
maintain a constant current to the load until the circuit
breaker trips. When the circuit breaker trips, the GATE pin
shuts down abruptly.
8
421012f
Page 9
SENSE RESISTOR
CURRENT FLOW
TO LOAD
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
W
TO
V
CC
TO
SENSE
4210 F01
CURRENT FLOW
TO LOAD
WUUU
APPLICATIO S I FOR ATIO
Current Limit Circuit Breaker Function
The LTC4210 features a current limiting circuit breaker
instead of a traditional comparator circuit breaker. When
there is a sudden load current surge, such as a low
impedance fault, the bus supply voltage can drop significantly to a point where the power to an adjacent card is
affected, causing system malfunctions. The LTC4210 fast
response error amplifier (EA) instantly limits current by
reducing the external MOSFET GATE pin voltage. This
minimizes the bus supply voltage drop and permits power
budgeting and fault isolation without affecting neighboring cards. A compensation circuit should be connected to
the GATE pin for current limit loop stability.
LTC4210-1/LTC4210-2
Figure 1. Making PCB Connections to the Sense Resistor
Calculating Current Limit
Sense Resistor Consideration
The nominal fault current limit is determined by a sense
resistor connected between VCC and the SENSE pin as
given by Equation 1.
I
LIMIT NOM
()
V
CB NOM
==
()
R
SENSE NOM SENSE NOM
() ()
mV
50
R
(1)
The power rating of the sense resistor should be rated at
the fault current level. Table 2 in the Appendix lists some
common sense resistors.
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4210
VCC and SENSE pins are strongly recommended. The
drawing in Figure 1 illustrates the connections between
the LTC4210 and the sense resistor. PCB layout should be
balanced and symmetrical to minimize wiring errors. In
addition, the PCB layout for the sense resistor should
include good thermal management techniques for optimal
sense resistor power dissipation.
For a selected R
, the nominal load current is given by
SENSE
Equation 1. The minimum load current is given by
Equation 2:
I
LIMIT MIN
()
V
CB MIN
==
()
R
SENSE MAX SENSE MAX
() ()
mV
44
R
(2)
where
R
RR
SENSE MAX SENSE
()
•=+
1
TOL
100
The maximum load current is given by Equation 3:
I
LIMIT MAX
()
V
CB MAX
==
()
R
SENSE MIN SENSE MIN
() ()
mV
56
R
(3)
where
R
RR
SENSE MIN SENSE
()
•–=
1
TOL
100
421012f
9
Page 10
LTC4210-1/LTC4210-2
WUUU
APPLICATIO S I FOR ATIO
If a 7mΩ sense resistor with ±1% tolerance is used for
current limiting, the nominal current limit is 7.14A. From
Equations 2 and 3, I
LIMIT(MIN)
= 6.22A and I
LIMIT(MAX)
=
8.08A. For proper operation, the minimum current limit
must exceed the circuit maximum operating load current
with margin. The sense resistor power rating must exceed
V
CB(MAX)
2
/R
SENSE(MIN)
.
Frequency Compensation
A compensation circuit should be connected to the GATE
pin for current limit loop stability.
Method 1
The simplest frequency compensation network consists
of RC and CC (Figure 2a). The total GATE capacitance is:
C
GATE
= C
ISS
+ C
C
(4)
Generally, the compensation value in Figure 2a is sufficient for a pair of input wires less than a foot in length.
Applications with longer input wires may require the RC or
CC value to be increased for better fault transient performance. For a pair of three foot input wires, users can start
with CC = 47nF and RC = 100Ω. Despite the wire length, the
general rule for AC stability required is CC ≥ 8nF and RC ≤
1kΩ.
Method 2
The compensation network in Figure 2b is similar to the
circuitry used in method 1 but with an additional gate resistor RG. The RG resistor helps to minimize high frequency
parasitic oscillations frequently associated with the power
MOSFET. In some applications, the user may find that R
G
helps in short-circuit transient recovery as well. However,
too large of an RG value will slow down the turn-off time.
The recommended RG range is between 5Ω and 500Ω.
Usually, method 2 is preferred when the input supply voltage is greater than 10V. RG limits the current flow into the
GATE pin’s internal zener clamp during transient events.
The recommended RC and CC values are the same as
method 1. The parasitic compensation capacitor CP is
required when 0.2µF < load capacitance CL < 9µF, other-
wise it is optional.
Parasitic MOSFET Oscillation
There are two possible parasitic oscillations when the
MOSFET operates as a source follower when ramping at
power-up or during current limiting. The first type of oscillation occurs at high frequencies, typically above 1MHz.
This high frequency oscillation is easily damped with RG as
mentioned in method 2.
The second type of oscillation occurs at frequencies between 200kHz and 800kHz due to the load capacitance
being between 0.2µF and 9µF, the presence of RG and R
C
resistance, the absence of a drain bypass capacitor, a combination of bus wiring inductance and bus supply output
impedance. There are several ways to prevent this second
type of oscillation. The simplest way is to avoid load capacitance below 10µF, the second choice is connecting an
external CP > 1.5nF.
10
V
5V
IN
V
R
SENSE
0.007ΩQ1Si4410DY
65
SENSE
CC
LTC4210*
GATE
4
(2a)
Method 1
R
C
100Ω
C
10nF
V
OUT
+
C
L
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
IF 0.2µF < CL < 9µF,
**USE C
P
OTHERWISE NOT REQUIRED
C
Figure 2. Frequency Compensation
V
12V
IN
V
R
SENSE
0.007Ω
65
SENSE
CC
LTC4210*
GATE
(2b)
Method 2
Q1
Si4410DY
R
200Ω
4
R
100Ω
G
C
C
C
10nF
4210 F02
**
C
P
2.2nF
V
OUT
+
C
L
421012f
Page 11
WUUU
APPLICATIO S I FOR ATIO
LTC4210-1/LTC4210-2
Whichever method of compensation is used, board level
short-circuit testing is highly recommended as board
layout can affect transient performance. Beside frequency
compensation, the total gate capacitance C
determines the GATE start-up as in Equation 6. The C
GATE
also
GATE
should be kept below 0.15µF at high supply operation as
the capacitive energy ( 0.5 • C
GATE
• V
2
) is discharged
GATE
by the LTC4210 internal pull-down transistor. This prevents the internal pull-down transistor from overheating
when the GATE turns off and /or is servoing during current
limiting.
Timer Function
The TIMER pin handles several key functions with an
external capacitor, C
. There are two comparator
TIMER
thresholds: COMP1 (0.2V) and COMP2 (1.3V). The four
timing current sources are:
5µA pull-up
60µA pull-up
2µA pull-down
100µA pull-down
The 100µA is a nonideal current source approximating a
7k resistor below 0.4V.
ends. The 100µA current source then pulls down the
TIMER pin until it reaches 0.2V at time point 4. The initial
cycle delay (time point 2 to time point 4) is related to
C
by equation:
TIMER
t
INITIAL
≈ 272.9 • C
ms/µF (5)
TIMER
When the initial cycle terminates, a start-up cycle is
activated and the GATE pin ramps high. The TIMER pin
continues to be pulled down towards ground.
1
2345 6 7
>2.5V
V
IN
>1.3V
V
ON
COMP2
V
V
TIMER
GATE
V
OUT
RESET
MODE
5µA
INITIAL
CYCLE
100µA
COMP1
10µA
V
TH
START-UP
CYCLE
DISCHARGE
BY LOAD
4210 F03
NORMAL
CYCLE
Initial Timing Cycle
When the card is being inserted into the bus connector, the
long pins mate first which brings up the supply VIN at time
point 1 of Figure 3. The LTC4210 is in reset mode as the
ON pin is low. GATE is pulled low and the TIMER pin is
pulled low with a 100µA source. At time point 2, the short
pin makes contact and ON is pulled high. At this instant, a
start-up check requires that the supply voltage be above
UVLO, the ON pin be above 1.3V and the TIMER pin voltage
be less than 0.2V. When these three conditions are fulfilled, the initial cycle begins and the TIMER pin is pulled
high with 5µA. At time point 3, the TIMER reaches the
COMP2 threshold and the first portion of the initial cycle
Figure 3. Normal Operating Sequence
Start-Up Cycle Without Current Limit
The GATE is released with a 10µA pull-up at time point 4
of Figure 3. At time point 5, GATE reaches the external
MOSFET threshold VTH and V
ramp up. If the R
current is below the current limit,
SENSE
starts to follow the GATE
OUT
the GATE ramps at a constant rate of:
∆
V
GATE GATE
∆
where C
T
I
=
C
GATE
is the total capacitance at the GATE pin.
GATE
(6)
421012f
11
Page 12
LTC4210-1/LTC4210-2
tC
V
I
C
V
I
C
V
I
C
V
II
STARTUP GATE
TH
GATE
LOAD
IN
CLOAD
GATE
TH
GATE
LOAD
IN
RSENSE LOAD
=+
=+
••
••
–
WUUU
APPLICATIO S I FOR ATIO
The current through R
components; I
(C
LOAD
) and I
LOAD
due to the total load capacitance
CLOAD
due to the noncapacitive load elements.
can be divided into two
SENSE
The capacitive load typically dominates.
For a successful start-up without current limit, I
I
:
LIMIT
I
RSENSE
IC
RSENSE LOAD
= I
=
CLOAD
+ I
LOAD
V
∆
∆
< I
OUT
T
LIMIT
II
+<•
LOAD LIMIT
Due to the voltage follower configuration, the V
rate approximately tracks V
∆
V
OUT CLOAD
∆
I
=≈
T
C
LOAD
At time point 6, V
∆
V
is approximately VIN but GATE ramp-
OUT
:
GATE
GATE GATE
∆
T
I
=
C
GATE
RSENSE
OUT
<
(7)
ramp
(8)
up continues until it reaches a maximum voltage. This
maximum voltage is determined either by the charge
pump or the internal clamp.
V
TIMER
V
GATE
V
I
RSENSE
V
OUT
12 345 5A5B6 7
>2.5V
V
IN
>1.3V
ON
RESET
MODE
5µA
INITIAL
CYCLE
COMP2
100µA
COMP1
10µA
V
TH
REGULATED AT 50mV/R
START-UP
CYCLE
60µA
<10µA
2µA
10µA
SENSE
NORMAL
CYCLE
100µA
DISCHARGE
BY LOAD
4210 F04
Start-Up Cycle With Current Limit
If the duration of the current limit is brief during start-up
(Figure 4) and it did not last beyond the circuit breaker
function time out, the GATE behaves the same as in startup without current limit except for the time interval between time point 5A and time point 5B. The servo amplifier
limits I
RSENSE
II
RSENSE LIMIT
by decreasing the I
mV
==
50
R
SENSE
current (<10µA).
GATE
(9)
Equations 8 and 9 are applicable but with a lower GATE and
V
ramp rate.
OUT
Gate Start-Up Time
The start-up time without current limit is given by:
VV
+
tC
STARTUP GATE
tC
STARTUP GATE
=
=+
TH IN
•
I
GATE
V
TH
••
I
GATE
C
GATE
V
I
GATE
IN
(10)
Figure 4. Operating Sequence with
Current Limiting at Start-Up Cycle
During current limiting, the second term in Equation 10 is
partly modified from C
VIN/I
. The start-up time is now given by:
CLOAD
GATE
• VIN/I
GATE
to C
LOAD
•
(11)
For successful completion of current limit start-up cycle
there must be a net current to charge C
current limit duration must be less than t
and the
LOAD
CBDELAY
. The
second term in equation 11 has to fulfill equation 12.
V
C
LOAD
•
II
RSENSE LOAD
IN
t
<
–
CBDELAY
(12)
12
421012f
Page 13
WUUU
APPLICATIO S I FOR ATIO
LTC4210-1/LTC4210-2
Circuit Breaker Timer Operation
When a current limit fault is encountered at time point A in
Figure 5, the circuit breaker timing is activated with a 60µA
pull-up. The circuit breaker trips at time point B if the fault
is still present and the TIMER pin voltage reaches the
COMP2 threshold and the LTC4210 shuts down. For a
continuous fault, the circuit breaker delay is:
C
tV
CBDELAY
=µ1360.•
TIMER
A
(13)
Intermittent overloads may exceed the current limit as in
Figure 6, but if the duration is sufficiently short, the TIMER
pin may not reach the COMP2 threshold and the LTC4210
will not shut down. To handle this situation, the TIMER
discharges with 2µA whenever (VCC – SENSE) voltage is
below the 50mV limit and the TIMER voltage is between
the COMP1 and COMP2 thresholds. When the TIMER
voltage falls below the COMP1 threshold, the TIMER pin is
discharged with an equivalent 7k resistor (normal mode,
100µA source) when (VCC – SENSE) voltage is below the
50mV limit. If the TIMER pin does not drop below the
COMP1 threshold, any intermittent overload with an aggregate duty cycle of more than 3.8% will eventually trip
the circuit breaker. Figure 7 shows the circuit breaker
response time in seconds normalized to 1µF. The asym-
metric charging and discharging of TIMER is a fair gauge
of MOSFET heating.
V
TIMER
100µA
NORMAL
MODE
AB
COMP2
COMP1
FAULT
MODE
CIRCUIT BREAKER
TRIPS
LATCHED OFF (5µA PULL-UP)
OR RETRY (2µA PULL-DOWN)
60µA
4210 F05
Figure 5. A Continuous Fault Timing
A1 B1 A2 B2 A3 B3
~50mV/R
I
LOAD
COMP2
V
TIMER
V
GATE
60µA
10µA 10µA
CB
FAULT
60µA
2µA
CB
FAULT
60µA
2µA
LATCHED OFF (5µA PULL-UP)
OR RETRY (2µA PULL-DOWN)
CB
FAULT
SENSE
CIRCUIT BREAKER
TRIPS
COMP1
4210 F06
Figure 6. Mulitple Intermittent Overcurrent Conditon
1
C
TIMER
t
(s/µF) =
1.3V • 1µF
60µA • D – 2µA
C
TIMER
t
sF
(/ )
µ=
()
VF
13 1
.•
µ
AD A
60 2
•–
µ
µ
(14)
When the circuit breaker trips, the GATE pin is pulled low.
The TIMER enters latchoff mode with a 5µA pull-up for the
LTC4210-2 (latched-off version), while an autoretry “cooloff” cycle begins with a 2µA pull-down for the LTC4210-1
(autoretry version). An autoretry cool-off delay of the
LTC4210-1 between COMP2 and COMP1 thresholds takes:
C
tV
COOLOFF
=µ112.•
TIMER
A
(15)
0.1
NORMALIZED RESPONSE TIME (s/µF)
0.01
20 100
10
0
40
50
30
OVERLOAD DUTY CYCLE, D (%)
807060
90
4210 F07
Figure 7. Circuit Breaker Timer Response
for Intermittent Overload
421012f
13
Page 14
LTC4210-1/LTC4210-2
WUUU
APPLICATIO S I FOR ATIO
Autoretry After Current Fault (LTC4210-1)
Figure 8 shows the waveforms of the LTC4210-1 (autoretry
version) during a circuit breaker fault. At time point B1, the
TIMER trips the COMP2 threshold of 1.3V. The GATE pin
pulls to ground while TIMER begins a “cool-off” cycle with
a 2µA pull-down to the COMP1 threshold of 0.2V. At time
point C1, the TIMER pin pulls down with approximately a
7k resistor to ground and a GATE start-up cycle is initiated.
If the fault persists, the fault autoretry duty cycle is
approximately 3.8%. Pulling the ON pin low for more than
30µs will stop the autoretry function and put the LTC4210
in reset mode.
A1
B1 C1 A2 B2
2µA
COMP2
COMP1
V
TIMER
V
V
I
GATE
LOAD
60µA
OUT
REGULATING AT 50mV/R
2µA
60µA
100µA
SENSE
Latch-Off After Current Fault (LTC4210-2)
Figure 9 shows the waveforms of the LTC4210-2 (latch-off
version) during a circuit breaker fault. At time point B, the
TIMER trips the COMP2 threshold. The GATE pin pulls to
ground while the TIMER pin is latched high by a 5µA pull-
up. The TIMER pin eventually reaches the soft-clamped
voltage (V
) of 2.3V. To clear the latchoff mode, the
CLAMP
user can either pull the TIMER pin to below 0.2V externally
or cycle the ON pin low for more than 30µs.
AB C
V
CLAMP
V
TIMER
V
I
GATE
V
LOAD
60µA
OUT
REGULATING AT 50mV/R
SENSE
COMP2
COMP1
0V
0V
14
CB
FAULT
COOL OFF
CYCLE
4210 F08
NORMAL
MODE
CB
FAULT
COOL OFF
CYCLE
Figure 8. Automatic Retry After Overcurrent Fault
NORMAL
MODE
LATCHED OFF CYCLE
CB
FAULT
2410 F09
Figure 9. Latchoff After Overcurrent Fault
421012f
Page 15
WUUU
APPLICATIO S I FOR ATIO
LTC4210-1/LTC4210-2
Normal Mode/External Timer Control
Whenever the TIMER pin voltage drops below the COMP1
threshold, but is not in reset mode, the TIMER enters
normal (100µA source) mode with an equivalent 7k resis-
tive pull-down. Table 1 shows the relationship of t
t
CBDELAY
, t
COOLOFF
vs C
TIMER
.
INITIAL
,
If the TIMER pin is pulled beyond the COMP2 threshold,
the GATE pin is pulled to ground immediately. This allows
the TIMER pin to be used for overvoltage detection, see
Figure 11.
Externally forcing the TIMER pin below the COMP1 threshold will reset the TIMER to normal mode. During overvoltage detection, the TIMER’s 100µA pull-down current will
continue to be on if (VCC – SENSE) voltage is below 50mV.
If the (VCC – SENSE) voltage exceeds 50mV during the
overvoltage detection, the TIMER current will be the same
as described for latched-off or autoretry mode. See the
Table 1. t
C
TIMER
0.033 9.0 0.7 18.2
0.047 12.8 1 25.9
0.068 18.6 1.5 37.4
0.082 22.4 1.8 45.1
0.1 27.3 2.2 55
0.22 60.0 4.8 121
0.33 90.1 7.2 181.5
0.47 128.3 10.2 258.5
0.68 185.6 14.7 374
0.82 223.8 17.8 451
1 272.9 21.7 550
2.2 600.5 47.7 1210
3.3 900.7 71.5 1815
, t
INITIAL
(µF) t
CBDELAY
INITIAL
, t
COOLOFF
(ms) t
vs C
CBDELAY
TIMER
(ms) t
COOLOFF
(ms)
section OVERVOLTAGE DETECTION USING TIMER PIN
for details of the application.
Power-Off Cycle
The system can be reset by toggling the ON pin low for
more than 30µs as shown at time point 7 of Figure 3. The
GATE pin is pulled to ground. The TIMER capacitor is also
discharged to ground. C
discharges through the load.
LOAD
Alternatively, the TIMER pin can be externally driven above
the COMP2 threshold to turn off the GATE pin.
POWER MOSFET SELECTION
Power MOSFETs can be classified by R
at VGS gate
DSON
drive ratings of 10V, 4.5V, 2.5V and 1.8V. Use the typical
curves ∆VGATE vs Supply Voltage and ∆VGATE vs Temperature to determine whether the gate drive voltage is
adequate for the selected MOSFET at the operating voltage.
In addition, the selected MOSFET should fulfill two V
GS
criteria:
1. Positive VGS absolute maximum rating > LTC4210
maximum ∆V
GATE
, and
2. Negative VGS absolute maximum rating > supply
voltage. The gate of the MOSFET can discharge faster
than V
C
LOAD
when shutting down the MOSFET with a large
OUT
.
If one of the conditions cannot be met, an external Zener
clamp shown on Figure 10a or Figure 10b can be used. The
selection of RG should be within the allowed LTC4210
package dissipation when discharging V
via the Zener
OUT
clamp.
421012f
15
Page 16
LTC4210-1/LTC4210-2
WUUU
APPLICATIO S I FOR ATIO
V
GND
IN
5V
V
CC
BACKPLANE
CONNECTOR
(FEMALE)
R
SENSE
Q1
D1*
R
S
200Ω
GATE
(10a) (10b)
V
OUT
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE
IS RECOMMENDED)
1N4688 (5V)
1N4692 (7V)
1N4695 (9V)
1N4702 (15V)
V
CC
Figure 10. Gate Protection Zener Clamp
PCB EDGE
CONNECTOR
(MALE)
LONG
R
X
10Ω
Z1
C
X
0.1µF
R
ON1
SHORT
LONG
20k
R
ON2
10k
Z1: SMAJ10A Z2: BZX84C6V2
R
10k
D1
1N4148
R
TIMER
18Ω
C
TIMER
0.22µF
B
3
1
Z2
R
SENSE
V
ON
TIMER
R
SENSE
0.01Ω
6
CC
LTC4210
Q1
GATE
GND
R
S
200Ω
SENSE
GATE
2
5
D2*D1*
Q1
Si4410DY
R
100Ω
4
R4
100Ω
G
C
C
10nF
V
OUT
V
OUT
5V
C
LOAD
470µF
4210 F11
4A
GND
+
16
Figure 11. Supply Side Overvoltage Protection
421012f
Page 17
WUUU
APPLICATIO S I FOR ATIO
LTC4210-1/LTC4210-2
A MOSFET with a VGS absolute maximum rating of ±20V
meets the two criteria for all the LTC4210 applications
ranges from 2.7V to 16.5V. Typically most 10V gate rated
MOSFETs have VGS absolute maximum ratings of ±20V or
greater, so no external VGS Zener clamp is needed. There
are 4.5V gate rated MOSFETs with VGS absolute maximum
ratings of ±20V.
In addition to the MOSFET gate drive rating and V
absolute maximum rating, other criteria such as V
I
D(MAX)
, R
DS(ON)
, PD, θJA, T
and maximum safe
J(MAX)
operating area should also be carefully reviewed. V
GS
BDSS
BDSS
,
should exceed the maximum supply voltage inclusive of
spikes and ringing. I
current limit, I
LIMIT
. R
which together with VCB yields an error in the V
should be greater than the
D(MAX)
determines the MOSFET V
DS(ON)
voltage.
OUT
DS
At 2.7V supply voltage, the total of VDS + VCB of 0.1V yields
3.7% V
OUT
error.
The maximum power dissipated in the MOSFET is
2
I
LIMIT
• R
and this should be less than the maxi-
DS(ON)
mum power dissipation, PD allowed in that package.
Given power dissipation, the MOSFET junction temperature, TJ can be computed from the operating temperature
(TA) and the MOSFET package thermal resistance (θJA).
The operating TJ should be less than the T
J(MAX)
specifi-
cation.
Next review the short-circuit condition under maximum
supply V
I
LIMIT(MAX)
t
CBDELAY
IN(MAX)
with the maximum safe operating area of the
conditions and maximum current limit,
during the circuit breaker time-out interval of
MOSFET. The operation during output short-circuit conditions must be well within the manufacturer’s recommended safe operating region with sufficient margin. To
ensure a reliable design, fault tests should be evaluated in
the laboratory.
VIN TRANSIENT PROTECTION
Unlike most circuits, Hot Swap controllers typically are
not allowed the good engineering practice of supply
bypass capacitors, since controlling the surge current to
bypass capacitors at plug-in is the primary motivation for
the Hot Swap controller. Although wire harness, backplane and PCB trace inductances are usually small, these
can create large spikes when large currents are suddenly
drawn, cut-off or limited. This can cause detrimental
damage to board components unless measures are taken.
Abrupt intervention can prevent subsequent damage
caused by a catastrophic fault but it does cause a large
supply transient. The energy stored in the lead/trace
inductance is easily controlled with snubbers and/or
transient voltage suppressors. Even when ferrite beads
are used for electromagnetic interference (EMI) control,
the low saturating current of ferrite will not pose a major
problem if the transient voltage suppressors with adequate ratings are used. The transient associated with the
GATE turn off can be controlled with a snubber and/or
transient voltage suppressor. Snubbers such as RC networks are effective especially at low voltage supplies. The
choice of RC is usually determined experimentally. The
value of the snubber capacitor is usually chosen between
10 to 100 times the MOSFET C
. The value of the
OSS
snubber resistor is typically between 3Ω to 100Ω. When
the supply exceeds 7V or EMI beads exist in the wire
harness, a transient voltage suppressor and snubber are
recommended to clip off large spikes and reduce the
ringing. For supply voltages of 6V or below, a snubber
network should be sufficient to protect against transient
voltages. In many cases, a simple short-circuit test can be
performed to determine the need of the transient voltage
suppressor.
OVERVOLTAGE DETECTION USING THE TIMER PIN
Figure 11 shows a supply side overvoltage detection
circuit. A Zener diode, a diode and COMP2 threshold sets
the overvoltage threshold. Resistor RB biases the Zener
diode voltage. Diode D1 blocks forward current in the
Zener during start-up or output short-circuit. R
C
sets the overload noise filter.
TIMER
TIMER
with
421012f
17
Page 18
LTC4210-1/LTC4210-2
U
APPE DIX
Table 2 lists some current sense resistors that can be used
with the circuit breaker. Table 3 lists some power MOSFETs
manufacturers. Since this information is subject to change,
please verify the part numbers with the manufacturer.
that are available. Table 4 lists the web sites of several
Table 2. Sense Resistor Selection Guide
CURRENT LIMIT VALUE PART NUMBER DESCRIPTION MANUFACTURER
1A LR120601R050 0.05Ω 0.5W 1% Resistor IRC-TT
2A LR120601R025 0.025Ω 0.5W 1% Resistor IRC-TT
2.5A LR120601R020 0.02Ω 0.5W 1% Resistor IRC-TT
3.3A WSL2512R015F 0.015Ω 1W 1% Resistor Vishay-Dale
5A LR251201R010F 0.01Ω 1.5W 1% Resistor IRC-TT
10A WSR2R005F 0.005Ω 2W 1% Resistor Vishay-Dale
Table 3. N-Channel Selection Guide
CURRENT LEVEL (A) PART NUMBER DESCRIPTION MANUFACTURER
0 to 2 MMDF3N02HD Dual N-Channel SO-8 ON Semiconductor
R
= 0.1Ω, C
DS(ON)
2 to 5 MMSF5N02HD Single N-Channel SO-8 ON Semiconductor
R
= 0.025Ω, C
DS(ON)
5 to 10 MTB50N06V Single N-Channel DD Pak ON Semiconductor
= 0.028Ω, C
R
DS(ON)
10 to 20 MTB75N05HD Single N-Channel DD Pak ON Semiconductor
R
= 0.0095Ω, C
DS(ON)
= 455pF
ISS
ISS
ISS
ISS
= 1130pF
= 1570pF
= 2600pF
Table 4. Manufacturers’ Web Sites
MANUFACTURER WEB SITE
TEMIC Semiconductor www.temic.com
International Rectifier www.irf.com
ON Semiconductor www.onsemi.com
Harris Semiconductor www.semi.harris.com
IRC-TT www.irctt.com
Vishay-Dale www.vishay.com
Vishay-Siliconix www.vishay.com
Diodes, Inc. www.diodes.com
18
421012f
Page 19
PACKAGE DESCRIPTIO
LTC4210-1/LTC4210-2
U
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
0.62
MAX
3.85 MAX
2.62 REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.20 BSC
DATUM ‘A’
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
0.95
REF
1.22 REF
1.4 MIN
0.30 – 0.50 REF
2.80 BSC
0.09 – 0.20
(NOTE 3)
1.50 – 1.75
(NOTE 4)
1.00 MAX
0.95 BSC
0.80 – 0.90
2.90 BSC
(NOTE 4)
PIN ONE ID
1.90 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
0.01 – 0.10
S6 TSOT-23 0302
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
421012f
19
Page 20
LTC4210-1/LTC4210-2
U
TYPICAL APPLICATIO
12V Hot Swap Application
PCB EDGE
CONNECTOR
(MALE)
LONG
SHORT
LONG
Z1: SMAJ12A
Z1
R
62k
ON1
R
10Ω
R
10k
X
C
X
0.1µF
ON2
VCCSENSE
3
ON
1
TIMER
C
TIMER
0.22µF
R
SENSE
0.01Ω
6
LTC4210
GND
Q1
Si4410DY
+
5
GATE
2
R
G
200Ω
4
R
C
100Ω
C
C
10nF
C
LOAD
470µF
4210 TA03
V
OUT
12V
4A
GND
V
12V
GND
BACKPLANE
CONNECTOR
(FEMALE)
IN
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1421 Two Channel, Hot Swap Controller Operates from 3V to 12V and Supports –12V
LTC1422 Single Channel, Hot Swap Controller in SO-8 Operates from 2.7V to 12V, Reset Output
LT1640AL/LT1640AH Negative Voltage Hot Swap Controller in SO-8 Operates from –10V to –80V
LTC1642 Single Channel, Hot Swap Controller Overvoltage Protection to 33V, Foldback Current Limiting
LTC1643AL/LTC1643AH PCI Hot Swap Controller 3.3V, 5V, Internal FETs for ±12V
LTC1647 Dual Channel, Hot Swap Controller Operates from 2.7V to 16.5V, Separate ON pins for Sequencing
LTC4211 Single Channel, Hot Swap Controller 2.5V to 16.5V, Multifunction Current Control
LTC4230 Triple Channel, Hot Swap Controller 1.7V to 16.5V, Multifunction Current Control
LTC4251 –48V Hot Swap Controller in SOT-23 Floating Supply, Three-Level Current Limiting
LTC4252 –48V Hot Swap Controller in MSOP Floating Supply, Power Good, Three-Level Current Limiting
LTC4253 –48V Hot Swap Controller with Triple Supply Sequencing Floating Supply, Three-Level Current Limiting
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
421012f
LT/TP 0603 1K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2002
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