Datasheet LTC3813EG, LTC3813 Datasheet (Linear Technology)

LTC3813

100V Current Mode

Synchronous Step-Up Controller

FEATURES

n

High Output Voltages: Up to 100V

n

Large 1Ω Gate Drivers

n

No Current Sense Resistor Required

n

Dual N-Channel MOSFET Synchronous Drive

n

±0.5% 0.8V Voltage Reference

n

Fast Transient Response

n

Programmable Soft-Start

n

Generates 10V Driver Supply from Input Supply

n

Synchronizable to External Clock

n

Power Good Output Voltage Monitor

n

Adjustable Off-Time/Frequency: t

n

Adjustable Cycle-by-Cycle Current Limit

n

Programmable Undervoltage Lockout

n

Output Overvoltage Protection

n

28-Pin SSOP Package

OFF(MIN)

< 100ns

APPLICATIONS

n

24V Fan Supplies

n

48V Telecom and Base Station Power Supplies

n

Networking Equipment, Servers

n

Automotive and Industrial Control Systems

DESCRIPTION

The LTC3813 is a synchronous step-up switching regulator
controller that can generate output voltages up to 100V.
The LTC3813 uses a constant off-time peak current control
architecture with accurate cycle-by-cycle current limit,
without requiring a sense resistor.

A precise internal reference provides ±0.5% DC accuracy.
A high bandwidth (25MHz) error amplifi er provides very
fast line and load transient response. Large 1Ω gate drivers
allow the LTC3813 to drive multiple MOSFETs for higher
current applications. The operating frequency is selected
by an external resistor and is compensated for variations

and can also be synchronized to an external clock

in V

IN

for switching-noise sensitive applications. A shutdown pin
allows the LTC3813 to be turned off, reducing the supply
current to 240μA.

PARAMETER LTC3813 LTC3814-5

Maximum V

OUT

MOSFET Gate Drive 6.35V to 14V 4.5V to 14V

+

UV

INTV

CC

–

UV

INTV

CC

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611.

100V 60V

6.2V 4.2V

6V 4V

TYPICAL APPLICATION

High Effi ciency High Voltage Step-Up Converter

500k

V

OUT

1000pF

0.01

100pF

I

OFF

PGOOD

V

RNG

SYNC

SS

SHDN

I

100k

TH

V

FB

SGND

μ

F

LTC3813

BOOST

EXTV

DRV

INTV

SENSE

SENSE

BGRTN

NDRV

TG

SW

CC

CC

CC

+

BG

–

50k

0.1μF

Effi ciency vs Load Current

100

V

IN

22

30.9k

499

μ

Ω

3813 TA01

10V TO 40V

F

+

V

OUT

50V/5A

270μF

× 2

95

90

EFFICIENCY (%)

85

80

04

VIN = 12V

123 5

LOAD (A)

M1
Si7850DP

+

10

μ

H

D1
MBR1100

M2
Si7850DP

× 2

1

μ

F

VIN = 36V

VIN = 24V

3813 TA01b

3813fa

1

LTC3813

ABSOLUTE MAXIMUM RATINGS

(Note 1)

Supply Voltages
INTV
(DRV

BOOST ................................................ –0.3V to 114V

BGRTN ....................................................... –5V to 0V

EXTV
(NDRV - INTV
SW, SENSE
I

OFF

SS Voltage ................................................... –0.3V to 5V

PGOOD Voltage ............................................ –0.3V to 7V

V

RNG

UVIN Voltages ........................................ –0.3V to 14V

PLL/LPF, FB Voltages ................................. –0.3V to 2.7V

TG, BG, INTV

Operating Temperature Range (Note 2).... –40°C to 85°C

Junction Temperature (Notes 3, 7)........................ 125°C

Storage Temperature Range ................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ..................300°C

, DRVCC ...................................... –0.3V to 14V

CC

- BGRTN), (BOOST - SW) ......... –0.3V to 14V

CC

.................................................. –0.3V to 15V

CC

) Voltage ........................... –0.3V to 10V

CC

+

Voltage ................................... –1V to 100V

Voltage .............................................. –0.3V to 100V

, V

, SYNC, SHDN,

OFF

, EXTVCC RMS Currents .................50mA

CC

PIN CONFIGURATION

TOP VIEW

I

1

OFF

NC

2

NC

3

V

4

OFF

V

5

RNG

PGOOD

6

SYNC

7

I

8

TH

V

9

FB

PLL/LPF

10

SS

11

SGND

12

SHDN

13

UVIN

14

G PACKAGE

28-LEAD PLASTIC SSOP

T

= 125°C, θJA = 100°C/W

JMAX

28

27

26

25

24

23

22

21

20

19

18

17

16

15

BOOST

TG

SW

SENSE

NC

NC

NC

SENSE

BGRTN

BG

DRV

CC

INTV

EXTV

NDRV

+

–

CC

CC

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3813EG#PBF LTC3813EG#TRPBF LTC3813EG 28-Lead Plastic SSOP –40°C to 85°C

Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

The

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifi cations are at TA = 25°C, INTVCC = DRVCC = V
V

NDRV

= 10V, V

SYNC

= V

SENSE

+

= V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loop

INTV

I

Q

I

BOOST

V

FB

CC

INTVCC Supply Voltage

INTVCC Supply Current
INTV

Shutdown Current

CC

BOOST Supply Current (Note 5)

Feedback Voltage (Note 4)

SENSE

–

= V

= VSW = 0V, unless otherwise specifi ed.

BGRTN

l denotes specifi cations which apply over the full operating

= V

= V

= SHDN = UVIN = V

RNG

l

6.35 14 V

3

240

SHDN > 1.5V, I
SHDN = 0V

= 9.5V (Note 5)

NTVCC

BOOST

OFF

270

SHDN = 0V

0°C to 85°C
–40°C to 85°C

0.796

l

0.794

l

0.792

0

0.800

0.800

0.800

EXTVCC

6

600

400

5

0.804

0.806

0.806

=

mA

μA

μA
μA

V
V
V

2

3813fa

LTC3813

ELECTRICAL CHARACTERISTICS

The l denotes specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
V

NDRV

= 10V, V

SYNC

= V

SENSE

+

= V

SENSE

–

= V

BGRTN

= 25°C, INTVCC = DRVCC = V

A

= V

= 0V, unless otherwise specifi ed.

SW

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ΔV

FB,LINE

V

SENSE(MAX)

V

SENSE(MIN)

I

VFB

(EA) Error Amplifi er DC Open Loop Gain 65 100 dB

A

VOL

f

U

I

SYNC

V

SHDN

I

SHDN

I

SS

V

VINUV

Feedback Voltage Line Regulation 7V < INTVCC < 14V (Note 4)

Maximum Current Sense Threshold V

Minimum Current Sense Threshold V

= 2V, VFB = 0.76V

RNG

V

= 0V, VFB = 0.76V

RNG

V

= INTVCC, VFB = 0.76V

RNG

= 2V, VFB = 0.84V

RNG

V

= 0V, VFB = 0.84V

RNG

V

= INTVCC, VFB = 0.84V

RNG

Feedback Current VFB = 0.8V 20 150 nA

Error Amp Unity Gain Crossover Frequency (Note 6) 25 MHz

SYNC Current 01 μA

Shutdown Threshold 1.2 1.5 2 V
SHDN Pin Input Current 01 μA

SS Source Current VSS > 0.5V 0.7 1.4 2.5 μA

VIN Undervoltage Lockout VIN Rising

V

Falling

IN

Hysteresis

V

VCCUV

INTVCC Undervoltage Lockout INTVCC Rising

Hysteresis

Oscillator and Phase-Locked Loop

t

OFF

t

OFF(MIN)

t

ON(MIN)

t

OFF(PLL)

I

PLL/LPF

Off-Time I

Minimum Off-Time I

Minimum On-Time 250 ns

t

Modulation Range by PLL

OFF

Down Modulation
Up Modulation

Phase Detector Output Current

Sinking Capability
Sourcing Capability

= 100μA

OFF

I

= 300μA

OFF

= 2000μA 100 ns

OFF

I

= 100μA, V

OFF

I

= 100μA, V

OFF

f

< f

PLLIN

f

> f

PLLIN

SW
SW

PLL/LPF
PLL/LPF

= 0.6V
= 1.8V

Driver

I

BG,PEAK

R

BG,SINK

I

TG,PEAK

R

TG,SINK

BG Driver Peak Source Current VBG = 0V 1.5 2 A

BG Driver Pulldown R

DS(ON)

TG Driver Peak Source Current VTG – VSW = 0V 1.5 2 A

TG Driver Pulldown R

DS(ON)

PGOOD Output

ΔV

FBOV

PGOOD Upper Threshold
PGOOD Lower Threshold

ΔV

FB,HYST

V

PGOOD

I

PGOOD

PGOOD Hysteresis VFB Returning 1.5 3 %

PGOOD Low Voltage I

PGOOD Leakage Current V

PG Delay PGOOD Delay V

VFB Rising
V

Falling

FB

= 5mA 0.3 0.6 V

PGOOD

= 5V 0 2 μA

PGOOD

Falling 125 μs

FB

BOOST

= V

OFF

= V

= SHDN = UVIN = V

RNG

l

256

70

170

l

0.86

l

0.78

0.07

l

6.05 6.2

1.55
515

2.2

0.6

7.5

–7.5

=

EXTVCC

0.002 0.02 %/V

320

95

215

–300

–85

–200

0.88

0.80

0.10

384
120
260

0.92

0.82

0.12

mV
mV
mV

mV
mV
mV

6.35 V

0.2

1.85
605

3.6

1.2

15

–25

2.15
695

5

1.8

μA
μA

11.5

11.5

10

–10

12.5

–12.5

V
V
V

V

μs
ns

μs
μs

Ω

Ω

%
%

3813fa

3

LTC3813

ELECTRICAL CHARACTERISTICS

The l denotes specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
V

NDRV

= 10V, V

SYNC

= V

SENSE

+

= V

SENSE

–

= V

BGRTN

= 25°C, INTVCC = DRVCC = V

A

= V

= 0V, unless otherwise specifi ed.

SW

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Regulators

V

CC

V

EXTVCC

V

INTVCC,1

ΔV

EXTVCC,1

ΔV

LOADREG,1

V

INTVCC,2

ΔV

LOADREG,2

I

NDRV

V

CCSR

I

CCSR

EXTVCC Switchover Voltage

EXTV

Rising

CC

EXTV

Hysteresis

CC

INTVCC Voltage from EXTV

V

EXTVCC

- V

at Dropout ICC = 20mA, V

INTVCC

CC

INTVCC Load Regulation from EXTV

CC

10.5V < V

I

CC

EXTVCC

= 0mA to 20mA, V

< 15V 9.4 10 10.6 V

= 9.1V 170 250 mV

EXTVCC

EXTVCC

INTVCC Voltage from NDRV Regulator Linear Regulator in Operation 9.4 10 10.6 V

INTVCC Load Regulation from NDRV ICC = 0mA to 20mA, V

Current into NDRV Pin V

NDRV

– V

INTVCC

EXTVCC

= 3V 20 40 60 μA

Maximum Supply Voltage Trickle Charger Shunt Regulator 15 V

Maximum Current into NDRV/INTV

CC

Trickle Charger Shunt Regulator,
INTV

≤ 16.7V (Note 8)

CC

= V

= V

BOOST

OFF

= SHDN = UVIN = V

RNG

l

6.4

0.1

6.7

0.25 0.5

EXTVCC

=

= 12V 0.01 %

= 0 0.01 %

10 mA

V
V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: The LTC3813E is guaranteed to meet performance specifi cations
from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: T
dissipation P

LTC3813: T
Note 4: The LTC3813 is tested in a feedback loop that servos V

reference voltage with the I

is calculated from the ambient temperature TA and power

J

according to the following formula:

D

= TA + (PD • 100°C/W)

J

pin forced to a voltage between 1V and 2V.

TH

FB

to the

Note 5: The dynamic input supply current is higher due to the power
MOSFET gate charging being delivered at the switching frequency
(Q

• fSW).

G

Note 6: Guaranteed by design. Not subject to test.
Note 7: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specifi ed maximum operating junction
temperature may impair device reliability.

Note 8: I

is the sum of current into NDRV and INTVCC.

CC

4

3813fa

LTC3813

TYPICAL PERFORMANCE CHARACTERISTICS

Load Transient Response Start-Up

V

OUT

200mV/

DIV

I

OUT

2A/DIV

FIGURE 14 CIRCUIT

= 12V

V

IN

0A TO 4A LOAD STEP

Effi ciency vs Load Current

100

V

= 24V

OUT

95

90

EFFICIENCY (%)

85

80

0

1

100μs/DIV

VIN = 12V

VIN = 5V

2

LOAD (A)

3813 G01

3

3813 G04

4

V

OUT

20V/DIV

SS

4V/DIV

I

L

5A/DIV

FRONT PAGE CIRCUIT

= 24V

V

IN

= 2A

I

LOAD

Frequency vs Input Voltage

300

FRONT PAGE CIRCUIT

280

260

240

FREQUENCY (kHz)

220

200

15

10

INPUT VOLTAGE (V)

20

1ms/DIV

25

I

LOAD

I

LOAD

30 35

= 0A

= 1A

3813 G02

3813 G05

40

Overcurrent Operation

V

OUT

20V/DIV

I

L

5A/DIV

FRONT PAGE CIRCUIT

= 24V

V

IN

= 1Ω

R

SHORT

Frequency vs Load Current

280

FRONT PAGE CIRCUIT

270

260

250

240

230

FREQUENCY (kHz)

220

210

200

0

1

LOAD CURRENT (A)

500μs/DIV

VIN = 12V

2

VIN = 24V

3

3813 G03

4

3813 G06

Current Sense Threshold

Voltage

vs I

TH

400

300

200

100

0

–100

–200

CURRENT SENSE THRESHOLD (mV)

–300

–400

0

0.5

1 1.5 2

ITH VOLTAGE (V)

V

RNG

1.4V

1V

0.7V

0.5V

2.5 3

= 2V

3813 G07

Off-Time vs I

10000

1000

OFF-TIME (ns)

100

10

10

Current

OFF

V

= INTV

OFF

CC

100 1000 10000
I

CURRENT (μA)

OFF

3813 G08

Off-Time vs V

700

I

OFF

600

500

400

300

OFF-TIME (ns)

200

100

0

0

= 300μA

0.5 1

Voltage

OFF

1.5 2.5

V

VOLTAGE (V)

OFF

23

3813 G09

3813fa

5

LTC3813

TYPICAL PERFORMANCE CHARACTERISTICS

Off-Time vs Temperature

680

I

= 300μA

OFF

660

640

620

OFF-TIME (ns)

600

580

560

–50

–25 0

25 75

TEMPERATURE (°C)

Feedback Reference Voltage
vs Temperature

0.803

0.802

0.801

0.800

0.799

REFERENCE VOLTAGE (V)

0.798

50 100 125

3813 G10

Maximum Current Sense
Threshold vs V

400

300

200

100

MAXIMUM CURRENT SENSE THRESHOLD (mV)

0

0.5
V

Voltage

RNG

1 1.5

VOLTAGE (V)

RNG

Driver Peak Source Current
vs Temperature

2.5
V

= V

INTVCC

= 10V

BOOST

2.0

1.5

PEAK SOURCE CURRENT (A)

3813 G11

Maximum Current Sense
Threshold vs Temperature

230

V

= INTV

RNG

220

210

200

190

MAXIMUM CURRENT SENSE THRESHOLD (mV)

180

2

–50 –25

CC

25

0

TEMPERATURE (°C)

Driver Pulldown R
vs Temperature

1.50
V

= V

INTVCC

= 10V

1.25

1.00

(Ω)

0.75

DS(ON)

R

0.50

0.25

BOOST

50

DS(ON)

100

125

3813 G12

75

6

0.797
–50 –25

50

25

0

TEMPERATURE (°C)

Driver Peak Source Current
vs Supply Voltage

3.0

2.5

2.0

1.5

1.0

PEAK SOURCE CURRENT (A)

0.5

0

56 8 10 12 14

75

125

100

3813 G13

7 9 11 13

DRVCC/BOOST VOLTAGE (V)

1

–25 0 25 50

–50

15

3813 G16

TEMPERATURE (°C)

(Ω)

R

75 100 125

3813 G14

Driver Pulldown R
vs Supply Voltage

1.1

1.0

0.9

DS(ON)

0.8

0.7

0.6
79

8

6

DRVCC/BOOST VOLTAGE (V)

0

–50

–25 0

DS(ON)

11 15

12

10

25 75

TEMPERATURE (°C)

13

14

3813 G17

50 100 125

3813 G15

3813fa

TYPICAL PERFORMANCE CHARACTERISTICS

LTC3813

EXTVCC LDO Resistance at
Dropout vs Temperature

14

12

10

8

6

RESISTANCE (Ω)

4

2

0

–25 0 50

–50

25

TEMPERATURE (°C)

INTVCC Current vs INTVCC Voltage

4.0

3.5

3.0

2.5

2.0

CURRENT (mA)

1.5

CC

INTV

1.0

0.5

0

0

24

INTVCC VOLTAGE (V)

81214

610

75 100 125

3813 G18

3813 G21

INTV

Current vs Temperature

CC

4

3

2

CURRENT (mA)

CC

INTV

1

0

–50 –25

25

0

TEMPERATURE (°C)

INTVCC Shutdown Current
vs INTVCC Voltage

300

250

200

150

CURRENT (μA)

CC

100

INTV

50

0

0

24

610

INTVCC VOLTAGE (V)

50

75

81214

100

125

3813 G19

3813 G22

Shutdown Current

INTV

CC

vs Temperature

400

300

200

CURRENT (μA)

CC

INTV

100

0

–25 0 50

–50

SS Pull-Up Current
vs Temperature

3

2

1

SS CURRENT (μA)

0

–50

–25 0

25

TEMPERATURE (°C)

50 100 125

25 75

TEMPERATURE (°C)

75 100 125

3813 G20

3813 G23

ITH Voltage
vs Load Current

3

FRONT PAGE CIRCUIT

= 24V

V

IN

V

RNG

2

VOLTAGE (V)

TH

I

1

0

0

= 1V

1234

LOAD CURRENT (A)

3813 G24

Shutdown Threshold
vs Temperature

2.2

2.0

1.8

1.6

1.4

1.2

1.0

SHUTDOWN THRESHOLD (V)

0.8

0.6
–25 0 50

–50

25

TEMPERATURE (°C)

75 100 125

3813 G25

3813fa

7

LTC3813

PIN FUNCTIONS

I

(Pin 1): Off-Time Current Input. Tie a resistor from

OFF

to this pin to set the one-shot timer current and

V

OUT

thereby set the switching frequency.

(Pin 4): Off-Time Voltage Input. Voltage trip point

V

OFF

for the on-time comparator. Tying this pin to an external
resistive divider from the input makes the off-time pro­portional to V
the pin is grounded and defaults to 2.4V when the pin is
connected to INTV

(Pin 5): Sense Voltage Limit Set. The voltage at this

V

RNG

pin sets the nominal sense voltage at maximum output
current and can be set from 0.5V to 2V by a resistive
divider from INTV
to 95mV when this pin is tied to ground, and 215mV when
tied to INTV

PGOOD (Pin 6): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage
is not between ±10% of the regulation point. The output
voltage must be out of regulation for at least 125μs before
the power good output is pulled to ground.

SYNC (Pin 7): Sync Pin. This pin provides an external
clock input to the phase detector. The phase-locked loop
will force the rising top gate signal to be synchronized
with the rising edge of the clock signal.

(Pin 8): Error Amplifi er Compensation Point and Cur-

I

TH

rent Control Threshold. The current comparator threshold
increases with control voltage. The voltage ranges from
0V to 2.6V with 1.2V corresponding to zero sense voltage
(zero current).

(Pin 9): Feedback Input. Connect VFB through a resistor

V

FB

divider network to V

PLL/LPF (Pin 10): The phase-locked loop’s lowpass fi lter
is tied to this pin. The voltage at this pin defaults to 1.2V
when the IC is not synchronized with an external clock at
the SYNC pin.

. The comparator defaults to 0.7V when

IN

.

CC

. The nominal sense voltage defaults

CC

.

CC

to set the output voltage.

OUT

SS (Pin 11): Soft-Start Input. A capacitor to ground at
this pin sets the ramp rate of the maximum current sense
threshold.

SGND (Pin 12): Signal Ground. All small signal components
should connect to this ground and eventually connect to
PGND at one point.

SHDN (Pin 13): Shutdown Pin. Pulling this pin below 1.5V
will shut down the LTC3813, turn off both of the external
MOSFET switches and reduce the quiescent supply cur­rent to 240μA.

UVIN (Pin 14): UVLO Input. This pin is input to the internal
UVLO and is compared to an internal 0.8V reference. An
external resistor divider is connected to this pin and the
input supply to program the undervoltage lockout voltage.
When UVIN is less than 0.8V, the LTC3813 is shut down.

NDRV (Pin 15): Drive Output for External Pass Device of
the Linear Regulator for INTV

. Connect to the gate of an

CC

external NMOS pass device and a pull-up resistor to the
input voltage V

EXTV

(Pin 16): External Driver Supply Voltage. When

CC

or the output voltage V

IN

OUT

.

this voltage exceeds 6.7V, an internal switch connects
this pin to INTV

through an LDO and turns off the exter-

CC

nal MOSFET connected to NDRV, so that controller and
gate drive are drawn from EXTV

INTV

(Pin 17): Main Supply Pin. All internal circuits

CC

CC

.

except the output drivers are powered from this pin.
INTV

should be bypassed to ground (Pin 10) with at

CC

least a 0.1μF capacitor in close proximity to the
LTC3813.

(Pin 18): Driver Supply Pin. DRVCC supplies power

DRV

CC

to the BG output driver. This pin is normally connected to
INTV

. DRVCC should be bypassed to BGRTN (Pin 20)

CC

with a low ESR (X5R or better) 1μF capacitor in close
proximity to the LTC3813.

8

3813fa

PIN FUNCTIONS

LTC3813

BG (Pin 19): Bottom Gate Drive. The BG pin drives the
gate of the bottom N-channel main switch MOSFET. This
pin swings from BGRTN to DRV

BGRTN (Pin 20): Bottom Gate Return. This pin connects to
the source of the pulldown MOSFET in the BG driver and
is normally connected to ground. Connecting a negative
supply to this pin allows the main MOSFET’s gate to be
pulled below ground to help prevent false turn-on during
high dV/dt transitions on the SW node. See the Applica­tions Information section for more details.

+

SENSE

parator Input. The (+) input to the current comparator is
normally connected to SW unless using a sense resistor.
The (–) input is used to accurately kelvin sense the bottom
side of the sense resistor or MOSFET.

, SENSE– (Pin 25, Pin 21): Current Sense Com-

CC

.

SW (Pin 26): Switch Node Connection to Inductor and
Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground
to V

TG (Pin 27): Top Gate Drive. The TG pin drives the gate of
the top N-channel synchronous switch MOSFET. The TG
driver draws power from the BOOST pin and returns to the
SW pin, providing true fl oating drive to the top MOSFET.

BOOST (Pin 28): Top Gate Driver Supply. The BOOST pin
supplies power to the fl oating TG driver. BOOST should
be bypassed to SW with a low ESR (X5R or better) 0.1μF
capacitor. An additional fast recovery Schottky diode from
DRV
charge-pumped supply at BOOST.

.

OUT

to the BOOST pin will create a complete fl oating

CC

3813fa

9

LTC3813

FUNCTIONAL DIAGRAM

V

IN

R

UVIN

UV1

14

R

UV2

SYNC

7

R

C

C

PLL-SYNC

t

= (76pF)

OFF

1.4V

0.7V

C1

V

VOFF

I

IOFF

I

CMP

PLL/LPF

10

V

OFF

4

I

OFF

R

OFF

V

OUT

1

V

RNG

5

I

TH

8

C

C2

0.8V

–

+

20k

+

–

×

2.6V

EA

+

VINUV

R

SQ

–

5V

REG

FAULT

0.8V
REF

1.4μA

Σ

+

INTV

CC

UV

OVERTEMP

SENSE

RUN

SHDN

+

–

1.5V

4V

V

IN

10V

+

NDRV

15

M3

–

OFF

–

6.2V

+

ON

+

–

+

–

ON

SWITCH

LOGIC

SHDN

OV

10V

6.7V

INTV

17

EXTV

16

BOOST

28

TG

27

SW

26

SENSE

25

DRV

18

BG

19

BGRTN

20

SENSE

21

PGOOD

6

CC

CC

+

V

D

B

+

CC

–

IN

+

C

IN

M2

L

V

M1

+

OUT

C

OUT

R2

C

B

C

VCC

–

0.72V

+

UV

13

SHDN

–

+

OV

–

0.85V

V

FB

9

SGND

12

R1

10

0.8V
SS

11

3813 FD

3813fa

OPERATION

LTC3813

Main Control Loop

The LTC3813 is a current mode controller for DC/DC step­up converters. In normal operation, the top MOSFET is
turned on for a fi xed interval determined by a one-shot
timer (OST). When the top MOSFET is turned off, the bot­tom MOSFET is turned on until the current comparator

trips, restarting the one-shot timer and initiating the

I

CMP

next cycle. Inductor current is determined by sensing the

–

voltage between the SENSE

and SENSE+ pins using a
sense resistor or the bottom MOSFET on-resistance. The
voltage on the I

pin sets the comparator threshold cor-

TH

responding to the inductor peak current. The fast 25MHz
error amplifi er EA adjusts this voltage by comparing the
feedback signal V

to the internal 0.8V reference volt-

FB

age. If the load current increases, it causes a drop in the
feedback voltage relative to the reference. The I

voltage

TH

then rises until the average inductor current again matches
the load current.

The operating frequency is determined implicitly by the
top MOSFET on-time (t

) and the duty cycle required to

OFF

maintain regulation. The one-shot timer generates a top
MOSFET on-time that is inversely proportional to the I
current and proportional to the V
V

OUT

to I

and VIN to V

OFF

with a resistive divider keeps

OFF

voltage. Connecting

OFF

the frequency approximately constant with changes in V

OFF

IN

.
The nominal frequency can be adjusted with an external
resistor R

OFF

.

For applications with stringent constant-frequency require­ments, the LTC3813 can be synchronized with an external
clock. By programming the nominal frequency the same as
the external clock frequency, the LTC3813 behaves as a con­stant-frequency part against the load and supply variations.

Pulling the SHDN pin low forces the controller into its
shutdown state, turning off both M1 and M2. Forcing a
voltage above 1.5V will turn on the device.

Fault Monitoring/Protection

Constant off-time current mode architecture provides ac­curate cycle-by-cycle current limit protection—a feature
that is very important for protecting the high voltage
power supply from output overcurrent conditions. The
cycle-by-cycle current monitor guarantees that the induc-

tor current will never exceed the value programmed on

RNG

pin.

the V

Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point after the
internal 125μs power bad mask timer expires. Furthermore,
in an overvoltage condition, M1 is turned off and M2 is
turned on immediately and held on until the overvoltage
condition clears.

The LTC3813 provides two undervoltage lockout com­parators—one for the INTV
the input supply V

. The INTVCC UV threshold is 6.2V to

IN

/DRVCC supply and one for

CC

guarantee that the MOSFETs have suffi cient gate drive volt­age before turning on. The V

UV threshold (UVIN pin) is

IN

0.8V with 10% hysteresis which allows programming the
V

threshold with the appropriate resistor divider con-

IN

nected to V

. If either comparator inputs are under the

IN

UV threshold, the LTC3813 is shut down and the drivers
are turned off.

Strong Gate Drivers

The LTC3813 contains very low impedance drivers capable
of supplying amps of current to slew large MOSFET gates
quickly. This minimizes transition losses and allows paral­leling MOSFETs for higher current applications. A 100V
fl oating high side driver drives the top side MOSFET and
a low side driver drives the bottom side MOSFET (see
Figure 1). The bottom side driver is supplied directly
from the DRV
from fl oating bootstrap capacitor C

pin. The top MOSFET drivers are biased

CC

, which normally is

B

recharged during each off cycle through an external diode

DRV

CC

LTC3813

Figure 1. Floating TG Driver Supply and Negative BG Return

DRV

BGRTN

0V TO –5V

CC

BOOST

TG

SW

BG

V

IN

+

D

B

C

B

M2

C

M1

3813 F01

IN

V

OUT

+

C

OUT

L

3813fa

11

LTC3813

OPERATION

from DRVCC when the top MOSFET turns off. In an output
overvoltage condition, where it is possible that the bot­tom MOSFET will be off for an extended period of time,
an internal timeout guarantees that the bottom MOSFET
is turned on at least once every 25μs for one top MOSFET
on-time period to refresh the bootstrap capacitor.

The bottom driver has an additional feature that helps
minimize the possibility of external MOSFET shoot-thru.
When the top MOSFET turns on, the switch node dV/dt
pulls up the bottom MOSFET’s internal gate through the
Miller capacitance, even when the bottom driver is hold­ing the gate terminal at ground. If the gate is pulled up
high enough, shoot-thru between the top side and bottom
side MOSFETs can occur. To prevent this from occurring,
the bottom driver return is brought out as a separate pin
(BGRTN) so that a negative supply can be used to reduce
the effect of the Miller pull-up. For example, if a –2V sup-

ply is used on BGRTN, the switch node dV/dt could pull
the gate up 2V before the V
more than 0V across it.

IC/Driver Supply Power and Linear Regulators

The LTC3813’s internal control circuitr y and top and bottom
MOSFET drivers operate from a supply voltage (INTV
DRV
voltage or another available supply is within this voltage
range it can be used to supply IC/driver power. If a supply
in this range is not available, two internal regulators are
available to generate a 10V supply from the input or output.
An internal low dropout regulator is good for voltages up to
15V, and the second, a linear regulator controller, controls
the gate of an external NMOS to generate the 10V supply.
Since the NMOS is external, the user has the fl exibility to
choose a BV

pins) in the range of 6.2V to 14V. If the input supply

CC

as high as necessary.

DSS

of the bottom MOSFET has

GS

CC

,

12

3813fa

APPLICATIONS INFORMATION

LTC3813

The basic LTC3813 application circuit is shown on the fi rst
page of this data sheet. External component selection is
primarily determined by the maximum input voltage and
load current and begins with the selection of the sense
resistance and power MOSFET switches. The LTC3813
uses either a sense resistor or the on-resistance of the
synchronous power MOSFET for determining the induc­tor current. The desired amount of ripple current and
operating frequency largely determines the inductor
value. Next, C

is selected for its ability to handle the

OUT

large RMS current and with low enough ESR to meet the
output voltage ripple and transient specifi cation. Finally,
loop compensation components are selected to meet the
required transient/phase margin specifi cations.

Duty Cycle Considerations

For a boost converter, the duty cycle of the main switch
is:

V

D= 1

V

IN

OUT

The maximum V

;D

MAX

capability of the LTC3813 is inversely

OUT

= 1

V

IN(MIN)

V

OUT

proportional to the minimum desired operating frequency
and minimum off-time:

V

IN(MIN)

f

MIN•tOFF(MIN)

 100V

RNG

Pin

V

OUT(MAX)

=

Maximum Sense Voltage and the V

The control circuit in the LTC3813 measures the input
current by using the R

of the bottom MOSFET or

DS(ON)

by using a sense resistor in the bottom MOSFET source,
so the output current needs to be refl ected back to the
input in order to dimension the power MOSFET properly
and to choose the maximum sense voltage. Based on the
fact that, ideally, the output power is equal to the input
power, the maximum average input current and average
inductor current is:

I

=

O(MAX)

1 D

MAX

I

IN(MAX)

= I

L,AVG(MAX)

should allow some margin for variations in the LTC3813
and external component values, and a good guide for
selecting the maximum sense voltage when V

sensing

DS

is used is:

V

SENSE(MAX)

V

SENSE

V

SENSE

1.7 • R

=

is set by the voltage applied to the V
is chosen, the required V

DS(ON)•IO(MAX)

1 D

MAX

voltage is calculated

RNG

pin. Once

RNG

to be:

V

= 5.78 • (V

RNG

SENSE(MAX)

An external resistive divider from INTV
to set the voltage of the V

+ 0.026)

can be used

CC

pin between 0.5V and 2V

RNG

resulting in nominal sense voltages of 60mV to 320mV.
Additionally, the V

pin can be tied to SGND or INTVCC

RNG

in which case the nominal sense voltage defaults to 95mV
or 215mV, respectively.

+

Connecting the SENSE

and SENSE– Pins

The LTC3813 can be used with or without a sense resis­tor. When using a sense resistor, place it between the
source of the bottom MOSFET, M2, and PGND. Connect

+

the SENSE

and SENSE– pins to the top and bottom of
the sense resistor. Using a sense resistor provides a well
defi ned current limit, but adds cost and reduces effi ciency.
Alternatively, one can eliminate the sense resistor and use
the bottom MOSFET as the current sense element by simply

+

connecting the SENSE

–

and SENSE

pin to the MOSFET source. This improves

pin to the lower MOSFET drain

effi ciency, but one must carefully choose the MOSFET
on-resistance, as discussed in the following section.

The current mode control loop will not allow the induc­tor peak to exceed V

SENSE(MAX)/RSENSE

. In practice, one

3813fa

13

LTC3813

APPLICATIONS INFORMATION

Power MOSFET Selection

The LTC3813 requires two external N-channel power
MOSFETs, one for the bottom (main) switch and one for
the top (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage BV
threshold voltage V
capacitance and maximum current I

, on-resistance R

(GS)TH

DS(MAX)

DS(ON)

.

,

DSS

, Miller

When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-resis­tance. MOSFET on-resistance is typically specifi ed with
a maximum value R

DS(ON)(MAX)

at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:

R

R

DS(ON)(MAX)

=

SENSE



T

The ρT term is a normalization factor (unity at 25°C)
accounting for the signifi cant variation in on-resistance

temperature (see Figure 2) and typically varies

with

°

from 0.4%/

C to 1.0%/°C depending on the particular

MOSFET used.

2.0

The most important parameter in high voltage applications
is breakdown voltage BV

. Both the top and bottom

DSS

MOSFETs will see full output voltage plus any additional
ringing on the switch node across its drain-to-source dur­ing its off-time and must be chosen with the appropriate
breakdown specifi cation. Since most MOSFETs in the 60V
to 100V range have higher thresholds (typically V

GS(MIN)

≥ 6V), the LTC3813 is designed to be used with a 6.2V to
14V gate drive supply (DRV

For maximum effi ciency, on-resistance R
capacitance should be minimized. Low R

CC

pin).

DS(ON)

DS(ON)

and input

minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi­nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 3).

V

OUT

V

GS

MILLER EFFECT

ab

Q

C

MILLER

IN

= (QB – QA)/V

DS

V

+

V

+

V

GS

–

DS

–

3813 F03

1.5

1.0

0.5

NORMALIZED ON-RESISTANCE

T

ρ

0

–50

0

JUNCTION TEMPERATURE (°C)

Figure 2. R

DS(ON)

50

100

vs Temperature

150

3813 F02

Figure 3. Gate Charge Characteristic

The curve is generated by forcing a constant input cur­rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The fl at portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the

3813fa

14

APPLICATIONS INFORMATION

LTC3813

increase in coulombs on the horizontal axis from a to b
while the curve is fl at) is specifi ed for a given V
voltage, but can be adjusted for different V
multiplying by the ratio of the application V
specifi ed V

values. A way to estimate the C

DS

DS

DS

drain

DS

voltages by

to the curve

term

MILLER

is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated

voltage specifi ed. C

V

DS

is the most important se-

MILLER

lection criteria for determining the transition loss term in
the top MOSFET but is not directly specifi ed on MOSFET
data sheets. C

and COS are specifi ed sometimes but

RSS

defi nitions of these parameters are not included.

When the controller is operating in continuous mode

duty cycles for the top and bottom MOSFETs are

the
given by:

Main Switch Duty Cycle =

Synchronous SwitchDuty Cycle =

OUT

V

OUT

IN

V

V

IN

OUT

V

 V

The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:

MAX

I

O(MAX)

1D

2






MAX

(T)R



(R




+

V

TH(IL)

DS(ON)

)(C

DR

1

MILLER



(f)






)

P

= D

MAIN

+

•

MAX

1

2




DRV





V

OUT

I



O(MAX)



1D





2




1

CC–VTH(IL)

where ρT is the temperature dependency of R

DS(ON)

, RDR

is the effective top driver resistance (approximately 2Ω at

= V

V

GS

MILLER

). V

is the data sheet specifi ed typical

TH(IL)

gate threshold voltage specifi ed in the power MOSFET data
sheet at the specifi ed drain current. C

is the calculated

MILLER

capacitance using the gate charge curve from the MOSFET
data sheet and the technique described above.

2

Both MOSFETs have I

R losses while the bottom N-channel

equation includes an additional term for transition losses.

2

Both top and bottom MOSFET I
lowest V

, and the top MOSFET I2R losses also peak

IN

R losses are greatest at

during an overcurrent condition when it is on close to
100% of the period. For most LTC3813 applications,

2

the transition loss and I

R loss terms in the bottom
MOSFET are comparable, so best effi ciency is obtained
by choosing a MOSFET that optimizes both R
C

. Since there is no transition loss term in the syn-

MILLER

DS(ON)

and

chronous MOSFET, however, optimal effi ciency is obtained
by minimizing R

—by using larger MOSFETs or

DS(ON)

paralleling multiple MOSFETs.

Multiple MOSFETs can be used in parallel to lower R

DS(ON)

and meet the current and thermal requirements if desired.
The LTC3813 contains large low impedance drivers capable
of driving large gate capacitances without signifi cantly
slowing transition times. In fact, when driving MOSFETs
with very low gate charge, it is sometimes helpful to slow
down the drivers by adding small gate resistors (10Ω or
less) to reduce noise and EMI caused by the fast transi­tions.

P

SYNC

=



1D





1

MAX



(I





O(MAX)

)2(T)R

DS(0N)

3813fa

15

LTC3813

APPLICATIONS INFORMATION

Operating Frequency

The choice of operating frequency is a tradeoff between
effi ciency and component size. Low frequency operation
improves effi ciency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.

The operating frequency of LTC3813 applications is de­termined implicitly by the one-shot timer that controls
the on-time t
The on-time is set by the current into the I
voltage at the V

V

t

=

OFF

Tying a resistor R

of the synchronous MOSFET switch.

OFF

pin and the

OFF

pin according to:

OFF

VOFF

76pF

()

I

IOFF

from V

OFF

OUT

to the I

pin yields a

OFF

synchronous MOSFET on-time inversely proportional to

. This results in the following operating frequency

V

OUT

and also keeps frequency constant as V

ramps up at

OUT

start-up:

V

f =

V

VOFF•ROFF

IN

(76pF)

(Hz)

The V
can be connected to a resistive divider from V

pin can be connected to INTVCC or ground or

OFF

. The V

IN

OFF

pin has internal clamps that limit its input to the one-shot
timer. If the pin is tied below 0.7V, the input to the one­shot is clamped at 0.7V. Similarly, if the pin is tied above

2.4V, the input is clamped at 2.4V. Note, however, that

if the V

pin is connected to a constant voltage, the

OFF

operating frequency will be proportional to the input
voltage V

. Figures 4a and 4b illustrate how R

IN

relates

OFF

to switching frequency as a function of the input voltage
and V
voltage changes, tie the V
V

IN

that the V
of V

voltage. To hold frequency constant for input

OFF

pin to a resistive divider from

OFF

, as shown in Figure 5. Choose the resistor values so

voltage equals about 1.55V at the mid-point

RNG

as follows:

IN

V

IN,MID

=

V

IN(MAX)

+ V

2

IN(MIN)

= 1.55V • 1+






R1
R2






1000

VIN = 5V

VIN = 12V

SWITCHING FREQUENCY (kHz)

100

10

Figure 4a. Switching Frequency vs R

100 1000

R

OFF

VIN = 24V

(kΩ)

OFF

1000

1+R1/R2 = 3.2

= 5V)

(V

IN,MID

1+R1/R2 = 7.7

=12V)

(V

IN,MID

1+R1/R2 = 15.5

= 24V)

(V

IN,MID

SWITCHING FREQUENCY (kHz)

100

3813 F04a

(V

= INTVCC) Figure 4b. Switching Frequency vs R

OFF

10

(V

Connected to a Resistor Divider from VIN)

OFF

100 1000

R

(kΩ)

OFF

3813 F04b

OFF

3813fa

16

V

IN(MAX)

= V

OUT

t

OFF

t

ON(MIN)

+ t

OFF

APPLICATIONS INFORMATION

LTC3813

With these resistor values, the frequency will remain
relatively constant at:

1+ R1/ R2

f =

R

(76pF)

OFF

(Hz)

for the range of 0.45VIN to 1.55 • VIN, and will be propor­tional to V

outside of this range.

IN

Changes in the load current magnitude will also cause
a frequency shift. Parasitic resistance in the MOSFET
switches and inductor reduce the effective voltage across
the inductance, resulting in increased duty cycle as the
load current increases. By shortening the off-time slightly
as current increases, constant-frequency operation can be
maintained. This is accomplished with a resistor connected
from the I

TH

slightly as V

pin to the I

increases. The values required will depend

ITH

pin to increase the I

OFF

OFF

current

on the parasitic resistances in the specifi c application. A
good starting point is to feed about 10% of the R
rent with R

as shown in Figure 6.

ITH

V

IN

R1

V

OFF

OFF

cur-

Minimum On-Time and Dropout Operation

The minimum on-time t

ON(MIN)

is the smallest amount of
time that the LTC3813 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 250ns. The
minimum on-time limit imposes a minimum duty cycle
of t

ON(MIN)

/(t

ON(MIN)

+ t

). If the minimum duty cycle is

OFF

reached, due to a rising input voltage, for example, then
the output will rise out of regulation. The maximum input
voltage to avoid dropout is:

A plot of maximum duty cycle vs switching frequency is
shown in Figure 7.

2.0

1.5

1.0

DROPOUT

REGION

R2

Figure 5. V
Frequency Constant as the Input Supply Varies

V

OUT

Figure 6. Correcting Frequency Shift with Load Current Changes

Connection to Keep the Operating

OFF

R

OFF

1000pF

R

ITH

LTC3813

3813 F05

I

OFF

R

LTC3813

ITH

I

TH

10R

OFF

=

V

OUT

3813 F06

0.5

SWITCHING FREQUENCY (MHz)

0

0 0.25 0.50 0.75

Figure 7. Maximum Duty Cycle vs Switching Frequency

VIN/V

OUT

1.0

3813 F07

Inductor Selection

An inductor should be chosen that can carry the maximum
input DC current which occurs at the minimum input volt­age. The peak-to-peak ripple current is set by the inductance
and a good starting point is to choose a ripple current of
at least 40% of its maximum value:

I

IL= 40% •

O(MAX)

1 D

MAX

3813fa

17

LTC3813

APPLICATIONS INFORMATION

The required inductance can then be calculated to be:

V

IN(MIN)•DMAX

L =

f•I

L

The required saturation of the inductor should be chosen
to be greater than the peak inductor current:

I

L(SAT)



I

O(MAX)

1 D

MAX

I

L

+

2

Once the value for L is known, the type of inductor must
be selected. High effi ciency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy

®

or Kool Mμ

cores. A variety of inductors designed for
high current, low voltage applications are available from
manufacturers such as Sumida, Panasonic, Coiltronics,
Coilcraft and Toko.

Schottky Diode D1 Selection

The Schottky diode D1 shown in the front page schematic
conducts during the dead time between the conduction of
the power MOSFET switches. It is intended to prevent the
body diode of the synchronous MOSFET from turning on
and storing charge during the dead time, which can cause
a modest (about 1%) effi ciency loss. The diode can be
rated for about one half to one fi fth of the full load current
since it is on for only a fraction of the duty cycle. The peak
reverse voltage that the diode must withstand is equal to
the regulator output voltage. In order for the diode to be
effective, the inductance between it and the synchronous
MOSFET must be as small as possible, mandating that
these components be placed adjacently. The diode can
be omitted if the effi ciency loss is tolerable.

Output Capacitor Selection

In a boost converter, the output capacitor requirements
are demanding due to the fact that the current waveform
is pulsed. The choice of component(s) is driven by the
acceptable ripple voltage which is affected by the ESR,
ESL and bulk capacitance as shown in Figure 8e. The total
output ripple voltage is:



V

OUT

= I

O(MAX)




f•C

1

OUT

+

ESR

1–D

MAX






where the fi rst term is due to the bulk capacitance and
second term due to the ESR.

For many designs it is possible to choose a single capacitor
type that satisfi es both the ESR and bulk C requirements
for the design. In certain demanding applications, however,
the ripple voltage can be improved signifi cantly by con­necting two or more types of capacitors in parallel. For
example, using a low ESR ceramic capacitor can minimize
the ESR step, while an electrolytic capacitor can be used
to supply the required bulk C.

LD

V

IN

I

L

8b. Inductor and Input Currents

I

SW

I

D

8d. Diode and Output Currents

V

OUT

(AC)

8e. Output Voltage Ripple Waveform

Figure 8. Switching Waveforms for a Boost Converter

SW

8a. Circuit Diagram

t

ON

8c. Switch Current

t

OFF

ΔV

COUT

ΔV

ESR

V

OUT

C

R

OUT

L

I

IN

I

O

RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)

3813 F08

3813fa

18

APPLICATIONS INFORMATION

LTC3813

Once the output capacitor ESR and bulk capacitance
have been determined, the overall ripple voltage wave­form should be verifi ed on a dedicated PC board (see PC
Board Layout Checklist section for more information on
component placement). Lab breadboards generally suffer
from excessive series inductance (due to inter-component
wiring), and these parasitics can make the switching
waveforms look signifi cantly worse than they would be
on a properly designed PC board.

The output capacitor in a boost regulator experiences high
RMS ripple currents, as shown in Figure 8d. The RMS
output capacitor ripple current is:

I

RMS(COUT)IO(MAX)

V

•

O–VIN(MIN)

V

IN(MIN)

Note that the ripple current ratings from capacitor manu­facturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.

Manufacturers such as Nichicon, Nippon Chemi-con
and Sanyo should be considered for high performance
throughhole capacitors. The OS-CON (organic semicon­ductor dielectric) capacitor available from Sanyo has the
lowest product of ESR and size of any aluminum electrolytic
at a somewhat higher price. An additional ceramic capaci­tor in parallel with OS-CON capacitors is recommended
to reduce the effect of their lead inductance.

In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handling and load step requirements. Dry tantalum, special
polymer and aluminum electrolytic capacitors are available
in surface mount packages. Special polymer capacitors
offer very low ESR but have lower capacitance density
than other types. Tantalum capacitors have the highest
capacitance density but it is important to only use types
that have been surge tested for use in switching power
supplies. Several excellent surge-tested choices are the
AVX TPS and TPSV or the KEMET T510 series. Aluminum
electrolytic capacitors have signifi cantly higher ESR, but

can be used in cost-driven applications providing that
consideration is given to ripple current ratings and long
term reliability. Other capacitor types include Panasonic
SP and Sanyo POSCAPs. In applications with V

OUT

> 30V,
however, choices are limited to aluminum electrolytic and
ceramic capacitors.

Input Capacitor Selection

The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input and the input current waveform
is continuous (see Figure 8b). The input voltage source
impedance determines the size of the input capacitor,
which is typically in the range of 10μF to 100μF. A low
ESR capacitor is recommended though not as critical as
for the output capacitor.

The RMS input capacitor ripple current for a boost con­verter is:

I

RMS(CIN)

= 0.3 •

V

IN(MIN)

L•f

•D

MAX

Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to
the input of the converter and solid tantalum capacitors
can fail catastrophically under these conditions. Be sure

to specify surge-tested capacitors!

Output Voltage

The LTC3813 output voltage is set by a resistor divider
according to the following formula:

V



= 0.8V 1+

OUT







R

FB1



R



FB2

The external resistor divider is connected to the output as
shown in the Functional Diagram, allowing remote voltage
sensing. The resultant feedback signal is compared with
the internal precision 800mV voltage reference by the
error amplifi er. The internal reference has a guaranteed
tolerance of <1%. Tolerance of the feedback resistors
will add additional error to the output voltage. 0.1% to
1% resistors are recommended.

3813fa

19

LTC3813

APPLICATIONS INFORMATION

Input Voltage Undervoltage Lockout

A resistor divider connected from the input supply to the
UVIN pin (see Functional Diagram) is used to program the
input supply undervoltage lockout thresholds. When the
rising voltage at UVIN reaches 0.88V, the LTC3813 turns
on, and when the falling voltage at UVIN drops below 0.8V,
the LTC3813 is shut down—providing 10% hysteresis.
The input voltage UVLO thresholds are set by the resistor
divider according to the following formulas:

V

IN,FALLING

= 0.8V • 1+






R

R

UV1

UV2






and

V

IN,RISING

= 0.88V • 1+






R
R

UV1

UV2






If input supply undervoltage lockout is not needed, it can
be disabled by connecting UVIN to INTV

Top MOSFET Driver Supply (C

An external bootstrap capacitor C

, DB)

B

connected to the BOOST

B

CC

.

pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode D

from DRVCC

B

when the switch node is low. When the top MOSFET turns
on, the switch node rises to V
rises to approximately V

+ DRVCC. The boost capacitor

OUT

and the BOOST pin

OUT

needs to store about 100x the gate charge required by the
top MOSFET. In most applications, 0.1μF to 0.47μF, X5R
or X7R dielectric capacitor is adequate.

The reverse breakdown of the external diode, D
greater than V

. Another important consideration for the

OUT

, must be

B

external diode is the reverse recovery and reverse leakage,
either of which may cause excessive reverse current to fl ow
at full reverse voltage. If the reverse current times reverse
voltage exceeds the maximum allowable power dissipa­tion, the diode may be damaged. For best results, use an
ultrafast recovery diode such as the MMDL770T1.

Bottom MOSFET Driver Return Supply (BGRTN)

The bottom gate driver, BG, switches from DRV

CC

to
BGRTN where BGRTN can be a voltage between ground
and –5V. Why not just keep it simple and always connect
BGRTN to ground? In high voltage switching converters,

the switch node dV/dt can be many volts/ns, which will
pull up on the gate of the bottom MOSFET through its
Miller capacitance. If this Miller current, times the internal
gate resistance of the MOSFET plus the driver resistance,
exceeds the threshold of the FET, shoot-through will oc­cur. By using a negative supply on BGRTN, the BG can be
pulled below ground when turning the bottom MOSFET off.
This provides a few extra volts of margin before the gate
reaches the turn-on threshold of the MOSFET. Be aware
that the maximum voltage difference between DRV
BGRTN is 14V. If, for example, V
voltage on DRV

pin is now 12V instead of 14V.

CC

IC/MOSFET Driver Supplies (INTV

= –2V, the maximum

BGRTN

and DRVCC)

CC

The LTC3813 drivers are supplied from the DRV
and the LTC3813 internal circuits from INTV

CC

and

CC

pin

CC

pin (see

Figure 1). These pins have an operating range between

6.2V and 14V. If the input voltage or another supply is not
available in this voltage range, two internal regulators are
provided to simplify the generation of this IC/driver supply
voltage as described in the next sections.

The N

The N

Pin Regulator

DRV

pin controls the gate of an external NMOS as

DRV

shown in Figure 9b and can be used to generate a regulated
10V supply from V

IN

or V

it can be chosen with a BV

. Since the NMOS is external,

OUT

or power rating as high

DSS

as necessary to safely derive power from a high voltage
input or output voltage. In order to generate an INTV

CC

supply that is always above the 6.2V UV threshold, the
supply connected to the drain must be greater than 6.2V
+ R

The EXTV

• 40μA + VT.

NDRV

Pin Regulator

CC

A second low dropout regulator is available for voltages
≤ 15V. When a supply that is greater than 6.7V is con­nected to the EXTV
10V on INTV

from the EXTVCC pin voltage and will also

CC

pin, the internal LDO will regulate

CC

disable the NDRV pin regulator. This regulator is disabled
when the IC is shut down, when INTV
EXTV

< 6.7V.

CC

< 6.2V, or when

CC

20

3813fa

APPLICATIONS INFORMATION

LTC3813

Using the INTVCC Regulators

One, both or neither of these regulators can be used to
generate the 10V IC/driver supply depending on the circuit
requirements, available supplies, and the voltage range

or V

of V

IN

effi cient, however deriving it from V
of maintaining regulation of V

. Deriving the 10V supply from VIN is more

OUT

has the advantage

OUT

when VIN drops below

OUT

the UV threshold. Four possible confi gurations are shown
in Figures 9a through 9d, and are described as follows:

1. Figure 9a. If the V

voltage or another low voltage

IN

supply between 6.2V and 14V is available, the sim­plest approach is to connect this supply directly to the
INTV
disabled by shorting NDRV and EXTV

2. Figure 9b. If V

and DRVCC pins. The internal regulators are

CC

to INTVCC.

CC

IN(MAX)

> 14V, an external NMOS con­nected to the NDRV pin can be used to generate 10V
from V

IN

. V

must be > 6.2V + R

IN(MIN)

• 40μA + VT

NDRV

to keep INTV

above the UV threshold and the BV

CC

DSS

of the external NMOS must be chosen to be greater
than V

IN(MAX)

grounding the EXTV

3. Figure 9c. If the V

. The EXTVCC regulator is disabled by

pin.

CC

IN(MAX)

< 14.7V and VIN is allowed to
fall below 6.2V without disrupting the boost converter
operation, use this confi guration. The INTV
is derived from V

IN

is derived from V

until the V

, VIN can fall below the 6V UV

OUT

> 6.7V. Once INTVCC

OUT

threshold without losing regulation of V
in this confi guration, V

must be > 7V at least long

IN

enough to start up the LTC3813 and charge V

6.7V. Also, since V
this confi guration is limited to V

is connected to the EXTVCC pin,

OUT

< 15V.

OUT

4. Figure 9d. Similar to confi guration 3 except that V
is allowed to be >15V since V

is connected to an

OUT

external NMOS with appropriately rated BV

supply

CC

. Note that

OUT

. VIN has

DSS

OUT

OUT

same start-up requirement as 3.

V

IN

>

NDRV

INTV

LTC3813

EXTV

(a) 6.2V to 14V

Supply Available

NDRV

INTV

LTC3813

EXTV

(c) INTVCC from V

V

≤ 15V

OUT

CC

CC

CC

CC

OUT

VIN < 14.7V

+

V

OUT

,

R

NDRV

NDRV

INTV

EXTV

CC

CC

+

+

6.2V to

–

14V

LTC3813

10V

+

(b) INTVCC from VIN,

10V

≤ 15V

VIN > 14V

NDRV

INTV

LTC3813

EXTV

(d) INTVCC from V

V

> 15V

OUT

CC

CC

OUT

,

R

NDRV

V

OUT

+

VIN < 14.7V

10V

3813 F09

Figure 9. Four Possible Ways to Generate INTVCC Supply

3813fa

21

LTC3813

APPLICATIONS INFORMATION

Power Dissipation Considerations

Applications using large MOSFETs and high frequency
of operation may result in a large DRV

/INTVCC supply

CC

current. Therefore, when using the linear regulators, it is
necessary to verify that the resulting power dissipation
is within the maximum limits. The DRV

/INTVCC supply

CC

current consists of the MOSFET gate current plus the
LTC3813 quiescent current:

I

CC

= (f)(Q

G(TOP)

+ Q

G(BOTTOM)

) + 3mA

When using the internal LDO regulator, the power dissipa­tion is internal so the rise in junction temperature can be
estimated from the equation given in Note 2 of the Electrical
Characteristics as follows:

T

J

= TA + I

EXTVCC

• (V

EXTVCC

– V

INTVCC

)(100°C/W)

and must not exceed 125°C.

Likewise, if the external NMOS regulator is used, the worst
case power dissipation is calculated to be:

P

MOSFET

= (V

DRAIN(MAX)

– 10V) • I

CC

and can be used to properly size the device.

FEEDBACK LOOP/COMPENSATION

Introduction

In a typical LTC3813 circuit, the feedback loop consists of
two sections: the modulator/output stage and the feedback
amplifi er/compensation network. The modulator/output
stage consists of the current sense component and in­ternal current comparator, the power MOSFET switches
and drivers, and the output fi lter and load. The transfer
function of the modulator/output stage for a boost con­verter consists of an output capacitor pole, R
an ESR zero, R
(R

/L)(V

L

IN

2

/V

ESRCOUT

OUT

, and also a “right-half plane” zero,

2

). It has a gain/phase curve that is typi-

LCOUT

, and

cally like the curve shown in Figure 10 and is expressed
mathematically in the following equation.

H(s)=

V

(s)

OUT

V

(s)

ITH



1+ s•R

•



1+ s•RL•C




•1 s•




s = j2 f



R

L•VIN•VSENSE(MAX)

=



2.4 • V



ESR•COUT

L

R

L

OUT•RDS(ON)

OUT

2

V

OUT

•

2

V

IN
















(1)

This portion of the power supply is pretty well out of the
user’s control since the current sense is chosen based on
maximum output load, and the output capacitor is usually
chosen based on load regulation and ripple requirements
without considering AC loop response. The feedback am­plifi er, on the other hand, gives us a handle on which to
adjust the AC response. The goal is to have an 180° phase
shift at DC so the loop regulates and less than 360° phase
shift at the point where the loop gain falls below 0dB, i.e.,
the crossover frequency, with as much gain as possible
at frequencies below the crossover frequency. Since the
feedback amplifi er adds an additional 90° phase shift to
the phase shift already present from the modulator/output
stage, some phase boost is required at the crossover
frequency to achieve good phase margin. The design
procedure (described in more detail in the next section) is
to (1) obtain a gain/phase plot of modulator/output stage,
(2) choose a crossover frequency and the required phase
boost, and (3) calculate the compensation network.

180

90

GAIN

00

GAIN (dB)

PHASE

PHASE (DEG)

–90

22

FREQUENCY (Hz)

Figure 10. Bode Plot of Boost Modulator/Output Stage

–180

3813 F10

3813fa

APPLICATIONS INFORMATION

LTC3813

IN

3813 F12

R1

R

IN

3813 F11

B

C2

C1

R2

R1

FB

–

R

B

V

+

REF

OUT

GAIN (dB)

GAIN

0

PHASE

–6dB/OCT

–6dB/OCT

PHASE (DEG)

FREQ

–90

–180

–270

–360

Figure 11. Type 2 Schematic and Transfer Function

C2

C3

R3

FB

–

V

+

REF

C1

R2

OUT

GAIN (dB)

GAIN

0

–6dB/OCT

+6dB/OCT –6dB/OCT

PHASE

PHASE (DEG)

FREQ

–90

–180

–270

–360

Figure 12. Type 3 Schematic and Transfer Function

The two types of compensation networks, Type 2 and Type
3 are shown in Figures 11 and 12. When component values
are chosen properly, these networks provide a “phase
bump” at the crossover frequency. Type 2 uses a single
pole-zero pair to provide up to about 60° of phase boost
while Type 3 uses two poles and two zeros to provide up
to 150° of phase boost.

The compensation of boost converters are complicated
by two factors: the RHP zero and the dependence of the
loop gain on the duty cycle. The RHP zero adds additional
phase lag and gain. The phase lag degrades phase margin
and the added gain keeps the gain high typically in the
frequency region where the user is trying the roll off the
gain below 0dB. This often forces the user to choose a
crossover frequency at a lower frequency than originally
desired. The duty cycle effect of gain (see above transfer
function) causes the phase margin and crossover frequency
to be dependent on the input supply voltage which may
cause problems if the input voltage varies over a wide range
since the compensation network can only be optimized

for a specifi c crossover frequency. These two factors
usually can be overcome if the crossover frequency is
chosen low enough.

Feedback Component Selection

Selecting the R and C values for a typical Type 2 or
Type 3 loop is a nontrivial task. The applications shown
in this data sheet show typical values, optimized for the
power components shown. They should give acceptable
performance with similar power components, but can be
way off if even one major power component is changed
signifi cantly. Applications that require optimized transient
response will require recalculation of the compensation
values specifi cally for the circuit in question. The underly­ing mathematics are complex, but the component values
can be calculated in a straightforward manner if we know
the gain and phase of the modulator at the crossover
frequency.

Modulator gain and phase can be obtained in one of
three ways: measured directly from a breadboard, or if

3813fa

23

LTC3813

APPLICATIONS INFORMATION

the appropriate parasitic values are known, simulated or
generated from the modulator transfer function. Mea­surement will give more accurate results, but simulation
or transfer function can often get close enough to give
a working system. To measure the modulator gain and
phase directly, wire up a breadboard with an LTC3813
and the actual MOSFETs, inductor and input and output
capacitors that the fi nal design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close
to the LTC3813, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
amplifi er with a 0.1μF feedback capacitor from I
and a 10k to 100k resistor from V
bias resistor (R
voltage. Disconnect R

) as required to set the desired output

B

from ground and connect it to

B

to FB. Choose the

OUT

to FB

TH

a signal generator or to the source output of a network
analyzer to inject a test signal into the loop. Measure the
gain and phase from the I

pin to the output node at the

TH

positive terminal of the output capacitor. Make sure the
analyzer’s input is AC coupled so that the DC voltages
present at both the I

and V

TH

nodes do not corrupt

OUT

the measurements or damage the analyzer.

If breadboard measurement is not practical, mathemat­ical software such as MATHCAD or MATLAB can be used
to generate plots from the transfer function given in
equation 1. A SPICE simulation can also be used to gener­ate approximate gain/phase curves. Plug the expected
capacitor, inductor and MOSFET values into the following
SPICE deck and generate an AC plot of V

OUT/VITH

with gain
in dB and phase in degrees. Refer to your SPICE manual
for details of how to generate this plot.

*This fi le simulates a simplifi ed model of
the LTC3813 for generating a v(out)/(vith)
or a v(out)/v(outin) bode plot

.param vout=24
.param vin=12
.param L=10u
.param cout=270u
.param esr=.018
.param rload=24
*

.param rdson=0.02
.param Vrng=1
.param vsnsmax={0.173*Vrng-0.026}
.param K={vsnsmax/rdson/1.2}
.param wz={1/esr/cout}
.param wp={2/rload/cout}
*
* Feedback Amplifi er
rfb1 outin vfb 29k
rfb2 vfb 0 1k
eithx ithx 0 laplace {0.8-v(vfb)} =
{1/(1+s/1000)}
eith ith 0 value={limit(1e6*v(ithx),0,2.4)}
cc1 ith vfb 100p
cc2 ith x1 0.01μ
rc x1 vfb 100k
*
* Modulator/Output Stage
eout out 0 laplace {v(ith)} =
{0.5*K*Rload*vin/vout *(1+s/wz)/(1+s/wp)
*(1-s*L/Rload*vout*vout/vin/vin)}
rload out 0 {rload}
*
vstim out outin dc=0 ac=10m; ac stimulus
.ac dec 100 10 10meg
.probe
.end

With the gain/phase plot in hand, a loop crossover fre­quency can be chosen. Usually the curves look something
like Figure 10. Choose the crossover frequency about 25%
of the switching frequency for maximum bandwidth. Al­though it may be tempting to go beyond f

/4, remember

SW

that signifi cant phase shift occurs at half the switching
frequency that isn’t modeled in the above H(s) equation
and PSPICE code. Note the gain (GAIN, in dB) and phase
(PHASE, in degrees) at this point. The desired feedback
amplifi er gain will be –GAIN to make the loop gain at 0dB
at this frequency. Now calculate the needed phase boost,
assuming 60° as a target phase margin:

BOOST = – (PHASE + 30°)

If the required BOOST is less than 60°, a Type 2 loop can
be used successfully, saving two external components.
BOOST values greater than 60° usually require Type 3
loops for satisfactory performance.

3813fa

24

I

LIMIT

=

V

SNS(MAX)

R

DS(ON)T



1

2

I

L

APPLICATIONS INFORMATION

LTC3813

Finally, choose a convenient resistor value for R1 (10k
is usually a good value). Now calculate the remaining
values:

(K is a constant, used in the calculations)

f = chosen crossover frequency

G = 10
absolute gain)

TYPE 2 Loop:

C2 =

C1= C2 K

R2 =

R

TYPE 3 Loop:

C2 =

C1= C2 K 1

R2 =

R3 =

C3 =

(GAIN/20)

K = tan

2 •f•G•K •R

()

2 •f•C1

V

REF

=

B

V

OUT

K = tan

2

2 •f•G•R

()

2 •f•C

R1

K 

2fK

(this converts GAIN in dB to G in

BOOST






2

K

 V

BOOST






1

K

1

1

2

1

1

(R1)

REF

4

1

1

•R3

+ 45°

1

+ 45°











SPICE or mathematical software can be used to generate
the gain/phase plots for the compensated power supply to
do a sanity check on the component values before trying
them out on the actual hardware. For software, use the
following transfer function:

T(s) = A(s)H(s)

where H(s) was given in equation 1 and A(s) depends on
compensation circuit used:

Type 2:

A (s)=

s•R1• C2+ C3

Type 3:

A (s)=

For SPICE, simulate the previous PSPICE code with
calculated compensation values entered and generate a
gain/phase plot of V

Fault Conditions: Current Limit

The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3813, the maximum sense voltage is controlled
by the voltage on the V
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor peak current.
The corresponding output current limit is:

s•R1• C2+ C3

1+ s• R1+ R3

()

1+ s•R3•C3

()

1+ s•R3•C2



()

1

•1+ s•R3•





•

( )

•C3

()

OUT/VOUTIN

pin. With peak current control,

RNG

•1+ s•R2•C1

()



•1+ s•R2•





.

C1• C2

C1+ C2

C2 • C3

C2 + C3











(R1)

V

R

B

REF

=

V

 V

OUT

REF

The current limit value should be checked to ensure that
I

LIMIT(MIN)

generally occurs at the lowest V
temperature, conditions that cause the largest power loss
in the converter. Note that it is important to check for

> I

OUT(MAX)

. The minimum value of current limit

at the highest ambient

IN

3813fa

25

LTC3813

APPLICATIONS INFORMATION

self-consistency between the assumed MOSFET junction
temperature and the resulting value of I

which heats

LIMIT

the MOSFET switches.

Caution should be used when setting the current limit
based upon the R

of the MOSFETs. The maximum

DS(ON)

current limit is determined by the minimum MOSFET
on-resistance. Data sheets typically specify nominal
and maximum values for R
A reasonable assumption is that the minimum R

, but not a minimum.

DS(ON)

DS(ON)

lies the same percentage below the typical value as the
maximum lies above it. Consult the MOSFET manufacturer
for further guidelines.

Note that in a boost mode architecture, it is only possible
to provide protection for “soft” shorts where V

OUT

> VIN.
For hard shorts, the inductor current is limited only by the
input supply capability.

Soft-Start

The LTC3813 has the ability to soft-start with a capacitor
connected to the SS pin. The LTC3813 is put in a low
quiescent current shutdown state (I

~240μA) if the

Q

SHDN pin voltage is below 1.5V. The SS pin is actively
pulled to ground in this shutdown state. Once the SHDN
pin voltage is above 1.5V, the LTC3813 is powered up. A
soft-start current of 1.4μA then starts to charge the soft­start capacitor C

. Soft-start is achieved by limiting the

SS

maximum output current of the controller by controlling
the ramp rate of the I

voltage. The total soft-start time

TH

can be calculated as:

t

SOFTSTART

 2.4 •

C

SS

1.4μA

Phase-Locked Loop and Frequency Synchronization

the phase-locked loop function. The pulse width of the
clock has to be greater than 400ns and the amplitude of
the clock should be greater than 2V.

The internal oscillator locks to the external clock after the
second clock transition is received. If an external clock
transition is not detected for three successive periods, the
internal oscillator will revert to the frequency programmed
by the R

resistor.

OFF

During the start-up phase, phase-locked loop function is
disabled. When LTC3813 is not in synchronization mode,
PLL/LPF pin voltage is set to around 1.215V. Frequency
synchronization is accomplished by changing the inter­nal off-time current according to the voltage on the
PLL/LPF pin.

The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the ex­ternal and internal pulses. This type of phase detector will
not lock up on input frequencies close to the harmonics
of the V
is equal to the capture range, Δf

ΔfH = ΔfC = ±0.3 f

center frequency. The PLL hold-in range, ΔfH,

CO

C:

O

The output of the phase detector is a complementary pair of
current sources charging or discharging the external fi lter

/LPF

network on the PLL
is shown in Figure 13

2.4V

SYNC

DIGITAL

PHASE/

FREQUENCY

DETECTOR

pin. A simplifi ed block diagram

.

R

LP

C

PLL/LPF

VCO

LP

The LTC3813 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is ±30% around the
center frequency f

. The center frequency is the operating

O

frequency discussed in the Operating Frequency section.
The LTC3813 incorporates a pulse detection circuit that
will detect a clock on the SYNC pin. In turn, it will turn on

26

3813 F13

Figure 13. Phase-Locked Loop Block Diagram

3813fa

APPLICATIONS INFORMATION

LTC3813

If the external frequency (f
lator frequency f

, current is sourced continuously, pull-

O

) is greater than the oscil-

SYNC

ing up the PLL/LPF pin. When the external frequency is
less than f

, current is sunk continuously, pulling down

O

the PLL/LPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLL/LPF
pin is adjusted until the phase and frequency of the external
and internal oscillators are identical. At this stable operating
point the phase comparator output is open and the fi lter
capacitor C

holds the voltage. The LTC3813 SYNC pin

LP

must be driven from a low impedance source such as a
logic gate located close to the pin.

The loop fi lter components (C

, RLP) smooth out the

LP

current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The fi lter
components C
acquires lock. Typically R

and RLP determine how fast the loop

LP

= 10kΩ and CLP is 0.01μF

LP

to 0.1μF.

Pin Clearance/Creepage Considerations

The LTC3813 is available in the G28 package which
has 0.0106" spacing between adjacent pins. To
maximize PC board trace clearance between high volt­age pins, the LTC3813 has three unconnected pins
between all adjacent high voltage and low voltage
pins, providing 4(0.0106") = 0.042" clearance which
will be suffi cient for most applications up to 100V.
For more information, refer to the printed circuit board
design standards described in IPC-2221 (www.ipc.org).

Effi ciency Considerations

The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3813 circuits:

2

1. DC I

R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause
the effi ciency to drop at high input currents. The input

current is maximum at maximum output current and
minimum input voltage. The average input current fl ows
through L, but is chopped between the top and bottom
MOSFETs. If the two MOSFETs have approximately the
same R

, then the resistance of one MOSFET can

DS(ON)

simply be summed with the resistances of L and the

2

board traces to obtain the DC I
R

= 0.01Ω and RL = 0.005Ω, the loss will range

DS(ON)

R loss. For example, if

from 15mW to 1.5W as the input current varies from
1A to 10A.

2. Transition loss. This loss arises from the brief amount
of time the bottom MOSFET spends in the saturated
region during switch node transitions. It depends upon
the output voltage, load current, driver strength and
MOSFET capacitance, among other factors. The loss
is signifi cant at output voltages above 20V and can be
estimated from the second term of the P

MAIN

equa­tion found in the Power MOSFET Selection section.
When transition losses are signifi cant, effi ciency can
be improved by lowering the frequency and/or using a
bottom MOSFET(s) with lower C
higher R

DS(ON)

.

at the expense of

RSS

3. INTVCC/DRVCC current. This is the sum of the MOSFET
driver and control currents. Control current is typically
about 3mA and driver current can be calculated by:
I

GATE

= f(Q

G(TOP)

+ Q

G(BOT)

), where Q

G(TOP)

and Q

G(BOT)

are the gate charges of the top and bottom MOSFETs.
This loss is proportional to the supply voltage that
INTVCC/DRVCC is derived from, i.e., VIN, V

OUT

or an

external supply connected to INTVCC/DRVCC.

4. C

loss. The output capacitor has the diffi cult job

OUT

tering the large RMS input current out of the syn-

of fi l
chronous MOSFET. It must

have a very low ESR to

minimize the AC I2R loss.

Other losses, including CIN ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss. When
making adjustments to improve effi ciency, the input cur­rent is the best indicator of changes in effi ciency. If you
make a change and the input current decreases, then the
effi ciency has increased. If there is no change in input
current, then there is no change in effi ciency.

3813fa

27

LTC3813

APPLICATIONS INFORMATION

Checking Transient Response

The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
load step occurs, V
equal to ΔI
resistance of C
charge C

OUT

(ESR), where ESR is the effective series

LOAD

OUT

generating a feedback error signal used by the
regulator to return V
this recovery time, V

immediately shifts by an amount

OUT

. ΔI

also begins to charge or dis-

LOAD

to its steady-state value. During

OUT

can be monitored for overshoot

OUT

or ringing that would indicate a stability problem.

Design Example

As a design example, take a supply with the following speci­fi cations: VIN = 12V± 20%, V

= 24V ±5%, I

OUT

OUT(MAX)

=
5A, f = 250kHz. Since VIN can vary around the 12V nominal
value, connect a resistive divider from VIN to V

to keep

OFF

the frequency independent of VIN changes:

12V

R1

=

2

1.55V

R

 1= 6.74

The peak inductor current is:

=

1 0.5

5A

I

L(PEAK)

Choose the CDEP147 5.9μH inductor with I

1

+

(4A)= 12A

2

= 16.4A

SAT

at 100°C.

Next, choose the bottom MOSFET switch. Since the drain
of the MOSFET will see the full output voltage plus any
ringing, choose a 40V MOSFET to provide a margin of
safety. The Si7848DP has:

BV
R
δ
C
V
θ

= 40V

DSS

= 9mΩ(max)/7.5mΩ(nom),

DS(ON)

= 0.006/°C,

= (14nC – 6nC)/20V = 400pF,

MILLER
GS(MILLER)

= 20°C/W.

JA

= 3.5V,

This yields a nominal sense voltage of:

V

SNS(NOM)

1.7 • 0.0075 •5A

=

1 0.5

= 128mV

Choose R1 = 133k and R2 = 20k. Now calculate timing
resistor R

R

OFF

:

OFF

1+ 133k / 20k

=

250kHz • 76pF

= 402.6k

The duty cycle is:

D= 1

12V
24V

= 0.5

and the maximum input current is:

=

1 0.5

5A

= 10A

I

IN(MAX)

Choose the inductor for about 40% ripple current at the
maximum V

L =

250kHz • 0.4 • 10A

IN

:

12V

12V



1





24V



= 6μH





To guarantee proper current limit at worst-case conditions,
increase nominal V
current limit is acceptable at V

by 50% to 190mV. To check if the

SNS

= 190mV, assume a

SNS

junction temperature of about 30°C above a 70°C ambient
(ρ

I

and double-check the assumed T

= 1.4):

100°C

I

IN(MAX)

OUT(MAX)

P

TOP



1.4 • 0.009

= I



=





1 0.5

190mV

IN(MAX)

1

• (1-D



6.5A

()





1



•4A = 13A

2

) = 6.5A

MAX

in the MOSFET:

J

2

(1.4)(0.009) = 1.06W

TJ = 70°C + 1.06W • 20°C/W = 91°C

28

3813fa

APPLICATIONS INFORMATION

LTC3813

Verify that the Si7848DP is also a good choice for the
bottom MOSFET by checking its power dissipation at
current limit and minimum input voltage, assuming a
junction temperature of 30°C above a 70°C ambient
(ρ

= 1.4):

100°C

P

BOT

1

+

2



•





12V  3.5

= 0.5

(24V)

1






1 0.5



2





V

6.5A

1

6.5A

0.5

+

3.5V

2



(1.4)(0.009)







(2)(400pF)





1



(250kHz)





= 1.06W + 0.30W = 1.36W

TJ = 70°C + 1.36W • 20°C/W = 97°C

The junction temperature will be signifi cantly less at
nominal current, but this analysis shows that careful at­tention to heat sinking on the board will be necessary in
this circuit.

V

OUT

PGOOD

SHDN

R

UV1

115k

R

UV2

10k

133k

20k

R

1k

FB2

C

SS

1000pF

R
250k

C

C2

470pF

C

C

OFF

100pF

C

C1

47pF

R

OFF

403k

10

11

12
13

14

1

4
5
6
7
8
9

LTC3813

I

OFF

V

OFF

V

RNG

PGOOD
SYNC
I

TH

V

FB

PLL/LPF

SS

SGND

SHDN

VIN

U

SGND PGND

R

FB1

29.4k

BOOST

SENSE
SENSE

BGRTN

DRV

INTV

EXTV

NDRV

TG

SW

BG

28

27

26

25

+

21

–

20

19
18

CC

17

CC

16

CC

15

Since V
nected directly to the INTV

C

OUT

is always between 6.2V and 14V, it can be con-

IN

and DRVCC pins.

CC

is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR
of 0.018Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:

V

OUT(RIPPLE)

= 0.25V (about 1%)

= (5A)




250kHz • 330μF



1

+

0.018

1 0.5






A 0A to 5A load step will cause an output change of up to:

ΔV

OUT(STEP)

= ΔI

• ESR = 5A • 0.018Ω

LOAD

= 90mV

An optional 10μF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 14.

V

C

IN2

1μF
20V

PGND

M1
Si7848DP

12V

IN

V

OUT

24V
5A

C

OUT

330μF
35V

× 2

C

B

0.1μF

C

DRVCC

0.1μF

10

CV
1μF

CC

BAS19

Ω

DB

C5
22μF

L1

μ

H

5.9

M2
Si7848DP

C

IN1

68μF
20V

D1

B1100

3813 F14

Figure 14. 12V Input Voltage to 24V/5A

3813fa

29

LTC3813

APPLICATIONS INFORMATION

PC Board Layout Checklist

When laying out a PC board follow one of two suggested
approaches. The simple PC board layout requires a dedi­cated ground plane layer. Also, for higher currents, it is
recommended to use a multilayer board to help with heat
sinking power components.

• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.

• Place C

IN

, C

, MOSFETs, D1 and inductor all in one

OUT

compact area. It may help to have some components
on the bottom side of the board.

•

Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3813.
Use several bigger vias for power components.

• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.

• Use planes for V

and V

IN

to maintain good voltage

OUT

fi ltering and to keep power losses low.

• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
component. You can connect the copper areas to any
DC net (V

IN

, V

, GND or to any other DC rail in your

OUT

system).

When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera­tion of the controller.

• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.

• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.

•

Connect the input capacitor(s) CIN close to the pow­er MOSFETs. This capacitor carries the MOSFET AC
current.

• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.

• Connect the INTV
to the INTV

CC

• Connect the top driver boost capacitor C

decoupling capacitor C

CC

and SGND pins.

closely

VCC

closely to

B

the BOOST and SW pins.

• Connect the bottom driver decoupling capacitor C
closely to the DRV

and BGRTN pins.

CC

DRVCC

30

3813fa

PACKAGE DESCRIPTION

G Package

28-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

1.25 ±0.12

2526 22 21 20 19 181716 1523242728

LTC3813

9.90 – 10.50*
(.390 – .413)

7.8 – 8.2

0.42 ±0.03

RECOMMENDED SOLDER PAD LAYOUT

5.00 – 5.60**
(.197 – .221)

0.09 – 0.25

(.0035 – .010)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE
*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

0.55 – 0.95

(.022 – .037)

MILLIMETERS

(INCHES)

5.3 – 5.7

0.65 BSC

0° – 8°

12345678 9 10 11 12 1413

0.65

(.0256)

BSC

0.22 – 0.38

(.009 – .015)

TYP

2.0

(.079)

MAX

0.05

(.002)

MIN

G28 SSOP 0204

7.40 – 8.20

(.291 – .323)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3813fa

31

LTC3813

TYPICAL APPLICATION

V

143k

C

OFF

100pF

10k

PGOOD
250kHz

CLOCK

SHDN

R

UV1

140k

R
10k

UV2

0.01

R

499Ω

FB2

μ

F

1000pF

10k

C

SS

C

C2

R

C

300k

330pF

C

C1

150pF

24V Input Voltage to 50V/5A Synchronized at 250kHz

OUT

R
806k

OFF

10

11

12
13

14

1

4

5
6

7
8
9

LTC3813

I

OFF

V

OFF

V

RNG

PGOOD
SYNC
I

TH

V

FB

PLL/LPF

SS

SGND

SHDN

U

VIN

SGND PGND

30.9k

R

FB1

BOOST

SENSE

SENSE

BGRTN

DRV

INTV

EXTV

NDRV

TG
SW

28

27

26

25

+

21

–

20

19

BG

18

CC

17

CC

16

CC

15

R

NDRV

100k

CB, 0.1μF

C

DRVCC

0.1μF

CV

CC

1μF

DB

BAS19

10

Ω

M3
ZXMN10A07F

C5

μ

F

1

L1

μ

10

M2
Si7850

× 2

H

D1

B1100

C

IN1

68μF
50V

3813 TA02

M1
Si7850DP

C

IN2

1μF
50V

PGND

V
12V TO 40V

C

OUT1

220μF
63V

× 2

IN

V

OUT

50V
5A

C

OUT2

10μF

× 2

100V

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Linear Technology Corporation

32

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

VIN Up to 36V

, Current Mode Control, 2.5V ≤ VIN ≤ 36V

SENSE

, Current Mode Control, 50kHz to 1MHz

SENSE

6V ≤ VIN ≤ 40V

VIN and V

OUT

16V, Miniature Design

IN

Limited Only by External Components

LT 0807 REV A • PRINTED IN USA

© LINEAR TECHNOLOGY CORPORATION 2007

IN

≤ 5V

3813fa