Page 1
FEATURES
No R
Wide Operating Range,
TM
SENSE
Step-Down Controller
DESCRIPTIO
LTC3778
U
■
Wide VIN Range: 4V to 36V
■
Sense Resistor Optional
■
True Current Mode Control
■
2% to 90% Duty Cycle at 200kHz
■
t
ON(MIN)
■
Stable with Ceramic C
■
Dual N-Channel MOSFET Synchronous Drive
■
Power Good Output Voltage Monitor
■
±1% 0.6V Reference
■
Adjustable Current Limit
■
Adjustable Switching Frequency
■
Programmable Soft-Start
■
Output Overvoltage Protection
■
Optional Short-Circuit Shutdown Timer
■
Micropower Shutdown: IQ ≤ 30µA
■
Available in a 1mm 20-Lead TSSOP Package
≤ 100ns
OUT
U
APPLICATIO S
■
Notebook and Palmtop Computers, PDAs
■
Battery Chargers
■
Distributed Power Systems
■
DDR Memory Power Supply
■
Automobile DC Power Supply
The LTC®3778 is a synchronous step-down switching
regulator controller for computer memory, automobile
and other DC/DC power supplies. The controller uses a
valley current control architecture to deliver very low duty
cycles without requiring a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in V
IN
and V
OUT
.
Discontinuous mode operation provides high efficiency
operation at light loads. A forced continuous control pin
reduces noise and RF interference, and can assist secondary winding regulation when the main output is lightly
loaded. SENSE+ and SENSE– pins provide true Kelvin
sensing across the optional sense resistor or the
sychronous MOSFET.
Fault protection is provided by internal foldback current
limiting, an output overvoltage comparator, optional shortcircuit shutdown timer and input undervoltage lockout.
Soft-start capability for supply sequencing is accomplished using an external timing capacitor. The regulator
current limit level is user programmable. Wide supply
range allows operation from 4V to 36V at the input and
from 0.6V up to (0.9)VIN at the output.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No R
is a trademark of Linear Technology Corporation.
SENSE
TYPICAL APPLICATIO
1.4M
I
TH
LTC3778
SENSE
SENSE
BOOST
INTV
DRV
PGND
ON
V
IN
TG
SW
CB 0.22µF
CC
CC
BG
+
+
–
V
FB
C
500pF
C
SS
0.1µF
20k
RUN/SS
I
R
C
SGND
PGOOD
C
Figure 1. High Efficiency Step-Down Converter
R
ON
D
B
CMDSH-3
C
VCC
4.7µF
U
M1
Si4884
M2
Si4874
L1
1.8µH
D1
B340A
+
R2
40.2k
R1
12.7k
C
IN
10µF
35V
×3
C
OUT
180µF
4V
×2
V
IN
5V TO 28V
V
OUT
2.5V
10A
3778 F01a
Efficiency vs Load Current
100
VIN = 5V
90
VIN = 25V
80
EFFICIENCY (%)
70
60
0.01
0.1
LOAD CURRENT (A)
1
10
3778 F01b
3778f
1
Page 2
LTC3778
WWWU
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
UU
W
(Note 1)
Input Supply Voltage (VIN, ION)..................36V to –0.3V
Boosted Topside Driver Supply Voltage
(BOOST) ................................................... 42V to –0.3V
SENSE+, SW Voltage.................................... 36V to –5V
DRVCC, EXTVCC, (BOOST – SW), FCB,
RUN/SS, PGOOD Voltages .................... 7V to –0.3V
V
ON, VRNG
Voltages................... INTVCC + 0.3V to –0.3V
ITH, VFB Voltages...................................... 2.7V to –0.3V
TG, BG, INTVCC Peak Currents.................................. 2A
TG, BG, INTVCC RMS Currents ............................ 50mA
Operating Ambient Temperature
Range (Note 4) ................................... –40°C to 85°C
Junction Temperature (Note 2)............................ 125°C
1
RUN/SS
2
V
ON
3
PGOOD
4
V
RNG
5
I
TH
6
FCB
7
SGND
8
I
ON
9
V
FB
10
EXTV
CC
20-LEAD PLASTIC TSSOP
T
= 125°C, θJA = 110°C/W
JMAX
TOP VIEW
F PACKAGE
20
BOOST
19
TG
18
SW
SENSE
SENSE
PGND
BG
DRV
INTV
V
IN
+
–
CC
CC
17
16
15
14
13
12
11
ORDER PART
NUMBER
LTC3778EF
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
I
Q
V
FB
∆V
FB(LINEREG)
∆V
FB(LOADREG)
I
FB
g
m(EA)
V
FCB
I
FCB
t
ON
t
ON(MIN)
t
OFF(MIN)
V
SENSE(MAX)
V
SENSE(MIN)
∆V
FB(OV)
∆V
FB(UV)
Input DC Supply Current
Normal 900 2000 µA
Shutdown Supply Current 15 30 µA
Feedback Reference Voltage ITH = 1.2V (Note 3) ● 0.594 0.600 0.606 V
Feedback Voltage Line Regulation VIN = 4V to 30V, ITH = 1.2V (Note 3) 0.002 %/V
Feedback Voltage Load Regulation ITH = 0.5V to 1.9V (Note 3) –0.05 –0.3 %
Feedback Pin Input Current –5 ±100 nA
Error Amplifier Transconductance ITH = 1.2V (Note 3) ● 1.4 1.7 2 mS
Forced Continuous Threshold ● 0.57 0.6 0.63 V
Forced Continuous Pin Current V
On-Time ION = 60µA, VON = 1.5V 200 250 300 ns
Minimum On-Time ION = 180µA, VON = 0V 50 100 ns
Minimum Off-Time ION = 60µA, VON = 1.5V 250 400 ns
Maximum Current Sense Threshold V
–
– V
V
SENSE
Minimum Current Sense Threshold V
+
– V
V
SENSE
SENSE
SENSE
+
–
Output Overvoltage Fault Threshold 7.5 10 12.5 %
Output Undervoltage Fault Threshold 340 400 460 mV
The ● denotes specifications which apply over the full operating
= 0.6V –1 –2 µA
FCB
= 60µA, VON = 0V 110 ns
I
ON
= 1V, VFB = 0.56V ● 113 133 153 mV
RNG
V
= 0V, VFB = 0.56V ● 79 93 107 mV
RNG
V
= INTVCC, VFB = 0.56V ● 158 186 214 mV
RNG
= 1V, VFB = 0.64V 67 mV
RNG
V
= 0V, VFB = 0.64V 47 mV
RNG
= INTVCC, VFB = 0.64V 93 mV
V
RNG
Consult LTC Marketing for parts specified with wider operating temperature ranges.
2
3778f
Page 3
LTC3778
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
RUN/SS(ON)
V
RUN/SS(LE)
V
RUN/SS(LT)
I
RUN/SS(C)
I
RUN/SS(D)
V
IN(UVLO)
V
IN(UVLOR)
TG R
UP
TG R
DOWN
BG R
UP
BG R
DOWN
TG t
r
TG t
f
BG t
r
BG t
f
Internal VCC Regulator
V
INTVCC
∆V
LDO(LOADREG)
V
EXTVCC
∆V
EXTVCC
∆V
EXTVCC(HYS)
PGOOD Output
∆V
FBH
∆V
FBL
∆V
FB(HYS)
V
PGL
Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.
Note 2: T
dissipation P
LTC3778E: TJ = TA + (PD • 110°C/W)
RUN Pin Start Threshold ● 0.8 1.5 2 V
RUN Pin Latchoff Enable Threshold RUN/SS Pin Rising 4 4.5 V
RUN Pin Latchoff Threshold RUN/SS Pin Falling 3.5 4.2 V
Soft-Start Charge Current –0.5 –1.2 –3 µA
Soft-Start Discharge Current 0.8 1.8 3 µA
Undervoltage Lockout Threshold VIN Falling ● 3.4 3.9 V
Undervoltage Lockout Threshold VIN Rising ● 3.5 4 V
TG Driver Pull-Up On Resistance TG High 2 3 Ω
TG Driver Pull-Down On Resistance TG Low 2 3 Ω
BG Driver Pull-Up On Resistance BG High 3 4 Ω
BG Driver Pull-Down On Resistance BG Low 1 2 Ω
TG Rise Time C
TG Fall Time C
BG Rise Time C
BG Fall Time C
Internal VCC Voltage 6V < VIN < 30V, V
Internal VCC Load Regulation ICC = 0mA to 20mA, V
EXTVCC Switchover Voltage ICC = 20mA, V
EXTVCC Switch Drop Voltage ICC = 20mA, V
= 3300pF 20 ns
LOAD
= 3300pF 20 ns
LOAD
= 3300pF 20 ns
LOAD
= 3300pF 20 ns
LOAD
= 4V ● 4.7 5 5.3 V
EXTVCC
= 4V –0.1 ±2%
EXTVCC
Rising ● 4.5 4.7 V
EXTVCC
= 5V 150 300 mV
EXTVCC
EXTVCC Switchover Hysteresis 200 mV
PGOOD Upper Threshold VFB Rising 7.5 10 12.5 %
PGOOD Lower Threshold VFB Falling – 7.5 – 10 –12.5 %
PGOOD Hysteresis VFB Returning 1 2.5 %
PGOOD Low Voltage I
= 5mA 0.15 0.4 V
PGOOD
Note 3: The LTC3778 is tested in a feedback loop that adjusts V
is calculated from the ambient temperature TA and power
J
as follows:
D
a specified error amplifier output voltage (I
Note 4: The LTC3778E is guaranteed to meet performance specifications from
0°C to 70°C. Specifications over the –40°C to 85°C operating temperature
).
TH
range are assured by design, characterization and correlation with statistical
process controls.
to achieve
FB
3778f
3
Page 4
LTC3778
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Transient Response
Transient Response
(Discontinuous Mode)
Start-Up
V
OUT
50mV/DIV
I
L
5A/DIV
LOAD STEP 0A TO 10A
= 15V
V
IN
V
= 2.5V
OUT
FCB = 0V
FIGURE 1 CIRCUIT
Efficiency vs Load Current
100
DISCONTINUOUS
90
80
70
EFFICIENCY (%)
60
50
0.001
MODE
0.01
LOAD CURRENT (A)
Load Regulation
20µs/DIV
V
IN
V
OUT
EXTV
FIGURE 1 CIRCUIT
0.1
CONTINUOUS
MODE
= 10V
= 2.5V
= 5V
CC
1
3778 G03
3778 G01
10
V
OUT
50mV/DIV
5A/DIV
I
L
LOAD STEP 1A TO 10A
= 15V
V
IN
V
= 2.5V
OUT
FCB = INTV
CC
FIGURE 1 CIRCUIT
20µs/DIV
3778 G02
RUN/SS
2V/DIV
V
OUT
1V/DIV
5A/DIV
I
L
VIN = 15V
= 2.5V
V
OUT
R
= 0.125Ω
LOAD
Efficiency vs Input Voltage Frequency vs Input Voltage
100
FCB = 5V
FIGURE 1 CIRCUIT
95
90
I
LOAD
EFFICIENCY (%)
85
80
0
I
= 1A
LOAD
= 10A
5101520
INPUT VOLTAGE (V)
25 30
3778 G04
300
FCB = 0V
FIGURE 1 CIRCUIT
280
260
240
FREQUENCY (kHz)
220
200
5
10
INPUT VOLTAGE (V)
Current Sense Threshold
ITH Voltage vs Load Current
vs ITH Voltage
50ms/DIV 3778 G19
I
= 10A
OUT
I
= 0A
OUT
15
20
3778 G05
25
–0.1
(%)
–0.2
OUT
∆V
–0.3
–0.4
4
0
2
0
LOAD CURRENT (A)
4
FIGURE 1 CIRCUIT
6
8
3778 G06
10
2.5
FIGURE 1 CIRCUIT
V
RNG
2.0
1.5
CONTINUOUS
VOLTAGE (V)
1.0
TH
I
0.5
0
0
= 1V
MODE
DISCONTINUOUS
MODE
5
LOAD CURRENT (A)
10
15
3778 G07
300
200
100
0
–100
CURRENT SENSE THRESHOLD (mV)
–200
0
1.0 1.5 2.0
0.5
ITH VOLTAGE (V)
RNG
=
2V
1.4V
1V
0.7V
0.5V
2.5 3.0
3778 G08
3778f
V
Page 5
UW
TEMPERATURE (°C)
–50
ON-TIME (ns)
200
250
300
25 75
3778 G22
150
100
–25 0
50 100 125
50
0
I
ION
= 30µA
V
ON
= 0V
RUN/SS VOLTAGE (V)
1.5
0
MAXIMUM CURRENT SENSE THRESHOLD (mV)
25
50
75
100
125
150
V
RNG
= 1V
2 2.5 3 3.5
3778 G23
TYPICAL PERFOR A CE CHARACTERISTICS
On-Time vs ION Current On-Time vs VON Voltage On-Time vs Temperature
10k
V
= 0V
VON
1000
800
I
ION
= 30µA
LTC3778
1k
ON-TIME (ns)
100
10
1
ION CURRENT (µA)
Current Limit Foldback
150
125
100
= 1V
V
RNG
75
50
25
10 100
3778 G20
600
400
ON-TIME (ns)
200
0
0
1
VON VOLTAGE (V)
Maximum Current Sense
Threshold vs V
300
250
200
150
100
50
RNG
2
Voltage
3
3778 G21
Maximum Current Sense
Threshold vs RUN/SS Voltage
MAXIMUM CURRENT SENSE THRESHOLD (mV)
0
0
0.15 0.30 0.45 0.60
VFB (V)
Maximum Current Sense
Threshold vs Temperature
150
V
= 1V
RNG
140
130
120
110
MAXIMUM CURRENT SENSE THRESHOLD (mV)
100
–50 –25
25
0
TEMPERATURE (°C)
50
MAXIMUM CURRENT SENSE THRESHOLD (mV)
3778 G09
0
0.5
0.75
1.0 1.25 1.5
V
VOLTAGE (V)
RNG
1.75 2.0
3778 G10
Feedback Reference Voltage
vs Temperature Error Amplifier gm vs Temperature
0.62
0.61
0.60
0.59
FEEDBACK REFERENCE VOLTAGE (V)
100
125
3778 G11
75
0.58
–50
–25 0 25 50
TEMPERATURE (°C)
75 100 125
3778 G12
2.0
1.8
1.6
(mS)
m
g
1.4
1.2
1.0
–50 –25
50
25
0
TEMPERATURE (°C)
100
125
3778 G13
3778f
75
5
Page 6
LTC3778
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Input and Shutdown Currents
vs Input Voltage
1200
1000
INPUT CURRENT (µA)
800
600
400
200
0
0
EXTVCC OPEN
EXTVCC = 5V
510
INPUT VOLTAGE (V)
FCB PIN CURRENT (µA)
SHUTDOWN
20 30 35
15 25
0
–0.25
–0.50
–0.75
–1.00
–1.25
INTVCC Load Regulation
3778 G24
60
50
SHUTDOWN CURRENT (µA)
40
30
20
10
0
–0.1
–0.2
(%)
CC
–0.3
∆INTV
–0.4
–0.5
0
0
FCB Pin Current vs Temperature
10
INTVCC LOAD CURRENT (mA)
30
20
3
2
1
0
RUN/SS PIN CURRENT (µA)
–1
EXTVCC Switch Resistance
vs Temperature
10
8
6
4
SWITCH RESISTANCE (Ω)
CC
2
EXTV
0
40
50
3778 G25
–50 –25
RUN/SS Pin Current
vs Temperature
PULL-DOWN CURRENT
PULL-UP CURRENT
50
25
0
TEMPERATURE (°C)
100
125
3778 G14
75
–1.50
–50
–25 0
25 75
TEMPERATURE (°C)
RUN/SS Latchoff Thresholds
vs Temperature
5.0
4.5
LATCHOFF ENABLE
4.0
3.5
RUN/SS THRESHOLD (V)
3.0
–50
LATCHOFF THRESHOLD
–25 0 25 50
TEMPERATURE (°C)
50 100 125
3778 G15
75 100 125
3778 G17
–2
–50 –25
0
TEMPERATURE (°C)
50
25
75
Undervoltage Lockout Threshold
vs Temperature
4.0
3.5
3.0
2.5
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
2.0
–50
–25 0 25 50
TEMPERATURE (C)
75 100 125
100
125
3778 G16
3778 G18
3778f
6
Page 7
LTC3778
U
UU
PI FU CTIO S
RUN/SS (Pin 1): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.
VON (Pin 2): On-Time Voltage Input. Voltage trip point for
the on-time comparator. Tying this pin to the output
voltage makes the on-time proportional to V
comparator input defaults to 0.7V when the pin is grounded,
2.4V when the pin is tied to INTVCC.
PGOOD (Pin 3): Power Good Output. Open drain logic
output that is pulled to ground when the output voltage is
not within ±10% of the regulation point.
V
(Pin 4): Sense Voltage Range Input. The voltage at
RNG
this pin is ten times the nominal sense voltage at maximum
output current and can be set from 0.5V to 2V by a resistive
divider from INTVCC. The nominal sense voltage defaults
to 70mV when this pin is tied to ground, 140mV when tied
to INTVCC.
I
(Pin 5): Current Control Threshold and Error Amplifier
TH
Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 0.8V corresponding to zero sense
voltage (zero current).
FCB (Pin 6): Forced Continuous Input. Tie this pin to
ground to force continuous synchronous operation at low
load, to INTVCC to enable discontinuous mode operation at
low load or to a resistive divider from a secondary output
when using a secondary winding.
OUT
. The
and shuts down the internal regulator so that controller
power is drawn from EXTVCC. Do not exceed 7V at this pin
and ensure that EXTVCC < VIN.
VIN (Pin 11): Main Input Supply. Decouple this pin to
SGND with an RC filter (1Ω, 0.1µF).
INTVCC (Pin 12): Internal 5V Regulator Output. The internal control circuits are powered from this voltage. Decouple this pin to power ground with a minimum of 1µF
low ESR tantalum or ceramic capacitor.
DRVCC (Pin 13): Voltage Supply to Bottom Gate Driver.
Normally connected to the INTVCC pin through a decoupling
RC filter (1Ω, 0.1µF). Decouple this pin to power ground
with a minimum of 4.7µF low ESR tantalum or ceramic
capacitor. Do not exceed 7V at this pin.
BG (Pin 14): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and DRVCC.
PGND (Pin 15): Power Ground. Connect this pin closely to
the source of the bottom N-channel MOSFET or to the
bottom of the sense resistor when used, the (–) terminal
of C
SENSE– (Pin 16): Current Sense Comparator Input. The
(–) input to the current comparator is used to accurately
Kelvin sense the bottom side of the sense resistor or
MOSFET.
SENSE+ (Pin 17): Current Sense Comparator Input. The
(+) input to the current comparator is normally connected
to the SW node unless using a sense resistor (See Applications Information).
and the (–) terminal of CIN.
VCC
SGND (Pin 7): Signal Ground. All small-signal components and compensation components should connect to
this ground, which in turn connects to PGND at one point.
ION (Pin 8): On-Time Current Input. Tie a resistor from V
to this pin to set the one-shot timer current and thereby set
the switching frequency.
VFB (Pin 9): Error Amplifier Feedback Input. This pin
connects the error amplifier input to an external resistive
divider from V
EXTVCC (Pin 10): External VCC Input. When EXTVCC ex-
ceeds 4.7V, an internal switch connects this pin to INTV
OUT
.
IN
CC
SW (Pin 18): Switch Node. The (–) terminal of the bootstrap capacitor CB connects here. This pin swings from a
diode voltage drop below ground up to VIN.
TG (Pin 19): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to DRVCC superimposed on the switch node voltage SW.
BOOST (Pin 20): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below DRVCC up to
V
+ DRVCC.
IN
3778f
7
Page 8
LTC3778
U
U
W
FU CTIO AL DIAGRA
R
V
OUT
V
2.4V
0.7V
tON = (10pF)
1.4V
V
RNG
4
0.7V
ON
V
I
CMP
I
VON
ION
+
–
(0.5~2)
ON
I
82
ON
R
SQ
20k
+
I
REV
–
×
3.3µA
FCB EXTV
6
1µA
–
F
4.7V
+
0.6V
+
–
FCNT
ON
SHDN
OV
10
SWITCH
LOGIC
V
IN
V
11
CC
IN
+
C
IN
0.6V
REF
5V
REG
BOOST
SENSE
SENSE
DRV
C
PGND
PGOOD
TG
SW
BG
VCC
20
19
18
+
17
–
16
CC
13
14
15
3
INTV
CC
12
C
B
M1
D
B
L1
V
OUT
+
C
OUT
M2
R
SENSE
(OPTIONAL)*
R2
8
1
240k
I
+
–
×5.3
THB
0.8V
0.54V
UV
OV
1.2µA
+
–
+
0.66V
–
+
SENSE
6V
C
SS
BG
–
SENSE
*CONNECTION W/O
SENSE RESISTOR
SGND
SW
PGND
V
M2
FB
9
R1
7
1778 FD
3778f
Q2
Q4
Q6
Q3
Q1
EA
–
+
0.6V
1V
Q5
RUN
SS
–
+
+
–
0.6V
C
I
5
C1
TH
R
C
SHDN/
LATCH-OFF
0.4V
1
RUN/SS
Page 9
OPERATIO
LTC3778
U
Main Control Loop
The LTC3778 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by a
one-shot timer OST. When the top MOSFET is turned off,
the bottom MOSFET is turned on until the current comparator I
ating the next cycle. Inductor current is determined by
sensing the voltage between the SENSE– and SENSE
pins. The voltage on the ITH pin sets the comparator
threshold corresponding to inductor valley current. The
error amplifier EA adjusts this voltage by comparing the
feedback signal VFB from the output voltage with an
internal 0.6V reference. If the load current increases, it
causes a drop in the feedback voltage relative to the
reference. The ITH voltage then rises until the average
inductor current again matches the load current.
At low load currents, the inductor current can drop to zero
and become negative. This is detected by current reversal
comparator I
discontinuous operation. Both switches will remain off
with the output capacitor supplying the load current until
the ITH voltage rises above the zero current level (0.8V) to
initiate another cycle. Discontinuous mode operation is
disabled by comparator F when the FCB pin is brought
below 0.6V, forcing continuous synchronous operation.
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in V
IN
with an external resistor RON.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point.
trips, restarting the one-shot timer and initi-
CMP
which then shuts off M2, resulting in
REV
and V
. The nominal frequency can be adjusted
OUT
+
Furthermore, in an overvoltage condition, M1 is turned off
and M2 is turned on and held on until the overvoltage
condition clears.
Foldback current limiting is provided if the output is
shorted to ground. As VFB drops, the buffered current
threshold voltage I
level set by Q4 and Q6. This reduces the inductor valley
current level to one sixth of its maximum value as V
approaches 0V.
Pulling the RUN/SS pin low forces the controller into its
shutdown state, turning off both M1 and M2. Releasing
the pin allows an internal 1.2µA current source to charge
up an external soft-start capacitor CSS. When this voltage
reaches 1.5V, the controller turns on and begins switching, but with the ITH voltage clamped at approximately
0.6V below the RUN/SS voltage. As CSS continues to
charge, the soft-start current limit is removed.
EXTVCC/INTVCC/DRV
Power for the top and bottom MOSFET drivers is derived
from DRVCC and most of the internal controller circuitry
is powered from the INTVCC pin. The top MOSFET driver
is powered from a floating bootstrap capacitor CB. This
capacitor is recharged from DRVCC through an external
Schottky diode DB when the top MOSFET is turned off.
When the EXTVCC pin is grounded, an internal 5V low
dropout regulator supplies the INTVCC power from VIN. If
EXTVCC rises above 4.7V, the internal regulator is turned
off, and an internal switch connects EXTVCC to INTVCC.
This allows a high efficiency source connected to EXTVCC,
such as an external 5V supply or a secondary output from
the converter, to provide the INTVCC power. Voltages up
to 7V can be applied to DRVCC for additional gate drive.
If the input voltage is low and INTVCC drops below 3.5V,
undervoltage lockout circuitry prevents the power
switches from turning on.
is pulled down by clamp Q3 to a 1V
THB
Power
CC
FB
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APPLICATIO S I FOR ATIO
The basic LTC3778 application circuit is shown in
Figure 1. External component selection is primarily determined by the maximum load current and begins with
the selection of the sense resistance and power MOSFET
switches. The LTC3778 can use either a sense resistor or
the on-resistance of the synchronous power MOSFET for
determining the inductor current. The desired amount of
ripple current and operating frequency largely determines the inductor value. Finally, CIN is selected for its
ability to handle the large RMS current into the converter
and C
is chosen with low enough ESR to meet the
OUT
output voltage ripple and transient specification.
Maximum Sense Voltage and V
RNG
Pin
Inductor current is determined by measuring the voltage
across a sense resistance that appears between the SENSE
–
and SENSE+ pins. The maximum sense voltage is set by
the voltage applied to the V
approximately (0.133)V
RNG
pin and is equal to
RNG
. The current mode control
loop will not allow the inductor current valleys to exceed
(0.133)V
RNG/RSENSE
. In practice, one should allow some
margin for variations in the LTC3778 and external component values and a good guide for selecting the sense
resistance is:
V
R
SENSE
=
10•
RNG
I
()
OUT MAX
An external resistive divider from INTVCC can be used to
set the voltage of the V
pin between 0.5V and 2V
RNG
resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the V
pin can be tied to SGND or INTV
RNG
CC
in which case the nominal sense voltage defaults to 70mV
or 140mV, respectively. The maximum allowed sense
voltage is about 1.33 times this nominal value.
Connecting the SENSE+ and SENSE– Pins
The LTC3778 can be used with or without a sense resistor.
When using a sense resistor, it is placed between the
source of the bottom MOSFET, M2, and PGND. Connect
the SENSE+ and SENSE– pins to the top and bottom of the
sense resistor. Using a sense resistor provides a well
defined current limit, but adds cost and reduces efficiency.
Alternatively, one can eliminate the sense resistor and use
the bottom MOSFET as the current sense element by
simply connecting the SENSE+ pin to the SW pin and
SENSE– pin to PGND. This improves efficiency, but one
must carefully choose the MOSFET on-resistance as discussed below.
Power MOSFET Selection
The LTC3778 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V
threshold voltage V
transfer capacitance C
, on-resistance R
(GS)TH
and maximum current I
RSS
DS(ON)
(BR)DSS
, reverse
DS(MAX)
The gate drive voltage is set by the 5V INTVCC and DRV
,
.
CC
supplies. Consequently, logic-level threshold MOSFETs
must be used in LTC3778 applications. If the input voltage
or DRVCC voltage is expected to drop below 5V, then sublogic level threshold MOSFETs should be considered.
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its onresistance. MOSFET on-resistance is typically specified
with a maximum value R
DS(ON)(MAX)
at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
R
R
DS ON MAX
()( )
=
SENSE
ρ
T
10
3778f
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APPLICATIO S I FOR ATIO
LTC3778
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 2. For a maximum junction temperature of 100°C,
using a value ρT = 1.3 is reasonable.
2.0
1.5
1.0
0.5
NORMALIZED ON-RESISTANCE
T
ρ
0
–50
JUNCTION TEMPERATURE (°C)
Figure 2. R
50
0
vs. Temperature
DS(ON)
100
150
3778 F02
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
the load current. When the LTC3778 is operating in
continuous mode, the duty cycles for the MOSFETs are:
V
D
D
TOP
BOT
OUT
=
V
IN
–
VV
IN OUT
=
V
IN
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The operating frequency of LTC3778 applications is determined implicitly by the one-shot timer that controls the
on-time tON of the top MOSFET switch. The on-time is set
by the current into the ION pin and the voltage at the V
ON
pin according to:
V
t
ON
VON
= ()10
I
ION
pF
Tying a resistor RON from VIN to the ION pin yields an ontime inversely proportional to VIN. For a step-down converter, this results in approximately constant frequency
operation as the input supply varies:
V
f
=
VR pF
()()
OUT
VON ON
10
Hz
[]
To hold frequency constant during output voltage changes,
tie the VON pin to V
. The VON pin has internal clamps
OUT
that limit its input to the one-shot timer. If the pin is tied
below 0.7V, the input to the one-shot is clamped at 0.7V.
Similarly, if the pin is tied above 2.4V, the input is clamped
at 2.4V. If output is above 2.4V, use a resistive divider from
V
to VON pin.
OUT
The resulting power dissipation in the MOSFETs at maximum output current are:
P
P
TOP
BOT
= D
TOP IOUT(MAX)
+ k V
IN
= D
BOT IOUT(MAX)
2
I
2
ρ
T(TOP) RDS(ON)(MAX)
OUT(MAX) CRSS
2
ρ
T(BOT) RDS(ON)(MAX)
f
Both MOSFETs have I2R losses and the top MOSFET
includes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottom MOSFET losses are greatest when the bottom duty
cycle is near 100%, during a short-circuit or at high input
voltage.
Because the voltage at the ION pin is about 0.7V, the
current into this pin is not exactly inversely proportional to
VIN, especially in applications with lower input voltages.
To correct for this error, an additional resistor R
ON2
connected from the ION pin to the 5V INTVCC supply will
further stabilize the frequency.
V
07=.
5
R
V
R
ON ON2
Changes in the load current magnitude will also cause
frequency shift. Parasitic resistance in the MOSFET
switches and inductor reduce the effective voltage across
the inductance, resulting in increased duty cycle as the
3778f
11
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LTC3778
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APPLICATIO S I FOR ATIO
load current increases. By lengthening the on-time slightly
as current increases, constant frequency operation can be
maintained. This is accomplished with a resistive divider
from the ITH pin to the VON pin and V
. The values
OUT
required will depend on the parasitic resistances in the
specific application. A good starting point is to feed about
25% of the voltage change at the ITH pin to the VON pin as
shown in Figure 3a. Place capacitance on the VON pin to
filter out the ITH variations at the switching frequency. The
resistor load on ITH reduces the DC gain of the error amp
and degrades load regulation, which can be avoided by
using the PNP emitter follower of Figure 3b.
R
VON1
30k
V
OUT
R
VON2
100k
R
VON1
V
INTV
Figure 3. Correcting Frequency Shift with Load Current Changes
3k
OUT
10k
CC
2N5087
R
C
C
C
(3a)
R
VON2
10k
Q1
(3b)
C
VON
0.01µF
C
VON
0.01µF
R
C
C
C
V
ON
LTC3778
I
TH
V
ON
LTC3778
I
TH
3778 F03a
3778 F03b
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
V
OUT OUT
fL
V
−
1
V
IN
I
∆=
L
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
A reasonable starting point is to choose a ripple current
that is about 40% of I
OUT(MAX)
. The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:
=
fI
V
∆
LMAX
L
OUT
() ()
V
−
1
V
IN MAX
OUT
Once the value for L is known, the type of inductor must be
selected. A variety of inductors designed for high current,
low voltage applications are available from manufacturers
such as Sumida, Panasonic, Coiltronics, Coilcraft and
Toko.
Schottky Diode D1 Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
of the bottom MOSFET from turning on and storing charge
during the dead time, which can cause a modest (about
1%) efficiency loss. The diode can be rated for about one
half to one fifth of the full load current since it is on for only
a fraction of the duty cycle. In order for the diode to be
effective, the inductance between it and the bottom MOSFET must be as small as possible, mandating that these
components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable.
CIN and C
Selection
OUT
The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
V
II
≅
RMS OUT MAX
()
OUT
V
This formula has a maximum at VIN = 2V
I
RMS
= I
OUT(MAX)
/2. This simple worst-case condition is
IN
V
V
IN
OUT
–1
OUT
, where
12
3778f
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APPLICATIO S I FOR ATIO
LTC3778
commonly used for design because even significant
deviations do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often
based on only 2000 hours of life which makes it advisable
to derate the capacitor.
The selection of C
required to minimize voltage ripple and load step
transients. The output ripple ∆V
bounded by:
∆≤∆ +
V I ESR
OUT L
Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, POSCAP aluminum electrolytic and ceramic capacitors are all available in surface
mount packages. Special polymer capacitors offer very
low ESR but have lower capacitance density. Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested for
use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications providing that consideration
is given to ripple current ratings and long term reliability.
Ceramic capacitors have excellent low ESR characteristics
but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with
trace inductance can also lead to significant ringing. When
used as input capacitors, care must be taken to ensure that
ringing from inrush currents and switching does not pose
an overvoltage hazard to the power switches and controller. When necessary, adding a small 5µF to 50µF alumi-
num electrolytic capacitor with an ESR in the range of
0.5Ω to 2Ω dampens input voltage transients. High performance through-hole capacitors may also be used, but
is primarily determined by the ESR
OUT
is approximately
OUT
8
fC
1
OUT
an additional ceramic capacitor in parallel is recommended
to reduce the effect of their lead inductance.
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode DB from DRV
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + DRVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications a 0.1µF to 0.47µF, X5R
or X7R dielectric ceramic capacitor is adequate.
Discontinuous Mode Operation and FCB Pin
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.6V threshold enables discontinuous
operation where the bottom MOSFET turns off when
inductor current reverses. The load current at which
inductor current reverses and discontinuous operation
begins depends on the amplitude of the inductor ripple
current and will vary with changes in VIN. Tying the FCB pin
below the 0.6V threshold forces continuous synchronous
operation, allowing current to reverse at light loads and
maintaining high frequency operation.
In addition to providing a logic input to force continuous
operation, the FCB pin provides a means to maintain a
flyback winding output when the primary is operating in
discontinuous mode. The secondary output V
mally set as shown in Figure 4 by the turns ratio N of the
transformer. However, if the controller goes into discontinuous mode and halts switching due to a light primary
load current, then V
divider from V
V
OUT2(MIN)
until V
OUT2
VV
OUT MIN2
OUT2
below which continuous operation is forced
has risen above its minimum.
()
08 1
will droop. An external resistor
OUT2
to the FCB pin sets a minimum voltage
.=+
R
4
R
3
OUT2
CC
is nor-
3778f
13
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LTC3778
WUUU
APPLICATIO S I FOR ATIO
V
IN
+
C
V
IN
OPTIONAL
EXTV
CONNECTION
5V < V
CC
< 7V
OUT2
Figure 4. Secondary Output Loop and EXTVCC Connection
EXTV
R4
FCB
R3
SGND
LTC3778
CC
TG
SW
BG
PGND
IN
1N4148
V
C
C
1µF
OUT
3778 F04
SEC
V
OUT2
OUT1
•
T1
1:N
+
•
+
Fault Conditions: Current Limit and Foldback
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the LTC3778, the maximum sense voltage is controlled by
the voltage on the V
pin. With valley current control,
RNG
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
To further limit current in the event of a short circuit to
ground, the LTC3778 includes foldback current limiting. If
the output falls by more than 50%, then the maximum
sense voltage is progressively lowered to about one sixth
of its full value.
Minimum Off-time and Dropout Operation
The minimum off-time t
OFF(MIN)
is the smallest amount of
time that the LTC3778 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 250ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON + t
OFF(MIN)
). If the maximum duty cycle is reached,
due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:
tt
+
VV
IN MIN OUT
=
()
ON OFF MIN
t
ON
()
INTVCC Regulator
V
SNS MAX
I
=+∆
LIMIT
()*ρ
()
R
DS ON T
()
1
I
L
2
The current limit value should be checked to ensure that
I
LIMIT(MIN)
> I
OUT(MAX)
. The minimum value of current limit
generally occurs with the lowest VIN at the highest ambient
temperature. Note that it is important to check for selfconsistency between the assumed MOSFET junction temperature and the resulting value of I
which heats the
LIMIT
MOSFET switches.
Caution should be used when setting the current limit
based upon the R
of the MOSFETs. The maximum
DS(ON)
current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and
maximum values for R
reasonable assumption is that the minimum R
, but not a minimum. A
DS(ON)
DS(ON)
lies
the same amount below the typical value as the maximum
lies above it. Consult the MOSFET manufacturer for further
guidelines.
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3778. The INTVCC pin can supply up to
50mA RMS and must be bypassed to ground with a
minimum of 4.7µF tantalum or other low ESR capacitor.
Good bypassing is necessary to supply the high transient
currents required by the MOSFET gate drivers. Applications using large MOSFETs with a high input voltage and
high frequency of operation may cause the LTC3778 to
exceed its maximum junction temperature rating or RMS
current rating. Most of the supply current drives the
MOSFET gates unless an external EXTVCC source is used.
In continuous mode operation, this current is I
f(Q
g(TOP)
+ Q
). The junction temperature can be
g(BOT)
GATECHG
=
estimated from the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC3778EF is
limited to less than 15mA from a 30V supply:
TJ = 70°C + (15mA)(30V)(110°C/W) = 120°C
For larger currents, consider using an external supply with
the DRVCC pin.
*Use R
SENSE
.
14
value here if a sense resistor is connected between SENSE+ and SENSE
–
3778f
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APPLICATIO S I FOR ATIO
LTC3778
EXTVCC Connection
The EXTVCC pin can be used to provide MOSFET gate drive
and control power from the output or another external
source during normal operation. Whenever the EXTV
CC
pin is above 4.7V the internal 5V regulator is shut off and
an internal 50mA P-channel switch connects the EXTV
CC
pin to INTVCC. INTVCC power is supplied from EXTVCC until
this pin drops below 4.5V. Do not apply more than 7V to
the EXTVCC pin and ensure that EXTVCC ≤ VIN. The following list summarizes the possible connections for EXTVCC:
1. EXTVCC grounded. INTV
is always powered from the
CC
internal 5V regulator.
2. EXTVCC connected to an external supply. A high efficiency supply compatible with the MOSFET gate drive
requirements (typically 5V) can improve overall
efficiency.
3. EXTVCC connected to an output derived boost network.
The low voltage output can be boosted using a charge
pump or flyback winding to greater than 4.7V. The system
will start-up using the internal linear regulator until the
boosted output supply is available.
External Gate Drive Buffers
The LTC3778 drivers are adequate for driving up to about
60nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
frequencies requiring greater RMS currents will benefit
from using external gate drive buffers such as the LTC1693.
Alternately, the external buffer circuit shown in Figure 5
can be used. Note that the bipolar devices reduce the
signal swing at the MOSFET gate, and benefit from an
increased EXTVCC voltage of about 6V.
BOOST
Q1
FMMT619
10Ω 10Ω
TG
SW
Figure 5. Optional External Gate Driver
Q2
FMMT720
GATE
OF M1
BG
DRV
PGND
CC
Q3
FMMT619
Q4
FMMT720
GATE
OF M2
3778 F05
Soft-Start and Latchoff with the RUN/SS Pin
The RUN/SS pin provides a means to shut down the
LTC3778 as well as a timer for soft-start and overcurrent
latchoff. Pulling the RUN/SS pin below 0.8V puts the
LTC3778 into a low quiescent current shutdown (IQ <
30µA). Releasing the pin allows an internal 1.2µA current
source to charge up the external timing capacitor CSS. If
RUN/SS has been pulled all the way to ground, there is a
delay before starting of about:
15
.
t
DELAY SS SS
=
12
.
V
CsFC
A
µ
13
./
=µ
()
When the voltage on RUN/SS reaches 1.5V, the LTC3778
begins operating with a clamp on ITH of approximately
0.9V. As the RUN/SS voltage rises to 3V, the clamp on I
TH
is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF, during which the load current is folded
back until the output reaches 50% of its final value. The pin
can be driven from logic as shown in Figure 6. Diode D1
reduces the start delay while allowing CSS to charge up
slowly for the soft-start function.
After the controller has been started and given adequate
time to charge up the output capacitor, CSS is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8µA cur-
rent then begins discharging CSS. If the fault condition
persists until the RUN/SS pin drops to 3.5V, then the controller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.
The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has
reached the 4V threshold. In general, this will depend upon
the size of the output capacitance, output voltage and load
current characteristic. A minimum soft-start capacitor can
be estimated from:
CSS > C
OUT VOUT RSENSE
(10–4 [F/V s])
Generally 0.1µF is more than sufficient.
3778f
15
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APPLICATIO S I FOR ATIO
Overcurrent latchoff operation is not always needed or
desired. Load current is already limited during a shortcircuit by the current foldback circuitry and latchoff
operation can prove annoying during troubleshooting.
The feature can be overridden by adding a pull-up current
greater than 5µA to the RUN/SS pin. The additional
current prevents the discharge of CSS during a fault and
also shortens the soft-start period. Using a resistor to V
IN
as shown in Figure 6a is simple, but slightly increases
shutdown current. Connecting a resistor to INTVCC as
shown in Figure 6b eliminates the additional shutdown
current, but requires a diode to isolate CSS . Any pull-up
network must be able to maintain RUN/SS above the 4V
maximum latch-off threshold and overcome the 4µA
maximum discharge current.
INTV
CC
V
3.3V OR 5V RUN/SS
Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated
IN
RSS*
D1
C
SS
*OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF
(6a) (6b)
RSS*
D2*
2N7002
RUN/SS
C
SS
3778 F06
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3778 circuits:
1. DC I2R losses. These arise from the resistances of the
sense resistor, MOSFETs, inductor and PC board traces
and cause the efficiency to drop at high output currents. In
continuous mode the average output current flows through
L, but is chopped between the top and bottom MOSFETs.
If the two MOSFETs have approximately the same R
DS(ON)
,
then the resistance of one MOSFET can simply be summed
with the resistances of L and the board traces to obtain the
DC I2R loss. For example, if R
= 0.01Ω and
DS(ON)
RL = 0.005Ω, the loss will range from 15mW to 1.5W
as the output current varies from 1A to 10A for a 1.5V
output.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
Transition Loss ≅ (1.7A–1) V
IN
2
I
OUT CRSS
f
3. INTVCC current. This is the sum of the MOSFET driver
and control currents. This loss can be reduced by supplying INTVCC current through the EXTVCC pin from a high
efficiency source, such as an output derived boost network or alternate supply if available.
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including C
ESR loss, Schottky diode D1
OUT
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the
input current is the best indicator of changes in efficiency.
If you make a change and the input current decreases, then
the efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to ∆I
resistance of C
discharge C
(ESR), where ESR is the effective series
LOAD
OUT
generating a feedback error signal used by
OUT
the regulator to return V
immediately shifts by an amount
OUT
. ∆I
also begins to charge or
LOAD
to its steady-state value.
OUT
16
3778f
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P
VV
V
AW
BOT
=
()()
Ω
()
=
28 2 5
28
12 15 0010 197
2
–.
.. .
APPLICATIO S I FOR ATIO
LTC3778
During this recovery time, V
overshoot or ringing that would indicate a stability problem. The ITH pin external components shown in Figure 7
will provide adequate compensation for most applications. For a detailed explanation of switching control loop
theory see Linear Technology Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: VIN = 7V to 28V (15V nominal), V
±5%, I
timing resistor with VON = V
and choose the inductor for about 40% ripple current at
the maximum VIN:
OUT(MAX)
R
=
ON
L
250 0 4 10
()()()
= 10A, f = 250kHz. First, calculate the
1
kHz pF
250 10
()()
V
25
.
kHz A
.
can be monitored for
OUT
:
OUT
k
=
400 Ω
−
1
25
.
28
V
=µ
V
23
.
OUT
H=
= 2.5V
mV
I
LIMIT
and double check the assumed TJ in the MOSFET:
TJ = 70°C + (1.97W)(40°C/W) = 149°C
Because the top MOSFET is on for such a short time, an
Si4884 R
sufficient. Checking its power dissipation at current limit
with ρ
100°C
P
TOP
TJ = 70°C + (0.7W)(40°C/W) = 98°C
146
≥
15 0010
..
()
()
DS(ON)(MAX)
= 1.4:
25
V
.
=
28
V
1 7 28 12 100 250
.
()( )( )( )( )
030 040 07
=+=
...
= 0.0165Ω, C
2
12 1 4 0 0165
A
()()
2
VApFkHz
WWW
1
+
Ω
..
AA
=
51 12
.
()
2
= 100pF will be
RSS
Ω
()
+
Selecting a standard value of 1.8µH results in a maximum
ripple current of:
.
µ
1
–
= 1.5:
25
.
∆=
L
250 1 8
()
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (R
θJA = 40°C/W) yields a nominal sense voltage of:
V
SNS(NOM)
Tying V
for a nominal value of 110mV with current limit occurring
at 146mV. To check if the current limit is acceptable,
assume a junction temperature of about 80°C above a
70°C ambient with ρ
to 1.1V will set the current sense voltage range
RNG
V
kHz H
()
= 0.0083Ω (NOM) 0.010Ω (MAX),
DS(ON)
= (10A)(1.3)(0.0083Ω) = 108mV
150°C
25
.
28
V
51
.
=I
V
A
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
CIN is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR of
0.013Ω to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be
only:
∆V
OUT(RIPPLE)
However, a 0A to 10A load step will cause an output
change of up to:
∆V
OUT(STEP)
An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 7.
= ∆I
= (5.1A) (0.013Ω) = 66mV
= ∆I
LOAD
(ESR)
L(MAX)
(ESR) = (10A) (0.013Ω) = 130mV
3778f
17
Page 18
LTC3778
WUUU
APPLICATIO S I FOR ATIO
C
SS
R3
11k
C
C1
500pF
R1
12.7k
40.2k
0.1µF
C
R2
ON,
R4
39k
R
C
20k
C
100pF
0.01µF
C2
R
400k
R
100k
ON
LTC3778
1
2
PG
3
4
5
6
7
8
9
10
RUN/SS
V
ON
PGOOD
V
RNG
I
TH
FCB
SGND
I
ON
V
FB
EXTV
BOOST
SW
SENSE
SENSE
PGND
DRV
INTV
V
CC
D
B
CMDSH-3
20
C
B
0.22µF
19
TG
18
17
+
16
–
15
14
BG
13
C
CC
12
CC
11
IN
+
4.7µF
R
1Ω
C
0.1µF
VCC
F
F
M1
Si4884
M2
Si4874
L1, 1.8µH
D1
B340A
C
IN
10µF
35V
×3
C
OUT1-2
+
180µF
4V
×2
C
OUT3
22µF
6.3V
X7R
V
IN
5V TO 28V
V
OUT
2.5V
10A
CIN: UNITED CHEMICON THCR60EIHI06ZT
: CORNELL DUBILIER ESRE181E04B
C
OUT1-2
L1: SUMIDA CEP125-1R8MC-H
Figure 7. Design Example: 2.5V/10A at 250kHz
Active Voltage Positioning
Active voltage positioning (also termed load “deregulation” or droop) describes a technique where the output
voltage varies with load in a controlled manner. It is useful
in applications where rapid load steps are the main cause
of error in the output voltage. By positioning the output
voltage at or above the regulation point at zero load, and
below the regulation point at full load, one can use more
of the error budget for the load step. This allows one to
reduce the number of output capacitors by relaxing the
ESR requirement.
For example, in a 20A application, six 0.015Ω capacitors
are required in parallel to keep the output voltage within a
100mV tolerance:
±
1
()
6
0 015 50 100AmVmV.
Ω
=± =20
Using active voltage positioning, the same specification
can be met with only three capacitors. In this case, the load
step will cause an output voltage change of:
∆=
OUT STEP()
()
1
.20
0 015 100
()
3
=VA mV
Ω
3778 F07
By positioning the output voltage at the regulation point at
no load, it will drop 100mV below the regulation point after
the load step. However, when the load disappears or the
output is stepped from 20A to 0A, the 100mV is recovered.
This way, a total of 100mV change is observed on V
OUT
in
all conditions, whereas a total of ±100mV or 200mV is
seen on V
without voltage positioning while using only
OUT
three output capacitors.
Implementing active voltage positioning requires setting a
precise gain between the sensed current and the output
voltage. Because of the variability of MOSFET on-resistance, it is prudent to use a sense resistor with active
voltage positioning. In order to minimize power lost in this
resistor, a low value of 0.002Ω is chosen. The nominal
sense voltage will now be:
V
SNS(NOM)
= (0.002Ω)(20A) = 40mV
To maintain a reasonable current limit, the voltage on the
V
pin is reduced to 0.5V by connecting it to a resistor
RNG
divider from INTVCC, corresponding to a 50mV nominal
sense voltage.
Next, the gain of the LTC3778 error amplifier must be
determined. The change in ITH voltage for a corresponding
change in the output current is:
3778f
18
Page 19
WUUU
I
V
V
RI I V
V
V
AA V
V
TH NOM
RNG
SENSE OUT L()
–.
.
.–..
.
=
∆
+
=
Ω
()
+
=
12 1
2
075
12
05
0 002 0
1
2
58 075
061
APPLICATIO S I FOR ATIO
I
∆=
TH
=
()
The corresponding change in the output voltage is determined by the gain of the error amplifier and feedback
divider. The LTC3778 error amplifier has a transconductance gm that is constant over both temperature and a
wide ± 40mV input range. Thus, by connecting a load
resistance RVP to the ITH pin, the error amplifier gain can
be precisely set for accurate voltage positioning.
V
12
RI
V
RNG
24 0 002 20 0 96..
()()
∆
SENSE OUT
Ω
AV
=
LTC3778
these resistors must equal RVP and their ratio determines
nominal value of the ITH pin voltage when the error
amplifier input is zero. To set the beginning of the load line
at the regulation point, the ITH pin voltage must be set to
correspond to zero output current. The relation between
voltage and the output current is:
∆=
TH m VP
06.
V
OUT
V
∆IgR
V
OUT
Solving for this resistance value:
VI
∆
R
=
VP
==
OUT TH
Vg V
(. )
06
(. )(. )( )
06 17 75
∆
m OUT
VV
(. )(. )
125 096
VmSmV
.
15 7
k
The gain setting resistance RVP is implemented with two
resistors, R
connected from ITH to ground and R
VP1
VP2
connected from ITH to INTVCC. The parallel combination of
C
SS
0.1µF
R
R
RNG2
RNG1
45.3k
4.99k
C
C1
R
2.2nF
C
20k
C
0.01µF
ION
11.7k
R
ON
330k
Figure 8. CPU Core Voltage Regulator with Active Voltage Positioning 1.25V/20A at 300kHz
100k
R
VP2
129k
R
VP1
18k
C
FB
100pF
R
PG
C
C1
100pF
12.7k
5V
10
1
2
3
4
5
6
7
8
9
RUN/SS
V
ON
PGOOD
V
RNG
I
TH
FCB
SGND
I
ON
V
FB
EXTV
LTC3778
CC
BOOST
SENSE
SENSE
PGND
DRV
INTV
20
19
TG
18
SW
17
+
16
–
15
14
BG
13
CC
12
CC
11
V
IN
Solving for the required values of the resistors:
5
==
R
VP
1
5
18
=
===
R
VP
2
V
––.
VI
TH NOM
R
()
VP
k
55
V
R
I
TH NOM
()
VP
.
061
5
V
5061
VV
V
.
15 7 129
kk
V
15 7
.
k
The active voltage positioned circuit is shown in Figure 8.
Refer to Linear Technology Design Solutions 10 for additional information about output voltage positioning.
V
IN
7V TO 24V
C
3778 F08
IN
22µF
50V
×3
C
OUT
270µF
2V
×3
V
OUT
1.25V
20A
3778f
C
B
0.33µF
CMDSH-3
C
VCC
4.7µF
C
F
0.1µF
D
B
R
F
1Ω
M1
L1
IRF7811
0.68µH
×2
M2
IRF7811
×3
R
SENSE
0.002Ω
C
: UNITED CHEMICON
IN
THCR70EIH226ZT
: PANASONIC EEFUE0D271
C
OUT
L1: SUMIDA CEP125-4712-T007
D1
UPS840
19
Page 20
LTC3778
WUUU
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out a PC board follow one of the two suggested approaches. The simple PC board layout requires
a dedicated ground plane layer. Also, for higher currents,
it is recommended to use a multilayer board to help with
heat sinking power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place CIN, C
compact area. It may help to have some components on
the bottom side of the board.
, MOSFETs, D1 and inductor all in one
OUT
•
Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3778.
Use several bigger vias for power components.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• Use planes for VIN and V
to maintain good voltage
OUT
filtering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of
power component. You can connect the copper areas to
any DC net (VIN, V
, GND or to any other DC rail in
OUT
your system).
• Place LTC3778 chip with pins 11 to 20 facing the power
components. Keep the components connected to pins
1 to 9 close to LTC3778 (noise sensitive components).
C
SS
C
C1
R
C
C
C2
C
ION
C
FB
R1
10
1
2
3
4
5
6
7
8
9
LTC3778
RUN/SS
V
ON
PGOOD
V
RNG
I
TH
FCB
SGND
I
ON
V
FB
EXTV
20
BOOST
19
TG
18
SW
17
SENSE+
16
SENSE–
15
PGND
14
BG
13
DRV
CC
12
INTV
CC
11
V
CC
IN
C
C
VCC
+
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper operation of the controller. These items are also illustrated in
Figure 9.
B
D
B
M2
C
F
L
M1
D1
C
IN
+
V
IN
–
–
C
OUT
V
OUT
+
20
R
R2
BOLD LINES INDICATE HIGH CURRENT PATHS
ON
R
F
Figure 9. LTC3778 Layout Diagram
3778 F10
3778f
Page 21
WUUU
APPLICATIO S I FOR ATIO
LTC3778
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
source of M2.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
• Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC current.
U
TYPICAL APPLICATIO S
Figure 10 shows a DDR memory termination application in
which the output can sink and source up to 6A of current.
The resistive divider of R1 and R2 are meant to introduce
C
SS
0.1µF
R
100k
LTC3778
1
RUN/SS
2
V
ON
PG
3
PGOOD
BOOST
TG
SW
20
19
18
D
CMDSH-3
C
B
0.22µF
B
• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the INTVCC decoupling capacitor C
VCC
closely
to the INTVCC and PGND pins.
• Connect the top driver boost capacitor CB closely to the
BOOST and SW pins.
• Connect the VIN pin decoupling capacitor CF closely to
the VIN and PGND pins.
an offset to the SENSE– pin so that the current limit is
symmetrical during both sink and source.
V
IN
5V TO 25V
M1
IRF7811
L1, 1.8µH
C
IN
10µF
35V
×3
330µF
25V,
SANYO
ELECTROLYTIC
V
OUT
1.25V
±6A
4
V
C
C1
R
1500pF
CIN: UNITED CHEMICON THCR60EIHI06ZT
C
OUT1-2
L1: SUMIDA CEP125-1R8MC-H
C
20k
C
C2
100pF
C
0.01µF
ON,
R1
12.7k
R
ON
227k
R2
11.7k
: CORNELL DUBILIER ESRE181E04B
RNG
5
I
TH
6
FCB
7
SGND
8
I
ON
9
V
FB
10
EXTV
CC
Figure 10. 1.25V/±6A Sink and Source at 550kHz
SENSE
SENSE
PGND
DRV
INTV
17
+
R1
68Ω
1.2k
R2
C
VCC
+
4.7µF
R
F
1Ω
C
F
0.1µF
M2
IRF7811
D1
B340A
3778 F11
16
–
15
14
BG
13
CC
12
CC
11
V
IN
C
OUT1-2
+
180µF
4V
×2
C
OUT3
22µF
6.3V
X7R
3778f
21
Page 22
LTC3778
TYPICAL APPLICATIO S
Intel Compatible Tualatin Mobile CPU Power Supply with AVP
U
3.3V
PWRGOOD
MMBT3904-7
R1
2N7002
C2, 0.01µF
V
OUT
R10
3.2k
R13
10k
C9, 220pF
C11, 220pF
R17
24.9k, 1%
R19
330k
C18, 1000pF
3
Q14
2
3
Q1
2N7002
2
C1, 0.01µF
R8
1k
C8, 0.1µF
R18
221k, 1%
R41
0
1
OPT
V
RON
2
11
100k
R4
2k
3
Q3
MMMT3906-7
3
Q6
2
12.1k
R29
2
1
3.3V
DPSLP#
1
1
R2
R5
100ΩR61k
1
C7
1µF
6.3V
0603
R14
10k
2
R37
100k
3
2
R33
100k
Q2
2N7002
100k
V
IN
R3
R15
20k
R38
1M
V
IN
3
1
2
DPRSLPVR
5V
R9
221k
1%
Q13
2N7002
3.3V
INTV
SGND
1
2
3
4
5
6
7
8
9
10
CC
PGND
LTC3778E
RUN/SS
BOOST
V
ON
PGOOD
V
RNG
I
TH
FCB
SGND
I
ON
V
FB
EXTV
C41, 1µF C42, 1µF
GMUXSEL
SW
SENSE
SENSE
PGND
DRV
INTV
V
CC
R30
11.8k
1%
R28
100k
3
Q12
1
2N7002
2
V
IN
7.5V
CIN
2
1
R16
D1
0
CMDSH-3
20
19
TG
18
17
+
16
–
15
14
BG
13
CC
12
CC
11
IN
1
R39
1M
3
2
R23
R7
1Ω
33.2k
Q15
2N7002
1Ω
R34
1%
C10
0.22µF
V
IN
Q17
2N7002
2
QB
IRF7811A
×3
C21
1µF
C19
4.7µF
16V
R31
10k
V
CORE
1%
R11
9.76k
1%
3
1
QT
IRF7811A
×2
1
1
2
R21
0.003Ω
3
2
3
2
+
TO 24V
10µF
35V
×4
L1
0.68µH
SUMIDA
CEP125-4712F011
1
D2
UPS840
COUT
+
270µF
2V, SP
3
×4
R49*
178k
1%
Q19*
2N7002
Q20*
2N7002
*OPTIONAL
V
CORE
1.35V/1.15V/0.85V
23A
22
3778 F12
3778f
Page 23
PACKAGE DESCRIPTIO
U
F Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1650)
6.40 – 6.60*
(.252 – .260)
20 19 18 17 16 15
111214 13
6.25 – 6.50
(.246 – .256)
LTC3778
4.30 – 4.48**
(.169 – .176)
° – 8°
0
.09 – .18
(.0035 – .0071)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
*
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
.50 – .70
(.020 – .028)
MILLIMETERS
(INCHES)
1345678910
2
.65
(.0256)
BSC
.18 – .30
(.0071 – .0118)
1.10
(.0433)
MAX
.05 – .15
(.002 – .006)
F20 TSSOP 0501
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
3778f
23
Page 24
LTC3778
TYPICAL APPLICATIO
C
SS
0.1µF
R
C
C
C1
20k
2.2nF
R1
10k
R2
190k
: UNITED CHEMICON THCR70E1H226ZT
C
IN
: SANYO 16SV220M
C
OUT
D1: DIODES, INC B340A
L1: SUMIDA CDRH127-100
M1, M2: FAIRCHILD FDS6680A
U
100k
C
100pF
R
1.6M
C2
2200pF
12V/5A at 300kHz
D
C
4.7µF
VCC
C
0.22µF
C
0.1µF
CMDSH-3
B
F
B
V
IN
14V TO 28V
C
IN
M1
L1
10µH
M2
22µF
50V
V
OUT
12V
5A
+
C
OUT
220µF
D1
16V
+
R
F
1Ω
3778 TA01
LTC3778
1
RUN/SS
2
V
ON
3
PGOOD
4
V
RNG
5
I
TH
6
C2
ON
FCB
7
SGND
8
I
ON
9
V
FB
10
EXTV
20
BOOST
19
TG
18
SW
17
+
SENSE
16
–
SENSE
15
PGND
14
BG
13
DRV
CC
12
INTV
CC
11
V
CC
IN
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Burst Mode and ThinSOT are trademarks of Linear Technology Corporation.
Linear Technology Corporation
24
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
TM
Current Mode Synchronous Step-Down Controller 97% Efficiency; No Sense Resistor; 16-Pin SSOP
SENSE
≤ 2V
OUT
≤ 36V
IN
≤ 2V; 3.5V ≤ VIN ≤ 36V
OUT
≤ VIN, Synchronizable to 750kHz
OUT
≤ 9.8V
IN
≤ 2V; Mobile VIC Code
OUT
≤ 20A, Generates its own 5V Gate Drive,
OUT
Step-Down Controller GN16-Pin, 0.8V FB Reference
SENSE
Step-Down Controller 0.925V ≤ V
SENSE
3.5V ≤ V
0.8V ≤ V
2.5V ≤ V
Uses Standard N-Channel MOSFETs
●
www.linear.com
Step-Down G28 Package, V
SENSE
OUT
IN
= 0.6V to 1.75V, Active Voltage Positioning I
to 36V
= 0.6V to 1.75V 5-Bit Mobile VID,
OUT
, VIN to 36V
MVP2
LT/TP 0702 2K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2001
OUT
≤ 3.5V
MVP2
,
3778f
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