Datasheet LTC3738 Datasheet (LINEAR TECHNOLOGY)

FEATURES

■

3-Phase Controller with Onboard MOSFET Drivers

■

Programmable Active Voltage Positioning (AVP)
with True Current Sensing

■

Programmable External Thermal Detection or
Internal Thermal Sensing

■

Precise Output Current Matching Optimizes
Thermal Performance and Solution Size

■

Supports Starting into Precharged V

■

Differential Amplifier Accurately Senses V

■

PWM, Pulse Skip and Stage SheddingTM Operation

■

Synchronizable

■

210kHz to 530kHz Per Phase, Fixed Frequency

■

Output Power Good Indicator with Adaptive Blanking

■

Adjustable Soft-Start Current Ramping

■

Short-Circuit Shutdown Timer with Defeat Option

■

OPTI-LOOP® Compensation Minimizes C

■

38-Lead (5mm × 7mm) QFN Package

OUTS

OUT

OUT

U

APPLICATIO S

■

High Performance Notebook Computers

■

Servers, Desktop Computers and Workstations

U.S. Patent Numbers: 5481178, 5994885, 5929620, 6177787, 6144194, 6580258, 6462525,
6593724, 6674274, 6100678 pending on AVP technique.

LTC3738

3-Phase Buck Controller

for Intel VRM9/VRM10 with

Active Voltage Positioning

U

DESCRIPTIO

The LTC®3738 is a 3-phase synchronous step-down switch­ing regulator controller that drives all N-channel external
power MOSFET stages in a phase-lockable, fixed fre­quency architecture. The 3-phase technique effectively
triples the fundamental frequency, improving transient
response while operating each controller at an optimal
frequency for efficiency and ease of thermal design. Light
load efficiency is optimized by using a choice of output
Stage Shedding or Pulse Skip mode technology.

The LTC3738 also allows users to program load slope via
a resistor for AVP control. Both external and internal
thermal sensing are available from the on-chip thermal
detector and comparator.

A differential amplifier provides sensing of both the high
and low sides of the output voltage.

Soft-start and a defeatable, timed short-circuit shutdown
protect the MOSFETs and the load. A foldback current
circuit also provides protection for the external MOSFETs
under short-circuit or overload conditions. An all- “1” VID
detector turns off the regulator after a 1µs timeout.

, LTC and LT are registered trademarks of Linear Technology Corporation.

OPTI-LOOP is a registered trademark of Linear Technology Corporation.
Stage Shedding is a trademark of Linear Technology Corporation.

TYPICAL APPLICATIO

5V

POWER GOOD INDICATOR

MODE SELECTION/SYNC IN

THERMAL INPUT

VR HOT INDICATOR

U

10µF

0.1µF

SW3 SW2 SW1

ON/OFF

5k

100pF

VRM10 Step-Down Controller

LTC3738

TG1V

SW1

BG1

SENSE1
SENSE1

TG2

SW2

BG2

PGND

SENSE2
SENSE2

TG3

SW3

BG3

SENSE3
SENSE3

VID0-VID5

+
–

+
–

+
–

680pF

0.1µF

CC

BOOST1
BOOST2
BOOST3

PGOOD
FCB/SYNC

PLLFLTR

TSNS
VR_HOTB
OUTEN

I

TH

SS

SGND
EAIN
AVP

+

IN

–

IN

0.8µH

V

IN

0.8µH

V

IN

0.8µH

6 VID BITS

0.002Ω

0.002Ω

0.002Ω

+

22µF
×2

V

OUT

0.8375V TO 1.6000V

+

470µF
×4

3738 TA01

V

IN

5V TO 28V

3738f

1

LTC3738

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

Topside Driver Voltages (BOOSTN) ............ 38V to –0.3V

Switch Voltage (SWN)...................................32V to –5V

Boosted Driver Voltage (BOOST
Peak Output Current <1ms (TG
Supply Voltage (VCC), PGOOD, VR_HOTB

Pin Voltages ................................................ 7V to –0.3V

OUTEN, SS, PLLFLTR,

FCB/SYNC Voltages ................................... VCC to –0.3V

Voltage ................................................ 2.4V to –0.3V

I

TH

+

IN

, IN–, VID0-VID5, TSNS .............................. 5V to 0V

AVP, SENSE+, SENSE–.................................. 1.9V to 0V

Operating Ambient Temperature Range ....... 0°C to 85°C

Junction Temperature (Note 2)............................. 125°C

Storage Temperature Range ..................–65°C to 125°C

– SWN) .... 7V to –0.3V

N

, BGN) ..................... 5A

N

UU

W

PACKAGE/ORDER I FOR ATIO

TOP VIEW

OUTEN

VID2

VID1

VID0

VID5

PGOOD

BOOST1

38 37 36 35 34 33 32

VID4

31

30

29

28

27

26

25

24

23

22

21

20

BOOST3

TG1

SW1

BOOST2

TG2

SW2

V

CC

BG1

PGND

BG2

BG3

SW3

TG3

1FCB/SYNC

PLLFLTR

SENSE1

SENSE1

SENSE2

SENSE2

SENSE3

SENSE3

2

–

IN

3

+

IN

4

AVP

5

EAIN

6

+

7

–

8

+

9

–

10

–

11

+

12

13 14 15 16

SS

38-LEAD (7mm × 5mm) PLASTIC QFN

T

EXPOSED PAD (PIN 39) IS SGND MUST BE SOLDERED TO PCB

JMAX

39

17 18 19

TH

I

UHF PACKAGE

= 125°C, θJA = 34°C/W

TSNS

VID3

VR_HOTB

ORDER PART

NUMBER

LTC3738CUHF

UHF PART

MARKING

3738

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VCC = V

The ● denotes the specifications which apply over the full operating

= VSS = 5V unless otherwise noted.

OUTEN

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loop

V

REGULATED

V

SENSEMAX

I

MATCH

V

LOADREG

V

REFLNREG

g

m

g

mOL

V

FCB

I

FCB

Regulated Voltage at IN

Maximum Current Sense Threshold V

Current Match Worst-Case Error at V

Output Voltage Load Regulation (Note 3)

Output Voltage Line Regulation VCC = 4.5V to 7V 0.03 %/V

Transconductance Amplifier g

Transconductance Amplifier GBW ITH = 1.2V, (gm • ZL, ZL = Series 1k-100kΩ-1nF) 1.5 MHz

Forced Continuous Threshold ● 0.58 0.60 0.62 V

FCB Bias Current V

+

(Note 3); VID Code = 110101, V

= 0.5V, V

EAIN

V

SENSE1–, VSENSE2–, VSENSE3–

Open, 65 75 85 mV

ITH

SENSE(MAX)

Measured in Servo Loop, ∆I
Measured in Servo Loop, ∆I

ITH = 1.2V, Sink/Source 25µA (Note 3) 3.05 mmho

m

= 0.65V 0.2 0.7 µA

FCB

= 1.2V 1.166 1.175 1.184 V

ITH

● 1.163 1.175 1.187 V

= 0.8V, 1.85V ● 62 75 88 mV

–5 5 %

Voltage = 1.2V to 0.7V ● 0.1 0.5 %

TH

Voltage = 1.2V to 2V ● –0.1 –0.5 %

TH

3738f

2

LTC3738

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. VCC = V

A

= VSS = 5V unless otherwise noted.

OUTEN

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

PSTH

Pulse Skip Threshold Measured at FCB pin VCC – 1.5 V

CC

– 0.7 V

– 0.3 V

CC

UVR Undervoltage SS Reset VCC Lowered Until the SS Pin is Pulled Low 3.3 3.8 4.5 V

I

Q

V

OUTEN

I

SS

V

SSARM

Input DC Supply Current (Note 4)
Normal Mode V
Shutdown V

OUTEN Pin ON Threshold V

Soft-Start Charge Current V

= 5V 2.5 mA

CC

= 0V 20 100 µA

OUTEN

, Ramping Positive 0.4 0.6 0.8 V

OUTEN

= 1.9V –0.8 –1.5 –2.5 µA

SS

SS Pin Arming Threshold VSS, Ramping Positive Until Short-Circuit 3.8 4.5 V

Latch-Off is Armed

V

SSLO

I

SCL

I

SDLHO

I

SENSE

DF

MAX

TG tR,t

BG t

R, tF

TG/BG t

F

SS Pin Latch-Off Threshold VSS, Ramping Negative 3.3 V

SS Discharge Current Soft-Short Condition V

Shutdown Latch Disable Current V

Total SENSE Pins Source Current SENSE1+, SENSE1–, SENSE2+, SENSE2–, 90 120 µA

= 0.3V, VSS = 4.5V 1.5 5 µA

EAIN

+

SENSE3

, SENSE3– All Equal 1.2V

EAIN

= 0.3V, V

= 4.5V –5 –1.5 µA

SS

Maximum Duty Factor In Dropout 95 98.5 %

Top Gate Rise Time C
Top Gate Fall Time C

Bottom Gate Rise Time C
Bottom Gate Fall Time C

Top Gate Off to Bottom Gate On Delay All Controllers, C

1D

= 3300pF 30 90 ns

LOAD

= 3300pF 40 90 ns

LOAD

= 3300pF 30 90 ns

LOAD

= 3300pF 20 90 ns

LOAD

= 3300pF Each Driver 60 ns

LOAD

Synchronous Switch-On Delay Time

BG/TG t

Bottom Gate Off to Top Gate On Delay All Controllers, C

2D

= 3300pF Each Driver 60 ns

LOAD

Top Switch-On Delay Time

t

ON(MIN)

Minimum On-Time Tested with a Square Wave (Note 5) 120 ns

VID Parameters

VID

VID

IL

IH

Maximum Low Level Input Voltage 0.4 V

Minimum High Level Input Voltage 0.8 V

VID9/VID10 VRM9 Enable Threshold at VID5 3.5 VCC – 1 4.5 V

ATTEN

ERR

VID0 to VID4 (Note 6) ● –0.25 0.25 %

Power Good Output Indication

V

PGL

I

PGOOD

V

PGTHNEG

V

PGTHPOS

t

PGBLNK

PGOOD Voltage Output Low I

PGOOD Output Leakage V

PGOOD Trip Thesholds V
V

Ramping Negative VID Code = 110101 –7 –10 – 14 %

DIFFOUT

V

Ramping Positive PGOOD Goes Low After V

DIFFOUT

= 2mA 0.1 0.3 V

PGOOD

= 5V ±1 µA

PGOOD

with Respect to Set Output Voltage,

DIFFOUT

Delay 7 10 14 %

UVDLY

Power Good Blanking After VID Changes Outside PGOOD Window 100 µs

3738f

3

LTC3738

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. VCC = V

A

= VSS = 5V unless otherwise noted.

OUTEN

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Oscillator and Phase-Locked Loop

f

NOM

f

LOW

f

HIGH

R

FCB

I

PLL LPF

R

RELPHS

Nominal Frequency V

Lowest Frequency V

Highest Frequency V

= 1.2V 325 365 415 kHz

PLLFLTR

= 0V 190 220 250 kHz

PLLFLTR

= 2.4V 480 550 630 kHz

PLLFLTR

FCB Clock Input Threshold 1.2 V

Phase Detector Output Current
Sinking Capability f
Sourcing Capability f

PLLIN
PLLIN

< f
> f

OSC
OSC

20 µA
20 µA

Controller 2-Controller 1 Phase 120 Deg
Controller 3-Controller 1 Phase 240 Deg

No_CPU Detection

t

NOCPU

No-CPU Shutdown Latency After All VID Bits = “1” 0.5 1 µs

Differential Amplifier

A

V

V

OS

Differential Gain 1.000 V/V

Input Offset Voltage IN+ = IN

–

= 1.2V, Input Referred 0.5 mV

CM Common Mode Input Voltage Range 0 5 V

+

CMRR Common Mode Rejection Ratio 0V < IN

–

= IN

< 5V, Input Referred 70 dB

GBP Gain Bandwidth Product 2 MHz

V

O(MAX)

R

IN

Maximum High Output Voltage V

– 0.8 V

CC

Input Resistance Measured at IN+ Pin 160 kΩ

Active Voltage Positioning

I

SINK

I

SOURCE

V

AVP

– V

Sinking Current Ability of AVP Pin IN+ = 1.2V 0.250 mA

Sourcing Current Ability of AVP Pin IN+ = 1.2V 1.4 mA

Max Voltage Drops V

O(MAX)

to VO IN+ = 1.2V, VIN = 60mV 180 mV

AVP

Thermal Detection

V

INT

V

INT_HYS

V

TH_TH

Thermal Comparator Trip Threshold 1.67 V

Hysteresis 0.21 V

Internal Detection Enable Threshold 3.4 VCC – 1 V

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: T
dissipation P

is calculated from the ambient temperature TA and power

J

according to the following formula:

D

TJ = TA + (PD × 34°C/W)

Note 3: The IC is tested in a feedback loop that includes the differential
amplifier driving the VID DAC into the error amplifier and servoing the
resultant voltage to the midrange point for the error amplifier (V

ITH

= 1.2V).

Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.

4

Note 5: The minimum on-time condition corresponds to an inductor peak­to-peak ripple current of ≥40% of I

(see minimum on-time

MAX

considerations in the Applications Information Section).
Note 6: ATTEN

specification is in addition to the output voltage

ERR

accuracy specified at VID code 110101.
Note 7: This IC includes overtemperature protection that is intended to protect

the device during momentary overload conditions. Junction temperature will
exceed 125°C when overtemperature protection is active. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.

3738f

UW

TEMPERATURE (°C)

–45

65

MAXIMUM I

SENSE

THRESHOLD (mV)

85

45

3738 G06

70

80

75

–30

90

0

–15

157530

60

VO = 1.85V

VO = 0.8V

TEMPERATURE (°C)

–45

3.0

UNDERVOLTAGE RESET (V)

5.0

45

3738 G09

3.5

4.5

4.0

–30

90

0

–15

157530

60

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3738

TA = 25°C unless otherwise noted.

Efficiency vs I

100

90

V

FCB/SYNC

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0.1

Reference Voltage
vs Temperature

610

605

600

OUT

= 5V

V

= OPEN

FCB/SYNC

V

= 0V

FCB/SYNC

VIN = 12V

= 1.2V

V

OUT

FREQUENCY = 210kHz

1

INDUCTOR CURRENT (A)

10

3738 G01

100

Efficiency vs V

92

91

90

89

88

EFFICIENCY (%)

87

86

85

4

5

Error Amplifier g
vs Temperature

4.0

3.5

(mmho)

m

3.0

6

IL = 20A

7

8

IN

= 12V

V

IN

FREQUENCY = 210kHz

IL = 50A

11

9

10 12

VIN (V)

m

13

3733 G02

Efficiency vs Frequency

92

91

90

89

88

87

EFFICIENCY (%)

86

VIN = 12V

85

= 1.2V

V

OUT

= 20A

I

LOAD

14

84

250 300 400

200

Maximum I

FREQUENCY (kHz)

SENSE

VIN = 5V

VIN = 10V

VIN = 14V

350

Threshold

450

500

3738 G03

vs Temperature

595

REFERENCE VOLTAGE (mV)

590

–45

–30

Oscillator Frequency
vs Temperature

600

550

500

450

400

350

300

FREQUENCY (kHz)

250

200

150

100

–45

–30

–15

V

PLLFLTR

V

PLLFLTR

V

PLLFLTR

V

PLLFLTR

–15

0

157530

157530

45

45

TEMPERATURE (°C)

= 5V

= 2.4V

= 1.2V

= 0V

0

TEMPERATURE (°C)

2.5

ERROR AMPLIFIER g

90

60

3738 G04

2.0
–45

–30

–15

0

157530

TEMPERATURE (°C)

45

90

60

3738 G05

Undervoltage Reset Voltage

Oscillator Frequency vs V

550

500

450

400

350

FREQUENCY (kHz)

300

250

90

60

3738 G07

200

0.8

0

0.4

1.2 2.0

V

PLLFLTR

(V)

1.6

PLLFLTR

2.4

3738 G08

vs Temperature

3738f

5

LTC3738

TEMPERATURE (°C)

–45

25

30

40

SHUTDOWN CURRENT (µA)

65

45

3738 G12

50

60

35

45

55

–30

90

0

–15

157530

60

V

ITH

(V)

0

–20

–10

0

I

SENSE

VOLTAGE THRESHOLD (mV)

10

30

40

50

90

70

1.6

3738 G15

20

80

60

0.8

2.4

1.2

0.4

2.0

UW

TYPICAL PERFOR A CE CHARACTERISTICS

TA = 25°C unless otherwise noted.

Short-Circuit Arming and Latchoff
vs Temperature

5.0

4.5

4.0

3.5

3.0

SS PIN VOLTAGE (V)

2.5

2.0
–45

–30

ARMING

LATCHOFF

0

–15

157530

TEMPERATURE (°C)

45

SS Pull-Up Current
vs Temperature

2.5

2.0

1.5

Shutdown Current

Supply Current vs Temperature

2.9

2.7

2.5

2.3

SUPPLY CURRENT (mA)

2.1

1.9
–45

90

60

3738 G10

–30

0

–15

TEMPERATURE (°C)

157530

45

90

60

3738 G11

vs Temperature

Maximum Current Sense
Threshold vs Duty Factor Peak Current Threshold vs V

75

50

ITH

1.0

SS PULL-UP CURRENT (µA)

0.5

0

–45

–30

Percentage of Nominal Output
vs Peak I

80

70

60

50

40

VOLTAGE (mV)

30

SENSE

20

PEAK I

10

0

0

10

PERCENTAGE OF NOMINAL OUTPUT VOLTAGE (%)

6

0

–15

TEMPERATURE (°C)

SENSE

30

20

157530

(Foldback)

50

60

40

VOLTAGE (mV)

25

SENSE

I

90

60

45

3738 G13

0

0

40

20

DUTY FACTOR (%)

60

100

80

3738 G14

Maximum Duty Factors
vs Temperature Total I

100

V

= 0V

PLLFLTR

98

96

94

92

MAXIMUM DUTY FACTOR (%)

100

90

80

70

3738 G16

90

–45

–30

0

–15

157530

TEMPERATURE (°C)

45

90

60

3738 G17

0

–20

–40

–60

–80

CURRENT (µA)

–100

SENSE

–120

–140

TOTAL I

–160

–180

0.2 0.4 0.6 0.8 1 2

0

Current vs V

SENSE

V

(V)

OUT

OUT

1.2 1.4 1.6 1.8

3738 G18

3738f

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3738

TA = 25°C unless otherwise noted.

Maximum Current Threshold
Mismatch vs Temperature

3.0

2.5

2.0

1.5

1.0

0.5

0

MAXIMUM CURRENT THRESHOLD MISMATCH (mV)

–45

–30

0

–15

157530

TEMPERATURE (°C)

45

Shed Mode at 1A,
Light Load Current

V

OUT

10mV/DIV

V

SW1

5V/DIV

V

SW2

5V/DIV

V

SW3

5V/DIV

= 12V

IN

= 1.5V

V

OUT

= V

V

FCB

CC

FREQUENCY = 210kHz

2µs/DIVV

– V

0

+

V

IN

– V

SENSE

+

) vs

SENSE

15

+

– V

–

)

SENSE

30

45

–

(mV)

60

3738 G20

(V

AVP

(V

SENSE

180

135

90

(mV)

+

IN

– V

45

AVP

V

0

90

60

3738 G19

–45

–15

Pulse Skip Mode at 1A,
Light Load Current

V

OUT

10mV/DIV

V

SW1

5V/DIV

V

SW2

5V/DIV

V

SW3

5V/DIV

3738 G21

= 12V

IN

= 1.5V

V

OUT

= OPEN

V

FCB

FREQUENCY = 210kHz

2µs/DIVV

3738 G22

V

OUT

10mV/DIV

V

SW1

5V/DIV

V

SW2

5V/DIV

V

SW3

5V/DIV

Continuous Mode at 1A,
Light Load Current

= 12V

IN

= 1.5V

V

OUT

= GND

V

FCB

FREQUENCY = 210kHz

2µs/DIVV

3738 G23

V

OUT

50mV/DIV

∆I

OUT

100A STEP

dI/dt > 200A/µs

Load Transient with AVP

80mV

VIN = 12V

= 1.35V

V

OUT

= 10 × 330µF/2.5V

C

OUT

SANYO TPE POSCAP
+ 18 × 22µF/X5R CERAMIC

INTEL
SPEC

3738 G24

3738f

7

LTC3738

U

UU

PI FU CTIO S

FCB/SYNC (Pin 1): Forced Continuous Control Input. The
voltage applied to this pin sets the operating mode of the
controller. The forced continuous current mode is active
when the applied voltage is less than 0.6V. Pulse skip
mode operation will be active when the pin is allowed to
float and Stage Shedding mode will be active if the pin is
tied to the VCC pin. When an external clock is present, the
controller will be synchronized to the external clock and
forced continuous mode is selected internally. (Do not
apply voltage to this pin prior to the application of voltage
on the VCC pin.)

PLLFLTR (Pin 2): The phase-locked loop’s lowpass filter
is tied to this pin. Alternatively, this pin can be driven with
an AC or DC voltage source to vary the frequency of the
internal oscillator. (Do not apply voltage to this pin prior to
the application of voltage on the VCC pin.)

IN+, IN– (Pins 4, 3): Inputs to a Precision, Unity-Gain
Differential Amplifier with Internal Precision Resistors.
This provides true remote sensing of both the positive and
negative load terminals for precise output voltage control.

AVP (Pin 5): Active Voltage Positioning Load Slope Pro­gramming Pin. A resistor tied between this pin and IN
sets the load slope.

EAIN (Pin 6): This is the input to the error amplifier which
compares the VID divided feedback voltage to the internal

0.6V reference voltage.

SENSE1+, SENSE2+, SENSE3+, SENSE1–, SENSE2–,
SENSE3– (Pins 7 to 12): The Inputs to Each Differential

Current Comparator. The ITH pin voltage and built-in
offsets between the SENSE– and SENSE+ pins, in conjunc­tion with R

, set the current trip threshold level.

SENSE

+

SS (Pin 13): Combination of Soft-Start and Short-Circuit
Detection Timer. A capacitor to ground at this pin sets the
ramp time to full current output as well as the time delay
prior to an output voltage short-circuit shutdown.

ITH (Pin 14): Error Amplifier Output and Switching Regu­lator Compensation Point. All three current comparator’s
thresholds increase with this control voltage.

TSNS (Pin 15): This pin selects external or internal ther­mal detection. Tying this pin to VCC will enable the internal
thermal detector. When the voltage at this pin is less than
V

– 1.6V, the internal thermal detector is disabled and

CC

this pin serves as the input to an internal comparator
which is referenced to VCC/3.

VR_HOTB (Pin 16): This open-collector output is pulled
low when voltage at the TSNS pin is less than VCC/3. If
TSNS is tied to VCC, this pin is pulled low when the internal
thermal detector is tripped.

PGND (Pin 24): Driver Power Ground. This pin connects
to the sources of the bottom N-channel external MOSFETs
and the (–) terminals of CIN.

BG1, BG2, BG3 (Pins 25, 23, 22): High Current Gate
Drives for the Bottom N-Channel MOSFETs. Voltage swing
at these pins is from ground to VCC.

VCC (Pin 26): Main Supply Pin. Because this pin supplies
both the controller circuit power as well as the high power
pulses supplied to drive the external MOSFET gates, this
pin needs to be very carefully and closely decoupled to the
IC’s PGND pin.

8

3738f

LTC3738

U

UU

PI FU CTIO S

SW1, SW2, SW3 (Pins 30, 27, 21): Switch Node Connec­tions to Inductors. Voltage swing at these pins is from a
Schottky diode (external) voltage drop below ground to
VIN (where VIN is the external MOSFET supply rail).

TG1, TG2, TG3 (Pins 31, 28, 20): High Current Gate Drives
for Top N-Channel MOSFETs. These are the outputs of the
floating drivers with a voltage swing equal to the boost
voltage source superimposed on the switch node voltage
SW.

BOOST1, BOOST2, BOOST3 (Pins 32, 29, 19): Positive
Supply Pins to the Topside Floating Drivers. Bootstrapped
capacitors, charged with external Schottky diodes and a
boost voltage source are connected between the BOOST and
SW pins. Voltage swing at the BOOST pins is from the boost
source voltage (typically VCC) to this boost source voltage
+VIN (where VIN is the external MOSFET supply rail).

PGOOD (Pin 33): This open-drain output is pulled low
when the output voltage is outside the PGOOD tolerance
window. PGOOD is blanked during VID transitions for
approximately 100µs.

VID0, VID1, VID2, VID3, VID4, VID5 (Pins 35, 36, 37, 17,
18, 34): Output Voltage Programming Input Pins. When

VID5 is tied to VCC, the Intel VRM9 VID table is selected.
When voltage of VID5 is less than VCC – 2V, VID5 serves
as the fifth VID bit of VRM10.

OUTEN (Pin 38): On/Off Control of the Controller.

SGND (Pin 39, Exposed Pad): Signal Ground. This pin

must be soldered to the ground plane.

3738f

9

LTC3738

U

U

W

FU CTIO AL DIAGRA

PGOOD

2.4V

2.5µA

+

FCB

–

0.6V

V

FB

SENSE1
SENSE1
SENSE2
SENSE2
SENSE3
SENSE3

PHASE DET

OSCILLATOR

80k80k

–

A1

+

80k80k

+
–
+
–
+
–

–

EA

+

OV

+

–

CLK1

CLK2
CLK3

R2 VARIABLE

PLLFLTR

R

LP

C

LP

–

+

+

–

–
+

–
+

+

–

ADDER

0.600V

0.660V

VID

VRM9/VRM10 VID DECODER

R

AVP

FCB/SYNC

IN

IN

R

PRE-AVP

AVP

EAIN

I

TH

C

C

R

C

SELECTION

100µs

BLANKING

VID TRANSITIONS

DUPLICATE FOR SECOND AND THIRD
CONTROLLER CHANNELS

R1

8k

V

CC

6V

5(VFB)

1.5µA

RS

LATCH

SRQ

SLOPE
COMP

TSNS

0.66V

–

+

EAIN

–

+

0.54V

DROP

OUT

DET

Q

–

I

1

5(V

+

2.4V

SHDN

RST

+–

)

FB

INTERNAL
THERMAL

DETECTION

FORCED BOT

+–

3mV

SHED

RUN

SOFT-

START

VCC/3

TOP ON

FCB

SHDN

45k45k

–

I

+

–

+

SWITCH

LOGIC

2

0.600V

INTERNAL

SUPPLY

TCMP

TOP

BOT

MUX

V

V

CC

30k

30k

V

CC

REF

VR_HOTB

BOOST

TG

SW

BG

PGND

SENSE

SENSE

V

CC

SGND

SS

V

CC

+

R

SENSE

–

V

IN

D

B

C

B

L

+

C

IN

C

OUT

+

V

OUT

V

CC

+

C

CC

10

VID0 VID1 VID2 VID3 VID4

VID5

NO_CPU

1µs

Figure 1

100k

OUTEN

C

SS

3738 F01

3738f

OPERATIO

LTC3738

U

(Refer to Functional Diagram)

Main Control Loop

The IC uses a constant frequency, current mode step­down architecture. During normal operation, each top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator, I1, resets each RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by the
voltage on the I
amplifier EA. The EAIN pin receives a portion of the voltage
feedback signal via the differential amplifier through the
internal VID DAC and is compared to the internal reference
voltage. When the load current increases, it causes a slight
decrease in the EAIN pin voltage relative to the 0.6V
reference, which in turn causes the ITH voltage to increase
until each inductor’s average current matches one third of
the new load current (assuming all three current sensing
resistors are equal). In pulse skip mode and Stage Shed­ding mode, after each top MOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current compara­tor I2, or the beginning of the next cycle.

The top MOSFET drivers are biased from floating boot­strap capacitor CB, which is normally recharged during
each off cycle through an external Schottky diode. When
VIN decreases to a voltage close to V
loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector counts the
number of oscillator cycles that the bottom MOSFET
remains off and periodically forces a brief on period to
allow CB to recharge.

The main control loop is shut down by pulling the OUTEN
pin low. Pulling up OUTEN allows an internal 1.5µA current
source to charge soft-start capacitor CSS at the SS pin. The
internal ITH voltage is clamped to the SS voltage while C
is slowly charged up. This “soft-start” clamping prevents
abrupt current from being drawn from the input power
source. When the OUTEN pin is low, all functions are kept
in a controlled state.

pin, which is the output of the error

TH

, however, the

OUT

SS

Low Current Operation

The FCB/SYNC pin is a multifunction pin: 1) a logic input
to select between three modes of operation and 2) external
clock input pin for synchronization.

When the FCB
controller performs as a continuous, PWM current mode
synchronous switching regulator. The top and bottom
MOSFETs are alternately turned on to maintain the output
voltage independent of direction of inductor current.

When the FCB/SYNC pin is below VCC – 1.5V, but greater
than 0.6V, the controller performs as a pulse skip mode
switching regulator. Pulse skip mode operation turns off
the synchronous MOSFET(s) when the inductor current
goes negative. Switching cycles will be skipped when the
output load current drops below 3% of the maximum
designed load current in order to maintain the output
voltage. Pulse skip operation provides low noise, constant
frequency operation at light load conditions.

When the FCB/SYNC pin is tied to the VCC pin, Stage
Shedding mode is enabled. This mode provides constant
frequency, discontinuous current operation over the wid­est possible output current range. At approximately 10%
of maximum designed load current, the second and third
output stages are shut off and the first controller alone is
active in discontinuous current mode. This “stage shed­ding” optimizes efficiency by eliminating the gate charging
losses and switching losses of the other two output
stages. Additional cycles will be skipped when the output
load current drops below 1% of maximum designed load
current in order to maintain the output voltage. This
constant frequency operation is more efficient than pulse
skip mode operation at very light load conditions.

/SYNC

pin voltage is below 0.6V, the

3738f

11

LTC3738

OPERATIO

U

(Refer to Functional Diagram)

Tying the FCB
current operation. This is the least efficient operating
mode, but may be desirable in certain applications. The
output can source or sink current in this mode. When
forcing continuous operation and sinking current, this
current will be forced back into the main power supply,
potentially boosting the input supply to dangerous volt­age levels.

Feeding a clock signal into the FCB/SYNC pin will syn­chronize the LTC3738 to the external clock. See Fre­quency Synchronization or Setup for more information.

Frequency Synchronization or Setup

The phase-locked loop allows the internal oscillator to be
synchronized to an external source using the FCB/SYNC
pin. The output of the phase detector at the PLLFLTR pin
is also the DC frequency control input of the oscillator
which operates over a 210kHz to 530kHz range corre­sponding to a voltage input from 0V to 2.4V. When locked,
the PLL aligns the turn on of the top MOSFET to the rising
edge of the synchronizing signal and forced continuous
mode is set internally. When no frequency information is
supplied to the FCB/SYNC pin, PLLFLTR goes low, forcing
the oscillator to minimum frequency. A DC source can be
applied to the PLLFLTR pin to externally set the desired
operating frequency.

Differential Amplifier

This amplifier provides true differential output voltage
sensing. Sensing both V
tion in high current applications and/or applications hav­ing electrical interconnection losses. This sensing also
isolates the physical power ground from the physical
signal ground preventing the possibility of troublesome
“ground loops” on the PC layout and prevents voltage
errors caused by board-to-board interconnects, particu­larly helpful in VRM designs.

/SYNC

pin to ground will force continuous

OUT

+

and V

–

benefits regula-

OUT

Power Good

The PGOOD pin is connected to the drain of an internal
MOSFET. The MOSFET is turned on when the output
voltage exceeds the PGOOD ±10% tolerance window. The
PGOOD signal is blanked for approximately 100µs during
VID transitions. If a new VID transition occurs before the
previous blanking time expires, the timer is reset.

Short-Circuit Detection

The SS capacitor is used initially to limit the inrush current
from the input power source. Once the controllers have
been given time, as determined by the capacitor on the SS
pin, to charge up the output capacitors and provide full
load current, the SS capacitor is then used as a short­circuit timeout circuit. If the output voltage falls to less
than 62.5% of its nominal output voltage, the SS capacitor
begins discharging, assuming that the output is in a severe
overcurrent and/or short-circuit condition. If the condition
lasts for a long enough period, as determined by the size
of the SS capacitor, the controller will be shut down until
the OUTEN pin voltage is recycled. This built-in latchoff
can be overridden by providing > 5µA at a compliance of 4V
to the SS pin. This current shortens the soft-start period
but prevents net discharge of the SS capacitor during a
severe overcurrent and/or short-circuit condition. Foldback
current limiting is activated when the output voltage falls
below 62.5% of its nominal level whether or not the short­circuit latchoff circuit is enabled. Foldback current limit
can be overridden by clamping the EAIN pin such that the
voltage is held above the (62.5%)(0.6V) or 0.375V level
even when the actual output voltage is low.

The SS capacitor will be reset if the input voltage, (VCC) is
allowed to fall below approximately 4V. The capacitor on
the pin will be discharged until the short-circuit arming
latch is disarmed. The SS capacitor will attempt to cycle
through a normal soft-start ramp up after the VCC supply
rises above 4V. This circuit prevents power supply latchoff
in the event of input power switching break-before-make
situations.

12

3738f

OPERATIO

LTC3738

U

(Refer to Functional Diagram)

Start-Up

The start-up of the LTC3738 is controlled by the voltage
ramp on the SS pin. The start-up is not completed until the
short-circuit arming latch is enabled. During start-up, the
foldback current limit is temporarily defeated and at the
same time no reverse inductor current is allowed. This is
helpful for situations where output voltage has been “pre­biased” at some voltage before the controller is enabled.
This will prevent sinking current during start-up which
would otherwise pull current from the pre-biased output.

VID Table and NO_CPU Detection

The LTC3738 has a VID block which is compatible with
VRM9 and VRM10. Tying VID5 to VCC will select the VRM9
table. When the voltage at VID5 is less than V
VRM10 table is selected and this pin serves as the VID5 bit
of VRM10. There is a built in –25mV output offset for the
VRM10 VID table and a –12.5mV output offset for the
VRM9 VID table.

The LTC3738 detects the presence of CPU by monitoring
the VID bits. If a VID0-VID4 all “1” condition is detected,
the controller acknowledges a NO_CPU fault. If this fault
condition persists for more than 1µs, the SS pin is pulled
low and the controller is shut down. The LTC3738 will
attempt a normal start-up when the NO_CPU fault is
removed.

– 1.5V, the

CC

Thermal Detection

An accurate comparator and a thermal detector are inte­grated into the LTC3738 for external or internal thermal
detection. Tying TSNS to VCC will enable an internal
thermal detector which generates a thermal event at or
above 120°C with 10°C hysteresis. When the voltage at
TSNS is less than V
is disabled and this pin serves as the input to an accurate
comparator which is referenced to VCC/3 with a hysteresis
of VCC/24. A thermal event is generated when the voltage
at TSNS is less than VCC/3. VR_HOTB, an open-collector
output pin, will be pulled low when a thermal event occurs.

Active Voltage Positioning

Load slope is programmable in the LTC3738 through
external resistors. The inductor current information for all
three channels is sensed and combined; the final result is
presented as a voltage drop between AVP and IN+. This
voltage drop is scaled through two external resistors
attached to IN+ and then added to the output voltage as the
compensation for load slope. The final load slope is
defined by the inductor current sense resistors and the
two external resistors mentioned above.

– 1.6V, the internal thermal detector

CC

3738f

13

LTC3738

WUUU

APPLICATIO S I FOR ATIO

The basic application circuit is shown on the first page of
this data sheet. External component selection is driven by
the load requirement, and normally begins with the selec­tion of an inductance value based upon the desired
operating frequency, inductor current and output voltage
ripple requirements. Once the inductors and operating
frequency have been chosen, the current sensing resis­tors can be calculated. Next, the power MOSFETs and
Schottky diodes are selected. Finally, CIN and C

OUT

are
selected according to the required voltage ripple require­ments. The circuit shown on the first page of this data
sheet can be configured for operation up to a MOSFET
supply voltage of 28V (limited by the external MOSFETs).

Operating Frequency

The IC uses a constant frequency architecture with the
frequency determined by an internal capacitor. This ca­pacitor is charged by a fixed current plus an additional
current which is proportional to the voltage applied to the
PLLFLTR pin. Refer to the Phase-Locked Loop and Fre­quency Synchronization and Setup sections for additional
information.

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter­related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge and transition losses. In addition to
this basic tradeoff, the effect of inductor value on ripple
current and low current operation must also be consid­ered. The PolyPhase approach reduces both input and
output ripple currents while optimizing individual output
stages to run at a lower fundamental frequency, enhancing
efficiency.

The inductor value has a direct effect on ripple current. The
inductor ripple current ∆IL per individual section, N,
decreases with higher inductance or frequency and in­creases with higher VIN or V

⎛

∆I

= −

L

V

OUT OUT

fL

V

1

⎜
⎝

V

IN

:

OUT

⎞
⎟

⎠

A graph for the voltage applied to the PLLFLTR pin versus
frequency is given in Figure 2. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 530kHz.

550

450

350

250

OPERATING FREQUENCY (kHz)

150

0 0.5 1.0 1.5 2.0 2.5

PLLFLTR PIN VOLTAGE (V)

3738 F02

Figure 2. Operating Frequency vs V

PLLFLTR

where f is the individual output stage operating frequency.

In a PolyPhase converter, the net ripple current seen by the
output capacitor is much smaller than the individual
inductor ripple currents due to the ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.

Figure 3 shows the net ripple current seen by the output
capacitors for the different phase configurations. The
output ripple current is plotted for a fixed output voltage as
the duty factor is varied between 10% and 90% on the
x-axis. The output ripple current is normalized against the
inductor ripple current at zero duty factor. The graph can
be used in place of tedious calculations. As shown in
Figure 3, the zero output ripple current is obtained when:

V

OUT

V

k

==12 1, ,..., –

where k N

N

IN

14

3738f

WUUU

APPLICATIO S I FOR ATIO

1.0

0.9

0.8

0.7

0.6

/fL

0.5

O

O(P-P)

V

I

0.4

0.3

0.2

0.1

0

0.1 0.2 0.3 0.4
DUTY FACTOR (V

Figure 3. Normalized Peak Output Current
vs Duty Factor [I

0.5 0.6 0.7 0.8 0.9

= 0.3(I

RMS

So the number of phases used can be selected to minimize
the output ripple current and therefore the output ripple
voltage at the given input and output voltages. In applica­tions having a highly varying input voltage, additional
phases will produce the best results.

Accepting larger values of ∆IL allows the use of low
inductances but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
∆IL = 0.4(I
I

is the total load current. Remember, the maximum

OUT

)/N, where N is the number of channels and

OUT

∆IL occurs at the maximum input voltage. The individual
inductor ripple currents are constant determined by the
inductor, input and output voltages.

OUT/VIN

O(P-P)

1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE

)

3738 F03

]

LTC3738

Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!

Power MOSFET and Schottky Diode Selection

At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N-channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and “on” resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as the
actual position (main or synchronous) in which the MOSFET
will be used. A much smaller and much lower input
capacitance MOSFET should be used for the top MOSFET
in applications that have an output voltage that is less than
1/3 of the input voltage. In applications where V
the top MOSFETs’ “on” resistance is normally less impor­tant for overall efficiency than its input capacitance at
operating frequencies above 300kHz. MOSFET manufac­turers have designed special purpose devices that provide
reasonably low “on” resistance with significantly reduced
input capacitance for the main switch application in switch­ing regulators.

IN

>> V

OUT

,

Inductor Core Selection

Once the value for the inductors is known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of ferrite, molyper­malloy or Kool Mµ® cores. Actual core loss is independent
of core size for a fixed inductor value, but it is very
dependent on inductance selected. As inductance in­creases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.

The peak-to-peak MOSFET gate drive levels are set by the
voltage, VCC, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BV

specification for the MOSFETs as well; many of the

DSS

logic-level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the “on”
resistance R

, input capacitance, input voltage and

SD(ON)

maximum output current.

MOSFET input capacitance is a combination of several
components but can be taken from the typical “gate
charge” curve included on most data sheets (Figure 4).

Kool Mµ is a registered trademark of Magnetics, Inc.

3738f

15

LTC3738

WUUU

APPLICATIO S I FOR ATIO

V

IN

V

GS

The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gate­to-drain capacitance. The flat portion of the curve is the
result of the Miller capacitance effect of the drain-to­source capacitance as the drain drops the voltage across
the current source load. The upper sloping line is due to
the drain-to-gate accumulation capacitance and the gate­to-source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given V
adjusted for different VDS voltages by multiplying by the
ratio of the application VDS to the curve specified V
values. A way to estimate the C
change in gate charge from points a and b on a manufac­turers data sheet and divide by the stated VDS voltage
specified. C
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C
and COS are specified sometimes but definitions of these
parameters are not included.

When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:

Main Switch Duty Cycle

Synchronous Switch Duty Cycle

MILLER EFFECT

ab

V

Q

C

MILLER

IN

= (QB – QA)/V

Figure 4. Gate Charge Characteristic

MILLER

DS

is the most important selection criteria

=

GS

drain voltage, but can be

DS

MILLER

V

OUT

V

IN

V

3738 F04

V

DS

term is to take the

RSS

⎛

VV

IN OUT

=

⎜
⎝

–

V

IN

⎞
⎟

⎠

DS

The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:

2

I

⎞
⎟

⎠

N

RC

()( )

DR MILLER

N

11

() ()

⎛
⎜

⎝

N

R

+

1

()

DS ON

()

•

⎤

+

2

⎞

1δδ

()

⎟
⎠

()

⎥
⎥

⎦

R

+

DS ON

+

f

()

P

MAIN

P

SYNC

V

⎛

OUTINMAX

=

⎜
⎝

V

I

2

MAX

V

IN

2

⎡
⎢

VV V

–

CC TH MIN TH MIN

⎢

⎣

VVVI

–

IN OUTINMAX

=

where N is the number of output stages, δ is the tempera­ture dependency of R
resistance (approximately 2Ω at VGS = V
drain potential

and

the change in drain potential in the

particular application. V

, RDR is the effective top driver

DS(ON)

MILLER

TH(MIN)

is the data sheet specified

), VIN is the

typical gate threshold voltage specified in the power
MOSFET data sheet. C

is the calculated capacitance

MILLER

using the gate charge curve from the MOSFET data sheet
and the technique described above.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For VIN < 12V, the
high current efficiency generally improves with larger
MOSFETs, while for V

> 12V, the transition losses

IN

rapidly increase to the point that the use of a higher
R

DS(ON)

device with lower C

actually provides higher

RSS

efficiency. The synchronous MOSFET losses are greatest
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.

The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized R

vs temperature curve, but

DS(ON)

δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.

16

3738f

WUUU

APPLICATIO S I FOR ATIO

LTC3738

The Schottky diodes shown in the Typical Application on
the first page of this data sheet conduct during the dead
time between the conduction of the two large power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead
time and requiring a reverse recovery period which could
cost as much as several percent in efficiency. A 2A to 8A
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance.

CIN and C

Selection

OUT

Input capacitance ESR requirements and efficiency losses
are reduced substantially in a multiphase architecture
because the peak current drawn from the input capacitor
is effectively divided by the number of phases used and
power loss is proportional to the RMS current squared. A
3-stage, single output voltage implementation can reduce
input path power loss by 90%.

In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V

OUT/VIN

.
A low ESR input capacitor sized for the maximum RMS
current must be used. The details of a close form equation
can be found in Application Note 77. Figure 5 shows the
input capacitor ripple current for different phase configu­rations with the output voltage fixed and input voltage
varied. The input ripple current is normalized against the
DC output current. The graph can be used in place of
tedious calculations. The minimum input ripple current
can be achieved when the product of phase number and
output voltage, N(V

), is approximately equal to the

OUT

input voltage VIN or:

V

OUT

V

k

==12 1, ,..., –

where k N

N

IN

So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages.

In the graph of Figure 5, the local maximum input RMS
capacitor currents are reached when:

V

OUT

V

IN

k

21

==

where k N

12–, ,...,

N

These worst-case conditions are commonly used for de­sign because even significant deviations do not offer much
relief. Note that capacitor manufacturer’s ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than re­quired. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult
the capacitor manufacturer if there is any question.

The Figure 5 graph shows that the peak RMS input current
is reduced linearly, inversely proportional to the number N
of stages used. It is important to note that the efficiency
loss is proportional to the input RMS current squared and
therefore a 3-stage implementation results in 90% less
power loss when compared to a single phase design. Bat­tery/input protection fuse resistance (if used), PC board
trace and connector resistance losses are also reduced by
the reduction of the input ripple current in a PolyPhase
system. The required amount of input capacitance is
further reduced by the factor, N, due to the effective in­crease in the frequency of the current pulses.

Ceramic capacitors are becoming very popular for small
designs but several cautions should be observed. “X7R”,
“X5R” and “Y5V” are examples of a few of the ceramic
materials used as the dielectric layer, and these different
dielectrics have very different effect on the capacitance
value due to the voltage and temperature conditions

0.6

0.5

0.4

0.3

0.2

DC LOAD CURRENT

RMS INPUT RIPPLE CURRNET

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Figure 5. Normalized Input RMS Ripple Current
vs Duty Factor for One to Six Output Stages

DUTY FACTOR (V

1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE

OUT/VIN

0.9

)

3738 F05

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APPLICATIO S I FOR ATIO

applied. Physically, if the capacitance value changes due
to applied voltage change, there is a concommitant piezo
effect which results in radiating sound! A load that draws
varying current at an audible rate may cause an attendant
varying input voltage on a ceramic capacitor, resulting in
an audible signal. A secondary issue relates to the energy
flowing back into a ceramic capacitor whose capacitance
value is being reduced by the increasing charge. The
voltage can increase at a considerably higher rate than the
constant current being supplied because the capacitance
value is decreasing as the voltage is increasing! Ceramic
capacitors, when properly selected and used however, can
provide the lowest overall loss due to their extremely low
ESR.

The selection of C

is driven by the required effective

OUT

series resistance (ESR). Typically once the ESR require­ment is satisfied the capacitance is adequate for filtering.
The steady-state output ripple (∆V

∆∆V I ESR

≈ +

OUT RIPPLE

⎛
⎜

⎝

NfC

8

) is determined by:

OUT

⎞

1

⎟
⎠

OUT

where f = operating frequency of each stage, N is the
number of output stages, C

= output capacitance and

OUT

∆IL = ripple current in each inductor. The output ripple is
highest at maximum input voltage since ∆IL increases
with input voltage. The output ripple will be less than 50mV
at max VIN with ∆IL = 0.4I

C

required ESR < N • R

OUT

OUT(MAX)

assuming:

SENSE

and

C

> 1/(8Nf)(R

OUT

SENSE

)

The emergence of very low ESR capacitors in small,
surface mount packages makes very small physical imple­mentations possible. The ability to externally compensate
the switching regulator loop using the ITH pin allows a
much wider selection of output capacitor types. The
impedance characteristics of each capacitor type is sig­nificantly different than an ideal capacitor and therefore
requires accurate modeling or bench evaluation during
design.

Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance through-

hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo and the Panasonic SP
surface mount types have a good (ESR)(size) product.
Once the ESR requirement for C
RMS current rating generally far exceeds the I

has been met, the

OUT

RIPPLE(P-P)

requirement. Ceramic capacitors from AVX, Taiyo Yuden,
Murata and Tokin offer high capacitance value and very
low ESR, especially applicable for low output voltage
applications.

In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum elec­trolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer sur­face mount capacitors offer very low ESR also but have
much lower capacitive density per unit volume. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
choices are the AVX TPS, AVX TPSV, the KEMET T510
series of sur

face-mount tantalums or the Panasonic SP
series of surface mount special polymer capacitors avail­able in case heights ranging from 2mm to 4mm. Other
capacitor types include Sanyo POS-CAP, Sanyo OS-CON,
Nichicon PL series and Sprague 595D series. Consult the
manufacturer for other specific recommendations.

R

Selection for Output Current

SENSE

Once the frequency and inductor have been chosen,
R

SENSE1, RSENSE2, RSENSE3

are determined based on the
required peak inductor current. The current comparator
has a maximum threshold of 75mV/R

SENSE

and an input
common mode range of SGND to (1.1) • VCC. The current
comparator threshold sets the peak inductor current,
yielding a maximum average output current I

MAX

equal to

the peak value less half the peak-to-peak ripple current,
∆IL.

Allowing a margin for variations in the IC and external
component values yields:

mV

RN

SENSE

The IC works well with values of R

50

=

I

MAX

from 0.001Ω to

SENSE

0.02Ω.

3738f

18

R

R

R

VA

SENSE

AVP

PRE AVP

•/

−

⎛
⎝

⎜

⎞
⎠

⎟

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APPLICATIO S I FOR ATIO

LTC3738

VCC Decoupling

The VCC pin supplies power not only to the internal circuits
of the controller but also to the top and bottom gate
drivers and therefore must be bypassed very carefully to
ground with a ceramic capacitor, type X7R or X5R (de­pending upon the operating temperature environment) of

at least 1µF imme

diately next to the IC

and preferably an
additional 10µF placed very close to the IC due to the
extremely high instantaneous currents involved. The total
capacitance, taking into account the voltage coefficient of
ceramic capacitors, should be 100 times as large as the
total combined gate charge capacitance of ALL of the
MOSFETs being driven. Good bypassing close to the IC is
necessary to supply the high transient currents required
by the MOSFET gate drivers while keeping the 5V supply
quiet enough so as not to disturb the very small-signal
high bandwidth of the current comparators.

Topside MOSFET Driver Supply (CB, DB)

External bootstrap capacitors, CB, connected to the BOOST
pins, supply the gate drive voltages for the topside
MOSFETs. Capacitor CB in the Functional Diagram is
charged though diode DB from VCC when the SW pin is
low. When one of the topside MOSFETs turns on, the
driver places the CB voltage across the gate-source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply (V

BOOST

=
VCC + VIN). The value of the boost capacitor CB needs to be
30 to 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of DB must be
greater than V

IN(MAX).

common, tightly coupled pair of PC traces. The differen­tial amplifier rejects common mode signals capacitively
or inductively radiated into the feedback PC traces as well
as ground loop disturbances. The differential amplifier
output signal is divided down through the VID DAC and
is compared with the internal, precision 0.6V voltage
reference by the error amplifier.

The amplifier has a 0 to VCC common mode input range
and an output swing range of 0 to V

– 1.2V. The output

CC

uses an NPN emitter follower with 160kΩ feedback
resistance.

Output Voltage

Selection of the VRM9 or VRM10 VID table is through the
VID5 pin. Tying VID5 to VCC will select the VRM9 VID table.

If the VRM9 VID table is selected (Table 1), output voltage
in 25mV increments is produced from 1.1V to 1.85V.
There is a built-in –12.5mV DC offset for the output
voltage.

If the VRM10 VID table is selected (Table 2), output voltage
in 12.5mV increments is produced from 0.8375V to 1.6V.
There is a built-in –25mV DC offset for output voltage.

Active Voltage Position Control

The LTC3738 senses inductor current information through
monitoring voltage drops on the sense resistor R

SENSE

of
all three channels. The voltage drops are added together
and applied as V

PRE-AVP

which are connected through resistor R
V

PRE-AVP

is scaled through R

between the AVP and IN+ pins,

PRE-AVP

and added to output

AVP

. Then

voltage as the compensation for the load voltage drop. In
summary, the load slope is:

Differential Amplifier

The IC has a true remote voltage sense capability. The
sensing connections should be returned from the load,
back to the differential amplifier’s inputs through a

The recommended value for R

is 90Ω to 100Ω.

AVP

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Table 1. VRM9 VID Table

PROCESSOR PINS (0 = L0W, 1 = HIGH)

VID4 VID3 VID2 VID1 VID0 (VDC)

1 1 1 1 1 Output Off

1 1 1 1 0 1.100

1 1 1 0 1 1.125

1 1 1 0 0 1.150

1 1 0 1 1 1.175

1 1 0 1 0 1.200

1 1 0 0 1 1.225

1 1 0 0 0 1.250

1 0 1 1 1 1.275

1 0 1 1 0 1.300

1 0 1 0 1 1.325

1 0 1 0 0 1.350

1 0 0 1 1 1.375

1 0 0 1 0 1.400

1 0 0 0 1 1.425

1 0 0 0 0 1.450

0 1 1 1 1 1.475

0 1 1 1 0 1.500

0 1 1 0 1 1.525

0 1 1 0 0 1.550

0 1 0 1 1 1.575

0 1 0 1 0 1.600

0 1 0 0 1 1.625

0 1 0 0 0 1.650

0 0 1 1 1 1.675

0 0 1 1 0 1.700

0 0 1 0 1 1.725

0 0 1 0 0 1.750

0 0 0 1 1 1.775

0 0 0 1 0 1.800

0 0 0 0 1 1.825

0 0 0 0 0 1.850

V

CC(CORE)

Thermal Control

When external thermal detection is enabled, the TSNS pin
serves as the input to an accurate comparator which is
referenced to VCC/3 and has a hysteresis of VCC/24.
VR_HOTB is pulled low when the voltage at TSNS is less
than VCC/3. In this case, the input of TSNS is an analog
signal. If necessary, lowpass filter the signal before feed­ing it into the pin to avoid a false thermal trip.

When VR_HOTB is reported, the operation of LTC3738 will
not be affected, although there is another thermal sensor
inside the IC for self protection. When the temperature of
the IC is around 140°C, the LTC3738 will shut down and
not start-up again until this overtemperature situation has
been removed. This self shutdown feature is not tested but
is guaranteed by design.

ON/OFF Control

The OUTEN pin provides simple ON/OFF control for the
LTC3738. Driving the OUTEN pin above 0.8V permits the
controller to start operating. Pulling OUTEN below 0.4V
puts the LTC3738 into low current shutdown (IQ ≈ 50µA).

Soft-Start Function

The SS pin provides two functions: 1) soft-start and 2) a
defeatable short-circuit latch off timer. Soft-start reduces
the input power sources’ surge currents by gradually
increasing the controller’s current limit (proportional to an
internal buffered and clamped V

). The latchoff timer

ITH

prevents very short, extreme load transients from tripping
the overcurrent latch. A small pull-up current (>5µA)
supplied to the SS pin will prevent the overcurrent latch
from operating. The following explanation describes how
this function operates.

An internal 1.5µA current source charges up the C

SS

capacitor. As the voltage on SS increases from 0V to 2.4V,

20

3738f

LTC3738

Table 2. VRM10 VID Table

PROCESSOR PINS (0 = LOW, 1 = HIGH) PROCESSOR PINS (0 = LOW, 1 = HIGH)

VID4 VID3 VID2 VID1 VID0 VID5

0 1 0 1 0 0 0.8375 1 1 0 1 0 0 1.2125

0 1 0 0 1 1 0.8500 1 1 0 0 1 1 1.2250

0 1 0 0 1 0 0.8625 1 1 0 0 1 0 1.2375

0 1 0 0 0 1 0.8750 1 1 0 0 0 1 1.2500

0 1 0 0 0 0 0.8875 1 1 0 0 0 0 1.2625

0 0 1 1 1 1 0.9000 1 0 1 1 1 1 1.2750

0 0 1 1 1 0 0.9125 1 0 1 1 1 0 1.2875

0 0 1 1 0 1 0.9250 1 0 1 1 0 1 1.3000

0 0 1 1 0 0 0.9375 1 0 1 1 0 0 1.3125

0 0 1 0 1 1 0.9500 1 0 1 0 1 1 1.3250

0 0 1 0 1 0 0.9625 1 0 1 0 1 0 1.3375

0 0 1 0 0 1 0.9750 1 0 1 0 0 1 1.3500

0 0 1 0 0 0 0.9875 1 0 1 0 0 0 1.3625

0 0 0 1 1 1 1.0000 1 0 0 1 1 1 1.3750

0 0 0 1 1 0 1.0125 1 0 0 1 1 0 1.3875

0 0 0 1 0 1 1.0250 1 0 0 1 0 1 1.4000

0 0 0 1 0 0 1.0375 1 0 0 1 0 0 1.4125

0 0 0 0 1 1 1.0500 1 0 0 0 1 1 1.4250

0 0 0 0 1 0 1.0625 1 0 0 0 1 0 1.4375

0 0 0 0 0 1 1.0750 1 0 0 0 0 1 1.4500

0 0 0 0 0 0 1.0875 1 0 0 0 0 0 1.4625

1 1 1 1 1 1 Off* 0 1 1 1 1 1 1.4750

1 1 1 1 1 0 Off* 0 1 1 1 1 0 1.4875

1 1 1 1 0 1 1.1000 0 1 1 1 0 1 1.5000

1 1 1 1 0 0 1.1125 0 1 1 1 0 0 1.5125

1 1 1 0 1 1 1.1250 0 1 1 0 1 1 1.5250

1 1 1 0 1 0 1.1375 0 1 1 0 1 0 1.5375

1 1 1 0 0 1 1.1500 0 1 1 0 0 1 1.5500

1 1 1 0 0 0 1.1625 0 1 1 0 0 0 1.5625

1 1 0 1 1 1 1.1750 0 1 0 1 1 1 1.5750

1 1 0 1 1 0 1.1875 0 1 0 1 1 0 1.5875

1 1 0 1 0 1 1.2000 0 1 0 1 0 1 1.6000

*Output disabled—same as deasserting the Output Enable input

V

OUT

(V)

VID4 VID3 VID2 VID1 VID0 VID5

V

OUT

(V)

the internal current limit is increased from 0V/R
75mV/R

. The output current limit ramps up slowly,

SENSE

SENSE

to

taking 1.6s/µF to reach full current. The output current
thus ramps up slowly, eliminating the starting surge
current required from the input power supply.

24 0

.–

t

IRAMP SS SS

=

VV

15

.

A

µ

CsFC

16

./

=µ

()

The SS pin has an internal 6V zener clamp (see the
Functional Diagram).

Fault Conditions: Overcurrent Latchoff

The SS pin also provides the ability to latch off the
controllers when an overcurrent condition is detected. The
SS capacitor is used initially to limit the inrush current of
all three output stages. After the controllers have been

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APPLICATIO S I FOR ATIO

given adequate time to charge up the output capacitor and
provide full load current, the SS capacitor is used for a
short-circuit timer. If the output voltage falls to less than

62.5% of its nominal value, the SS capacitor begins
discharging on the assumption that the output is in an
overcurrent condition. If the condition lasts for a long
enough period, as determined by the size of the SS
capacitor, the controller will be shut down until the RUN
pin voltage is recycled. If the overload occurs during start­up, the time can be approximated by:

>> (CSS • 0.6V)/(1.5µA) = 4 • 105 (CSS)

t

LO1

If the overload occurs after start-up, the voltage on the SS
capacitor will continue charging and will provide addi­tional time before latching off:

t

>> (CSS • 3V)/(1.5µA) = 2 • 106 (CSS)

LO2

This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the SS pin from VCC as
shown in Figure 6. When VCC is 5V, a 200k resistance will
prevent the discharge of the SS capacitor during an
overcurrent condition but also shortens the soft-start
period, so a larger SS capacitor value will be required.

Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem with
noise pick-up or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
foldback current limiting still remains active, thereby
protecting the power supply system from failure. A deci­sion can be made after the design is complete whether to
rely solely on foldback current limiting or to enable the
latchoff feature by removing the pull-up resistor.

The value of the soft-start capacitor CSS may need to be
scaled with output current, output capacitance and load
current characteristics. The minimum soft-start capaci­tance is given by:

CSS > (C

OUT

)(V

) (10–4) (R

OUT

SENSE

)

The minimum recommended soft-start capacitor of
CSS = 0.1µF will be sufficient for most applications.

Current Foldback

In certain applications, it may be desirable to defeat the
internal current foldback function. A negative impedance
is experienced when powering a switching regulator.
That

is, the input current is higher at a lower VIN and
decreases as VIN is increased. Current foldback is de­signed to accommodate a normal, resistive load having
increasing current draw with increasing voltage. The EAIN
pin should be artificially held 62.5% above its nominal
operating level of 0.6V, or 0.375V in order to prevent the
IC from “folding back” the peak current level. A suggested
circuit is shown in Figure 7.

The emitter of Q1 will hold up the EAIN pin to a voltage in
the absence of V

that will prevent the internal sensing

OUT

circuitry from reducing the peak output current. Remov­ing the function in this manner eliminates the external
MOSFET’s protective feature under short-circuit condi­tions. This technique will also prevent the short-circuit
latchoff function from turning off the part during a short­circuit event and the output current will only be limited to
N • 75mV/R

SENSE

.

V

CC

V

CC

22

V

Figure 6. Defeating Overcurrent Latchoff

SS PIN

CC

R

SS

C

SS

3738 F06

Q1

CALCULATE FOR

0.375V TO 0.55V

Figure 7. Foldback Current Elimination

LTC3738

EAIN

3738 F07

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APPLICATIO S I FOR ATIO

Undervoltage Reset

In the event that the input power source to the IC (VCC)
drops below 4V, the SS capacitor will be discharged to
ground and the controller will be shut down. When V
rises above 4V, the SS capacitor will be allowed to re­charge and initiate another soft-start turn-on attempt. This
may be useful in applications that switch between two
supplies that are not diode connected, but note that this
cannot make up for the resultant interruption of the
regulated output.

Phase-Locked Loop and Frequency Synchronization

The IC has a phase-locked loop comprised of an internal
voltage controlled oscillator and phase detector. This
allows the top MOSFET of output stage 1’s turn-on to be
locked to the rising edge of an external source. The
frequency range of the voltage controlled oscillator is
±50% around the center frequency fO. A voltage applied to
the PLLFLTR pin of 1.2V corresponds to a frequency of
approximately 350kHz. The nominal operating frequency
range of the IC is 210kHz to 530kHz.

The phase detector used is an edge sensitive digital type
that provides zero degrees phase shift between the
external and internal oscillators. This type of phase
detector will not lock the internal oscillator to harmonics
of the input frequency. The PLL hold-in range, ∆fH, is
equal to the capture range, ∆fC:

∆fH = ∆fC = ±0.5 f

O

The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter components on the PLLFLTR pin. A simplified block
diagram is shown in Figure 8.

If the external frequency (f
lator frequency, f

, current is sourced continuously,

OSC

) is greater than the oscil-

PLLIN

pulling up the PLLFLTR pin. When the external frequency
is less than f

, current is sunk continuously, pulling

OSC

down the PLLFLTR pin. If the external and internal fre­quencies are the same, but exhibit a phase difference, the
current sources turn on for an amount of time correspond­ing to the phase difference. Thus, the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this

CC

LTC3738

R

LP

3738 F08

10k

PLLFLTR

OSC

C

LP

3738f

PHASE

DETECTOR/

EXTERNAL

OSC

FCB/SYNC

Figure 8. Phase-Locked Loop Block Diagram

OSCILLATOR

DIGITAL

PHASE/

FREQUENCY

DETECTOR

2.4V

stable operating point, the phase comparator output is
open and the filter capacitor CLP holds the voltage. The IC
FCB/SYNC pin must be driven from a low impedance
source such as a logic gate located close to the pin. When
using multiple ICs for a phase-locked system, the PLLFLTR
pin of the master oscillator should be biased at a voltage
that will guarantee the slave oscillator(s) ability to lock
onto the master’s frequency. A voltage of 1.7V or below
applied to the master oscillator’s PLLFLTR pin is recom­mended in order to meet this requirement. The resultant
operating frequency will be approximately 500kHz for

1.7V.

The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically R

=10k and CLP ranges from

LP

0.01µF to 0.1µF.

Minimum On-Time Considerations

Minimum on-time, t

ON(MIN)

, is the smallest time duration
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:

V

t

ON MIN

()

<

Vf

OUT

IN

()

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If the duty cycle falls below what can be accommodated by
the minimum on-time, the IC will begin to skip every other
cycle, resulting in half-frequency operation. The output
voltage will continue to be regulated, but the ripple current
and ripple voltage will increase.

The minimum on-time for the IC is generally about 120ns.
However, as the peak sense voltage decreases the mini­mum on-time gradually increases. This is of particular
concern in forced continuous applications with low ripple
current at light loads. If the duty cycle drops below the
minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.

If an application can operate close to the minimum on­time limit, an inductor must be chosen that is low enough
in value to provide sufficient ripple amplitude to meet the
minimum on-time requirement.

As a general rule, keep
the inductor ripple current equal to or greater than 30%
of I

OUT(MAX)

at V

IN(MAX)

.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage
of input power.

Checking Transient Response

The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
amount equal to ∆I
series resistance of C
discharge C

, generating the feedback error signal that

OUT

• ESR, where ESR is the effective

LOAD

OUT

. ∆I

also begins to charge or

LOAD

shifts by an

OUT

forces the regulator to adapt to the current change and
return V

to its steady-state value. During this recovery

OUT

time, V

can be monitored for excessive overshoot or

OUT

ringing, which would indicate a stability problem. The

availability of the I

pin not only allows optimization of

TH

control loop behavior, but also provides a DC coupled
and AC filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed-loop response. Assuming a predominantly

second order system, phase margin and/or damping
factor can be estimated using the percentage of overshoot
seen at this pin. The bandwidth can also be estimated by
examining the rise time at the pin. The I

external com-

TH

ponents shown in the Figure 1 circuit will provide an
adequate starting point for most applications.

The I

series RC-CC filter sets the dominant pole-zero

TH

loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to maximize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 80% of full load current having a rise time
of <2µs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step,
resulting from the step change in output current, may not
be within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why it
is better to look at the ITH pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing RC and the bandwidth of the loop will be
increased by decreasing CC. If RC is increased by the same
factor that CC is decreased, the zero frequency will be kept
the same, thereby keeping the phase the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual over­all supply performance.

A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C

, causing a rapid drop in V

OUT

. No regulator can

OUT

24

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µ

APPLICATIO S I FOR ATIO

LTC3738

alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If C
than 2% of C
so that the load rise time is limited to approximately
1000 • R
R

SENSE

the charging current to about 1A.

Design Example (Using Three Phases)

As a design example, assume V
20V(max), V
AVP slope is 1mV/A. The inductance value is chosen first
based upon a 30% ripple current assumption. The highest
value of ripple current in each output stage occurs at the
maximum input voltage.

Using L = 0.6µH, a commonly available value results in
34% ripple current. The worst-case output ripple for the
three stages operating in parallel will be less than 11% of
the peak output current.

R

SENSE1, RSENSE2

a conservative maximum sense current threshold of 65mV
and taking into account half of the ripple current:

Use a commonly available 0.003Ω sense resistor.

SENSE

resistor would require a 500µs rise time, limiting

V

L

=

fIVV

()

=

400 30 15

()()()

≥

068

.

R

SENSE

, the switch rise time should be controlled

OUT

• C

OUT

⎛

OUT OUT

⎜
⎝

∆

kHz A

H

=

15 1

. Thus a 250µF capacitor and a 2mΩ

LOAD

= 12V(nominal), V

IN

= 1.3V, I

−

1

V

13

.

and R

65

⎛

A

⎜
⎝

IN

%

mV

+

34

= 45A, f = 400kHz and the

MAX

⎞
⎟

⎠

V

13

.

⎛

−

1

⎜

SENSE3

%

⎞
⎟

⎠

2

⎝

can be calculated by using

= Ω

20

0 0037

.

V

⎞
⎟

⎠

LOAD

is greater

IN

=

Next verify the minimum on-time is not violated. The
minimum on-time occurs at maximum V

V

t

ON MIN

()

The output voltage will be set by the VID code according
to Table 1.

The power dissipation on the topside MOSFET can be
estimated. Using a Siliconix Si7390DP for example, R
= 13.5mΩ, C
input voltage with T(estimated) = 50°C:

P

≈

MAIN

0 0135 20

⎛
⎜

⎝

using a Siliconix Si7356DP as bottom side MOSFET.

The worst-case power dissipation by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem­perature rise is:

P

SYNC

A short circuit to ground will result in a folded back current
of:

I

SC

with a typical value of R

0.25. The resulting power dissipated in the bottom MOSFET
is:

20 1 3

=

25

≈

23

()

OUT

=

VfVV kHz

IN MAX

()

MILLER

13

V

.

15 1 0 005 50 25

()+()

20

V

.

Ω

1

518118

VV V

–. .

VV

−

V

20

mV

m

+

Ω

=

()

= 2.1nC/15V = 140pF. At maximum

2

[]

+

()

+

.

AW

15 1 25 0 004 1 05

()( )

⎛

150 20

1

+

⎜

2

⎝

DS(ON)

.13

20 400

()

.

()

⎛

45

A

2

⎜

23

()()

⎝

⎞

400 0 51

()

⎟
⎠

2

.. .

ns V

()

H

µ

0675.

and d = (0.005/°C)(50°C) =

:

CC

162

ns

=

DS(ON)

CC

° − °

⎞

2 140

Ω

()( )

⎟
⎠

kHz W

()

⎞

=

⎟
⎠

pF

=

.

Ω

=

A

.

Take R

R

as recommended value 100Ω, the R

AVP

Ω

PREAVP

= Ω

100

mV A

1

= Ω0 003

300.

/

PREAVP

is:

P

= (7.5A)2(1.25)(0.004Ω) ≈ 0.28W

SYNC

which is less than one third of the normal, full load
conditions. Incidentally, since the load no longer dissi­pates any power, total system power is decreased by over
90%. Therefore, the system actually cools significantly
during a shorted condition!

3738f

25

LTC3738

WUUU

APPLICATIO S I FOR ATIO

PC Board Layout Checklist

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. These items are also illustrated graphically in the layout
diagram of Figure 9. Check the following in the PC layout:

1) Are the signal and power ground paths isolated? Keep the
SGND at one end of a printed circuit path thus preventing
MOSFET currents from traveling under the IC. The IC signal
ground pin should be used to hook up all control circuitry
on one side of the IC, routing the copper through SGND,
under the IC covering the “shadow” of the package, connect­ing to the PGND pin and then continuing on to the (–) plates
of C

and C

IN

placed immediately adjacent to the IC between the VCC pin
and PGND. A 1µF ceramic capacitor of the X7R or X5R type
is small enough to fit very close to the IC to minimize the ill
effects of the large current pulses drawn to drive the bottom
MOSFETs. An additional 5µF to 10uF of ceramic, tantalum
or other very low ESR capacitance is recommended in or­der to keep the internal IC supply quiet. The power ground
returns to the sources of the bottom N-channel MOSFETs,
anodes of the Schottky diodes and (–) plates of CIN, which
should have as short lead lengths as possible.

2) Does the IC IN+ pin connect to the (+) plates of C
A 30pF to 300pF feedforward capacitor between the
DIFFOUT and EAIN pins should be placed as close as
possible to the IC.

. The VCC decoupling capacitor should be

OUT

OUT

?

6) The filter capacitors between the ITH and SGND pins
should be as close as possible to the pins of the IC.

Figure 9 illustrates all branch currents in a three-phase
switching regulator. It becomes very clear after studying
the current waveforms why it is critical to keep the high
switching current paths to a small physical size. High elec­tric and magnetic fields will radiate from these “loops” just
as radio stations transmit signals. The output capacitor
ground should return to the negative terminal of the input
capacitor and not share a common ground path with any
switched current paths. The left half of the circuit gives rise
to the “noise” generated by a switching regulator. The
ground terminations of the synchronous MOSFETs and
Schottky diodes should return to the bottom plate(s) of the
input capacitor(s) with a short isolated PC trace since very
high switched currents are present. A separate isolated path
from the bottom plate(s) of the input and output capacitor(s)
should be used to tie in the IC power ground pin (PGND).
This technique keeps inherent signals generated by high
current pulses taking alternate current paths that have
finite impedances during the total period of the switching
regulator. External OPTI-LOOP compensation allows over­compensation for PC layouts which are not optimized but
this is not the recommended design procedure.

Simplified Visual Explanation of How a 3-Phase
Controller Reduces Both Input and Output RMS
Ripple Current

3) Are the SENSE– and SENSE+ printed circuit traces for
each channel routed together with minimum PC trace
spacing? The filter capacitors between SENSE+ and SENSE
for each channel should be as close as possible to the pins
of the IC. Connect the SENSE– and SENSE+ pins to the
pads of the sense resistor as illustrated in Figure 10.

4) Do the (+) plates of CIN connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the pulsed current to the MOSFETs.

5) Keep the switching nodes, SWITCH, BOOST and TG
away from sensitive small-signal nodes. Ideally the
SWITCH, BOOST and TG printed circuit traces should be
routed away and separated from the IC and the “quiet” side
of the IC.

–

26

The effect of multiphase power supply design significantly
reduces the amount of ripple current in both the input and
output capacitors. The RMS input ripple current is divided
by, and the effective ripple frequency is multiplied up by
the number of phases used (assuming that the input
voltage is greater than the number of phases used times
the output voltage). The output ripple amplitude is also
reduced by, and the effective ripple frequency is increased
by the number of phases used. Figure 11 graphically
illustrates the principle.

The worst-case input RMS ripple current for a single stage
design peaks at twice the value of the output voltage. The
worst-case input RMS ripple current for a two stage
design results in peaks at 1/4 and 3/4 of the input voltage,

3738f

WUUU

APPLICATIO S I FOR ATIO

SW1

LTC3738

L1

R

SENSE1

D1

V

IN

R

IN

+

C

IN

BOLD LINES INDICATE HIGH,
SWITCHING CURRENT LINES.
KEEP LINES TO A MININMUM
LENGTH

L2

SW2

D2

SW3

D3

R

SENSE2

L3

R

SENSE3

Figure 9. Branch Current Waveforms

C

OUT

3738 F09

V

OUT

+

R

L

INDUCTOR

LTC3738

+

SENSE

SENSE

1000pF

–

OUTPUT CAPACITOR

SENSE
RESISTOR

3738 F10

Figure 10. Kelvin Sensing R

SENSE

3738f

27

LTC3738

WUUU

APPLICATIO S I FOR ATIO

SINGLE PHASE

SW V

I

CIN

I

COUT

TRIPLE PHASE

SW1 V

subtract current from the (VCC – V

)/L charging current

OUT

resulting from the stage which has its top MOSFET on. The
output ripple current for a 3-phase design is:

V

=

fL

()( )

OUT

DC V V

13 3–

()

>

IN OUT

I

P-P

The ripple frequency is also increased by three, further
reducing the required output capacitance when VCC < 3V

OUT

as illustrated in Figure 3.

SW2 V

SW3 V

I

L1

I

L2

I

L3

I

CIN

I

COUT

Figure 11. Single and Polyphase Current Waveforms

3738 F11

and the worst-case input RMS ripple current for a three
stage design results in peaks at 1/6, 1/2, and 5/6 of the
input voltage. The peaks, however, are at ever decreasing
levels with the addition of more phases. A higher effective
duty factor results because the duty factors “add” as long
as the currents in each stage are balanced. Refer to AN19
for a detailed description of how to calculate RMS current
for the single stage switching regulator.

Figure 5 illustrates the RMS input current drawn from the
input capacitance versus the duty cycle as determined by
the ration of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 2/3
in a 3-phase solution due to the current splitting between
the three stages.

The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the V

/L discharge currents

OUT

term from the stages that has their bottom MOSFETs on

Efficiency Calculation

To estimate efficiency, the DC loss terms include the input
and output capacitor ESR, each MOSFET R
tor resistance RL, the sense resistance R

SENSE

DS(ON)

, induc-

and the
forward drop of the Schottky rectifier at the operating
output current and temperature. Typical values for the
design example given previously in this data sheet are:

Main MOSFET R
Sync MOSFET R
C
C

= 20mΩ

INESR

OUTESR

= 3mΩ

= 13.5mΩ (18mΩ at 90°C)

DS(ON)

= 4mΩ (5.3mΩ at 90°C)

DS(ON)

RL = 2mΩ
R
V
V

= 3mΩ

SENSE

SCHOTTKY

= 1.3V

OUT

= 0.8V at 15A (0.7V at 90°C)

VIN = 12V
I

= 45A

MAX

δ = 0.5%°C
N = 3
f = 400kHz

The main MOSFET is on for the duty factor V

OUT/VIN

and
the synchronous MOSFET is on for the rest of the period
or simply (1 – V

OUT/VIN

). Assuming the ripple current is
small, the AC loss in the inductor can be made small if a
good quality inductor is chosen. The average current,
I

is used to simplify the calaculations. The equation

OUT

below is not exact but should provide a good technique
for the comparison of selected components and give a

28

3738f

WUUU

APPLICATIO S I FOR ATIO

LTC3738

result that is within 10% to 20% of the final application.
The temperature of the MOSFET’s die temperature may
require interative calculations if one is not familiar typical
performance. A maximum operating junction tempera­ture of 90° to 100°C for the MOSFETs is recommended
for high reliability applications.

Common output path DC loss:

2

I

⎛

⎞

PN

COMPATH

This totals 3.375W + C

MAX

≈

⎜
⎝

R R C Loss

+

()

⎟

L SENSE OUTESR

⎠

N

OUTESR

loss.

+

Total of all three main MOSFET’s DC loss:

⎛

⎞

V

⎛

=

OUTINMAX

⎜
⎝

V

⎜

⎟

⎝

⎠

PN

MAIN

This totals 1.3W + C

I

N

INESR

2

⎞
⎟

⎠

R C Loss

+

1 δ

()

DS ON INESR

loss.

+

()

Total of all three synchronous MOSFET’s DC loss:

⎛

PN

SYNC

=

V

11

–

⎜
⎝

⎞

⎛

OUTINMAX

⎜

⎟

⎝

⎠

V

2

I

⎞
⎟

⎠

N

R

+

δ

()

DS ON

()

This totals 0.14W at VIN = 8V, 0.315W at VIN = 12V and

0.875W at VIN = 20V.

Total of all three synchronous MOSFET’s AC loss:

V

G

V

IN

DSSPEC

fnC

=

() () ()( ) ( )3 3 16 400Q

This totals 0.085W at V

= 8V, 0.128W at VIN = 12V and

IN

V

IN

V

DSSPEC

kHz

0.213W at VIN = 20V. The bottom MOSFET does not
experience the Miller capacitance dissipation issue that
the main switch does because the bottom switch turns on
when its drain is close to ground.

The Schottky rectifier loss assuming 50ns nonoverlap
time:

2 • 3(0.7V)(15A)(50ns)(400kHz)

This totals 1.26W.

The total output power is (1.3V)(45A) = 58.5W and the
total input power is approximately 67W so the % loss of
each component is as follows:

Main switch AC loss (VIN = 12V) 0.315W 0.47%

Main switch DC loss 1.3W 1.9%

This totals 3.2W.

Total of all three main MOSFET’s AC loss:

A

45

PV

≈Ω

MAIN IN

2

3

()

()()

1

⎛
⎜

⎝

VV V

518118

–. .

2 140

()( )

23

+

pF

⎞

kHz W

400 6 3

().

⎟
⎠

Synchronous switch AC loss 0.128W 0.2%

Synchronous switch DC loss 3.2W 4.8%

Power path loss 3.375W 5.05%

The numbers above represent the values at VIN = 12V.

=

3738f

29

LTC3738

TYPICAL APPLICATIO

VID2 IN

OUTEN VID2 VID1 VID0 PGOODVID5

FCB/SYNC

PLLFLTR

–

IN

+

IN

AVP

EAIN

+

SENSE1

SENSE1

SENSE2

SENSE2

SENSE3

SENSE3

SS I

100pF

(EXPOSED PAD IS SGND)

–

+

–

–

+

TSNS

TH

CC

2.2k

2200pF

S1

S1

S2

S2

S3

S3

R

AVP

100Ω

30pF

+

–

+

–

–

+

10Ω ×6

100pF

R

PREAVP

10k

51k

220Ω

1000pF

1000pF

1000pF

V

CC

0.1µF

U

PGOOD

VID0 IN

VID5 INVID1 INON/0FF

LTC3738

VR_HOTB VID4

VID3 BOOST3

200Ω

VID3 IN

V

CC

VID4 INV

65A Power Supply for VRM10

V

CC

1µF

0.1µF

0.1µF

0.1µF

5V

V

10µF

CC

47k

BOOST1

SW1

BOOST2

SW2

PGND

SW3

TG1

TG2

V

BG1

BG2

BG3

TG3

1Ω

CC

V

CC

V

IN

M1

M2 D1

V

IN

M3

M4 D2

V

IN

M5

M6 D3

V

10µF

6.3V
×3

10µF
35V
×5

OUT

+

C

OUT

V

IN

7V TO 21V

+

C

IN

68µF
25V

L1

0.002Ω

+

S1

L2

S2

L3

S3

0.002Ω

+

0.002Ω

+

–

S1

–

S2

3738 TA02

–

S3

V

: 7V TO 21V

IN

: 0.8V TO 1.55V, 65A

V

OUT

SWITCHING FREQUENCY: 300kHz

CIN: SANYO OS-CON 25SP68M

: 330µF/2.5V ×10 SANYO POSCAP 2R5TPE330M9

C

OUT

D1 TO D3: MBRS340T3

L1 TO L3: 0.6µH PULSE PG0006.601 OR TOKO FDA1055 0.56µH
M1, M3, M5: Si7390DP ×1 OR HAT2168H × 1
M2, M4, M6: Si7356DP ×2 OR HAT2165H × 2

Block Diagram—6-Phase LTC3731/LTC3738 Supply

3-PHASE LTC3731

CLKOUT

V

IN

CLK
60°

FCB/SYNC

TH

I

EAIN

3-PHASE LTC3738

3738 TA03

V

OUT

VRM9/VRM10
90A TO 120A

30

3738f

PACKAGE DESCRIPTIO

5.50 ± 0.05
(2 SIDES)

4.10 ± 0.05
(2 SIDES)

3.20 ± 0.05
(2 SIDES)

U

UHF Package

38-Lead Plastic QFN (7mm × 5mm)

(Reference LTC DWG # 05-08-1701)

0.25 ± 0.05

0.50 BSC

5.20 ± 0.05 (2 SIDES)

6.10 ± 0.05 (2 SIDES)

7.50 ± 0.05 (2 SIDES)

RECOMMENDED SOLDER PAD LAYOUT

0.70 ± 0.05

PACKAGE
OUTLINE

LTC3738

7.00 ± 0.10
(2 SIDES)

0.75 ± 0.05

5.00 ± 0.10
(2 SIDES)

PIN 1
TOP MARK
(SEE NOTE 6)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

0.75 ± 0.05

0.00 – 0.05

5.15 ± 0.10
(2 SIDES)

0.200 REF

0.200 REF

0.00 – 0.05

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

0.25 ± 0.05

0.50 BSC

3.15 ± 0.10
(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

37

38

R = 0.115
TYP

0.435

0.18

1

0.23

2

0.40 ± 0.10

(UH) QFN 0303

0.18

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3738f

31

LTC3738

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PART NUMBER DESCRIPTION COMMENTS

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LTC1628-SYNC DC/DC Controllers 3.5V ≤ VIN ≤ 36V, I

LTC1629/ 20A to 200A PolyPhase Synchronous Controllers Expandable from 2-Phase to 12-Phase, Uses All
LTC1629-PG Surface Mount Components, No Heat Sink, V

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TM

2-Phase Dual Synchronous Step-Down 550kHz, No Sense Resistor

SENSE

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LTC1703 No R

Controller with 5-Bit Mobile VID Control V

2-Phase Dual Synchronous Step-Down Mobile Pentium® III Processors, 550kHz,

SENSE

IN

≤ 7V

LTC1708-PG 2-Phase, Dual Synchronous Controller with Mobile VID 3.5V ≤ VIN ≤ 36V, VID Sets V
LT®1709/ High Efficiency, 2-Phase Synchronous Step-Down 1.3V ≤ V

≤ 3.5V, Current Mode Ensures

OUT

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LTC1735 High Efficiency Synchronous Step-Down Output Fault Protection, 16-Pin SSOP

Switching Regulator

LTC1736 High Efficiency Synchronous Controller with 5-Bit Mobile Output Fault Protection, 24-Pin SSOP,

VID Control 3.5V ≤ V

LTC1778 No R

Controller I

Current Mode Synchronous Step-Down Up to 97% Efficiency, 4V ≤ VIN ≤ 36V, 0.8V ≤ V

SENSE

OUT

≤ 36V

IN

up to 20A

LTC1929/ 2-Phase Synchronous Controllers Up to 42A, Uses All Surface Mount Components,
LTC1929-PG No Heat Sinks, 3.5V ≤ VIN ≤ 36V

LTC3708 2-Phase, Dual DC/DC Synchronous Buck Controller with Tracks Two or More Supplies, Fast Transient Response, No R

Output Tracking

LTC3711 No R

Controller with Digital 5-Bit Interface 0.925V ≤ V

LTC3717 DDR/QDR Memory Termination Regulator V

Current Mode Synchronous Step-Down Up to 97% Efficiency, Ideal for Pentium III Processors,

SENSE

OUT

= 0.5VIN, ±20A, ±0.65% V

OUT

LTC3719 2-Phase, 5-Bit VID Current Mode, High Efficiency AMD Hammer-K8 Processors, Wide VIN Range: 4V to 36V Operation

Synchronous Step-Down Controller

LTC3729 20A to 200A, 550kHz PolyPhase Synchronous Controller Expandable from 2-Phase to 12-Phase, Uses all Surface Mount

Components, V

LTC3731 3-Phase, 600kHz Synchronous Buck Expandable from 3-Phase to 12-Phase, Uses all Surface Mount

Switching Regulator Controller Components, V

LTC3732 3-Phase, 5-Bit VID, 600kHz Synchronous Buck VRM9.0 and VRM9.1 (VID = 1.1V to 1.85V)

Switching Regulator Controller

LTC3733 3-Phase, 5-Bit VID, 600kHz Synchronous Buck AMD OpteronTM (VID = 0.8V to 1.55V)

Switching Regulator Controller

LTC3734 Single Phase DC/DC Controller for Intel IMVP-4 6-Bit IMVP-4 VID: 0.7V ≤ V

Compatible Processors Lossless Voltage Positioning

LTC3735 2-Phase DC/DC Controller for Pentium (Centrino) 40A, 0.7V ≤ V

Processors

No R

is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.

SENSE

Opteron is a trademark of AMD Corporation.

, Power Good Output Signal, Synchronizable,

OUT

up to 20A, 0.8V ≤ V

OUT

, PGOOD

OUT1

IN

≤ 2V, 4V ≤ VIN ≤ 36V, I

OUT

up to 36V

IN

up to 36V

IN

≤ 1.708V, 4V ≤ VIN ≤ 30V, I

OUT

≤1.708V, 4V ≤ VIN ≤ 30V

OUT

≤ 36V

Accuracy

up to 20A

OUT

≤ 5V

OUT

up to 36V

IN

OUT

≤ (0.9)(VIN),

OUT

SENSE

≤ 25A,

32

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

3738f

LT/TP 0604 1K • PRINTED IN USA

© LINEAR TECHNOLOGY CORPORATION 2004