Datasheet LTC3731H Datasheet (LINEAR TECHNOLOGY)

LTC3731H

3-Phase, 600kHz,

Synchronous Buck Switching

FEATURES

■

3-Phase Current Mode Controller with Onboard
MOSFET Drivers

■

±5% Output Current Matching Optimizes Thermal
Performance and Size of Inductors and MOSFETs

■

±2% V

■

Reduced Power Supply Induced Noise

■

±10% Power Good Output Indicator

■

250kHz to 600kHz Per Phase, PLL, Fixed Frequency

■

PWM, Stage SheddingTM or Burst Mode® Operation

■

OPTI-LOOP® Compensation Minimizes C

■

Adjustable Soft-Start Current Ramping

■

Short-Circuit Shutdown Timer with Defeat Option

■

Overvoltage Soft Latch

■

Adjustable Undervoltage Lockout Threshold

■

Selectable Phase Output for Up to 12-Phase Operation

■

Available in 36-Pin Narrow (0.209") SSOP Package

Accuracy Over Temperature up to 140°C

REF

OUT

U

APPLICATIO S

■

Automotive and Industrial Power Supplies

■

High Output Current DC/DC Power Supplies

Regulator Controller

U

DESCRIPTIO

The LTC®3731H is a PolyPhase® synchronous step-down
switching regulator controller that drives all N-channel
external power MOSFET stages in a phase-lockable fixed
frequency architecture. The LTC3731H is rated for opera­tion up to 140°C junction temperature. The 3-phase con­troller drives its output stages with 120° phase separation
at frequencies up to 600kHz per phase to minimize the
RMS current losses in both the input and output filter
capacitors. The 3-phase technique effectively triples the
fundamental frequency, improving transient response while
operating each controller at an optimal frequency for
efficiency and ease of thermal design. Light load efficiency
is optimized by using a choice of output Stage Shedding
or Burst Mode operation.

The precision reference supports output voltages from 0.6V
to 6V.

Current foldback provides protection for the exter­nal MOSFETs under short-circuit or overload conditions.
Please refer to the LTC3731 data sheet for 0°C to 70°C and
–40°C to 85°C rated versions.

, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.

Burst Mode, OPTI-LOOP and PolyPhase are registered trademarks of Linear Technology
Corporation. Stage Shedding is a trademark of Linear Technology Corporation.
Protected by U.S. Patents, including 5481178, 5929620, 6177787, 6144194, 6100678,
5408150, 6580258, 6462525, 6304066, 5705919.

TYPICAL APPLICATIO

V

CC

4.5V TO 7V

POWER GOOD INDICATOR

OPTIONAL SYNC IN

36k

V

IN

12k

5k

6.04k

U

LTC3731H

SW1

SENSE1
SENSE1

SW2

PGND

SENSE2
SENSE2

SW3

SENSE3
SENSE3

TG1V

BG1

TG2

BG2

TG3

BG3

0.8µH

0.003Ω

+
–

V

IN

0.8µH

0.003Ω

+
–

V

IN

0.8µH

0.003Ω

+
–

+

100pF

0.01µF

CC

BOOST1
BOOST2
BOOST3

PGOOD
PLLIN

PLLFLTR

UVADJ

I

TH

RUN/SS

SGND
EAIN

10µF

0.1µF

SW3 SW2 SW1

680pF

7.5k

Figure 1. High Current Triple Phase Step-Down Converter

V

IN

22µF
35V

V

1.35V
55A

C

OUT

470µF
4V

3731H F01

5V TO 28V

OUT

3731hfa

+

1

LTC3731H

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

TOP VIEW

G PACKAGE

36-LEAD PLASTIC SSOP

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

V

CC

PLLIN

PLLFLTR

FCB

NC

NC

NC

EAIN

SGND

SENSE1

+

SENSE1

–

SENSE2

+

SENSE2

–

SENSE3

–

SENSE3

+

RUN/SS

I

TH

UVADJ

CLKOUT

PGOOD

BOOST1

TG1

SW1

BOOST2

TG2

SW2

V

DR

BG1

PGND

BG2

BG3

SW3

TG3

BOOST3

PHASMD

SGND

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

Topside Driver Voltages (BOOSTN) ............ 38V to –0.3V

Switch Voltage (SW
Boosted Driver Voltage (BOOST
Peak Output Current <1ms (TG
Supply Voltages (V

Pin Voltage .................................................. 7V to –0.3V

RUN/SS, PLLFLTR, PLLIN, UVADJ,

FCB Voltages ............................................. V

SENSE
I

+

, SENSE– Voltages........................ 5.5V to –0.3V

Voltage ................................................ 2.4V to –0.3V

TH

Operating Junction

Temperature Range (Note 2) .................–40°C to 140°C

Storage Temperature Range ..................–65°C to 150°C

Lead Temperature G Package (Soldering, 10sec).. 300°C

)...................................32V to –5V

N

– SWN) .... 7V to –0.3V

N

, BGN) ..................... 5A

N

, VDR), PGOOD

CC

to –0.3V

CC

UU

W

PACKAGE/ORDER I FOR ATIO

T

= 140°C, θJA = 95°C/W, θJC = 32°C/W

JMAX

PINS 5 AND 6 CAN BE GROUNDED OR NC

PIN 7 MUST BE LEFT AS NC

ORDER PART NUMBER

LTC3731HG

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loop

V

REGULATED

V

SENSEMAX

I

MATCH

V

LOADREG

V

REFLNREG

g

m

g

mOL

V

FCB

2

Regulated Voltage at EAIN V

Maximum Current Sense Threshold V

Maximum Current Threshold Match Worst-Case Error at V

Output Voltage Load Regulation (Note 3)

Output Voltage Line Regulation VCC = 4.5V to 7V 0.03 %/V

Transconductance Amplifier g

Transconductance Amplifier GBW ITH = 1.2V (gm • ZL, ZL = Series 1k-100kΩ-1nF) 3 MHz

Forced Continuous Threshold

m

ITH

EAIN

V

SENSE1–, VSENSE2–, VSENSE3–

Measured in Servo Loop, ∆I
Measured in Servo Loop, ∆I

ITH = 1.2V, Sink/Source 25µA (Note 3)

The ● denotes the specifications which apply over the full operating

= 25°C. VCC = V

A

= 1.2V (Note 3) 0.594 0.600 0.606 V

= 0.5V, V

Open, 65 75 85 mV

ITH

SENSEMAX

= 5V unless otherwise noted.

RUN/SS

= 0.6V, 1.8V

Voltage = 1.2V to 0.7V

TH

Voltage = 1.2V to 2V

TH

●

0.590 0.600 0.614 V

●

60 75 90 mV

–5 5 %

●

●

●

3 5 7 mmho

●

0.54 0.60 0.66 V

0.1 0.7 %
–0.1 –0.7 %

3731hfa

LTC3731H

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. VCC = V

A

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

FCB

V

BINHIBIT

FCB Bias Current V

= 0.65V 0.2 0.7 µA

FCB

Burst Inhibit Threshold Measured at FCB Pin VCC – 1.5 V

– 0.7 V

CC

– 0.3 V

CC

UVR Undervoltage RUN/SS Reset VCC Lowered Until the RUN/SS Pin is Pulled Low 3.3 3.8 4.5 V

UVADJ Undervoltage Lockout Threshold 1.13 1.18 1.23 V

I

UVADJ

I

Q

I

RUN/SS

V

RUN/SS

V

RUN/SSARM

Undervoltage Bias Current At UVADJ Threshold 0.2 50 nA

Input DC Supply Current (Note 4)
Normal Mode V
Shutdown V

Soft-Start Charge Current V

RUN/SS Pin ON Threshold V

RUN/SS Pin Arming Threshold V

= 5V 2.3 3.5 mA

CC

= 0V 50 100 µA

RUN/SS

= 1.9V –0.8 – 1.5 –2.5 µA

RUN/SS

, Ramping Positive 1 1.5 1.9 V

RUN/SS

, Ramping Positive Until Short-Circuit 3.8 4.5 V

RUN/SS

Latch-Off is Armed

V

RUN/SSLO

I

SCL

I

SDLHO

I

SENSE

DF

MAX

TG tR,t

BG t

R, tF

TG/BG t

RUN/SS Pin Latch-Off Threshold V

RUN/SS Discharge Current Soft-Short Condition V

Shutdown Latch Disable Current V

SENSE Pins Source Current SENSE1+, SENSE1–, SENSE2+, SENSE2–, SENSE3

Maximum Duty Factor In Dropout, V

Top Gate Rise Time C

F

Top Gate Fall Time C

Bottom Gate Rise Time C
Bottom Gate Fall Time C

Top Gate Off to Bottom Gate On Delay All Controllers, C

1D

, Ramping Negative 3.2 V

RUN/SS

= 0.375V, V

EAIN

= 0.375V, V

EAIN

–

SENSE3

All Equal 1.2V; Current at Each Pin

SENSEMAX

= 3300pF 30 90 ns

LOAD

= 3300pF 40 90 ns

LOAD

= 3300pF 30 90 ns

LOAD

= 3300pF 20 90 ns

LOAD

= 4.5V 1.5 5 µA

RUN/SS

≤ 30mV 95 98.5 %

= 3300pF Each Driver 50 ns

LOAD

= 4.5V – 5 –1.5 µA

RUN/SS

+

13 20 µA

Synchronous Switch-On Delay Time

BG/TG t

Bottom Gate Off to Top Gate On Delay All Controllers, C

2D

= 3300pF Each Driver 60 ns

LOAD

Top Switch-On Delay Time

t

ON(MIN)

Minimum On-Time Tested with a Square Wave (Note 5) 110 ns

Power Good Output Indication

V

PGL

I

PGOOD

V

PGTHNEGVEAIN

V

PGTHPOSVEAIN

V

PGDLY

PGOOD Voltage Output Low I

PGOOD Output Leakage V

PGOOD Trip Thresholds V

Ramping Negative PGOOD Goes Low After V

= 2mA 0.1 0.3 V

PGOOD

= 5V 1 µA

PGOOD

with Respect to Set Output Voltage,

EAIN

Delay – 7 –10 –13 %

UVDLY

Ramping Positive 7 10 13 %

Power Good Fault Report Delay After V

is Forced Outside the PGOOD Thresholds 100 150 µs

EAIN

Oscillator and Phase-Locked Loop

f

NOM

f

LOW

f

HIGH

Nominal Frequency V

Lowest Frequency V

Highest Frequency V

= 1.2V 360 400 440 kHz

PLLFLTR

= 0V 190 225 260 kHz

PLLFLTR

= 2.4V 600 680 750 kHz

PLLFLTR

3731hfa

3

LTC3731H

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

PLLTH

R

PLLIN

I

PLLFLTR

R

RELPHS

CLKOUT Controller 1 TG to CLKOUT Phase PHASMD = 0V 30 Deg

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: The LTC3731H is guaranteed to meet specifications from –40°C to
140°C. Junction temperature (T
temperature T
formula:

LTC3731H: T
LTC3731H: T

High junction temperatures degrade operating lifetimes. Operating lifetime
at junction temperatures greater than 125°C is derated to 1000 hours.

PLLIN Input Threshold Minimum Pulse Width > 100ns 1 V

PLLIN Input Resistance 50 kΩ

Phase Detector Output Current
Sinking Capability f
Sourcing Capability f

Controller 2-Controller 1 Phase 120 Deg
Controller 3-Controller 1 Phase 240 Deg

) is calculated from the ambient

and power dissipation PD according to the following

A

= TA + (PD × 95°C/W)

J

= T

J

CASE

J

+ (PD × 32°C/W)

PLLIN
PLLIN

PHASMD = 5V 60 Deg

The ● denotes the specifications which apply over the full operating

= 25°C. VCC = V

A

< f

OSC

> f

OSC

= 5V unless otherwise noted.

RUN/SS

20 µA
20 µA

Note 3: The IC is tested in a feedback loop that servoes the error amplifier
output voltage to its midrange point (V

Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.

Note 5: The minimum on-time condition corresponds to an inductor peak­to-peak ripple current of ≥40% of I
considerations in the Applications Information Section).

Note 6: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions.
Overtemperature protection becomes active at a junction temperature
greater than the maximum operating temperature. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.

= 1.2V).

ITH

(see minimum on-time

MAX

4

3731hfa

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3731H

Efficiency vs I

100

V

= OPEN

FCB

90

V

= 5V

FCB

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0.1

V

= 0V

FCB

1 10 100

LOAD CURRENT (A)

Reference Voltage vs
Temperature

610

605

600

(Figure 14) Efficiency vs V

OUT

100

95

90

85

80

75

70

EFFICIENCY (%)

65

VIN = 8V

= 1.5V

V

OUT

3731H G01

60

55

50

0

Error Amplifier gm vs
Temperature

6.0

5.5

(mmho)

m

5.0

5

IL = 45A

(Figure 14) Efficiency vs Frequency (Figure 14)

IN

100

95

VIN = 5V

90

VIN = 12V

85

EFFICIENCY (%)

VIN = 20V

80

75

200

Maximum I

300

FREQUENCY (kHz)

SENSE

I

LOAD

V

OUT

400

500

Threshold vs

10

VIN (V)

IL = 15A

15

V

= 1.5V

OUT

f = 225kHz

20

3731H G02

25

Temperature

85

80

VO = 1.75V

THRESHOLD (mV)

75

SENSE

VO = 0.6V

= 20A

= 1.5V

VIN = 8V

600

3731H G03

595

REFERENCE VOLTAGE (mV)

590

–50

0255075

–25 150125100

TEMPERATURE (°C)

3731H G04

4.5

ERROR AMPLIFIER g

4.0
–50 0 25 50 75–25 150125100

TEMPERATURE (°C)

Oscillator Frequency vs
Temperature Operating Frequency vs V

700

V

PLLFLTR

600

500

400

V

PLLFLTR

300

FREQUENCY (kHz)

200

V

PLLFLTR

100

0

= 2.4V

V

PLLFLTR

= 1.2V

= 0V

TEMPERATURE (°C)

= 5V

3731H G07

700

600

500

400

300

OPERATING FREQUENCY (kHz)

200

0.5 1 1.5 22.5

0

PLLFLTR PIN VOLTAGE (V)

3731H G05

PLLFLTR

3731H G08

70

MAXIMUM I

65

–50 0 25 50 75–25 150125100

TEMPERATURE (°C)

Undervoltage Reset Voltage vs
Temperature

5

4

3

2

UNDER VOLTAGE RESET (V)

1

0

–50 0 25 50 75–25 150125100–50 0 25 50 75–25 150125100

TEMPERATURE (°C)

3731H G06

3731H G09

3731hfa

5

LTC3731H

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Short-Circuit Arming and Latchoff
vs Temperature Supply Current vs Temperature

5

ARMING

4

LATCHOFF

3

2

RUN/SS PIN VOLTAGE (V)

1

0

TEMPERATURE (°C)

3731H G10

VCC = 5V

2.8

2.4

2.0

1.6

1.2

0.8

SUPPLY CURRENT (mA)

0.4

0

TEMPERATURE (°C)

Maximum Current Sense

Maximum I

80

70

60

(mV)

50

SENSE

40

30

MAXIMUM I

20

10

0

0

1

SENSE

2

V

RUN/SS

vs V

RUN/SS

3

4

VOLTAGE (V)

56

3731H G13

Threshold vs Duty Factor

75

50

VOLTAGE (mV)

25

SENSE

I

0

0

20 40 60 80

DUTY FACTOR (%)

3731H G11

3731H G14

100

80

60

40

20

0

100

RUN/SS Pull-Up Current vs
Temperature

3.0
V

RUN/SS

SHUTDOWN CURRENT (µA)

2.5

2.0

1.5

1.0

RUN/SS PULLUP CURRENT (µA)

0.5

0

–50 0 255075–25 150125100–50 0 25 50 75–25 150125100–50 0 25 50 75–25 150125100

Peak Current Threshold vs V

75

60

45

30

15

VOLTAGE THRESHOLD (mV)

0

SENSE

I

–15

0

= 1.9V

TEMPERATURE (°C)

3731H G12

ITH

0.6 1.2 1.8 2.4
V

(V)

ITH

3731H G15

Percentage of Nominal Output vs
Peak I

80

70

60

50

40

VOLTAGE (mV)

30

SENSE

20

PEAK I

10

0

0

PERCENTAGE OF NOMINAL OUTPUT VOLTAGE (%)

(Foldback)

SENSE

2010 30 50 70 90

60

40

6

80

3731H G16

100

Maximum Duty Factor vs
Temperature

100

98

96

94

92

MAXIMUM DUTY FACTOR (%)

90

–50 0 25 50 75–25 150125100

TEMPERATURE (°C)

V

PLLFLTR

= 0V

3731H G17

PIN CURRENT (µA)

–10

SENSE

I

–20

–30

40

30

20

10

0

Pin Current vs V

I

SENSE

0

1

2

V

(V)

OUT

OUT

34

3731H G18

3731hfa

5

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3731H

V

OUT

AC, 20mV/DIV

V

SW1

10V/DIV

V

SW2

10V/DIV

V

SW3

10V/DIV

V

OUT

AC, 20mV/DIV

Shed Mode at 1 Amp, Light Load
Current (Circuit of Figure 14)

V

= 12V

IN

= 1.5V

V

OUT

= V

V

FCB

CC

FREQUENCY = 225kHz

4µs/DIV 4µs/DIV

3731H G20

Continuous Mode at 1 Amp, Light
Load Current (Circuit of Figure 14)

V

OUT

AC, 20mV/DIV

V

SW1

10V/DIV

V

SW2

10V/DIV

V

SW3

10V/DIV

V

OUT

AC, 20mV/DIV

Burst Mode at 1 Amp, Light Load
Current (Circuit of Figure 14)

V

= 12V

IN

= 1.5V

V

OUT

= OPEN

V

FCB

FREQUENCY = 225kHz

3731H G21

Transient Load Current Response: 0 Amp
to 50 Amp (Circuit of Figure 14)

V

SW1

10V/DIV

V

SW2

10V/DIV

V

SW3

10V/DIV

VIN = 12V

= 1.5V

V

OUT

V

= 0V

FCB

FREQUENCY = 225kHz

I

LOAD

20A/DIV

V

4µs/DIV 20µs/DIV

3731H G22 3731H G23

= 12V

IN

= 1.5V

V

OUT

V

= V

FCB

CC

FREQUENCY = 225kHz

3731hfa

7

LTC3731H

U

UU

PI FU CTIO S

BG1 to BG3: High Current Gate Drives for Bottom N-Channel
MOSFETs. Voltage swing at these pins is from ground to V

BOOST1 to BOOST3: Positive Supply Pins to the Topside
Floating Drivers. Bootstrapped capacitors, charged with
external Schottky diodes and a boost voltage source, are
connected between the BOOST and SW pins. Voltage swing
at the BOOST pins is from boost source voltage (typically
VCC) to this boost source voltage + VIN (where V
external MOSFET supply rail).

CLKOUT: Output clock signal available to synchronize other
controller ICs for additional MOSFET stages/phases.

EAIN: This is the input to the error amplifier that compares the
feedback voltage to the internal 0.6V reference voltage.

FCB: Forced Continuous Control Input. The voltage applied to
this pin sets the operating mode of the controller. The forced
continuous current mode is active when the applied voltage is
less than 0.6V. Burst Mode operation will be active when the
pin is allowed to float and a Stage Shedding mode will be active
if the pin is tied to the V
this pin prior to the application of voltage on the VCC pin.)

PGOOD: This open-drain output is pulled low when the output
voltage has been outside the PGOOD tolerance window for the
V

ITH: Error Amplifier Output and Switching Regulator Compen­sation Point. All three current comparator’s thresholds in­crease with this control voltage.

PGND: Driver Power Ground. This pin connects directly to the
sources of the bottom N-channel external MOSFETs and the
(–) terminals of CIN.

PHASMD: This pin determines the phase shift between the first
controller’s rising TG signal and the rising edge of the CLKOUT
signal. Logic 0 yields 30 degrees and Logic 1 yields 60 degrees.

PLLIN: Synchronization Input to Phase Detector. This pin is
internally terminated to SGND with 50kΩ. The phase-locked
loop will force the rising top gate signal of controller 1 to be
synchronized with the rising edge of the PLLIN signal.

delay of approximately 100µs.

PGDLY

pin. (Do not apply voltage directly to

CC

IN

CC

is the

.

PLLFLTR: The phase-locked loop’s lowpass filter is tied to this
pin. Alternatively, this pin can be driven with an AC or DC
voltage source to vary the frequency of the internal oscillator.
(Do not apply voltage directly to this pin prior to the application
of voltage on the V

RUN/SS: Combination of Soft-Start, Run Control Input and
Short-Circuit Detection Timer. A capacitor to ground at this
pin sets the ramp time to full current output as well as the time
delay prior to an output voltage short-circuit shutdown. A
minimum value of 0.01µF is recommended on this pin.

SENSE1+, SENSE2+, SENSE3+, SENSE1–, SENSE2–, SENSE3–:

The Inputs to Each Differential Current Comparator. The ITH pin
voltage and built-in offsets between SENSE
in conjunction with R

SGND: Signal Ground. This pin must be routed separately
under the IC to the PGND pin and then to the main ground
plane.

SW1 to SW3: Switch Node Connections to Inductors. Voltage
swing at these pins is from a Schottky diode (external) voltage
drop below ground to VIN (where V
supply rail).

TG1 to TG3: High Current Gate Drives for Top N-channel
MOSFETs. These are the outputs of floating drivers with a
voltage swing equal to the boost voltage source superimposed
on the switch node voltage SW.

UVADJ: Input to the Undervoltage Shutdown Comparator.
When the applied input voltage is less than 1.2V, this compara­tor turns off the output MOSFET driver stages and discharges
the RUN/SS capacitor.

VCC: Main Supply Pin. Because this pin supplies both the
controller circuit power as well as the high power pulses
supplied to drive the external MOSFET gates, this pin needs to
be very carefully and closely decoupled to the IC’s PGND pin.

VDR: Supplies power to the bottom gate drivers only. This pin
needs to be very carefully and closely decoupled to the IC’s
PGND pin.

CC

SENSE

pin.)

–

and SENSE+ pins,

, set the current trip threshold level.

is the external MOSFET

IN

8

3731hfa

LTC3731H

U

U

W

FU CTIO AL DIAGRA

PGOOD

R1

PLLIN

F

IN

PLLFLTR

R

LP

C

LP

CLKOUT

PHASMD

100µs

DELAY

PROTECTION

FCB

0.6V

EAIN

0.600V

R2

0.660V

I

TH

C

C

R

C

UVADJ

1.2V

50k

V

–

+

+

–

FB

PHASE DET

OSCILLATOR

FCB

–

EA

+

OV

+

–

CLK1

CLK2
CLK3

–

0.66V

+

EAIN

–

+

0.54V

DUPLICATE FOR SECOND AND THIRD
CONTROLLER CHANNELS

DROP

OUT

DET

5(VFB)

1.5µA

6V

0.86V

SLOPE
COMP

CLAMP

SRQ

I

1

SS

SHDN

5(V

Q

0.55V

–

+

2.4V

RST

FB

FCB

)

LATCH

RS

V

CC

+–

BOT

B

+–

3mV

SHED

RUN

SOFT-

START

FORCE BOT

FCB

SHDN

–

+

54k54k

UV RESET

SWITCH

LOGIC

I

2

0.600V

INTERNAL

SUPPLY

1.2V

TOP

BOT

V

CC

BOOST

TG

SW

V

(VDR)

CC

BG

PGND

V

CC

36k

36k

SENSE

SENSE

+

R

SENSE

–

V

IN

D

B

C

B

L

+

C

IN

C

OUT

+

V

OUT

V

REF

V

CC

V

CC

+

SGND

RUN/SS

C

CC

C

SS

Figure 2

3731H F02

3731hfa

9

LTC3731H

OPERATIO

U

(Refer to Functional Diagram)

Main Control Loop

The IC uses a constant frequency, current mode step­down architecture. During normal operation, each top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator, I
current at which I
voltage on the I

, resets each RS latch. The peak inductor

1

resets the RS latch is controlled by the

1

pin, which is the output of the error

TH

amplifier EA. The EAIN pin receives a portion of output
voltage feedback signal through the external resistive
divider and is compared to the internal reference voltage.
When the load current increases, it causes a slight de­crease in the EAIN pin voltage
ence, which in turn causes the I

relative to the 0.6V refer-

voltage to increase until

TH

each inductor’s average current matches one third of the
new load current (assuming all three current sensing
resistors are equal). In Burst Mode operation and Stage
Shedding mode, after each top MOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current compara-

, or the beginning of the next cycle.

tor I

2

The top MOSFET drivers are biased from floating boot­strap capacitor C

, which is normally recharged through

B

an external Schottky diode when the top FET is turned off.
When V

decreases to a voltage close to V

IN

, however,

OUT

the loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector counts the
number of oscillator cycles that the bottom MOSFET
remains off and periodically forces a brief on period to
allow C

to recharge.

B

The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.5µA
current source to charge soft-start capacitor C
C

reaches 1.5V, the main control loop is enabled and the

SS

internally buffered I

voltage is clamped but allowed to

TH

. When

SS

ramp as the voltage on CSS continues to ramp. This “soft­start” clamping prevents abrupt current from being drawn
from the input power source. When the RUN/SS pin is low,
all functions are kept in a controlled state. The RUN/SS pin
is pulled low when the supply input voltage is below 4V,
when the undervoltage lockout pin (UVADJ) is below 1.2V,
or when the IC die temperature rises above 160°C.

Low Current Operation

The FCB pin is a logic input to select between three modes
of operation.

A) Burst Mode Operation

When the FCB pin voltage is below 0.6V, the controller
performs as a continuous, PWM current mode synchro­nous switching regulator. The top and bottom MOSFETs
are alternately turned on to maintain the output voltage
independent of direction of inductor current. When the
FCB pin is below V

– 1.5V but greater than 0.6V, the

CC

controller performs as a Burst Mode switching regulator.
Burst Mode operation sets a minimum output current level
before turning off the top switch and turns off the synchro­nous MOSFET(s) when the inductor current goes nega­tive. This combination of requirements will, at low current,
force the I

pin below a voltage threshold that will

TH

temporarily shut off both output MOSFETs until the output
voltage drops slightly. There is a burst comparator having
60mV of hysteresis tied to the ITH pin. This hysteresis
results in output signals to the MOSFETs that turn them on
for several cycles, followed by a variable “sleep” interval
depending upon the load current. The resultant output
voltage ripple is held to a very small value by having the
hysteretic comparator after the error amplifier gain block.

B) Stage Shedding Operation

When the FCB pin is tied to the VCC pin, Burst Mode
operation is disabled and the forced minimum inductor
current requirement is removed. This provides constant
frequency, discontinuous current operation over the wid­est possible output current range. At approximately 10%
of maximum designed load current, the second and third
output stages are shut off and the phase 1 controller alone
is active in discontinuous current mode. This “stage
shedding” optimizes efficiency by eliminating the gate
charging losses and switching losses of the other two
output stages. Additional cycles will be skipped when the
output load current drops below 1% of maximum de­signed load

current in order to maintain the output volt­age. This stage shedding operation is not as efficient as
Burst Mode operation at very light loads, but does provide
lower noise, constant frequency operating mode down to
very light load conditions.

10

3731hfa

OPERATIO

LTC3731H

U

(Refer to Functional Diagram)

C) Continuous Current Operation

Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, the controller will
cause current to flow back into the input filter capacitor.
If large enough,
supply from boosting to unacceptably high levels; see C

selection in the Applications Information section.

C

OUT

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be
synchronized to an external source using the PLLIN pin.
The output of the phase detector at the PLLFLTR pin is also
the DC frequency control input of the oscillator, which
operates over a 250kHz to 600kHz range corresponding to
a voltage input from 0V to 2.4V. When locked, the PLL
aligns the turn on of the top MOSFET to the rising edge of
the synchronizing signal. When no frequency information
is supplied to the PLLIN pin, PLLFLTR goes low, forcing the
oscillator to minimum frequency. A DC source can be
applied to the PLLFLTR pin to externally set the desired
operating frequency. A discharge current of approximately
20µA will be present at the pin with no PLLIN input signal.

Input capacitance ESR requirements and efficiency losses
are reduced substantially in a multiphase architecture
because the peak current drawn from the input capacitor
is effectively divided by the number of phases used and
power loss is proportional to the RMS current squared. A
3-stage, single output voltage implementation can reduce
input path power loss by 90%.

Power Good

The PGOOD pin is connected to the drain of an internal
N-channel MOSFET. The MOSFET is turned on once an
internal delay of about 100µs has elapsed and the output
voltage has been away from its nominal value by greater than
10%. If the output returns to normal prior to the delay
timeout, the timer is reset. There is no delay time for the
rising of the PGOOD output once the output voltage is within
the ±10% “window.”

the input capacitor will prevent the input

/

IN

Phase Mode

The PHASMD pin determines the phase shift between the
rising edge of the TG1 output and the rising edge of the
CLKOUT signal. Grounding the pin will result in 30 degrees
phase shift and tying the pin to V
degrees. These phase shift values enable extension to 6­and 12-phase systems. The PGOOD function above and
the PHASMD function are tied to a common pin in the UH
package.

Undervoltage Shutdown Adjust

The voltage applied to the UVADJ pin is compared to the
internal 1.2V reference to have an externally program­mable undervoltage shutdown. The RUN/SS pin is inter­nally held low until the voltage applied to the UVADJ pin
exceeds the 1.2V threshold.

Short-Circuit Detection

The RUN/SS capacitor is used initially to turn on and limit
the inrush current from the input power source. Once the
controllers have been given time, as determined by the
capacitor on the RUN/SS pin, to charge up the output
capacitors and provide full load current, the RUN/SS
capacitor is then used as a short-circuit timeout circuit. If
the output voltage falls to less than 70% of its nominal
output voltage, the RUN/SS capacitor begins discharg­ing, assuming that the output is in a severe overcurrent
and/or short-circuit condition. If the condition lasts for a
long enough period, as determined by the size of the
RUN/SS capacitor, the controller will be shut down until
the RUN/SS pin voltage is recycled. This built-in latchoff
can be overridden by providing >5µA at a compliance of

3.8V to the RUN/SS pin. This additional current shortens
the soft-start period but prevents net discharge of the
RUN/SS capacitor during a severe overcurrent and/or
short-circuit condition. Foldback current limiting is acti­vated when the output voltage falls below 70% of its
nominal level whether or not the short-circuit latchoff
circuit is enabled. Foldback current limit can be overrid­den by clamping the EAIN pin such that the voltage is held
above the (70%)(0.6V) or 0.42V level even when the
actual output voltage is low. Up to 100µA of input current
can safely be accommodated by the RUN/SS pin.

will result in 60

CC

3731hfa

11

LTC3731H

∆I

V

fL

V

V

L

OUT OUT

IN

= −

⎛
⎝

⎜

⎞
⎠

⎟

1

OPERATIO

U

(Refer to Functional Diagram)

Input Undervoltage Reset

The RUN/SS capacitor will be reset if the input voltage
(V

) is allowed to fall below approximately 4V. The

CC

capacitor on the RUN/SS pin will be discharged until the
short-circuit arming latch is disarmed. The RUN/SS ca­pacitor will attempt to cycle through a normal soft-start

WUUU

APPLICATIO S I FOR ATIO

The basic application circuit is shown in Figure 1 on the
first page of this data sheet. External component selection
is driven by the load requirement, and normally begins
with the selection of an inductance value based upon the
desired operating frequency, inductor current and output
voltage ripple requirements. Once the inductors and
operating frequency have been chosen, the current sens­ing resistors can be calculated. Next, the power MOSFETs
and Schottky diodes are selected. Finally, C
are selected according to the voltage ripple requirements.
The circuit shown in Figure 1 can be configured for
operation up to a MOSFET supply voltage of 28V
(limited by the external MOSFETs and possibly the mini­mum on-time).

and C

IN

OUT

ramp up after the V

supply rises above 4V. This circuit

CC

prevents power supply latchoff in the event of input power
switching break-before-make situations. The PGOOD pin
is held low during start-up until the RUN/SS capacitor
rises above the short-circuit latchoff arming threshold of
approximately 3.8V.

700

600

500

400

300

OPERATING FREQUENCY (kHz)

200

0

0.5 1 1.5 2 2.5
PLLFLTR PIN VOLTAGE (V)

3731H F03

Figure 3. Operating Frequency vs V

PLLFLTR

Operating Frequency

The IC uses a constant frequency, phase-lockable archi­tecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current plus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to the Phase-Locked
Loop and Frequency Synchronization section for addi­tional information.

A graph for the voltage applied to the PLLFLTR pin versus
frequency is given in Figure 3. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 680kHz.

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter­related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge and transition losses. In addition to
this basic tradeoff, the effect of inductor value on ripple
current and low current operation must also be consid­ered. The PolyPhase approach reduces both input and
output ripple currents while optimizing individual output
stages to run at a lower fundamental frequency, enhancing
efficiency.

The inductor value has a direct effect on ripple current. The
inductor ripple current ∆I

per individual section, N,

L

decreases with higher inductance or frequency and in­creases with higher VIN or V

OUT

:

where f is the individual output stage operating frequency.

3731hfa

12

WUUU

APPLICATIO S I FOR ATIO

In a PolyPhase converter, the net ripple current seen by the
output capacitor is much smaller than the individual
inductor ripple currents due to the ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.

Figure 4 shows the net ripple current seen by the output
capacitors for the different phase configurations. The
output ripple current is plotted for a fixed output voltage as
the duty factor is varied between 10% and 90% on the
x-axis. The output ripple current is normalized against the
inductor ripple current at zero duty factor. The graph can
be used in place of tedious calculations. As shown in
Figure 4, the zero output ripple current is obtained when:

V

OUT

V

So the number of phases used can be selected to minimize
the output ripple current and therefore the output ripple
voltage at the given input and output voltages. In applica­tions having a highly varying input voltage, additional
phases will produce the best results.

Accepting larger values of ∆I
inductances but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
∆IL = 0.4(I

is the total load current. Remember, the maximum

I

OUT

∆I

occurs at the maximum input voltage. The individual

L

inductor ripple currents are constant determined by the
input and output voltages, and the inductance.

Inductor Core Selection

Once the value for L1 to L3 is determined, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of ferrite, molyper­malloy or Kool Mµ
of core size for a fixed inductor value, but it is very
dependent on inductance selected. As inductance in­creases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.

k

where k N

==12 1, , ..., –

N

IN

)/N, where N is the number of channels and

OUT

®

cores. Actual core loss is independent

allows the use of low

L

LTC3731H

1.0

0.9

0.8

0.7

0.6

/fL

0.5

O

O(P-P)

V

∆I

0.4

0.3

0.2

0.1

0

0.1 0.2 0.3 0.4
DUTY FACTOR (V

Figure 4. Normalized Peak Output Current
vs Duty Factor [I

0.5 0.6 0.7 0.8 0.9

= 0.3(I

RMS

Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu­facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be­cause they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.

Power MOSFET and D1, D2, D3 Selection

At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N-channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and “on” resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as the
actual position (main or synchronous) in which the MOS­FET will be used. A much smaller and much lower input
capacitance MOSFET should be used for the top MOSFET

OUT/VIN

O(P-P)

1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
12-PHASE

)

3731H F04

]

3731hfa

13

LTC3731H

Main Switch Duty Cycle

V

V

Synchronous Switch Duty Cycle

VV

V

OUT

IN

IN OUT

IN

=

=

⎛
⎝

⎜

⎞
⎠

⎟

–

WUUU

APPLICATIO S I FOR ATIO

in applications that have an output voltage that is less than
1/3 of the input voltage. In applications where V

IN

>> V

OUT

,
the top MOSFETs’ “on” resistance is normally less impor­tant for overall efficiency than its input capacitance at
operating frequencies above 300kHz. MOSFET manufac­turers have designed special purpose devices that provide
reasonably low “on” resistance with significantly reduced
input capacitance for the main switch application in switch­ing regulators.

The peak-to-peak MOSFET gate drive levels are set by the
voltage, VCC, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BV

specification for the MOSFETs as well; many of the

DSS

logic-level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the “on”
resistance R

, input capacitance, input voltage and

DS(ON)

maximum output current.

MOSFET input capacitance is a combination of several
components but can be taken from the typical “gate
charge” curve included on most data sheets (Figure 5).
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gate­to-drain capacitance. The flat portion of the curve is the
result of the Miller multiplication effect of the drain-to-gate
capacitance as the drain drops the voltage across the
current source load. The upper sloping line is due to the
drain-to-gate accumulation capacitance and the gate-to­source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given V
adjusted for different V

V

GS

MILLER EFFECT

ab

Q

C

MILLER

IN

= (QB – QA)/V

Figure 5. Gate Charge Characteristic

voltages by multiplying by the

DS

DS

drain voltage, but can be

DS

V

IN

V

+

V

+

V

GS

–

–

3731H F05

DS

ratio of the application V
values. A way to estimate the C

to the curve specified V

DS

term is to take the

MILLER

DS

change in gate charge from points a and b on a manufac­turers data sheet and divide by the stated V
specified. C

is the most important selection criteria

MILLER

voltage

DS

for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C

RSS

and COS are specified sometimes but definitions of these
parameters are not included.

When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:

The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:

2

I

⎞
⎟

⎠

N

RC

()( )

DR MILLER

11

() ()

⎛
⎜

⎝

N

R

1

+

()

DS ON

()

•

⎤

+

f

()

⎥
⎦

2

⎞

()

⎟
⎠

+

1δδ

R

DS ON

+

()

P

MAIN

P

SYNC

V

⎛

OUTINMAX

=

⎜
⎝

V

I

2

MAX

V

IN

N

2

⎡
⎢

VV V

–

CC TH IL TH IL

⎣

–

VVVI

IN OUTINMAX

=

where N is the number of output stages, δ is the tempera­ture dependency of R
resistance (approximately 2Ω at V
drain potential

and

the change in drain potential in the

particular application. V

, RDR is the effective top driver

DS(ON)

= V

GS

MILLER

is the data sheet specified

TH(IL)

), VIN is the

typical gate threshold voltage specified in the power
MOSFET data sheet at the specified drain current. C

MILLER

is the calculated capacitance using the gate charge curve
from the MOSFET data sheet and the technique described
above.

14

3731hfa

WUUU

APPLICATIO S I FOR ATIO

LTC3731H

Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V

< 12V, the

IN

high current efficiency generally improves with larger
MOSFETs, while for V

> 12V, the transition losses

IN

rapidly increase to the point that the use of a higher
R

device with lower C

DS(ON)

actually provides higher

MILLER

efficiency. The synchronous MOSFET losses are greatest
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.

The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized R

vs temperature curve, but

DS(ON)

δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.

The Schottky diodes (D1 to D3 in Figure 1) conduct during
the dead time between the conduction of the two large
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead time and requiring a reverse recovery period
which could cost as much as several percent in efficiency.
A 2A to 8A Schottky is generally a good compromise for
both regions of operation due to the relatively small
average current. Larger diodes result in additional transi­tion loss due to their larger junction capacitance.

V

OUT

V

k

where k N

==12 1, , ..., –

N

IN

So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages.

In the graph of Figure 4, the local maximum input RMS
capacitor currents are reached when:

V

OUT

V

IN

k

21

==

where k N

12–, , ...,

N

These worst-case conditions are commonly used for de­sign because even significant deviations do not offer much
relief. Note that capacitor manufacturer’s ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than re­quired. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult
the capacitor manufacturer if there is any question.

The Figure 6 graph shows that the peak RMS input current
is reduced linearly, inversely proportional to the number N
of stages used. It is important to note that the efficiency
loss is proportional to the input RMS current squared and
therefore a 3-stage implementation results in 90% less

C

IN

and C

Selection

OUT

In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V

OUT/VIN

.
A low ESR input capacitor sized for the maximum RMS
current must be used. The details of a close form equation
can be found in Application Note 77. Figure 6 shows the
input capacitor ripple current for different phase configu­rations with the output voltage fixed and input voltage
varied. The input ripple current is normalized against the
DC output current. The graph can be used in place of
tedious calculations. The minimum input ripple current
can be achieved when the product of phase number and
output voltage, N(V

), is approximately equal to the

OUT

input voltage VIN or:

0.6

0.5

0.4

0.3

0.2

DC LOAD CURRENT

RMS INPUT RIPPLE CURRENT

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Figure 6. Normalized Input RMS Ripple Current
vs Duty Factor for One to Six Output Stages

DUTY FACTOR (V

1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
12-PHASE

OUT/VIN

0.9

)

3731H F06

3731hfa

15

LTC3731H

WUUU

APPLICATIO S I FOR ATIO

power loss when compared to a single phase design.
Battery/input protection fuse resistance (if used), PC
board trace and connector resistance losses are also
reduced by the reduction of the input ripple current in a
PolyPhase system. The required amount of input capaci­tance is further reduced by the factor, N, due to the
effective increase in the frequency of the current pulses.

Ceramic capacitors are becoming very popular for small
designs but several cautions should be observed. “X7R”,
“X5R” and “Y5V” are examples of a few of the ceramic
materials used as the dielectric layer, and these different
dielectrics have very different effect on the capacitance
value due to the voltage and temperature conditions
applied. Physically, if the capacitance value changes due
to applied voltage change, there is a concommitant piezo
effect which results in radiating sound! A load that draws
varying current at an audible rate may cause an attendant
varying input voltage on a ceramic capacitor, resulting in
an audible signal. A secondary issue relates to the energy
flowing back into a ceramic capacitor whose capacitance
value is being reduced by the increasing charge. The
voltage can increase at a considerably higher rate than the
constant current being supplied because the capacitance
value is decreasing as the voltage is increasing! Neverthe­less, ceramic capacitors, when properly selected and
used, can provide the lowest overall loss due to their
extremely low ESR.

The selection of C

is driven by the required effective

OUT

series resistance (ESR). Typically once the ESR require­ment is satisfied the capacitance is adequate for filtering.
The steady-state output ripple (∆V

∆∆V I ESR

≈ +

OUT RIPPLE

⎛
⎜

⎝

8

) is determined by:

OUT

⎞

1

⎟

OUT

⎠

NfC

where f = operating frequency of each stage, N is the
number of output stages, C

= ripple current in each inductor. The output ripple is

∆I

L

= output capacitance and

OUT

highest at maximum input voltage since ∆IL increases

with input voltage. The output ripple will be less than 50mV
at max V

C

OUT

with ∆IL = 0.4I

IN

OUT(MAX)

required ESR < N • R

assuming:

SENSE

and

C

OUT

> 1/(8Nf)(R

SENSE

)

The emergence of very low ESR capacitors in small,
surface mount packages makes very small physical imple­mentations possible. The ability to externally compensate
the switching regulator loop using the I

pin allows a

TH

much wider selection of output capacitor types. The
impedance characteristics of each capacitor type is sig­nificantly different than an ideal capacitor and therefore
requires accurate modeling or bench evaluation during
design.

Manufacturers such as Nichicon, Nippon Chemi-Con and
Sanyo should be considered for high performance through­hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo and the Panasonic SP
surface mount types have a good (ESR)(size) product.
Once the ESR requirement for C
RMS current rating generally far exceeds the I

has been met, the

OUT

RIPPLE(P-P)

requirement. Ceramic capacitors from AVX, Taiyo Yuden,
Murata and Tokin offer high capacitance value and very
low ESR, especially applicable for low output voltage
applications.

In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum elec­trolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer sur­face mount capacitors offer very low ESR also but have
much lower capacitive density per unit volume. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
choices are the AVX TPS, AVX TPSV, the KEMET T510
series of sur

face-mount tantalums or the Panasonic SP

series of surface mount special polymer capacitors

16

3731hfa

WUUU

APPLICATIO S I FOR ATIO

LTC3731H

available in case heights ranging from 2mm to 4mm. Other
capacitor types include Sanyo POS-CAP, Sanyo OS-CON,
Nichicon PL series and Sprague 595D series. Consult the
manufacturer for other specific recommendations.

R

Selection for Output Current

SENSE

Once the frequency and inductor have been chosen,
R

SENSE1, RSENSE2, RSENSE3

are determined based on the
required peak inductor current. The current comparator
has a typical maximum threshold of 75mV/R
input common mode range of SGND to (1.1) • V

SENSE

and an

. The

CC

current comparator threshold sets the peak inductor cur­rent, yielding a maximum average output current I

MAX

equal to the peak value less half the peak-to-peak ripple
current, ∆I

.

L

Allowing a margin for variations in the IC and external
component values yields:

mV

RN

SENSE

The IC works well with values of R

50

=

I

MAX

from 0.002Ω to

SENSE

0.02Ω.

V

Decoupling

CC

The VCC and VDR pins supply power to the internal circuits
of the controller and to the top and bottom gate drivers.
Therefore, they must be bypassed very carefully to ground
with ceramic capacitors, type X7R or X5R (depending
upon the operating temperature environment) of

1

µ

F imme

diately next to the IC

and preferably an addi-

at least

tional 10µF placed very close to the IC due to the extremely
high instantaneous currents involved. The total capaci­tance, taking into account the voltage coefficient of ce­ramic capacitors, should be 100 times as large as the total
combined gate charge capacitance of ALL of the MOSFETs
being driven. Good bypassing close to the IC is necessary
to supply the high transient currents required by the
MOSFET gate drivers while keeping the 5V supply quiet
enough so as not to disturb the very small-signal high
bandwidth of the current comparators.

Topside MOSFET Driver Supply (C

External bootstrap capacitors, C

, DB)

B

, connected to the BOOST

B

pins, supply the gate drive voltages for the topside
MOSFETs. Capacitor C
charged though diode D

in the Functional Diagram is

B

from VCC when the SW pin is

B

low. When one of the topside MOSFETs turns on, the
driver places the C

voltage across the gate-source of the

B

desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply (V

+ VIN). The value of the boost capacitor CB needs to be

V

CC

BOOST

=

30 to 100 times that of the total gate charge capacitance of
the topside MOSFET(s) as specified on the manufacturer’s
data sheet. The reverse breakdown of D
than V

IN(MAX).

must be greater

B

The output voltage is set by an external resistive divider
according to the following formula:

R

1

VV

=+

OUT

⎛

06 1

.

⎜
⎝

⎞
⎟

⎠

R

2

The resistive divider is connected to the output as shown
in Figure 2.

Soft-Start/Run Function

The RUN/SS pin provides three functions: 1) ON/OFF, 2)
soft-start and 3) a defeatable short-circuit latch off timer.
Soft-start reduces the input power sources’ surge currents
by gradually increasing the controller’s current limit (pro­portional to an internal buffered and clamped V

ITH

). The
latchoff timer prevents very short, extreme load transients
from tripping the overcurrent latch. A small pull-up cur­rent (>5µA) supplied to the RUN/SS pin will prevent the
overcurrent latch from operating. A maximum pull-up
current of 200µA is allowed into the RUN/SS pin even
though the voltage at the pin may exceed the absolute
maximum rating for the pin. This is a result of the limited
current and the internal protection circuit on the pin. The
following explanation describes how this function operates.

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An internal 1.5µA current source charges up the C

SS

capacitor. When the voltage on RUN/SS reaches 1.5V, the
controller is permitted to start operating. As the voltage on
RUN/SS increases from 1.5V to 3.5V, the internal current
limit is increased from 20mV/R

to 75mV/R

SENSE

SENSE

.
The output current limit ramps up slowly, taking an
additional 1s/µF to reach full current. The output current
thus ramps up slowly, eliminating the starting surge
current required from the input power supply. If RUN/SS
has been pulled all the way to ground, there is a delay
before starting of approximately:

.

15

t

DELAY SS SS

t

IRAMP SS SS

V

=

.

15

A

µ

315

VV

−

=

.

15

µ

CsFC

.
A

/

1

=µ

()

/

CsFC

1

=µ

()

By pulling the RUN/SS controller pin below 0.4V the
IC is put into low current shutdown (I

< 100 µA). The

Q

RUN/SS pin can be driven directly from logic as shown in
Figure 7. Diode, D1, in Figure 7 reduces the start delay
but allows CSS to ramp up slowly, providing the soft-start
function. The RUN/SS pin has an internal 6V zener clamp
(see the Functional Diagram).

Fault Conditions: Overcurrent Latchoff

The RUN/SS pins also provide the ability to latch off the
controllers when an overcurrent condition is detected. The
RUN/SS capacitor is used initially to turn on and limit the
inrush current of all three output stages. After the control­lers have been started and been given adequate time to
charge up the output capacitor and provide full load
current, the RUN/SS capacitor is used for a short-circuit

timer. If the output voltage falls to less than 70% of its
nominal value, the RUN/SS capacitor begins discharging
on the assumption that the output is in an overcurrent
condition. If the condition lasts for a long enough period,
as determined by the size of the RUN/SS capacitor, the
discharge current, and the circuit trip point, the controller
will be shut down until the RUN/SS pin voltage is recycled.
If the overload occurs during start-up, the time can be
approximated by:

>> (CSS • 0.6V)/(1.5µA) = 4 • 105 (CSS)

t

LO1

If the overload occurs after start-up, the voltage on the
RUN/SS capacitor will continue charging and will provide
additional time before latching off:

t

>> (CSS • 3V)/(1.5µA) = 2 • 106 (CSS)

LO2

This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin from V

CC

as shown in Figure 7. When VCC is 5V, a 200k resistance
will prevent the discharge of the RUN/SS capacitor
during an overcurrent condition but also shortens the
soft-start period, so a larger RUN/SS capacitor value may
be required.

Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem with
noise pick-up or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
foldback current limiting still remains active, thereby
protecting the power supply system from failure. A deci­sion can be made after the design is complete whether to
rely solely on foldback current limiting or to enable the
latchoff feature by removing the pull-up resistor.

18

RUN/SS PIN3.3V OR 5V

SHDNSHDN

C

SS

Figure 7. RUN/SS Pin Interfacing

5V

V

D1

RUN/SS PIN

CC

R

SS

C

SS

3731H F07

The value of the soft-start capacitor C

may need to be

SS

scaled with output current, output capacitance and load
current characteristics. The minimum soft-start capaci­tance is given by:

> (C

C

SS

OUT

)(V

) (10–4) (R

OUT

SENSE

)

The minimum recommended soft-start capacitor of
C

= 0.1µF will be sufficient for most applications.

SS

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Current Foldback

In certain applications, it may be desirable to defeat the
internal current foldback function. A negative impedance
is experienced when powering a switching regulator.
That

is, the input current is higher at a lower VIN and

decreases as V

is increased. Current foldback is de-

IN

signed to accommodate a normal, resistive load having
increasing current draw with increasing voltage. The EAIN
pin should be artificially held 70% above its nominal
operating level of 0.6V, or 0.42V in order to prevent the IC
from “folding back” the peak current level. A suggested
circuit is shown in Figure 8.

The emitter of Q1 will hold up the EAIN pin to a voltage in
the absence of V

that will prevent the internal sensing

OUT

circuitry from reducing the peak output current. Remov­ing the function in this manner eliminates the external
MOSFET’s protective feature under short-circuit condi­tions. This technique will also prevent the short-circuit
latchoff function from turning off the part during a short­circuit event and the peak output current will only be
limited to N • 75mV/R

SENSE

.

Undervoltage Reset

In the event that the input power source to the IC (V

CC

)
drops below 4V, the RUN/SS capacitor will be discharged
to ground. When V

rises above 4V, the RUN/SS capaci-

CC

tor will be allowed to recharge and initiate another soft­start turn-on attempt. This may be useful in applications
that switch between two supplies that are not diode

connected, but note that this cannot make up for the
resultant interruption of the regulated output.

Phase-Locked Loop and Frequency Synchronization

The IC has a phase-locked loop comprised of an internal
voltage controlled oscillator and phase detector. This
allows the top MOSFET of output stage 1’s turn-on to be
locked to the rising edge of an external source. The
frequency range of the voltage controlled oscillator is
±50% around the center frequency f

. A voltage applied to

O

the PLLFLTR pin of 1.2V corresponds to a frequency of
approximately 400kHz. The nominal operating frequency
range of the IC is 225kHz to 680kHz.

The phase detector used is an edge sensitive digital type
that provides zero degrees phase shift between the
external and internal oscillators. This type of phase
detector will not lock the internal oscillator to harmonics
of the input frequency. The PLL hold-in range, ∆f
equal to the capture range, ∆f

∆fH = ∆fC = ±0.5 f

O

:

C

H

, is

The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter components on the PLLFLTR pin. A simplified block
diagram is shown in Figure 9.

If the external frequency (f
lator frequency, f

, current is sourced continuously,

OSC

) is greater than the oscil-

PLLIN

pulling up the PLLFLTR pin. When the external frequency
is less than f

, current is sunk continuously, pulling

OSC

V

CC

CALCULATE FOR

0.42V TO 0.55V

Figure 8. Foldback Current Elimination

V

CC

LTC3731H

Q1

EAIN

3731H F08

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EXTERNAL

OSC

PHASE
DETECTOR/
OSCILLATOR

OSC

2.4V

R

LP

10k

PLLFLTR

C

LP

PLLIN

50k

Figure 9. Phase-Locked Loop Block Diagram

DIGITAL

PHASE/

FREQUENCY

DETECTOR

down the PLLFLTR pin. If the external and internal fre­quencies are the same, but exhibit a phase difference, the
current sources turn on for an amount of time correspond­ing to the phase difference. Thus, the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point, the phase comparator output is
open and the filter capacitor C

holds the voltage. The IC

LP

PLLIN pin must be driven from a low impedance source
such as a logic gate located close to the pin. When using
multiple ICs for a phase-locked system, the PLLFLTR pin
of the master oscillator should be biased at a voltage that
will guarantee the slave oscillator(s) ability to lock onto the
master’s frequency. A voltage of 1.7V or below applied to
the master oscillator’s PLLFLTR pin is recommended in
order to meet this requirement. The resultant operating
frequency will be approximately 550kHz for 1.7V.

The loop filter components (C

, RLP) smooth out the

LP

current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically R

=10k and CLP ranges from

LP

0.01µF to 0.1µF.

Minimum On-Time Considerations

Minimum on-time, t

ON(MIN)

, is the smallest time duration

that the IC is capable of turning on the top MOSFET. It is

3731H F09

determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:

V

t

ON MIN

()

<

Vf

IN

OUT

()

If the duty cycle falls below what can be accommodated by
the minimum on-time, the IC will begin to skip every other
cycle, resulting in half-frequency operation. The output
voltage will continue to be regulated, but the ripple current
and ripple voltage will increase.

The minimum on-time for the IC is generally about 110ns.
However, as the peak sense voltage decreases the mini­mum on-time gradually increases. This is of particular
concern in forced continuous applications with low ripple
current at light loads. If the duty cycle drops below the
minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.

If an application can operate close to the minimum on­time limit, an inductor must be chosen that is low enough
in value to provide sufficient ripple amplitude to meet the
minimum on-time requirement.

As a general rule, keep
the inductor ripple current for each channel equal to or
greater than 30% of I

OUT(MAX)

at V

IN(MAX)

.

20

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Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage
of input power.

Checking Transient Response

The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
amount equal to ∆I
series resistance of C
discharge C

, generating the feedback error signal that

OUT

• ESR, where ESR is the effective

LOAD

OUT

. ∆I

also begins to charge or

LOAD

shifts by an

OUT

forces the regulator to adapt to the current change and
return V
time, V

to its steady-state value. During this recovery

OUT

can be monitored for excessive overshoot or

OUT

ringing, which would indicate a stability problem. The

availability of the I

pin not only allows optimization of

TH

control loop behavior, but also provides a DC coupled
and AC filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed-loop response. Assuming a predominantly

second order system, phase margin and/or damping
factor can be estimated using the percentage of overshoot
seen at this pin. The bandwidth can also be estimated by
examining the rise time at the pin. The I

external com-

TH

ponents shown in the Figure 1 circuit will provide an
adequate starting point for most applications.

The I

series RC-CC filter sets the dominant pole-zero

TH

loop compensation. The values can be modified slightly

(from 0.2 to 5 times their suggested values) to maximize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 80% of full load current having a rise time
of <2µs will produce output voltage and I

pin waveforms

TH

that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step,
resulting from the step change in output current, may not
be within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why it
is better to look at the I

pin signal which is in the

TH

feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing RC and the bandwidth of the loop will be
increased by decreasing C
factor that C

is decreased, the zero frequency will be kept

C

. If RC is increased by the same

C

the same, thereby keeping the phase the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual over­all supply performance.

A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C

, causing a rapid drop in V

OUT

. No regulator can

OUT

alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If C
than 2% of C

, the switch rise time should be controlled

OUT

LOAD

is greater

so that the load rise time is limited to approximately
1000 • R
R

SENSE

• C

SENSE

resistor would require a 500µs rise time, limiting

. Thus a 250µF capacitor and a 2mΩ

LOAD

the charging current to about 1A.

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Automotive Considerations: Plugging into the
Cigarette Lighter

As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during opera­tion. But before you connect, be advised: you are plugging
into the supply from hell. The main battery line in an
automobile is the source of a number of nasty potential
transients, including load dump, reverse battery and
double battery.

Load dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.

The network shown in Figure 10 is the most straightfor­ward approach to protect a DC/DC converter from the
ravages of an automotive battery line. The series diode
prevents current from flowing during reverse battery,
while the transient suppressor clamps the input voltage
during load dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the IC has a maximum input voltage
of 32V on the SW pins, most applications will be limited to
30V by the MOSFET BV

V

CC

5V

DSS

+

.

V

BAT

12V

Design Example

As a design example, assume V

= 20V(max), V

V

IN

OUT

= 1.3V, I

= 5V, V

CC

MAX

= 12V(nominal),

IN

= 45A and f = 400kHz.
The inductance value is chosen first based upon a 30%
ripple current assumption. The highest value of ripple
current in each output stage occurs at the maximum input
voltage.

=

fIVV

()

=

400 30.%

()(

≥ µ

068

.

−

1

⎜

∆

⎝

13

kHz

H

⎛

V

OUT OUT

L

IN

V

⎞
⎟

⎠

15

A

))( )

13

V

.

20

⎞
⎟

⎠

V

⎛

1

−

⎜

⎝

Using L = 0.6µH, a commonly available value results in
34% ripple current. The worst-case output ripple for the
three stages operating in parallel will be less than 11% of
the peak output current.

R

SENSE1, RSENSE2

and R

SENSE3

can be calculated by using
a conservative maximum sense current threshold of 65mV
and taking into account half of the ripple current:

R

SENSE

=

15 1

mV

34

⎛

A

+

⎜
⎝

%

⎞
⎟

⎠

2

= Ω

0 0037

.

65

Use a commonly available 0.003Ω sense resistor.

Next verify the minimum on-time is not violated. The
minimum on-time occurs at maximum V

.13

20 400

()

t

ON MIN

=

()

VfVV kHz

IN MAX

V

OUT

()

()

=

CC

=

:

162

ns

22

LTC3731H

3731H F10

Figure 10. Automotive Application Protection

The output voltage will be set by the resistive divider from
the DIFFOUT pin to SGND, R1 and R2 in the Functional
Diagram. Set R1 = 13.3k and R2 = 11.3k.

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The power dissipation on the topside MOSFET can be
estimated. Using a Fairchild FDS6688 for example, R
= 7mΩ, C
voltage with T(estimated) = 50°C:

The worst-case power dissipation by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem­perature rise is:

P

A short circuit to ground will result in a folded back current
of:

with a typical value of R

0.25. The resulting power dissipated in the bottom MOS­FET is:

which is less than one third of the normal, full load
conditions. Incidentally, since the load no longer dissi­pates any power, total system power is decreased by over
90%. Therefore, the system actually cools significantly
during a shorted condition!

PC Board Layout Checklist

MILLER

P

MAIN

=

SYNC

I

≈

SC

()

= (7.5A)2(1.25)(0.007Ω) ≈ 0.5W

P

SYNC

= 15nC/15V = 1000pF. At maximum input

18

.

V

2

≈

0 007 20

23

15 1 0 005 50 25

()+()

20

V

.

⎛
⎜

⎝

518118

20 1 3

25

+

+

Ω

()

1

–. .

VV V

.

VV

−

V

20

mV

m

+

Ω

.

[]

⎛

45

2

⎜

23

()()

⎝

+

15 1 25 0 007 1 84

()( )

1
2

DS(ON)

⎞

()

⎟
⎠

2

AW

⎛

150 20

ns V

⎜

0675.

⎝

µ

and d = (0.005/°C)(50°C) =

CC

° − °

()

⎞

A

2 1000

Ω

()( )

⎟
⎠

400 2 2

.. .

()

H

=

kHz W

()

⎞

=

⎟
⎠

Ω

DS(ON)

pF

.

=

.

A

1) Are the signal and power ground paths isolated? Keep the
SGND at one end of a printed circuit path thus preventing
MOSFET currents from traveling under the IC. The IC signal
ground pin should be used to hook up all control circuitry
on one side of the IC, routing the copper through SGND,
under the IC covering the “shadow” of the package, connect­ing to the PGND pin and then continuing on to the (–) plates
of C

and C

IN

placed immediately adjacent to the IC between the V
and PGND. A 1µF ceramic capacitor of the X7R or X5R type
is small enough to fit very close to the IC to minimize the ill
effects of the large current pulses drawn to drive the bottom
MOSFETs. An additional 5µF to 10µF of ceramic, tantalum
or other very low ESR capacitance is recommended in or­der to keep the internal IC supply quiet. The power ground
returns to the sources of the bottom N-channel MOSFETs,
anodes of the Schottky diodes and (–) plates of C
should have as short lead lengths as possible.

2) Does the VFB pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con­nected between the (+) plate of C

3) Are the SENSE– and SENSE+ printed circuit traces for
each channel routed together with minimum PC trace
spacing? The filter capacitors between SENSE
for each channel should be as close as possible to the pins
of the IC. Connect the SENSE
pads of the sense resistor as illustrated in Figure 12.

4) Do the (+) plates of C
topside MOSFETs as closely as possible? This capacitor
provides the pulsed current to the MOSFETs.

5) Keep the switching nodes, SWITCH, BOOST and TG
away from sensitive small-signal nodes (SENSE
SENSE–, EAIN). Ideally the SWITCH, BOOST and TG
printed circuit traces should be routed away and separated
from the IC and especially the “quiet” side of the IC.
Separate the high dv/dt traces from sensitive small-signal
nodes with ground traces or ground planes.

. The VCC decoupling capacitor should be

OUT

IN

and signal ground.

OUT

+

and SENSE

–

and SENSE+ pins to the

connect to the drains of the

PWR

pin

CC

, which

+

–

,

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. These items are also illustrated graphically in the layout
diagram of Figure 11. Check the following in the PC layout:

6) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.

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L1

SW1

D1

V

IN

R

IN

+

C

IN

SW2

D2

L2

R

R

SENSE2

SENSE1

V

OUT

+

C

OUT

R

L

BOLD LINES INDICATE HIGH,
SWITCHING CURRENTS.
KEEP LINES TO A MINIMUM LENGTH.

LTC3731H

+

SENSE

–

SENSE

Figure 12. Kelvin Sensing R

INDUCTOR

1000pF

OUTPUT CAPACITOR

L3

SW3

D3

R

SENSE3

Figure 11. Branch Current Waveforms

7) The 47pF to 330pF ceramic capacitor between the I
pin and signal ground should be placed as close as

SENSE
RESISTOR

possible to the IC.

Figure 11 illustrates all branch currents in a three-phase
switching regulator. It becomes very clear after studying

3731H F12b

the current waveforms why it is critical to keep the high
switching current paths to a small physical size. High elec­tric and magnetic fields will radiate from these “loops” just

SENSE

as radio stations transmit signals. The output capacitor

3731H F11

TH

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LTC3731H

ground should return to the negative terminal of the input
capacitor and not share a common ground path with any
switched current paths. The left half of the circuit gives rise
to the “noise” generated by a switching regulator. The
ground terminations of the synchronous MOSFETs and
Schottky diodes should return to the bottom plate(s) of the
input capacitor(s) with a short isolated PC trace since very
high switched currents are present. A separate isolated path
from the bottom plate(s) of the input and output capacitor(s)
should be used to tie in the IC power ground pin (PGND).
This technique keeps inherent signals generated by high
current pulses taking alternate current paths that have fi­nite impedances during the total period of the switching
regulator. External OPTI-LOOP compensation allows over­compensation for PC layouts which are not optimized but
this is not the recommended design procedure.

SINGLE PHASE

V

SW

I

CIN

Simplified Visual Explanation of How a 3-Phase
Controller Reduces Both Input and Output RMS
Ripple Current

The effect of multiphase power supply design significantly
reduces the amount of ripple current in both the input and
output capacitors. The RMS input ripple current is divided
by, and the effective ripple frequency is multiplied up by
the number of phases used (assuming that the input
voltage is greater than the number of phases used times
the output voltage). The output ripple amplitude is also
reduced by, and the effective ripple frequency is increased
by the number of phases used. Figure 13 graphically
illustrates the principle.

I

COUT

TRIPLE PHASE

V

SW1

V

SW2

V

SW3

I

L1

I

L2

I

L3

I

CIN

I

COUT

Figure 13. Single and Polyphase Current Waveforms

3731H F13

3731hfa

25

LTC3731H

WUUU

APPLICATIO S I FOR ATIO

The worst-case input RMS ripple current for a single stage
design peaks at twice the value of the output voltage. The
worst-case input RMS ripple current for a two stage
design results in peaks at 1/4 and 3/4 of the input voltage,
and the worst-case input RMS ripple current for a three
stage design results in peaks at 1/6, 1/2, and 5/6 of the
input voltage. The peaks, however, are at ever decreasing
levels with the addition of more phases. A higher effective
duty factor results because the duty factors “add” as long
as the currents in each stage are balanced. Refer to AN19
for a detailed description of how to calculate RMS current
for the single stage switching regulator.

Figure 6 illustrates the RMS input current drawn from the
input capacitance versus the duty cycle as determined by
the ratio of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 2/3
in a 3-phase solution due to the current splitting between
the three stages.

The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the V

/L discharge currents

OUT

term from the stages that has their bottom MOSFETs on
subtract current from the (V

CC

– V

)/L charging current

OUT

resulting from the stage which has its top MOSFET on. The
output ripple current for a 3-phase design is:

V

=

()( )

OUT

fL

DC V V

13 3–

()

IN OUT

>

I

P-P

The ripple frequency is also increased by three, further
reducing the required output capacitance when V

CC

< 3V

OUT

as illustrated in Figure 6.

The addition of more phases, by phase locking additional
controllers, always results in no net input or output ripple
at V

OUT/VIN

ratios equal to the number of stages
implemented. Designing a system with multiple stages
close to the V

OUT/VIN

ratio will significantly reduce the
ripple voltage at the input and outputs and thereby
improve efficiency, physical size and heat generation of
the overall switching power supply. Refer to Application
Note 77 for more information on Polyphase circuits.

Efficiency Calculation

To estimate efficiency, the DC loss terms include the input
and output capacitor ESR, each MOSFET R
tor resistance R

, the sense resistance R

L

DS(ON)

SENSE

, induc-

and the
forward drop of the Schottky rectifier at the operating
output current and temperature. Typical values for the
design example given previously in this data sheet are:

Main MOSFET R
Sync MOSFET R
C
C
R
R
V
V
V
I

= 20mΩ

INESR

OUTESR

= 2.5mΩ

L

= 3mΩ

SENSE

SCHOTTKY

= 1.3V

OUT

= 12V

IN

= 45A

MAX

= 3mΩ

= 0.8V at 15A (0.7V at 90°C)

= 7mΩ (9mΩ at 90°C)

DS(ON)

= 7mΩ (9mΩ at 90°C)

DS(ON)

δ = 0.5%°C (MOSFET temperature coefficient)
N = 3
f = 400kHz

The main MOSFET is on for the duty factor V

OUT/VIN

and
the synchronous MOSFET is on for the rest of the period
or simply (1 – V

OUT/VIN

). Assuming the ripple current is
small, the AC loss in the inductor can be made small if a
good quality inductor is chosen. The average current,
I

is used to simplify the calculations. The equation

OUT,

below is not exact but should provide a good technique
for the comparison of selected components and give a
result that is within 10% to 20% of the final application.
Determining the MOSFETs’ die temperature may require
iterative calculations if one is not familiar with typical
performance. A maximum operating junction tempera­ture of 90° to 100°C for the MOSFETs is recommended
for high reliability applications.

Common output path DC loss:

2

I

⎞

⎛

PN

COMPATH

MAX

≈

⎟

⎜

⎠

⎝

N

+

RR C Lo

()

L SENSE OUTESR

+

sss

26

This totals 3.7W + C

OUTESR

loss.

3731hfa

WUUU

APPLICATIO S I FOR ATIO

LTC3731H

Total of all three main MOSFETs’ DC loss:

⎛

⎞

V

⎛

PN

MAIN

OUT

=

⎜

⎝

⎜

⎟

⎝

V

⎠

IN

This totals 0.87W + C

I

MAX

N

INESR

2

⎞

+

R

1 δ

()

⎟

⎠

DS ON

loss (at 90°C).

+ C Loss

())

INESR

Total of all three synchronous MOSFETs’ DC loss:

⎛

PN

=

SYNC

V

11

–

⎜

⎝

OUT

V

IN

⎞

⎛
⎜

⎟

⎝

⎠

I

MAX

N

2

⎞

+

()

⎟

⎠

R

DS

(δOON)

This totals 7.2W at 90°C.

Total of all three main MOSFETs’ AC loss:

A

45

PV

≈Ω

MAIN IN

2

()

3

1

⎛
⎜

⎝

VV V

–. .

518118

()( )

()()

2 1000

23

+

pF

⎞

kHz W

().

400 6 3

⎟
⎠

=

This totals 1W at VIN = 8V, 2.25W at VIN = 12V and 6.25W
at V

= 20V.

IN

Total of all three synchronous MOSFETs’ AC gate loss:

() () ()( ) ( )361545Q

G

V

V

IN

DSSPEC

fnC

=

V

IN

V

DSSPEC

E

This totals 0.08W at V

0.19W at V

= 20V. The bottom MOSFET does not

IN

= 8V, 0.12W at VIN = 12V and

IN

experience the Miller capacitance dissipation issue that
the main switch does because the bottom switch turns on
when its drain is close to ground.

The Schottky rectifier loss assuming 50ns nonoverlap
time:

2 • 3(0.7V)(15A)(50ns)(4E5)

This totals 1.26W.

The total output power is (1.3V)(45A) = 58.5W and the
total input power is approximately 60W so the % loss of
each component is as follows:

Main switch’s AC loss (V

= 12V) 2.25W 3.75%

IN

Main switch’s DC loss 0.87W 1.5%
Synchronous switch AC loss 0.19W 0.3%
Synchronous switch DC loss 7.2W 12%
Power path loss 3.7W 6.1%

The numbers above represent the values at V

= 12V. It

IN

can be seen from this simple example that two things can
be done to improve efficiency: 1) Use two MOSFETs on the
synchronous side and 2) use a smaller MOSFET for the
main switch with smaller C

to better balance the AC

MILLER

loss with the DC loss. A smaller, less expensive MOSFET
can actually perform better in the task of the main switch.

3731hfa

27

LTC3731H

TYPICAL APPLICATIO S

U

OPTIONAL FILTER FOR

SYNCHRONIZATION

1000pF

0.01µF

10k

100pF

6.04k

9.09k

0.01µF

330pF

3.3nF

2.2k

VIN: 3.3V TO 20V

: 1.5V AT 65A

V

OUT

SWITCHING FREQUENCY: 300kHz

NC

3731H F14

1µF

0.1µF

V

CC

0.1µF

0.1µF

PGOOD

47k

1Ω

V

CC

10µF

V

CC

V

CC

5V TO 7V
V

IN

M1

M2 D1

M3

M4 D2

M5

M6 D3

L1 TO L3: 0.8µH SUMIDA CEP125-0R8
M1, M3, M5: IRF7821W ×2, Si7860DP

M2, M4, M6: IRF7832 ×2, Si7892DP × 2

L1

S1

V

IN

L2

S2

V

IN

L3

S3

OR HAT2168 ×2

OR HAT2165 ×2

0.002Ω

+

0.002Ω

+

0.002Ω

+

–

S1

–

S2

–

S3

V

OUT

1.5V AT 65A

+

10µF

6.3V
×3

+

10µF
25V
×5

C

OUT

C

IN

68µF
25V

V

IN

3.3V TO 20V

1µF

1

V

CC

SYNC IN

300kHz

300pF

+

S1

1000pF

–

S1

+

S2

1000pF

–

S2

–

S3

1000pF

+

S3

V

IN

18k

V

CC

2

PLLIN

3

PLLFLTR

4

FCB

5

NC

6

NC

7

NC

8

EAIN

9

SGND

10

SENSE1

11

SENSE1

12

SENSE2

13

SENSE2

14

SENSE3

15

SENSE3

16

RUN/SS

I

17

TH

I

TH

18

UVADJ

12k

CIN: SANYO OS-CON 25SP68M

: 270µF/2V ×8 PANASONIC SP EEUE0D271R

C

OUT

OR 470µF/2.5V ×6 SANYO POSCAP 2R5 TPD470M

D1 TO D3: DIODES INC. B340A

BOOST1

LTC3731H

BOOST2

+

–

+

–

–

+

BOOST3

PHASMD

10Ω

CLK

PGOOD

TG1

SW1

TG2

SW2

V

DR

BG1

PGND

BG2

BG3

SW3

TG3

SGND

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

Figure 14. 3-Phase 65A Power Supply

3731hfa

28

TYPICAL APPLICATIO S

LTC3731H

U

2.5V/100A Power Supply

270pF

1.2k

SYNC IN

330pF

I

TH

2700pF

V

CC

PGOOD

TG1

SW1

TG2

SW2

V

BG1

PGND

BG2

BG3

SW3

TG3

SGND2

36

CLK1

35

34

33

32

31

30

29

28

DR

27

26

25

24

23

22

21

20

19

0.1µF

0.1µF

+

1µF
Cer.

0.1µF

V

CC

1k

8.2k

3.3k

4.7k

0.1µF

V

IN

68pF

357k

121k

15k

220pF

EAIN

10Ω×6

+

S1

S1

S2

S2

S3

S3

–

+

–

–

+

1000pF

1000pF

1000pF

RUN/SS

V

CC

1

V

CC

10

11

12

13

14

15

16

17

18

2

3

4

5

6

7

8

9

V

PLLIN

PLLFLTR

FCB

NC

NC

NC

EAIN

SGND

SENSE1

SENSE1

SENSE2

SENSE2

SENSE3

SENSE3

RUN/SS

I

TH

UVADJ

CC

LTC3731H

CLKOUT

BOOST1

BOOST2

+

–

+

–

–

+

BOOST3

PHASMD

1µF

1Ω

4.7µF

10Ω

PGOOD

10k

M1

X2
M2,3

M4

X2
M5,6

M7

X2
M8,9

BOOST1

V

IN

V

V

BOOST2

L1

D1

IN

L2

D2

IN

L3

D3

BOOST3

0.002Ω

+

S1

0.002Ω

+

S2

0.002Ω

+

S3

10µF

Cer.

S1

S2

S3

–

–

–

+

10µF

10V

V5

V

OUT

+

C

OUT

V

IN

+

C

IN

1000pF

10k

1000pF

100pF

0.01µF

S4

S4

S5

S5

S6

S6

+

–

+

–

–

+

EAIN

10Ω×6

UVADJ

RUN/SS

100pF

10pF

1000pF

1000pF

1000pF

UVADJ

V

CLK1

1000pF

CC

10

11

12

13

14

15

16

17

18

1

2

3

4

5

6

7

8

9

V

CC

PLLIN

PLLFLTR

FCB

NC

LTC3731H

NC

NC

EAIN

SGND

SENSE4

SENSE4

SENSE5

SENSE5

SENSE6

SENSE6

RUN/SS

I

TH

UVADJ

+

–

+

–

–

+

PHASMD

CLKOUT

PGOOD

BOOST4

TG4

SW4

BOOST5

TG5

SW5

V

BG4

PGND

BG5

BG6

SW6

TG6

BOOST6

SGND2

V5

1µF
Cer.

0.1µF

PGOOD

0.1µF

0.1µF

+

10Ω

4.7µF

BOOST4

M10

X2
M11,12

M13

X2
M14,15

M16

X2
M17,18

BOOST5

V

IN

V

V

D4

IN

D5

IN

D6

BOOST6

L4

L5

L6

S4

S5

S6

0.002Ω

+

0.002Ω

+

0.002Ω

+

–

S4

–

S5

–

S6

36

CLKOUT

35

34

33

32

31

30

29

28

DR

27

26

25

24

23

22

21

20

19

NOTES:
V5: 5V TO 7V

: 10V TO 14V; V

V

IN

SWITCHING FREQUENCY: 500kHz (V5 = 5V)

: 2.5V/100A

OUT

M1, M4, M7, M10, M13, M16:
SILICONIX Si7390DP OR HAT2168
M2, M3, M5, M6, M8, M9, M11, M12, M14, M15,
M17, M18: SILICONIX Si7356DP OR HAT2165
D1 TO D6: B320A

L1 TO L6: TOKO FDH1040: 0.56µH

: 10µF/16V CERAMIC × 10 + 270µF/16V SANYO Os-Con

C

IN

: 100µF/6.3V/X5R × 10 + 330µF/4V × 8

C

OUT

3731H F15

3731hfa

29

LTC3731H

TYPICAL APPLICATIO S

U

+

IN

+

S1

–

S1

+

S2

–

S2

+

S3

–

S3

RUN/SS

C18
1µF
50V

R10 500Ω

R11 500Ω

R12 500Ω

R13 500Ω

R14 500Ω

R15 500Ω

8

5

V

OUT

RUN/SS

IN

LT3010

SHDN

+

R7
665k

R6

8.06k

C7

0.1µF

3-Phase Boost Converter. VIN = 10V to 18V with 36V Load Dump, V

1

GND

C4
1000pF

C5
1000pF

C6
1000pF

V

OUTV

ADJ

4

IN

+

R30
OPT

0Ω

R16
10k

2

R4

220pF

OPT

C3

OPT

1000pF

C9

R3

R2
1M

R5
249k

C8

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

C19
1µF
10V

R1

10Ω

V

CC

PLLIN

PLLFLTR

FCB

NC

NC

NC

EAIN

SGND

SENSE1

SENSE1

SENSE2

SENSE2

SENSE3

SENSE3

RUN/SS

I

TH

UVADJ

R17

121k

6.5V

C1

1µF

LTC3731H

+

–

+

–

–

+

PGOOD

BOOST1

BOOST2

PGND

BOOST3

PHASMD

SGND

R18

845k

C53
1000pF

CLK

TG1

SW1

TG2

SW2

V

BG1

BG2

BG3

SW3

TG3

L1

D4

36

35

34

33

32

31

30

29

28

DR

27

26

25

24

23

22

21

20

19

C

IN4-CIN6

C16-C26: 1µF, 100V X7R TAIYO YUDEN HMK432BJ105KM
C17: 150µF, 63V SANYO ALUMINUM ELECTROLYTIC 63MV150GX
C20: 33µF, 100V SANYO ALUMINUM ELECTROLYTIC 100CV33FS

+

V

IN

L1-L3: 12µH SUMIDA CDRH127/LD-120

12µH

30BQ060

Q1
Si7852DP

S1

R23

0.007Ω

S1

C1

4.7µF

L3
12µH

30BQ060

Q3

6.5V S3

Si7852DP

R23

0.007Ω

: 10µF, 50V X5R TDK C5750X5R1H106M

= 50V at 3A

OUT

+

OUT

+

V

IN

IN

10V TO 18V

–

WITH 36V

V

IN

LOAD DUMP

+

V

OUT

+

50V/3A

–

V

OUT

3731H TA01

V

+

C17
150µF
63V

+

L2

D4

12µH

+

–

30BQ060

Q2
Si7852DP

R23

0.007Ω

+

S2

S2

C16-C18,
C20-C26

–

1µF
100V

–

D4

S3

C

IN4-CIN6

10µF
50V

V

+

C20
33µF
100V

30

3731hfa

PACKAGE DESCRIPTIO

U

G Package

36-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

1.25 ±0.12

12.50 – 13.10*
(.492 – .516)

LTC3731H

2526 22 21 20 19232427282930313233343536

7.8 – 8.2

0.42 ±0.03 0.65 BSC

RECOMMENDED SOLDER PAD LAYOUT

5.00 – 5.60**
(.197 – .221)

0.09 – 0.25

(.0035 – .010)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE
*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

0.55 – 0.95

(.022 – .037)

MILLIMETERS

(INCHES)

5.3 – 5.7

0° – 8°

12345678 9 10 11 12 14 15 16 17 1813

0.65

(.0256)

BSC

0.22 – 0.38

(.009 – .015)

TYP

7.40 – 8.20

(.291 – .323)

2.0

(.079)

MAX

0.05

(.002)

MIN

G36 SSOP 0204

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3731hfa

31

LTC3731H

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PART NUMBER DESCRIPTION COMMENTS

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TM

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LTC1703 No R

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2-Phase Dual Synchronous Step-Down Mobile Pentium® III Processors, 550kHz,

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LTC1708-PG 2-Phase, Dual Synchronous Controller with Mobile VID 3.5V ≤ VIN ≤ 36V, VID Sets V
LT®1709/ High Efficiency, 2-Phase Synchronous Step-Down 1.3V ≤ V

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OUT

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Current Mode Synchronous Step-Down Up to 97% Efficiency, 4V ≤ VIN ≤ 36V, 0.8V ≤ V

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IN

Up to 20A

LTC1929/ 2-Phase Synchronous Controllers Up to 42A, Uses All Surface Mount Components,
LTC1929-PG No Heat Sinks, 3.5V ≤ V

LTC3711 No R

Controller with Digital 5-Bit Interface 0.925V ≤ V

Current Mode Synchronous Step-Down Up to 97% Efficiency, Ideal for Pentium III Processors,

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LTC3730 IMVP III 3-Phase Synchronous Controller I
LTC3732 VRM 9.0/9.1 3-Phase DC/DC Synchronous Step-Down 1.1V ≤ V

up to 60A, 0.6V ≤ V

OUT

≤ 1.85V, 4.5V ≤ VIN ≤ 32V, SSOP-36

OUT

Controller

LTC3733 AMD Opteron™ CPU, DC/DC Synchronous Step-Down 3-Phase Operation, Up to 60A, 0.8V ≤ V

Controller

LTC3734/LTC3735 Intel Pentium M (Centrino™) CPU, DC/DC Synchronous 25A/40A, 4.5V ≤ VIN ≤ 36V

Step-Down Controller

LTC3778 Optional R

Current Mode Synchronous Step-Down 4V ≤ VIN ≤ 36V, Adjustable Frequency Up to 1.2MHz, TSSOP-20

SENSE

Controller
LTC3832 Low VIN High Power Synchronous Controller V
No R

is a trademark of Linear Technology Corporation.

SENSE

≥ 0.6V, I

OUT

, Power Good Output Signal, Synchronizable,

OUT

Up to 20A, 0.8V ≤ V

OUT

, PGOOD

OUT1

≤ 36V

IN

≤ 2V, 4V ≤ VIN ≤ 36V, I

Up to 36V

IN

≤ 1.75V, Integrated MOSFET Drivers

OUT

≤ 20A, 3V ≤ VIN ≤ 8V

OUT

≤ 36V

IN

OUT

Up to 20A

OUT

≤ 1.55V

OUT

≤ 5V

Up to 36V

IN

OUT

≤ (0.9)(VIN),

32

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

3731hfa

LT 0106 REV A • PRINTED IN USA

© LINEAR TECHNOLOGY CORPORATION 2005