Datasheet LTC3731 Datasheet (LINEAR TECHNOLOGY)

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Page 1

LTC3731

3-Phase, 600kHz,

Synchronous Buck Switching

FEATURES

■

3-Phase Current Mode Controller with Onboard MOSFET Drivers

■

±5% Output Current Matching Optimizes Thermal Performance and Size of Inductors and MOSFETs

■

Differential Amplifier Accurately Senses V

■

±1% V

■

Reduced Power Supply Induced Noise

■

±10% Power Good Output Indicator

■

250kHz to 600kHz Per Phase, PLL, Fixed Frequency

■

PWM, Stage SheddingTM or Burst Mode® Operation

■

OPTI-LOOP® Compensation Minimizes C

■

Adjustable Soft-Start Current Ramping

■

Short-Circuit Shutdown Timer with Defeat Option

■

Overvoltage Soft Latch

■

Adjustable Undervoltage Lockout Threshold

■

Selectable Phase Output for Up to 12-Phase Operation

■

Available in 5mm × 5mm QFN and 36-Pin Narrow

Accuracy Over Temperature

REF

OUT

(0.209") SSOP Packages

APPLICATIO S

■

Desktop Computers and Servers

■

High Performance Notebook Computers

■

High Output Current DC/DC Power Supplies

Regulator Controller

DESCRIPTIO

The LTC®3731 is a PolyPhase® synchronous step-down switching regulator controller that drives all N-channel external power MOSFET stages in a phase-lockable fixed frequency architecture. The 3-phase controller drives its output stages with 120° phase separation at frequencies of up to 600kHz per phase to minimize the RMS current losses in both the input and output filter capacitors. The 3-phase technique effectively triples the fundamental frequency, improving transient response while operating each controller at an optimal frequency for efficiency and ease of thermal design. Light load efficiency is optimized by using a choice of output Stage Shedding or Burst Mode operation.

A differential amplifier provides true remote sensing of both the high and low side of the output voltage at the point of load. The precision reference supports output voltages from

0.6V to 6V. Soft-start and a defeatable, timed short-circuit shutdown

protect the MOSFETs and the load. Current foldback provides protection for the external MOSFETs under short-circuit or overload conditions.

, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode, OPTI-LOOP and PolyPhase are registered trademarks of Linear Technology Corporation. Stage Shedding is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258, 6462525, 6304066, 5705919.

TYPICAL APPLICATIO

4.5V TO 7V

POWER GOOD INDICATOR

OPTIONAL SYNC IN

36k

12k

6.04k

LTC3731

SW1

SENSE1 SENSE1

SW2

PGND

SENSE2 SENSE2

SW3

SENSE3 SENSE3

TG1V

BG1

TG2

BG2

TG3

BG3

0.8µH

0.003Ω

+ –

0.8µH

0.003Ω

+ –

0.8µH

0.003Ω

+ –

0.01µF

BOOST1 BOOST2 BOOST3

PGOOD PLLIN

PLLFLTR

UVADJ

RUN/SS

SGND EAIN

DIFFOUT

–

10µF

0.1µF

SW3 SW2 SW1

7.5k

680pF

100pF

Figure 1. High Current Triple Phase Step-Down Converter

C 470µF 4V

3731 F01

22µF 35V

OUT

1.35V 55A

OUT

5V TO 28V

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LTC3731

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

Topside Driver Voltages (BOOSTN) ............ 38V to –0.3V

Switch Voltage (SW Boosted Driver Voltage (BOOST Peak Output Current <1ms (TG Supply Voltages (V

)...................................32V to –5V

– SWN) .... 7V to –0.3V

, BGN) ..................... 5A

, VDR), PGOOD

Pin Voltage .................................................. 7V to –0.3V

RUN/SS, PLLFLTR, PLLIN, UVADJ,

FCB Voltages ............................................. VCC to –0.3V

SENSE

, SENSE– Voltages ........................ 5.5V to –0.3V

PACKAGE/ORDER I FOR ATIO

TOP VIEW

PLLIN

PLLFLTR

FCB

–

DIFFOUT

EAIN

SGND

SENSE1

–

SENSE1

SENSE2

–

SENSE2

–

SENSE3

RUN/SS

UVADJ

G PACKAGE

36-LEAD PLASTIC SSOP

= 125°C, θJA = 95°C/W, θJC = 32°C/W

JMAX

CLKOUT

PGOOD

BOOST1

TG1

SW1

BOOST2

TG2

SW2

BG1

PGND

BG2

BG3

SW3

TG3

BOOST3

PHASMD

SGND2

ITH Voltage ................................................ 2.4V to –0.3V

Operating Ambient Temperature Range

LTC3731C .................................................... 0°C to 70°C

LTC3731I ................................................. –40°C to 85°C

Junction Temperature (Note 2)............................. 125°C

Storage Temperature Range ..................–65°C to 125°C

Lead Temperature G Package (Soldering, 10sec).. 300°C

Peak Body Temperature UH Package................... 240°C

IN+FCB

PLLFLTR

PLLIN

CLKOUT

BOOST1

TG1

TG3

BOOST3

PHASMD/PG

SW1

SW3

BOOST2

TG2

SW2

BG1

PGND

BG2

BG3

32 31 30 29 28 27 26 25

–

1IN

DIFFOUT

EAIN

SENSE1

–

SENSE1

SENSE2

–

SENSE2

–

SENSE3

9 10 11 12 13 14 15 16

EXPOSED PAD (PIN 33) IS SIGNAL GROUND

(SGND) AND MUST BE SOLDERED TO PCB

JMAX

UVADJ

RUN/SS

SENSE3

UH PACKAGE

32-LEAD PLASTIC QFN

= 125°C, θJA = 34°C/W

ORDER PART NUMBER UH PART MARKING

LTC3731CUH LTC3731IUH

3731 3731I

Order Options

ORDER PART NUMBER

LTC3731CG LTC3731IG

Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. VCC = V

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loop

REGULATED

Regulated Voltage at IN

= 1.2V (Note 3) 0.596 0.600 0.604 V

ITH

LTC3731I

●

0.594 0.600 0.606 V

●

0.591 0.609 V

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LTC3731

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. VCC = V

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SENSEMAX

MATCH

LOADREG

REFLNREG

mOL

FCB

BINHIBIT

Maximum Current Sense Threshold V

Maximum Current Threshold Match Worst-Case Error at V

= 0.5V, V

EAIN

SENSE1–, VSENSE2–, VSENSE3–

Open, 65 75 85 mV

ITH

LTC3731I

SENSEMAX

= 0.6V, 1.8V

●

62 75 88 mV

●

60 90 mV

–5 5 %

Output Voltage Load Regulation (Note 3)

Measured in Servo Loop, ∆I LTC3731I Measured in Servo Loop, ∆I LTC3731I

Voltage = 1.2V to 0.7V

Voltage = 1.2V to 2V

●

0.1 0.5 %

0.1 0.7 % –0.1 –0.5 % –0.1 –0.7 %

Output Voltage Line Regulation VCC = 4.5V to 7V 0.03 %/V

Transconductance Amplifier g

ITH = 1.2V, Sink/Source 25µA (Note 3) LTC3731I

●

4 5 6 mmho 3 5 7 mmho

Transconductance Amplifier GBW ITH = 1.2V (gm • ZL, ZL = Series 1k-100kΩ-1nF) 3 MHz

Forced Continuous Threshold

LTC3731I

FCB Bias Current V

= 0.65V 0.2 0.7 µA

FCB

Burst Inhibit Threshold Measured at FCB Pin VCC – 1.5 V

●

0.58 0.60 0.62 V

●

0.54 0.60 0.66 V

– 0.7 V

– 0.3 V

UVR Undervoltage RUN/SS Reset VCC Lowered Until the RUN/SS Pin is Pulled Low 3.3 3.8 4.5 V

UVADJ Undervoltage Lockout Threshold 1.13 1.18 1.23 V

UVADJ

RUN/SS

RUN/SSARM

Undervoltage Bias Current At UVADJ Threshold 0.2 50 nA

Input DC Supply Current (Note 4) Normal Mode V Shutdown V

Soft-Start Charge Current V

RUN/SS Pin ON Threshold V

RUN/SS Pin Arming Threshold V

= 5V 2.3 3.5 mA

= 0V 50 100 µA

RUN/SS

= 1.9V –0.8 –1.5 – 2.5 µA

RUN/SS

, Ramping Positive 1 1.5 1.9 V

RUN/SS

, Ramping Positive Until Short-Circuit 3.8 4.5 V

RUN/SS

Latch-Off is Armed

RUN/SSLO

SCL

SDLHO

SENSE

RUN/SS Pin Latch-Off Threshold V

RUN/SS Discharge Current Soft-Short Condition V

Shutdown Latch Disable Current V

, Ramping Negative 3.2 V

RUN/SS

= 0.375V, V

EAIN

= 0.375V, V

EAIN

= 4.5V 1.5 5 µA

RUN/SS

= 4.5V –5 – 1.5 µA

RUN/SS

SENSE Pins Source Current SENSE1+, SENSE1–, SENSE2+, SENSE2–, SENSE3

13 20 µA

SENSE3– All Equal 1.2V; Current at Each Pin

MAX

TG tR,t

BG t

R, tF

TG/BG t

Maximum Duty Factor In Dropout, V

Top Gate Rise Time C

Top Gate Fall Time C

Bottom Gate Rise Time C Bottom Gate Fall Time C

Top Gate Off to Bottom Gate On Delay All Controllers, C

SENSEMAX

= 3300pF 30 90 ns

LOAD

= 3300pF 40 90 ns

LOAD

= 3300pF 30 90 ns

LOAD

= 3300pF 20 90 ns

LOAD

≤ 30mV 95 98.5 %

= 3300pF Each Driver 50 ns

LOAD

Synchronous Switch-On Delay Time

BG/TG t

Bottom Gate Off to Top Gate On Delay All Controllers, C

= 3300pF Each Driver 60 ns

LOAD

Top Switch-On Delay Time

ON(MIN)

Minimum On-Time Tested with a Square Wave (Note 5) 110 ns

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LTC3731

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. VCC = V

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Good Output Indication

PGL

PGOOD

PGTHNEG

PGTHPOS

PGDLY

PGOOD Voltage Output Low I

PGOOD Output Leakage V PGOOD/PHASMD Bias I 0 ≤ V

PGOOD Trip Thresholds V V

Ramping Negative HGOOD Goes Low After V

DIFFOUT

Ramping Positive 7 10 13 %

DIFFOUT

Power Good Fault Report Delay After V

= 2mA, G Package 0.1 0.3 V

PGOOD

= 1.6mA, UH Package 0.5 1.0 V

PGOOD

= 5V, G Package 1 µA

PGOOD

PHASMD/PG

DIFFOUT

EAIN

≤ VCC, UH Package –10 ±310 µA

with Respect to Set Output Voltage,

Delay –7 –10 –13 %

UVDLY

is Forced Outside the PGOOD Thresholds 100 150 µs

Oscillator and Phase-Locked Loop

NOM

LOW

HIGH

PLLTH

PLLIN

PLLFLTR

RELPHS

Nominal Frequency V

Lowest Frequency V

Highest Frequency V

= 1.2V 360 400 440 kHz

PLLFLTR

= 0V 190 225 260 kHz

PLLFLTR

= 2.4V 600 680 750 kHz

PLLFLTR

PLLIN Input Threshold Minimum Pulse Width > 100ns 1 V

PLLIN Input Resistance 50 kΩ

Phase Detector Output Current Sinking Capability f Sourcing Capability f

PLLIN PLLIN

< f > f

OSC OSC

20 µA 20 µA

Controller 2-Controller 1 Phase 120 Deg Controller 3-Controller 1 Phase 240 Deg

CLKOUT Controller 1 TG to CLKOUT Phase PHASMD = 0V 30 Deg

PHASMD = 5V 60 Deg

Differential Amplifier

Differential Gain 0.995 1.000 1.005 V/V

Input Offset Voltage Magnitude IN+ = IN

–

= 1.2V, I

= 1mA, 0.5 5 mV

OUT

Input Referred; Gain = 1

CM Common Mode Input Voltage Range 0 V

CMRR Common Mode Rejection Ratio 0V < IN

GBP Gain Bandwidth Product I

Output Current Sourcing 10 40 mA

= 1mA 2 MHz

OUT

= IN

–

< 5V, I

= 1mA, Input Referred 50 70 dB

OUT

SR Slew Rate RL = 2k 5 V/µs

O(MAX)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: T dissipation P

LTC3731CG/LTC3731IG: T LTC3731CG/LTC3731IG: TJ = T LTC3731CUH/LTC3731IUH: T

Note 3: The IC is tested in a feedback loop that includes the differential amplifier loaded with 100µA to ground driving the error amplifier and

Maximum High Output Voltage I

= 1mA V

OUT

– 1.2 V

– 0.8 V

Input Resistance Measured at IN+ Pin 80 kΩ

servoing the resultant voltage to the midrange point for the error amplifier (V

= 1.2V).

ITH

Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information.

is calculated from the ambient temperature TA and power

according to the following formula:

= TA + (PD × 95°C/W)

+ (PD × 32°C/W)

CASE

= TA + (PD × 34°C/W)

Note 5: The minimum on-time condition corresponds to an inductor peakto-peak ripple current of ≥40% of I

(see minimum on-time

MAX

considerations in the Applications Information Section). Note 6: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.

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LTC3731

PI FU CTIO S

BG1 to BG3: High Current Gate Drives for Bottom N-Channel MOSFETs. Voltage swing at these pins is from ground to V

BOOST1 to BOOST3: Positive Supply Pins to the Topside Floating Drivers. Bootstrapped capacitors, charged with external Schottky diodes and a boost voltage source, are connected between the BOOST and SW pins. Voltage swing at the BOOST pins is from boost source voltage (typically V

to this boost source voltage + VIN (where V

CC)

nal MOSFET supply rail).

CLKOUT: Output clock signal available to synchronize other controller ICs for additional MOSFET stages/phases.

DIFFOUT: Output of the Remote Output Voltage Sensing Differential Amplifier.

EAIN: This is the input to the error amplifier that compares the feedback voltage to the internal 0.6V reference voltage.

FCB: Forced Continuous Control Input. The voltage applied to this pin sets the operating mode of the controller. The forced continuous current mode is active when the applied voltage is less than 0.6V. Burst Mode operation will be active when the pin is allowed to float and a Stage Shedding mode will be active if the pin is tied to the V this pin prior to the application of voltage on the V

PGOOD: This open-drain output is pulled low when the output voltage has been outside the PGOOD tolerance window for the V

with internal precision resistors. This provides true remote sensing of both the positive and negative load terminals for precise output voltage control.

ITH: Error Amplifier Output and Switching Regulator Compensation Point. All three current comparator’s thresholds increase with this control voltage.

PGND: Driver Power Ground. This pin connects directly to the sources of the bottom N-channel external MOSFETs and the (–) terminals of C

PHASMD: This pin determines the phase shift between the first controller’s rising TG signal and the rising edge of the CLKOUT signal. Logic 0 yields 30 degrees and Logic 1 yields 60 degrees.

Note: the PHASMD and PGOOD functions are internally tied together in the LTC3731 UH package.

delay of approximately 100µs.

PGDLY

, IN–: Inputs to a precision, unity-gain differential amplifier

pin. (Do not apply voltage directly to

is the exter-

pin.)

PLLIN: Synchronization Input to Phase Detector. This pin is internally terminated to SGND with 50kΩ. The phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the PLLIN signal.

PLLFLTR: The phase-locked loop’s lowpass filter is tied to this pin. Alternatively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator. (Do not apply voltage directly to this pin prior to the application of voltage on the V

RUN/SS: Combination of Soft-Start, Run Control Input and Short-Circuit Detection Timer. A capacitor to ground at this pin sets the ramp time to full current output as well as the time delay prior to an output voltage short-circuit shutdown. A minimum value of 0.01µF is recommended on this pin.

SENSE1+, SENSE2+, SENSE3+, SENSE1–, SENSE2–, SENSE3–:

The Inputs to Each Differential Current Comparator. The I voltage and built-in offsets between SENSE– and SENSE+ pins, in conjunction with R

SGND: Signal Ground. This pin must be routed separately under the IC to the PGND pin and then to the main ground plane. The exposed pad on the LTC3731 UH package is SGND and must be soldered to the PCB.

SW1 to SW3: Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to V the external MOSFET supply rail).

TG1 to TG3: High Current Gate Drives for Top N-channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to the boost voltage source superimposed on the switch node voltage SW.

UVADJ: Input to the Undervoltage Shutdown Comparator. When the applied input voltage is less than 1.2V, this comparator turns off the output MOSFET driver stages and discharges the RUN/SS capacitor.

: Main Supply Pin. This pin supplies the controller

circuit power. In the LTC3731 UH package, it also supplies the high power pulses to drive the external MOSFET gates. This pin needs to be very carefully and closely decoupled to the IC’s PGND pin.

VDR: (LTC3731G Package Only) Supplies power to the bot-tom gate drivers only. This pin needs to be very carefully and closely decoupled to the IC’s PGND pin.

SENSE

pin.)

, set the current trip threshold level.

(where V

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Page 6

LTC3731

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs I

100

= OPEN

FCB

= 5V

FCB

EFFICIENCY (%)

0.1

= 0V

FCB

LOAD CURRENT (A)

Reference Voltage vs Temperature

610

605

600

(Figure 14) Efficiency vs V

OUT

100

EFFICIENCY (%)

VIN = 8V

= 1.5V

OUT

1 10 100

3731 G01

Error Amplifier gm vs Temperature

6.0

5.5

(mmho)

5.0

IL = 45A

(Figure 14) Efficiency vs Frequency (Figure 14)

100

VIN = 5V

VIN = 12V

EFFICIENCY (%)

VIN = 20V

200

Maximum I

300

FREQUENCY (kHz)

SENSE

LOAD

OUT

400

500

Threshold vs

VIN (V)

IL = 15A

= 1.5V

OUT

f = 250kHz

3731 G02

Temperature

VO = 1.75V

THRESHOLD (mV)

SENSE

VO = 0.6V

= 20A

= 1.5V

VIN = 8V

600

3731 G03

595

REFERENCE VOLTAGE (mV)

590

–50

0 255075

–25 125100

TEMPERATURE (°C)

3731 G04

4.5

ERROR AMPLIFIER g

4.0 –50 0 25 50 75–25 125100

TEMPERATURE (°C)

Oscillator Frequency vs Temperature Operating Frequency vs V

700

PLLFLTR

600

500

400

PLLFLTR

300

FREQUENCY (kHz)

200

PLLFLTR

100

= 2.4V

PLLFLTR

= 1.2V

= 0V

TEMPERATURE (°C)

= 5V

3731 G07

700

600

500

400

300

OPERATING FREQUENCY (kHz)

200

0.5 1 1.5 22.5

PLLFLTR PIN VOLTAGE (V)

3731 G05

PLLFLTR

3731 G08

MAXIMUM I

–50 0 25 50 75–25 125100

TEMPERATURE (°C)

Undervoltage Reset Voltage vs Temperature

UNDER VOLTAGE RESET (V)

–50 0 25 50 75–25 125100–50 0 255075–25 125100

TEMPERATURE (°C)

3731 G06

3731 G09

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Page 7

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3731

Short-Circuit Arming and Latchoff vs Temperature Supply Current vs Temperature

ARMING

LATCHOFF

RUN/SS PIN VOLTAGE (V)

TEMPERATURE (°C)

3731 G10

VCC = 5V

2.8

2.4

2.0

1.6

1.2

0.8

SUPPLY CURRENT (mA)

0.4

TEMPERATURE (°C)

Maximum Current Sense

Maximum I

(mV)

SENSE

MAXIMUM I

SENSE

RUN/SS

vs V

RUN/SS

VOLTAGE (V)

3731 G13

Threshold vs Duty Factor

VOLTAGE (mV)

SENSE

20 40 60 80

DUTY FACTOR (%)

3731 G11

3731 G14

100

RUN/SS Pull-Up Current vs Temperature

2.5 V

RUN/SS

SHUTDOWN CURRENT (µA)

2.0

1.5

1.0

0.5

RUN/SS PULLUP CURRENT (µA)

–50 0 255075–25 125100–50 0 255075–25 125100–50 0 255075–25 125100

Peak Current Threshold vs V

VOLTAGE THRESHOLD (mV)

SENSE

–15

= 1.9V

TEMPERATURE (°C)

3731 G12

ITH

0.6 1.2 1.8 2.4 V

(V)

ITH

3731 G15

Percentage of Nominal Output vs Peak I

VOLTAGE (mV)

SENSE

PEAK I

PERCENTAGE OF NOMINAL OUTPUT VOLTAGE (%)

(Foldback)

SENSE

2010 30 50 70 90

Maximum Duty Factor vs Temperature

100

MAXIMUM DUTY FACTOR (%)

100

3731 G16

–50 0 255075–25 125100

TEMPERATURE (°C)

PLLFLTR

= 0V

3731 G17

PIN CURRENT (µA)

–10

SENSE

–20

–30

Pin Current vs V

SENSE

(V)

OUT

3731 G18

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Page 8

LTC3731

TYPICAL PERFOR A CE CHARACTERISTICS

Differential Amplifier Gain-Phase

OUT

AC, 20mV/DIV

SW1

10V/DIV

SW2

10V/DIV

SW3

10V/DIV

–3

–6

GAIN (dB)

–9

–12

–15

Shed Mode at 1 Amp, Light Load Current (Circuit of Figure 14)

0001

0.01 FREQUENCY (MHz)

0.1

3731 G19

OUT

AC, 20mV/DIV

SW1

10V/DIV

SW2

10V/DIV

SW3

10V/DIV

–45

PHASE (DEG)

–90

–135

–180

–225

Burst Mode at 1 Amp, Light Load Current (Circuit of Figure 14)

AC, 20mV/DIV

= 12V

= 1.5V

OUT

= V

FCB

FREQUENCY = 250kHz

4µs/DIV 4µs/DIV

Continuous Mode at 1 Amp, Light Load Current (Circuit of Figure 14)

OUT

SW1

10V/DIV

SW2

10V/DIV

SW3

10V/DIV

VIN = 12V V

= 1.5V

OUT

= 0V

FCB

FREQUENCY = 250kHz

4µs/DIV 20µs/DIV

= 12V

= 1.5V

OUT

= OPEN

FCB

3731 G20

FREQUENCY = 250kHz

3731 G21

Transient Load Current Response: 0 Amp to 50 Amp (Circuit of Figure 14)

OUT

AC, 20mV/DIV

LOAD

20A/DIV

= 12V

= 1.5V

OUT

= V

FCB

3731 G22 3731 G23

FREQUENCY = 250kHz

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Page 9

LTC3731

FU CTIO AL DIAGRA

PGOOD**

PHASMD**

PLLIN

PLLFLTR

CLKOUT

100µs DELAY

FCB

–

DIFFOUT

EAIN

UVADJ

1.2V

PROTECTION

0.6V

0.600V

0.660V

50k

–

PHASE DET

OSCILLATOR

–

CLK1

CLK2 CLK3

–

0.66V

EAIN

–

0.54V

FCB

40k40k

–

40k40k

DUPLICATE FOR SECOND AND THIRD CONTROLLER CHANNELS

DROP

OUT DET

5(VFB)

1.5µA

0.86V

SLOPE

COMP

CLAMP

SRQ

5(VFB)

0.55V

–

SHDN

RST

2.4V

FCB

LATCH

+–

BOT

+–

3mV

SHED

RUN

SOFT-

START

FORCE BOT

FCB

SHDN

–

54k54k

UV RESET

SWITCH

LOGIC

0.600V

INTERNAL

SUPPLY

1.2V

TOP

BOT

(VDR)***

36k

REF

BOOST

PGND

SENSE

SGND*

RUN/SS

SENSE

–

OUT

*THE LTC3731UH USES THE EXPOSED DIE ATTACH PAD FOR THE SGND CONNECTIONS **THE PHASMD AND PGOOD PIN FUNCTIONS ARE TIED TOGETHER IN THE LTC3731 UH PACKAGE ***LTC3731CG/IG ONLY

Figure 2

3731 F02

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Page 10

LTC3731

OPERATIO

(Refer to Functional Diagram)

Main Control Loop

The IC uses a constant frequency, current mode stepdown architecture. During normal operation, each top MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the main current comparator, I current at which I voltage on the I

, resets each RS latch. The peak inductor

resets the RS latch is controlled by the

pin, which is the output of the error

amplifier EA. The EAIN pin receives a portion of output voltage feedback signal via the DIFFOUT pin through the external resistive divider and is compared to the internal reference voltage. When the load current increases, it causes a slight decrease in the EAIN pin voltage the 0.6V reference, which in turn causes the I

relative to

voltage to

increase until each inductor’s average current matches one third of the new load current (assuming all three current sensing resistors are equal). In Burst Mode operation and Stage Shedding mode, after each top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I

, or the beginning of the next cycle.

The top MOSFET drivers are biased from floating bootstrap capacitor C

, which is normally recharged through

an external Schottky diode when the top FET is turned off. When V

decreases to a voltage close to V

, however,

OUT

the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector counts the number of oscillator cycles that the bottom MOSFET remains off and periodically forces a brief on period to allow C

to recharge.

The main control loop is shut down by pulling the RUN/SS pin low. Releasing RUN/SS allows an internal 1.5µA current source to charge soft-start capacitor C C

reaches 1.5V, the main control loop is enabled and the

internally buffered I

voltage is clamped but allowed to

. When

ramp as the voltage on CSS continues to ramp. This “softstart” clamping prevents abrupt current from being drawn from the input power source. When the RUN/SS pin is low, all functions are kept in a controlled state. The RUN/SS pin is pulled low when the supply input voltage is below 4V, when the undervoltage lockout pin (UVADJ) is below 1.2V, or when the IC die temperature rises above 150°C.

Low Current Operation

The FCB pin is a logic input to select between three modes of operation.

A) Burst Mode Operation

When the FCB pin voltage is below 0.6V, the controller performs as a continuous, PWM current mode synchronous switching regulator. The top and bottom MOSFETs are alternately turned on to maintain the output voltage independent of direction of inductor current. When the FCB pin is below V

– 1.5V but greater than 0.6V, the

controller performs as a Burst Mode switching regulator. Burst Mode operation sets a minimum output current level before turning off the top switch and turns off the synchronous MOSFET(s) when the inductor current goes negative. This combination of requirements will, at low current, force the I

pin below a voltage threshold that will

temporarily shut off both output MOSFETs until the output voltage drops slightly. There is a burst comparator having 60mV of hysteresis tied to the ITH pin. This hysteresis results in output signals to the MOSFETs that turn them on for several cycles, followed by a variable “sleep” interval depending upon the load current. The resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block.

B) Stage Shedding Operation

When the FCB pin is tied to the VCC pin, Burst Mode operation is disabled and the forced minimum inductor current requirement is removed. This provides constant frequency, discontinuous current operation over the widest possible output current range. At approximately 10% of maximum designed load current, the second and third output stages are shut off and the phase 1 controller alone is active in discontinuous current mode. This “stage shedding” optimizes efficiency by eliminating the gate charging losses and switching losses of the other two output stages. Additional cycles will be skipped when the output load current drops below 1% of maximum designed load

current in order to maintain the output voltage. This stage shedding operation is not as efficient as Burst Mode operation at very light loads, but does provide lower noise, constant frequency operating mode down to very light load conditions.

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OPERATIO

LTC3731

(Refer to Functional Diagram)

C) Continuous Current Operation

Tying the FCB pin to ground will force continuous current operation. This is the least efficient operating mode, but may be desirable in certain applications. The output can source or sink current in this mode. When sinking current while in forced continuous operation, the controller will cause current to flow back into the input filter capacitor. If large enough, the input capacitor will prevent the input supply from boosting to unacceptably high levels. See C

IN/COUT

section.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be synchronized to an external source using the PLLIN pin. The output of the phase detector at the PLLFLTR pin is also the DC frequency control input of the oscillator, which operates over a 250kHz to 600kHz range corresponding to a voltage input from 0V to 2.4V. When locked, the PLL aligns the turn on of the top MOSFET to the rising edge of the synchronizing signal. When no frequency information is supplied to the PLLIN pin, PLLFLTR goes low, forcing the oscillator to minimum frequency. A DC source can be applied to the PLLFLTR pin to externally set the desired operating frequency. A discharge current of approximately 20µA will be present at the pin with no PLLIN input signal.

Input capacitance ESR requirements and efficiency losses are reduced substantially in a multiphase architecture because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the RMS current squared. A 3-stage, single output voltage implementation can reduce input path power loss by 90%.

Differential Amplifier

This amplifier provides true differential output voltage sensing. Sensing both V tion in high current applications and/or applications having electrical interconnection losses. This sensing also isolates the physical power ground from the physical signal ground preventing the possibility of troublesome “ground loops” on the PC layout and prevents voltage

Selection in the Applications Information

OUT

and V

–

benefits regula-

OUT

errors caused by board-to-board interconnects, particularly helpful in VRM designs.

Power Good

The PGOOD pin is connected to the drain of an internal N-channel MOSFET. The MOSFET is turned on once an internal delay of about 100µs has elapsed and the output voltage has been away from its nominal value by greater than 10%. If the output returns to normal prior to the delay timeout, the timer is reset. There is no delay time for the rising of the PGOOD output once the output voltage is within the ±10% “window.”

Phase Mode

The PHASMD pin determines the phase shift between the rising edge of the TG1 output and the rising edge of the CLKOUT signal. Grounding the pin will result in 30 degrees phase shift and tying the pin to V degrees. These phase shift values enable extension to 6and 12-phase systems. The PGOOD function above and the PHASMD function are tied to a common pin in the UH package.

Undervoltage Shutdown Adjust

The voltage applied to the UVADJ pin is compared to the internal 1.2V reference to have an externally programmable undervoltage shutdown. The RUN/SS pin is internally held low until the voltage applied to the UVADJ pin exceeds the 1.2V threshold.

Short-Circuit Detection

The RUN/SS capacitor is used initially to turn on and limit the inrush current from the input power source. Once the controllers have been given time, as determined by the capacitor on the RUN/SS pin, to charge up the output capacitors and provide full load current, the RUN/SS capacitor is then used as a short-circuit timeout circuit. If the output voltage falls to less than 70% of its nominal output voltage, the RUN/SS capacitor begins discharging, assuming that the output is in a severe overcurrent and/or short-circuit condition. If the condition lasts for a long enough period, as determined by the size of the RUN/SS capacitor, the controller will be shut down until

will result in 60

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LTC3731

OPERATIO

(Refer to Functional Diagram)

the RUN/SS pin voltage is recycled. This built-in latchoff can be overridden by providing >5µA at a compliance of

3.8V to the RUN/SS pin. This additional current shortens the soft-start period but prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. Foldback current limit can be overridden by clamping the EAIN pin such that the voltage is held above the (70%)(0.6V) or 0.42V level even when the actual output voltage is low. Up to 100µA of input current can safely be accommodated by the RUN/SS pin.

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APPLICATIO S I FOR ATIO

The basic application circuit is shown in Figure 1 on the first page of this data sheet. External component selection is driven by the load requirement, and normally begins with the selection of an inductance value based upon the desired operating frequency, inductor current and output voltage ripple requirements. Once the inductors and operating frequency have been chosen, the current sensing resistors can be calculated. Next, the power MOSFETs and Schottky diodes are selected. Finally, C are selected according to the voltage ripple requirements. The circuit shown in Figure 1 can be configured for operation up to a MOSFET supply voltage of 28V (limited by the external MOSFETs and possibly the minimum on-time).

and C

OUT

Input Undervoltage Reset

The RUN/SS capacitor will be reset if the input voltage (V

) is allowed to fall below approximately 4V. The

capacitor on the RUN/SS pin will be discharged until the short-circuit arming latch is disarmed. The RUN/SS capacitor will attempt to cycle through a normal soft-start ramp up after the V

supply rises above 4V. This circuit

prevents power supply latchoff in the event of input power switching break-before-make situations. The PGOOD pin is held low during start-up until the RUN/SS capacitor rises above the short-circuit latchoff arming threshold of approximately 3.8V.

700

600

500

400

300

OPERATING FREQUENCY (kHz)

200

0.5 1 1.5 2 2.5 PLLFLTR PIN VOLTAGE (V)

3731 F03

Figure 3. Operating Frequency vs V

PLLFLTR

Operating Frequency

The IC uses a constant frequency, phase-lockable architecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the PLLFLTR pin. Refer to the Phase-Locked Loop and Frequency Synchronization section for additional information.

A graph for the voltage applied to the PLLFLTR pin versus frequency is given in Figure 3. As the operating frequency is increased the gate charge losses will be higher, reducing

efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 680kHz.

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge and transition losses. In addition to this basic tradeoff, the effect of inductor value on ripple

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APPLICATIO S I FOR ATIO

current and low current operation must also be considered. The PolyPhase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency.

The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL per individual section, N, decreases with higher inductance or frequency and increases with higher V

⎛

OUT OUT

∆I

= −

⎜ ⎝

or V

⎞

⎟ ⎠

OUT

1.0

0.9

0.8

0.7

0.6

/fL

0.5

O(P-P)

∆I

0.4

0.3

0.2

0.1

0.1 0.2 0.3 0.4 DUTY FACTOR (V

0.5 0.6 0.7 0.8 0.9

OUT/VIN

LTC3731

1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 12-PHASE

)

3731 F04

where f is the individual output stage operating frequency.

In a PolyPhase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to the ripple cancellation. The details on how to calculate the net output ripple current can be found in Application Note 77.

Figure 4 shows the net ripple current seen by the output capacitors for the different phase configurations. The output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. The output ripple current is normalized against the inductor ripple current at zero duty factor. The graph can be used in place of tedious calculations. As shown in Figure 4, the zero output ripple current is obtained when:

OUT

where k N

==12 1, ,..., –

So the number of phases used can be selected to minimize the output ripple current and therefore the output ripple voltage at the given input and output voltages. In applications having a highly varying input voltage, additional phases will produce the best results.

Accepting larger values of ∆I

allows the use of low

inductances but can result in higher output voltage ripple. A reasonable starting point for setting ripple current is ∆I

= 0.4(I

is the total load current. Remember, the maximum

OUT

occurs at the maximum input voltage. The individual

∆I

)/N, where N is the number of channels and

OUT

inductor ripple currents are constant, determined by the input and output voltages and the inductance.

Figure 4. Normalized Peak Output Current vs Duty Factor [I

RMS

= 0.3(I

O(P-P)

]

Inductor Core Selection

Once the value for L1 to L3 is determined, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of ferrite, molypermalloy or Kool Mµ

cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase.

Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when you can use several layers of wire. Because they lack a bobbin, mounting is more difficult. However, designs for surface mount are available which do not increase the height significantly.

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LTC3731

Main Switch Duty Cycle

Synchronous Switch Duty Cycle

OUT

IN OUT

⎛ ⎝

⎜

⎞ ⎠

⎟

–

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APPLICATIO S I FOR ATIO

Power MOSFET and D1, D2, D3 Selection

At least two external power MOSFETs must be selected for each of the three output sections: One N-channel MOSFET for the top (main) switch and one or more N-channel MOSFET(s) for the bottom (synchronous) switch. The number, type and “on” resistance of all MOSFETs selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the MOSFET will be used. A much smaller and much lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output voltage that is less than 1/3 of the input voltage. In applications where V

>> V

OUT

, the top MOSFETs’ “on” resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide reasonably low “on” resistance with significantly reduced input capacitance for the main switch application in switching regulators.

The peak-to-peak MOSFET gate drive levels are set by the voltage, V

, requiring the use of logic-level threshold

MOSFETs in most applications. Pay close attention to the

specification for the MOSFETs as well; many of the

DSS

logic-level MOSFETs are limited to 30V or less.

stage and then plotting the gate voltage versus time. The initial slope is the effect of the gate-to-source and the gateto-drain capacitance. The flat portion of the curve is the result of the Miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. The upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-tosource capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given VDS drain voltage, but can be adjusted for different V ratio of the application V values. A way to estimate the C

voltages by multiplying by the

to the curve specified V

term is to take the

MILLER

change in gate charge from points a and b on a manufacturers data sheet and divide by the stated V specified. C

is the most important selection criteria

MILLER

voltage

for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. C

RSS

and COS are specified sometimes but definitions of these parameters are not included.

When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by:

Selection criteria for the power MOSFETs include the “on” resistance R

, input capacitance, input voltage and

DS(ON)

maximum output current.

MOSFET input capacitance is a combination of several components but can be taken from the typical “gate charge” curve included on most data sheets (Figure 5). The curve is generated by forcing a constant input current into the gate of a common source, current source loaded

MILLER EFFECT

MILLER

= (QB – QA)/V

Figure 5. Gate Charge Characteristic

The power dissipation for the main and synchronous MOSFETs at maximum output current are given by:

⎛

MAIN

OUTINMAX

⎜ ⎝

MAX

⎡

–

3731 F05

SYNC

⎢

VV V

–

CC TH IL TH IL

⎣

–

VVVI

IN OUTINMAX

⎞ ⎟

⎠

()( )

DR MILLER

() ()

⎛ ⎜

⎝

()

DS ON

()

•

⎤

()

⎥ ⎦

⎞

()

⎟ ⎠

1δδ

DS ON

()

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LTC3731

where N is the number of output stages, δ is the temperature dependency of R resistance (approximately 2Ω at V drain potential

and

the change in drain potential in the

particular application. V

, RDR is the effective top driver

DS(ON)

= V

MILLER

is the data sheet specified

TH(IL)

), VIN is the

typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current. C

MILLER

is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above.

Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For V

< 12V, the

high current efficiency generally improves with larger MOSFETs, while for V

> 12V, the transition losses

rapidly increase to the point that the use of a higher R

DS(ON)

device with lower C

actually provides higher

MILLER

efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period.

The term (1 + δ ) is generally given for a MOSFET in the form of a normalized R

vs temperature curve, but

DS(ON)

δ = 0.005/°C can be used as an approximation for low voltage MOSFETs.

The Schottky diodes (D1 to D3 in Figure 1) conduct during the dead time between the conduction of the two large power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead time and requiring a reverse recovery period which could cost as much as several percent in efficiency. A 2A to 8A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition loss due to their larger junction capacitance.

and C

Selection

OUT

In continuous mode, the source current of each top N-channel MOSFET is a square wave of duty cycle V

OUT/VIN

. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a close form equation

can be found in Application Note 77. Figure 6 shows the input capacitor ripple current for different phase configurations with the output voltage fixed and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple current can be achieved when the product of phase number and output voltage, N(V input voltage V

OUT

==12 1, ,..., –

or:

where k N

), is approximately equal to the

OUT

So the phase number can be chosen to minimize the input capacitor size for the given input and output voltages.

In the graph of Figure 4, the local maximum input RMS capacitor currents are reached when:

OUT

where k N

12–, ,...,

These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet

0.6

0.5

0.4

0.3

0.2

DC LOAD CURRENT

RMS INPUT RIPPLE CURRENT

0.1

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Figure 6. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Output Stages

DUTY FACTOR (V

1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 12-PHASE

OUT/VIN

0.9

)

3731 F06

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APPLICATIO S I FOR ATIO

size or height requirements in the design. Always consult the capacitor manufacturer if there is any question.

The Figure 6 graph shows that the peak RMS input current is reduced linearly, inversely proportional to the number N of stages used. It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 3-stage implementation results in 90% less power loss when compared to a single phase design. Battery/input protection fuse resistance (if used), PC board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a PolyPhase system. The required amount of input capacitance is further reduced by the factor, N, due to the effective increase in the frequency of the current pulses.

Ceramic capacitors are becoming very popular for small designs but several cautions should be observed. “X7R”, “X5R” and “Y5V” are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions applied. Physically, if the capacitance value changes due to applied voltage change, there is a concommitant piezo effect which results in radiating sound! A load that draws varying current at an audible rate may cause an attendant varying input voltage on a ceramic capacitor, resulting in an audible signal. A secondary issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. The voltage can increase at a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! Nevertheless, ceramic capacitors, when properly selected and used, can provide the lowest overall loss due to their extremely low ESR.

The selection of C

is driven by the required effective

OUT

series resistance (ESR). Typically once the ESR requirement is satisfied the capacitance is adequate for filtering. The steady-state output ripple (∆V

∆∆V I ESR

≈ +

OUT RIPPLE

⎛ ⎜

⎝

) is determined by:

OUT

⎞

⎟

OUT

⎠

NfC

where f = operating frequency of each stage, N is the number of output stages, C

= ripple current in each inductor. The output ripple is

∆I

highest at maximum input voltage since ∆I

= output capacitance and

OUT

increases

with input voltage. The output ripple will be less than 50mV at max V

OUT

with ∆IL = 0.4I

required ESR < N • R

OUT(MAX)

assuming:

SENSE

and

OUT

> 1/(8Nf)(R

SENSE

)

The emergence of very low ESR capacitors in small, surface mount packages makes very small physical implementations possible. The ability to externally compensate the switching regulator loop using the I

pin allows a

much wider selection of output capacitor types. The impedance characteristics of each capacitor type is significantly different than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design.

Manufacturers such as Nichicon, Nippon Chemi-Con and Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo and the Panasonic SP surface mount types have a good (ESR)(size) product. Once the ESR requirement for C RMS current rating generally far exceeds the I

has been met, the

OUT

RIPPLE(P-P)

requirement. Ceramic capacitors from AVX, Taiyo Yuden, Murata and Tokin offer high capacitance value and very low ESR, especially applicable for low output voltage applications.

In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV, the KEMET T510 series of sur

face-mount

tantalums or the Panasonic SP series of surface mount

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LTC3731

special polymer capacitors available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo POSCAP, Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult the manufacturers for other specific recommendations.

Selection for Output Current

SENSE

Once the frequency and inductor have been chosen, R

SENSE1, RSENSE2, RSENSE3

are determined based on the required peak inductor current. The current comparator has a typical maximum threshold of 75mV/R input common mode range of SGND to (1.1) • V

SENSE

and an

. The

current comparator threshold sets the peak inductor current, yielding a maximum average output current I

MAX

equal to the peak value less half the peak-to-peak ripple current, ∆I

Allowing a margin for variations in the IC and external component values yields:

SENSE

The IC works well with values of R

MAX

from 0.002Ω

SENSE

to 0.02Ω.

Decoupling

The VCC pin supplies power not only to the internal circuits of the controller but also to the top and bottom gate drivers in the LTC3731 UH package, and therefore must be bypassed very carefully to ground with a ceramic capacitor, type X7R or X5R (depending upon the operating temperature environment) of

next to the IC

and preferably an additional 10µF placed very

at least 1µF imme

diately

close to the IC due to the extremely high instantaneous currents involved. The total capacitance, taking into account the voltage coefficient of ceramic capacitors, should be 100 times as large as the total combined gate charge capacitance of ALL of the MOSFETs being driven. Good bypassing close to the IC is necessary to supply the high transient currents required by the MOSFET gate drivers while keeping the 5V supply quiet enough so as not to disturb the very small-signal high bandwidth of the current comparators.

Topside MOSFET Driver Supply (C

External bootstrap capacitors, C

, DB)

, connected to the

BOOST pins, supply the gate drive voltages for the topside MOSFETs. Capacitor C gram is charged though diode D

in the Functional Dia-

from VCC when the

SW pin is low. When one of the topside MOSFETs turns on, the driver places the C

voltage across the gate-

source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to V

and the BOOST pin

follows. With the topside MOSFET on, the boost voltage is above the input supply (V value of the boost capacitor C

= VCC + VIN). The

BOOST

needs to be 30 to 100

times that of the total gate charge capacitance of the topside MOSFET(s) as specified on the manufacturer’s data sheet. The reverse breakdown of D greater than V

IN(MAX).

must be

Differential Amplifier/Output Voltage Programming

The IC has a true remote voltage sense capability. The sensing connections should be returned from the load, back to the differential amplifier’s inputs through a common, tightly coupled pair of PC traces. The differential amplifier rejects common mode signals capacitively or inductively radiated into the feedback PC traces as well as ground loop disturbances. The differential amplifier output signal is divided down with an external resistive divider and compared with the internal, precision 0.6V voltage reference by the error amplifier.

The differential amplifier has a 0V to V input range and an output swing range of 0V to V

common mode

– 1.2V.

The output uses an NPN emitter follower without any internal pull-down current. A DC resistive load to ground is required in order to sink current.

The output voltage is set by an external resistive divider according to the following formula:

OUT

⎛

06 1

⎜ ⎝

⎞ ⎟

⎠

The resistive divider is connected to the output as shown in Figure 2, allowing remote voltage sensing.

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Soft-Start/Run Function

The RUN/SS pin provides three functions: 1) ON/OFF, 2) soft-start and 3) a defeatable short-circuit latch off timer. Soft-start reduces the input power sources’ surge currents by gradually increasing the controller’s current limit (proportional to an internal buffered and clamped V

ITH

). The latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. A small pull-up current (>5µA) supplied to the RUN/SS pin will prevent the overcurrent latch from operating. A maximum pull-up current of 200µA is allowed into the RUN/SS pin even though the voltage at the pin may exceed the absolute maximum rating for the pin. This is a result of the limited current and the internal protection circuit on the pin. The following explanation describes how this function operates.

An internal 1.5µA current source charges up the C

capacitor. When the voltage on RUN/SS reaches 1.5V, the controller is permitted to start operating. As the voltage on RUN/SS increases from 1.5V to 3.5V, the internal current limit is increased from 20mV/R

SENSE

to 75mV/R

SENSE

. The output current limit ramps up slowly, taking an additional 1s/µF to reach full current. The output current thus ramps up slowly, eliminating the starting surge current required from the input power supply. If RUN/SS has been pulled all the way to ground, there is a delay before starting of approximately:

DELAY SS SS

IRAMP SS SS

315

−

CsFC

. A

=µ

()

CsFC

=µ

()

By pulling the RUN/SS controller pin below 0.4V the IC is put into low current shutdown (I

< 100 µA). The RUN/SS

pin can be driven directly from logic as shown in Figure 7. Diode, D1, in Figure 7 reduces the start delay but allows CSS to ramp up slowly, providing the soft-start function.

RUN/SS PIN

RUN/SS PIN3.3V OR 5V

SHDNSHDN

Figure 7. RUN/SS Pin Interfacing

3731 F07

The RUN/SS pin has an internal 6V zener clamp (see the Functional Diagram).

Fault Conditions: Overcurrent Latchoff

The RUN/SS pins also provide the ability to latch off the controllers when an overcurrent condition is detected. The RUN/SS capacitor is used initially to turn on and limit the inrush current of all three output stages. After the controllers have been started and been given adequate time to charge up the output capacitor and provide full load current, the RUN/SS capacitor is used for a short-circuit timer. If the output voltage falls to less than 70% of its nominal value, the RUN/SS capacitor begins discharging on the assumption that the output is in an overcurrent condition. If the condition lasts for a long enough period, as determined by the size of the RUN/SS capacitor, the discharge current, and the circuit trip point, the controller will be shut down until the RUN/SS pin voltage is recycled. If the overload occurs during start-up, the time can be approximated by:

>> (CSS • 0.6V)/(1.5µA) = 4 • 105 (CSS)

LO1

If the overload occurs after start-up, the voltage on the RUN/SS capacitor will continue charging and will provide additional time before latching off:

>> (CSS • 3V)/(1.5µA) = 2 • 106 (CSS)

LO2

This built-in overcurrent latchoff can be overridden by providing a pull-up resistor to the RUN/SS pin from V

as shown in Figure 7. When VCC is 5V, a 200k resistance will prevent the discharge of the RUN/SS capacitor during an overcurrent condition but also shortens the soft-start period, so a larger RUN/SS capacitor value may be required.

Why should you defeat overcurrent latchoff? During the prototyping stage of a design, there may be a problem with noise pick-up or poor layout causing the protection circuit to latch off the controller. Defeating this feature allows troubleshooting of the circuit and PC layout. The internal foldback current limiting still remains active, thereby protecting the power supply system from failure. A decision can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor.

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The value of the soft-start capacitor CSS may need to be scaled with output current, output capacitance and load current characteristics. The minimum soft-start capacitance is given by:

> (C

OUT

)(V

) (10–4) (R

OUT

SENSE

)

The minimum recommended soft-start capacitor of C

= 0.1µF will be sufficient for most applications.

Current Foldback

In certain applications, it may be desirable to defeat the internal current foldback function. A negative impedance is experienced when powering a switching regulator. That

is, the input current is higher at a lower VIN and

decreases as V

is increased. Current foldback is de-

signed to accommodate a normal, resistive load having increasing current draw with increasing voltage. The EAIN pin should be artificially held 70% above its nominal operating level of 0.6V, or 0.42V in order to prevent the IC from “folding back” the peak current level. A suggested circuit is shown in Figure 8.

The emitter of Q1 will hold up the EAIN pin to a voltage in the absence of V

that will prevent the internal sensing

OUT

circuitry from reducing the peak output current. Removing the function in this manner eliminates the external MOSFET’s protective feature under short-circuit conditions. This technique will also prevent the short-circuit latchoff function from turning off the part during a shortcircuit event and the peak output current will only be limited to N • 75mV/R

SENSE

Undervoltage Reset

In the event that the input power source to the IC (V

) drops below 4V, the RUN/SS capacitor will be discharged to ground. When V

rises above 4V, the RUN/SS capaci-

tor will be allowed to recharge and initiate another softstart turn-on attempt. This may be useful in applications that switch between two supplies that are not diode connected, but note that this cannot make up for the resultant interruption of the regulated output.

Phase-Locked Loop and Frequency Synchronization

The IC has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET of output stage 1’s turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is ±50% around the center frequency f

. A voltage applied to

the PLLFLTR pin of 1.2V corresponds to a frequency of approximately 400kHz. The nominal operating frequency range of the IC is 225kHz to 680kHz.

The phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector will not lock the internal oscillator to harmonics of the input frequency. The PLL hold-in range, ∆f equal to the capture range, ∆f

∆fH = ∆fC = ±0.5 f

, is

The output of the phase detector is a complementary pair of current sources charging or discharging the external filter components on the PLLFLTR pin. A simplified block diagram is shown in Figure 9.

CALCULATE FOR

0.42V TO 0.55V

Figure 8. Foldback Current Elimination

LTC3731

EAIN

3731 F08

If the external frequency (f lator frequency, f

, current is sourced continuously,

OSC

) is greater than the oscil-

PLLIN

pulling up the PLLFLTR pin. When the external frequency is less than f

, current is sunk continuously, pulling

OSC

down the PLLFLTR pin. If the external and internal frequencies are the same, but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus, the voltage on the

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APPLICATIO S I FOR ATIO

3731 F09

10k

PLLFLTR

PHASE DETECTOR/

EXTERNAL

PLLIN

OSCILLATOR

OSC

50k

Figure 9. Phase-Locked Loop Block Diagram

OSC

DIGITAL

PHASE/

FREQUENCY

DETECTOR

2.4V

PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point, the phase comparator output is open and the filter capacitor CLP holds the voltage. The IC PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. When using multiple ICs for a phase-locked system, the PLLFLTR pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the master’s frequency. A voltage of 1.7V or below applied to the master oscillator’s PLLFLTR pin is recommended in order to meet this requirement. The resultant operating frequency will be approximately 550kHz for 1.7V.

The loop filter components (C

, RLP) smooth out the

current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically R

=10k and CLP ranges from

0.01µF to 0.1µF.

If the duty cycle falls below what can be accommodated by the minimum on-time, the IC will begin to skip every other cycle, resulting in half-frequency operation. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase.

The minimum on-time for the IC is generally about 110ns. However, as the peak sense voltage decreases the minimum on-time gradually increases. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple.

If an application can operate close to the minimum ontime limit, an inductor must be chosen that is low enough in value to provide sufficient ripple amplitude to meet the minimum on-time requirement.

inductor ripple current for each channel equal to or

the greater than 30% of I

OUT(MAX)

As a general rule, keep

at V

IN(MAX)

Efficiency Considerations

The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage of input power.

Minimum On-Time Considerations

Minimum on-time, t

ON(MIN)

, is the smallest time duration that the IC is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge of the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that:

ON MIN

()

OUT

()

Checking Transient Response

The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, V amount equal to ∆I series resistance of C discharge C

, generating the feedback error signal that

OUT

• ESR, where ESR is the effective

LOAD

OUT

. ∆I

also begins to charge or

LOAD

shifts by an

OUT

forces the regulator to adapt to the current change and return V

to its steady-state value. During this recovery

OUT

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time, V ringing, which would indicate a stability problem. The

availability of the I control loop behavior, but also provides a DC coupled and AC filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly

second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The I ponents shown in the Figure 1 circuit will provide an adequate starting point for most applications.

The I loop compensation. The values can be modified slightly (from 0.2 to 5 times their suggested values) to maximize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 80% of full load current having a rise time of <2µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step, resulting from the step change in output current, may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that C the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance.

can be monitored for excessive overshoot or

OUT

pin not only allows optimization of

external com-

series RC-CC filter sets the dominant pole-zero

is decreased, the zero frequency will be kept

A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with C alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If C than 2% of C so that the load rise time is limited to approximately 1000 • R R

SENSE

the charging current to about 1A.

Automotive Considerations: Plugging into the Cigarette Lighter

As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main battery line in an automobile is the source of a number of nasty potential transients, including load dump, reverse battery and double battery.

Load dump is the result of a loose battery cable. When the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60V which takes several hundred milliseconds to decay. Reverse battery is just what it says, while double battery is a consequence of tow-truck operators finding that a 24V jump start cranks cold engines faster than 12V.

The network shown in Figure 10 is the most straightforward approach to protect a DC/DC converter from the ravages of an automotive battery line. The series diode prevents current from flowing during reverse battery, while the transient suppressor clamps the input voltage during load dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the

, causing a rapid drop in V

OUT

, the switch rise time should be controlled

OUT

• C

SENSE

resistor would require a 500µs rise time, limiting

. Thus a 250µF capacitor and a 2mΩ

LOAD

. No regulator can

OUT

is greater

LOAD

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Page 22

LTC3731

SYNC

−

()( )

Ω

()

20 1 3

15 1 25 0 007 1 84

.. .

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APPLICATIO S I FOR ATIO

V 12V

BAT

Use a commonly available 0.003Ω sense resistor.

Next verify the minimum on-time is not violated. The minimum on-time occurs at maximum V

LTC3731

3731 F10

Figure 10. Automotive Application Protection

converter. Although the IC has a maximum input voltage of 32V on the SW pins, most applications will be limited to 30V by the MOSFET BV

DSS

Design Example

As a design example, assume V V

= 20V(max), V

OUT

= 1.3V, I

= 5V, V

MAX

= 12V(nominal),

= 45A and f = 400kHz. The inductance value is chosen first based upon a 30% ripple current assumption. The highest value of ripple current in each output stage occurs at the maximum input voltage.

()

400 30 15

()()()

−

⎜ ⎝

∆

kHz A

⎛

OUT OUT

⎞

⎟ ⎠

⎛

⎜ ⎝

−

⎞ ⎟

⎠

.13

20 400

()

162

ON MIN

()

VfVV kHz

IN MAX

OUT

()

The output voltage will be set by the resistive divider from the DIFFOUT pin to SGND, R1 and R2 in the Functional Diagram. Set R1 = 13.3k and R2 = 11.3k.

The power dissipation on the topside MOSFET can be estimated. Using a Fairchild FDS6688 for example, R = 7mΩ, C

MILLER

= 15nC/15V = 1000pF. At maximum input

DS(ON)

voltage with T(estimated) = 50°C:

MAIN

≈

15 1 0 005 50 25

()+()

Ω

0 007 20

⎛ ⎜

⎝

518118

()

VV V

–. .

[]

⎛

⎜

()()

⎝

⎞

()

⎟ ⎠

° − °

()

⎞

2 1000

Ω

()( )

⎟ ⎠

400 2 2

kHz W

The worst-case power dissipation by the synchronous MOSFET under normal operating conditions at elevated ambient temperature and estimated 50°C junction temperature rise is:

068

≥

Using L = 0.6µH, a commonly available value results in 34% ripple current. The worst-case output ripple for the three stages operating in parallel will be less than 11% of the peak output current.

SENSE1, RSENSE2

and R

SENSE3

can be calculated by using a conservative maximum sense current threshold of 65mV and taking into account half of the ripple current:

SENSE

⎛

15 1

⎜ ⎝

= Ω

0 0037

⎞ ⎟

⎠

A short-circuit to ground will result in a folded back current of:

≈

()

Ω

with a typical value of R

⎛

150 20

1 2

DS(ON)

ns V

⎜

0675.

⎝

and d = (0.005/°C)(50°C) =

⎞

()

⎟

⎠

0.25. The resulting power dissipated in the bottom MOSFET is:

= (7.5A)2(1.25)(0.007Ω) ≈ 0.5W

SYNC

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LTC3731

which is less than one third of the normal, full load conditions. Incidentally, since the load no longer dissipates any power, total system power is decreased by over 90%. Therefore, the system actually cools significantly during a shorted condition!

SW1

PC Board Layout Checklist

When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 11. Check the following in the PC layout:

SENSE1

BOLD LINES INDICATE HIGH, SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH.

SW2

SW3

SENSE2

SENSE3

OUT

3731 F11

OUT

Figure 11. Branch Current Waveforms

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APPLICATIO S I FOR ATIO

1) Are the signal and power ground paths isolated? Keep the

SGND at one end of a printed circuit path thus preventing MOSFET currents from traveling under the IC. The IC signal ground pin should be used to hook up all control circuitry on one side of the IC, routing the copper through SGND, under the IC covering the “shadow” of the package, connecting to the PGND pin and then continuing on to the (–) plates of C

and C

. The VCC decoupling

OUT

capacitor should be placed immediately adjacent to the IC between the V

pin and PGND. A 1µF ceramic capaci-

tor of the X7R or X5R type is small enough to fit very close to the IC to minimize the ill effects of the large current pulses drawn to drive the bottom MOSFETs. An additional 5µF to 10µF of ceramic, tantalum or other very low ESR capacitance is recommended in order to keep the internal IC supply quiet. The power ground returns to the sources of the bottom N-channel MOSFETs, anodes of the Schottky diodes and (–) plates of C

, which should

have as short lead lengths as possible.

2) Does the IC IN+ pin connect to the (+) plates of C

OUT

A 30pF to 300pF feedforward capacitor between the

and EAIN pins should be placed as close as

possible to the IC.

3) Are the SENSE– and SENSE+ printed circuit traces for

each channel routed together with minimum PC trace spacing? The filter capacitors between SENSE

–

SENSE to the pins of the IC. Connect the SENSE

for each channel should be as close as possible

–

and SENSE

and

pins to the pads of the sense resistor as illustrated in Figure 12.

INDUCTOR

LTC3731

SENSE

Figure 12. Kelvin Sensing R

1000pF

–

OUTPUT CAPACITOR

SENSE RESISTOR

3731 F12b

SENSE

4) Do the (+) plates of C

connect to the drains of the

PWR

topside MOSFETs as closely as possible? This capacitor provides the pulsed current to the MOSFETs.

5) Keep the switching nodes, SWITCH, BOOST and TG away from sensitive small-signal nodes (SENSE

–

SENSE

, IN+, IN–, EAIN). Ideally the SWITCH, BOOST

and TG printed circuit traces should be routed away and separated from the IC and especially the “quiet” side of the IC. Separate the high dv/dt traces from sensitive small-signal nodes with ground traces or ground planes.

6) Use a low impedance source such as a logic gate to drive the PLLIN pin and keep the lead as short as possible.

7) The 47pF to 330pF ceramic capacitor between the I

pin and signal ground should be placed as close as possible to the IC.

Figure 11 illustrates all branch currents in a three-phase switching regulator. It becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. High electric and magnetic fields will radiate from these “loops” just as radio stations transmit signals. The output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives rise to the “noise” generated by a switching regulator. The ground terminations of the synchronous MOSFETs and Schottky diodes should return to the bottom plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. A separate isolated path from the bottom plate(s) of the input and output capacitor(s) should be used to tie in the IC power ground pin (PGND). This technique keeps inherent signals generated by high current pulses taking alternate current paths that have finite impedances during the total period of the switching regulator. External OPTI-LOOP compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure.

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Simplified Visual Explanation of How a 3-Phase Controller Reduces Both Input and Output RMS Ripple Current

The effect of multiphase power supply design significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is divided by, and the effective ripple frequency is multiplied up by the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by, and the effective ripple frequency is increased by the number of phases used. Figure 13 graphically illustrates the principle.

The worst-case input RMS ripple current for a single stage design peaks at twice the value of the output voltage. The worst-case input RMS ripple current for a two stage design results in peaks at 1/4 and 3/4 of the input voltage, and the worst-case input RMS ripple current for a three stage design results in peaks at 1/6, 1/2, and 5/6 of the input voltage. The peaks, however, are at ever decreasing

levels with the addition of more phases. A higher effective duty factor results because the duty factors “add” as long as the currents in each stage are balanced. Refer to AN19 for a detailed description of how to calculate RMS current for the single stage switching regulator.

Figure 6 illustrates the RMS input current drawn from the input capacitance versus the duty cycle as determined by the ratio of input and output voltage. The peak input RMS current level of the single phase system is reduced by 2/3 in a 3-phase solution due to the current splitting between the three stages.

The output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the V

/L discharge currents

OUT

term from the stages that has their bottom MOSFETs on subtract current from the (V

– V

)/L charging current

OUT

resulting from the stage which has its top MOSFET on. The output ripple current for a 3-phase design is:

()( )

OUT

DC V V

13 3–

()

IN OUT

P-P

COUT

SW1

SW2

SW3

CIN

SINGLE PHASE

TRIPLE PHASE

3731 F13

Figure 13. Single and PolyPhase Current Waveforms

3731fb

Page 26

LTC3731

R R C Loss

COMPATH

MAX

L SENSE OUTESR

≈

⎛ ⎝

⎜

⎞ ⎠

⎟

()

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APPLICATIO S I FOR ATIO

The ripple frequency is also increased by three, further reducing the required output capacitance when V

< 3V

OUT

as illustrated in Figure 6.

The addition of more phases, by phase locking additional controllers, always results in no net input or output ripple at V

OUT/VIN

ratios equal to the number of stages implemented. Designing a system with multiple stages close to the V

OUT/VIN

ratio will significantly reduce the ripple voltage at the input and outputs and thereby improve efficiency, physical size and heat generation of the overall switching power supply. Refer to Application Note 77 for more information on PolyPhase circuits.

Efficiency Calculation

To estimate efficiency, the DC loss terms include the input and output capacitor ESR, each MOSFET R tor resistance R

, the sense resistance R

DS(ON)

SENSE

, induc-

and the forward drop of the Schottky rectifier at the operating output current and temperature. Typical values for the design example given previously in this data sheet are:

Main MOSFET R Sync MOSFET R C C R R V V V I

= 20mΩ

INESR

OUTESR

= 2.5mΩ

SENSE

SCHOTTKY

= 1.3V

OUT

= 12V

= 45A

MAX

= 3mΩ

= 0.8V at 15A (0.7V at 90°C)

= 7mΩ (9mΩ at 90°C)

DS(ON)

= 7mΩ (9mΩ at 90°C)

DS(ON)

δ = 0.5%°C (MOSFET temperature coefficient) N = 3 f = 400kHz

The main MOSFET is on for the duty factor V

OUT/VIN

and the synchronous MOSFET is on for the rest of the period or simply (1 – V

OUT/VIN

). Assuming the ripple current is small, the AC loss in the inductor can be made small if a good quality inductor is chosen. The average current, I

is used to simplify the calculations. The equation

OUT,

below is not exact but should provide a good technique for the comparison of selected components and give a result that is within 10% to 20% of the final application.

’

Determining the MOSFETs

die temperature may require iterative calculations if one is not familiar with typical performance. A maximum operating junction temperature of 90° to 100°C for the MOSFETs is recommended for high reliability applications.

Common output path DC loss:

This totals 3.7W + C

OUTESR

loss.

Total of all three main MOSFETs’ DC loss:

⎛

⎞

⎛

OUTINMAX

⎜

⎟

⎝

⎠

⎜ ⎝

MAIN

This totals 0.87W + C

⎞

1 δ

()

⎟ ⎠

loss (at 90°C).

INESR

R C Loss

DS ON INESR

()

Total of all three synchronous MOSFETs’ DC loss:

⎛

SYNC

–

⎜ ⎝

⎞

⎛

OUTINMAX

⎜

⎟

⎝

⎠

⎞ ⎟

⎠

()

DS ON

()

This totals 7.2W at 90°C.

Total of all three main MOSFETs’ AC loss:

≈Ω

MAIN IN

()

()()

()( )

2 1000

⎛ ⎜

⎝

VV V

–. .

518118

⎞

kHz W

().

400 6 3

⎟ ⎠

3731fb

Page 27

PACKAGE DESCRIPTIO

LTC3731

This totals 1W at VIN = 8V, 2.25W at VIN = 12V and 6.25W at V

= 20V.

Total of all three synchronous MOSFETs’ AC gate loss:

() () ()( ) ( )361545Q

This totals 0.08W at V

0.19W at V experience the Miller capacitance dissipation issue that the main switch does because the bottom switch turns on when its drain is close to ground.

The Schottky rectifier loss assuming 50ns nonoverlap time:

2 • 3(0.7V)(15A)(50ns)(4E5)

This totals 1.26W.

fnC

DSSPEC

= 20V. The bottom MOSFET does not

= 8V, 0.12W at VIN = 12V and

DSSPEC

The total output power is (1.3V)(45A) = 58.5W and the total input power is approximately 60W so the % loss of each component is as follows:

Main switch’s AC loss (V

Main switch’s DC loss 0.87W 1.5%

Synchronous switch AC loss 0.19W 0.3%

Synchronous switch DC loss 7.2W 12%

Power path loss 3.7W 6.1%

The numbers above represent the values at V can be seen from this simple example that two things can be done to improve efficiency: 1) Use two MOSFETs on the synchronous side and 2) use a smaller MOSFET for the main switch with smaller C loss with the DC loss. A smaller, less expensive MOSFET can actually perform better in the task of the main switch.

= 12V) 2.25W 3.75%

= 12V. It

to better balance the AC

MILLER

3731fb

Page 28

LTC3731

TYPICAL APPLICATIO

Figure 14. 3-Phase 65A Power Supply

OPTIONAL FILTER FOR

SYNCHRONIZATION

1000pF

0.01µF

10k

100pF

6.04k

0.01µF

330pF

3.3nF

2.2k

VIN: 3.3V TO 20V

: 1.5V AT 65A

OUT

SWITCHING FREQUENCY: 300kHz

9.09k

1000pF

–

1000pF

–

1000pF

SYNC IN

300kHz

300pF

18k

1µF

PLLIN

PLLFLTR

FCB

LTC3731G

–

DIFFOUT

EAIN

SGND

SENSE1

SENSE2

SENSE3

RUN/SS

UVADJ

12k

CIN: SANYO OS-CON 25SP68M

: 270µF/2V ×8 PANASONIC SP EEUE0D271R

OUT

OR 470µF/2.5V ×6 SANYO POSCAP 2R5 TPD470M

D1 TO D3: DIODES INC. B340A

BOOST1

BOOST2

–

BOOST3

PHASMD

10Ω

CLK

PGOOD

TG1

SW1

TG2

SW2

BG1

PGND

BG2

BG3

SW3

TG3

SGND

0.1µF

PGOOD

47k

1Ω

10µF

5V TO 7V

M2 D1

M4 D2

M6 D3

L1 TO L3: 0.8µH SUMIDA CEP125-0R8 M1, M3, M5: IRF7821W ×2, Si7860DP

M2, M4, M6: IRF7832 ×2, Si7892DP × 2

OR HAT2168 ×2

OR HAT2165 ×2

0.002Ω

–

OUT

1.5V AT 65A

10µF

6.3V ×3

10µF 25V ×5

OUT

68µF 25V

3.3V TO 20V

1µF

0.1µF

3731 TA01

3731fb

Page 29

TYPICAL APPLICATIO

LTC3731

Figure 15. 2.5V/100A Power Supply

270pF

1.2k

330pF

2700pF

PGOOD

TG1

SW1

TG2

SW2

BG1

PGND

BG2

BG3

SW3

TG3

SGND2

CLK1

0.1µF

1µF Cer.

0.1µF

8.2k

CLKOUT

3.3k

4.7k

OUTS

–

220pF

15k

DIFFOUT

EAIN

10Ω×6

0.1µF

1000pF

–

1000pF

–

1000pF

RUN/SS

357k

PLLIN

PLLFLTR

FCB

LTC3731G

–

DIFFOUT

EAIN

SGND

SENSE1

SENSE2

SENSE3

RUN/SS

UVADJ

CLKOUT

BOOST1

BOOST2

–

BOOST3

PHASMD

1µF

1Ω

4.7µF

10Ω

PGOOD

10k

X2 M2,3

X2 M5,6

X2 M8,9

BOOST1

BOOST2

BOOST3

0.002Ω

10µF

Cer.

–

121k

10µF

10V

OUT

1000pF

10k

1000pF

100pF

0.01µF

DIFFOUT

–

EAIN

10Ω×6

UVADJ

RUN/SS

100pF

10pF

1000pF

UVADJ

CLK1

OUTS

1000pF

–

PLLIN

PLLFLTR

FCB

LTC3731G

–

DIFFOUT

EAIN

SGND

SENSE4

SENSE5

SENSE6

RUN/SS

UVADJ

–

PHASMD

CLKOUT

PGOOD

BOOST4

TG4

SW4

BOOST5

TG5

SW5

BG4

PGND

BG5

BG6

SW6

TG6

BOOST6

SGND2

CLKOUT

1µF Cer.

PGOOD

0.1µF

10Ω

4.7µF

BOOST4

M10

X2 M11,12

M13

X2 M14,15

BOOST5

BOOST6

0.002Ω

–

0.1µF

M16

X2 M17,18

0.002Ω

–

NOTES: V5: 5V TO 7V

: 10V TO 14V; V

SWITCHING FREQUENCY: 500kHz (V5 = 5V)

: 2.5V/100A

OUT

M1, M4, M7, M10, M13, M16: SILICONIX Si7390DP OR HAT2168 M2, M3, M5, M6, M8, M9, M11, M12, M14, M15, M17, M18: SILICONIX Si7356DP OR HAT2165 D1 TO D6: B320A

L1 TO L6: TOKO FDH1040: 0.56µH

: 10µF/16V CERAMIC × 10 + 270µF/16V SANYO Os-Con

: 100µF/6.3V/X5R × 10 + 330µF/4V × 8

OUT

3731 F15

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Page 30

LTC3731

PACKAGE DESCRIPTIO

G Package

36-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

1.25 ±0.12

12.50 – 13.10* (.492 – .516)

2526 22 21 20 19232427282930313233343536

7.8 – 8.2

0.42 ±0.03 0.65 BSC

RECOMMENDED SOLDER PAD LAYOUT

5.00 – 5.60** (.197 – .221)

0.09 – 0.25

(.0035 – .010)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE *

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

0.55 – 0.95

(.022 – .037)

MILLIMETERS

(INCHES)

5.3 – 5.7

0° – 8°

12345678 9 10 11 12 14 15 16 17 1813

0.65

(.0256)

BSC

0.22 – 0.38

(.009 – .015)

TYP

7.40 – 8.20

(.291 – .323)

2.0

(.079)

MAX

0.05

(.002)

MIN

G36 SSOP 0204

3731fb

Page 31

PACKAGE DESCRIPTIO

5.50 ±0.05

4.10 ±0.05

3.45 ±0.05 (4 SIDES)

RECOMMENDED SOLDER PAD LAYOUT

5.00 ± 0.10 (4 SIDES)

PIN 1 TOP MARK (NOTE 6)

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693)

0.70 ±0.05

PACKAGE OUTLINE

0.25 ± 0.05

0.50 BSC

0.75 ± 0.05

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

R = 0.115

TYP

LTC3731

0.23 TYP

(4 SIDES)

0.40 ± 0.10

3.45 ± 0.10 (4-SIDES)

0.200 REF

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

0.25 ± 0.05

(UH) QFN 0603

0.50 BSC

3731fb

Page 32

LTC3731

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

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≤ 3.5V, Current Mode Ensures

OUT

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Switching Regulator

LTC1736 High Efficiency, Synchronous Controller with 5-Bit Mobile Output Fault Protection, 24-Pin SSOP,

VID Control 3.5V ≤ V

LTC1778 No R

Controller I

Current Mode Synchronous Step-Down Up to 97% Efficiency, 4V ≤ VIN ≤ 36V, 0.8V ≤ V

SENSE

OUT

≤ 36V

Up to 20A

LTC1929/ 2-Phase Synchronous Controllers Up to 42A, Uses All Surface Mount Components, LTC1929-PG No Heat Sinks, 3.5V ≤ V

LTC3711 No R

Controller with Digital 5-Bit Interface 0.925V ≤ V

Current Mode Synchronous Step-Down Up to 97% Efficiency, Ideal for Pentium III Processors,

SENSE

OUT

LTC3729 20A to 200A, 550kHz PolyPhase Synchronous Controller Expandable from 2-Phase to 12-Phase, Uses All Surface Mount

Components, V

LTC3730 IMVP III 3-Phase Synchronous Controller I LTC3732 VRM 9.0/9.1 3-Phase DC/DC Synchronous Step-Down 1.1V ≤ V

Up to 60A, 0.6V ≤ V

OUT

≤ 1.85V, 4.5V ≤ VIN ≤ 32V, SSOP-36

OUT

Controller

LTC3733 AMD Opteron™ CPU, DC/DC Synchronous Step-Down 3-Phase Operation, Up to 60A, 0.8V ≤ V

Controller

LTC3734/LTC3735 Intel Pentium M (Centrino™) CPU, DC/DC Synchronous 25A/40A, 4.5V ≤ VIN ≤ 36V

Step-Down Controller

LTC3778 Optional R

Current Mode Synchronous Step-Down 4V ≤ VIN ≤ 36V, Adjustable Frequency Up to 1.2MHz, TSSOP-20

SENSE

Controller

LTC3832 Low VIN High Power Synchronous Controller V

≥ 0.6V, I

OUT

LTC4008 4A Multichemistry Multicell Battery Charger NiCd, NiMH, Lead Acid, Li-Ion Batteries; 6V ≤ VIN ≤ 28V;

OUT

≤ 28V

No R

is a trademark of Linear Technology Corporation.

SENSE

1.19V ≤ V

, Power Good Output Signal, Synchronizable,

OUT

Up to 20A, 0.8V ≤ V

OUT

, PGOOD

OUT1

≤ 36V

≤ 2V, 4V ≤ VIN ≤ 36V, I

Up to 36V

≤ 1.75V, Integrated MOSFET Drivers

OUT

≤ 20A, 3V ≤ VIN ≤ 8V

OUT

≤ 36V

OUT

Up to 20A

OUT

≤ 1.55V

OUT

≤ 5V

Up to 36V

≤ (0.9)(VIN),

OUT

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

3731fb

LT 0106 REV B • PRINTED IN USA