Datasheet LTC3727, LTC3727-1 Datasheet (LINEAR TECHNOLOGY)

Synchronous Step-Down Switching Regulators

FEATURES

■

Wide Output Voltage Range: 0.8V ≤ V

■

Out-of-Phase Controllers Reduce Required Input

OUT

≤ 14V

Capacitance and Power Supply Induced Noise

■

OPTI-LOOP® Compensation Minimizes C

■

±1% Output Voltage Accuracy

■

Power Good Output Voltage Monitor

■

Phase-Lockable Fixed Frequency 250kHz to 550kHz

■

Latched Short-Circuit Shutdown (LTC3727 Only)

■

Dual N-Channel MOSFET Synchronous Drive

■

Wide VIN Range: 4V to 36V Operation

■

Very Low Dropout Operation: 99% Duty Cycle

■

Adjustable Soft-Start Current Ramping

■

Foldback Output Current Limiting

■

Output Overvoltage Protection

■

Low Shutdown IQ: 20µA

■

Selectable Constant Frequency or Burst Mode

OUT

®

Operation

■

Small 28-Lead SSOP Package

■

LTC3727-1 Also Available in the 5mm × 5mm QFN
Package

U

APPLICATIO S

■

Telecom Systems

■

Automotive Systems

■

Battery-Operated Digital Devices

LTC3727/LTC3727-1

High Efficiency, 2-Phase

U

DESCRIPTIO

®

The LTC
step-down switching regulator controllers that drive all
N-channel synchronous power MOSFET stages. A con­stant frequency current mode architecture allows phase­lockable frequency of up to 550kHz. Power loss and noise
due to the ESR of the input capacitors are minimized by
operating the two controller output stages out of phase.

OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance and
ESR values. There is a precision 0.8V reference and a power
good output indicator. A wide 4V to 30V (36V maximum)
input supply range encompasses all battery chemistries.

A RUN/SS pin for each controller provides soft-start, and
on the LTC3727GN, optional timed, short-circuit shut­down. Current foldback limits MOSFET heat dissipation
during short-circuit conditions when overcurrent latchoff
is disabled. Output overvoltage protection circuitry latches
on the bottom MOSFET until V
FCB mode pin can select among Burst Mode, constant
frequency mode and continuous inductor current mode or
regulate a secondary winding.

, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode
and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents, including
5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258, 6304066, 5705919.

3727/LTC3727-1 are high performance dual

returns to normal. The

OUT

TYPICAL APPLICATIO

8µH

0.015Ω

V

OUT1

5V
5A

+

M1, M2, M3, M4: FDS6680A

47µF
6V
SP

105k

1%

U

+

4.7µF

M1

0.1µF

M2

1000pF

20k
1%

220pF

15k

VINPGOOD INTV

TG1 TG2

BOOST1 BOOST2

SW1 SW2

LTC3727/

BG1 BG2

LTC3727-1

PLLIN

+

SENSE1

–

SENSE1

V

OSENSE1

I

TH1

RUN/SS1 RUN/SS2

SGND

0.1µF

PGND

SENSE2

SENSE2

V

OSENSE2

CC

+

–

I

TH2

0.1µF

Figure 1. High Efficiency Dual 12V/5V Step-Down Converter

0.1µF

1µF
CERAMIC

1000pF

220pF

15k

V

IN

18V TO 28V

22µF
50V
CERAMIC

M3

15µH

M4

0.015Ω

V

OUT2

12V

20k
1%

280k

1%

+

56µF
15V
SP

3727 F01

4A

3727fb

1

LTC3727/LTC3727-1

32 31 30 29 28 27 26 25

9 10 11 12 13

TOP VIEW

33

14 15 16

17

18

19

20

21

22

23

24

8

7

6

5

4

3

2

1V

OSENSE1

PLLFLTR

PLLIN

FCB

I

TH1

SGND

3.3V

OUT

I

TH2

BOOST1

V

IN

BG1

EXTV

CC

INTV

CC

PGND

BG2

BOOST2

NC

SENSE1–SENSE1+NC

RUN/SS1

PGOOD

TG1

SW1

V

OSENSE2

NC

SENSE2

–

SENSE2

+

RUN/SS2

TG2

SW2

NC

UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

Input Supply Voltage (VIN).........................36V to –0.3V

Top Side Driver Voltages

(BOOST1, BOOST2) ...................................42V to –0.3V

Switch Voltage (SW1, SW2) .........................36V to – 5V

INTV

EXTVCC, (BOOST1-SW1),

CC,

(BOOST2-SW2) ........................................ 8.5V to – 0.3V

RUN/SS1, RUN/SS2, PGOOD ..................... 7V to –0.3V

SENSE1+, SENSE2+, SENSE1–,

–

SENSE2

PLLIN, PLLFLTR, FCB Voltages ........... INTV

Voltages .....................................14V to – 0.3V

to –0.3V

CC

UU

W

PACKAGE/ORDER I FOR ATIO

ORDER PART

NUMBER

LTC3727EG
LTC3727EG-1

RUN/SS1

SENSE1

SENSE1

V

OSENSE1

PLLFLTR

PLLIN

FCB

I

TH1

SGND

3.3V

OUT

I

TH2

V

OSENSE2

SENSE2

SENSE2

TOP VIEW

1

+

2

–

3

4

5

6

7

8

9

10

11

12

–

13

+

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PGOOD

TG1

SW1

BOOST1

V

IN

BG1

EXTV

CC

INTV

CC

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

I

TH1, ITH2

, V

OSENSE1

, V

OSENSE2

Voltages ...2.7V to –0.3V
Peak Output Current <10µs (TG1, TG2, BG1, BG2) ... 3A
INTV

Peak Output Current ................................ 50mA

CC

Operating Temperature Range (Note 2) .. – 40°C to 85°C

Junction Temperature (Note 3)............................. 125°C

Storage Temperature Range ................. –65°C to 125°C

Lead Temperature

(Soldering, 10 sec, G Package)............................. 300°C

Solder Reflow Temperature (UH Package) ........... 265°C

ORDER PART

NUMBER

LTC3727EUH-1

UH PART

MARKING

37271

G PACKAGE

28-LEAD PLASTIC SSOP

T

= 125°C, θJA = 95°C/W

JMAX

T

= 125°C, θJA = 34°C/W

JMAX

EXPOSED PAD (PIN 33) IS SGND

(MUST BE SOLDERED TO PCB)

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops

V
I
V

2

ELECTRICAL CHARACTERISTICS

OSENSE1, 2

VOSENSE1, 2

REFLNREG

Regulated Feedback Voltage (Note 4); I
Feedback Current (Note 4) –5 – 50 nA
Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 4) 0.002 0.02 %/V

The ● denotes the specifications which apply over the full operating

= 5V unless otherwise noted.

●

0.792 0.800 0.808 V

Voltage = 1.2V

TH1, 2

RUN/SS1, 2

3727fb

LTC3727/LTC3727-1

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. VIN = 15V, V

A

RUN/SS1, 2

= 5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

LOADREG

g

m1, 2

g

mGBW1, 2

I

Q

V

FCB

I

FCB

V

BINHIBIT

Output Voltage Load Regulation (Note 4)

Transconductance Amplifier g

m

Transconductance Amplifier GBW I

Measured in Servo Loop; ∆I
Measured in Servo Loop; ∆I

I

= 1.2V; Sink/Source 5µA (Note 4) 1.3 mmho

TH1, 2

= 1.2V (Note 4) 3 MHz

TH1, 2

Voltage = 1.2V to 0.7V

TH

Voltage = 1.2V to 2.0V

TH

●

●

0.1 0.5 %
–0.1 –0.5 %

Input DC Supply Current (Note 5)
Normal Mode V
Shutdown V

Forced Continuous Threshold
Forced Continuous Pin Current V

= 15V, EXTVCC Tied to V

IN
RUN/SS1, 2

FCB

= 0V 20 35 µA

= 0.85V – 0.30 – 0.18 –0.05 µA

OUT1

, V

= 8.5V 670 µA

OUT1

●

0.76 0.800 0.84 V

Burst Inhibit (Constant Frequency) Measured at FCB pin 6.8 7.3 V

Threshold
UVLO Undervoltage Lockout VIN Ramping Down

V

OVL

I

SENSE

DF

MAX

I

RUN/SS1, 2

V

RUN/SS1, 2

V

RUN/SS1, 2

I

SCL1, 2

I

SDLHO

V

SENSE(MAX)

Feedback Overvoltage Lockout Measured at V

Sense Pins Total Source Current (Each Channel) V

OSENSE1, 2

SENSE1–, 2–

Maximum Duty Factor In Dropout 98 99.4 %

Soft-Start Charge Current V

ON RUN/SS Pin ON Threshold V
LT RUN/SS Pin Latchoff Arming Threshold V

RUN/SS1, 2

RUN/SS1, VRUN/SS2

RUN/SS1, VRUN/SS2

= 1.9V 0.5 1.2 µA

RUN/SS Discharge Current Soft-Short Condition V

= 4.5V (LTC 3727 Only)

= 0.5V (LTC3727 Only) 1.6 5 µA
= 0.7V,V

Shutdown Latch Disable Current V

Maximum Current Sense Threshold V

V

RUN/SS1, 2

OSENSE1, 2

OSENSE1, 2

= V

SENSE1+, 2+

= 0V – 85 – 60 µA

Rising 1.0 1.5 1.9 V
Rising from 3V (LTC3727 Only) 4.1 4.5 V

OSENSE1, 2

SENSE1–, 2

= 0.5V, 0.5 2 4 µA

–

= 12V

●

●

0.84 0.86 0.88 V

●

105 135 165 mV

3.5 4 V

TG Transition Time: (Note 6)
TG1, 2 t
TG1, 2 t

Rise Time C

r

Fall Time C

f

= 3300pF 50 90 ns

LOAD

= 3300pF 50 90 ns

LOAD

BG Transition Time: (Note 6)
BG1, 2 t
BG1, 2 t

TG/BG t

1D

Rise Time C

r

Fall Time C

f

Top Gate Off to Bottom Gate On Delay C

= 3300pF 40 90 ns

LOAD

= 3300pF 40 80 ns

LOAD

= 3300pF Each Driver 90 ns

LOAD

Synchronous Switch-On Delay Time
BG/TG t

2D

Bottom Gate Off to Top Gate On Delay C

= 3300pF Each Driver 90 ns

LOAD

Top Switch-On Delay Time
t

ON(MIN)

Minimum On-Time Tested with a Square Wave (Note 7) 180 ns

INTVCC Linear Regulator

V

INTVCC

V

INT INTVCC Load Regulation ICC = 0mA to 20mA, V

LDO

V

EXT EXTVCC Voltage Drop ICC = 20mA, V

LDO

V

EXTVCC

V

LDOHYS

Internal VCC Voltage 8.5V < VIN < 30V, V

EXTVCC

EXTVCC Switchover Voltage ICC = 20mA, EXTV

= 6V 7.2 7.5 7.8 V

EXTVCC

= 6V 0.2 1.0 %

EXTVCC

= 8.5V 70 160 mV
Ramping Positive

CC

●

6.9 7.3 V

EXTVCC Hysteresis 0.3 V

Oscillator and Phase-Locked Loop

f

NOM

f

LOW

f

HIGH

Nominal Frequency V

Lowest Frequency V

Highest Frequency V

= 1.2V 350 380 430 kHz

PLLFLTR

= 0V 220 255 290 kHz

PLLFLTR

≥ 2.4V 460 530 580 kHz

PLLFLTR

3727fb

3

LTC3727/LTC3727-1

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. VIN = 15V, V

A

RUN/SS1, 2

= 5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

R

PLLIN

I

PLLFLTR

PLLIN Input Resistance 50 kΩ

Phase Detector Output Current

Sinking Capability f

Sourcing Capability f

PLLIN

PLLIN

< f

> f

OSC

OSC

–15 µA

15 µA

3.3V Linear Regulator

V

3.3OUT

V

3.3IL

V

3.3VL

3.3V Regulator Output Voltage No Load

3.3V Regulator Load Regulation I

= 0mA to 10mA 0.5 2.5 %

3.3

3.3V Regulator Line Regulation 6V < V
6V < V

●

3.25 3.35 3.45 V

< 30V (LTC3727) 0.05 0.2 %

IN

< 30V (LTC3727-1) 0.05 0.3 %

IN

PGOOD Output

V

PGL

I

PGOOD

V

PG

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: The LTC3727E/LTC3727E-1 are guaranteed to meet performance
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.

Note 3: T
dissipation P

LTC3727EG/LTC3727EG-1: T
LTC3727EUH-1: T

PGOOD Voltage Low I
PGOOD Leakage Current V

PGOOD Trip Level, Either Controller V

is calculated from the ambient temperature TA and power

J

according to the following formulas:

D

= TA + (PD • 95 °C/W)

= TA + (PD • 34 °C/W)

J

J

PGOOD

PGOOD

OSENSE

V

OSENSE

V

OSENSE

= 2mA 0.1 0.3 V

= 5V ±1 µA

with Respect to Set Output Voltage

Ramping Negative –6 –7.5 –9.5 %
Ramping Positive 6 7.5 9.5 %

Note 4: The LTC3727/LTC3727-1 are tested in a feedback loop that servos

to a specified voltage and measures the resultant V

V

ITH1, 2

OSENSE1, 2.

Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.

Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥40% of I

(see minimum on-time

MAX

considerations in the Applications Information section).

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Output Current
and Mode (Figure 13)

100

Burst Mode

90

OPERATION

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0.001

0.01

CONSTANT
FREQUENCY
(BURST DISABLE)

0.1

OUTPUT CURRENT (A)

FORCED
CONTINUOUS
MODE

VIN = 15V
V

OUT

1

= 8.5V

10

3727 G01

Efficiency vs Output Current
(Figure 13)

100

90

80

70

EFFICIENCY (%)

60

50

0.001

VIN = 7V

VIN = 10V

= 15V

V

IN

= 20V

V

IN

0.01

0.1

OUTPUT CURRENT (A)

V

OUT

1

4

= 5V

3727 G02

Efficiency vs Input Voltage
(Figure 13)

100

90

80

70

EFFICIENCY (%)

60

50

10

5

15

INPUT VOLTAGE (V)

25

V
I

OUT

OUT

= 5V

= 3A

3727 G03

3727fb

35

UW

V

RUN/SS

(V)

0

50

V

SENSE

(mV)

75

100

125

150

1234

3727 G09

56

V

SENSE(CM)

= 1.6V

INPUT VOLTAGE (V)

0

6.8

INTV

CC

VOLTAGE (V)

6.9

7.1

7.2

7.3

20

7.7

3727 G06

7.0

10

5

25 30

15 35

7.4

7.5

7.6

I

LOAD

= 1mA

TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current vs Input Voltage
and Mode (Figure 13) EXTV

1000

800

600

400

SUPPLY CURRENT (µA)

200

0

0

BOTH
CONTROLLERS ON

SHUTDOWN

10

INPUT VOLTAGE (V)

20

30

3727 G04

160

140

120

100

80

60

VOLTAGE DROP (mV)

CC

40

EXTV

20

0

Voltage Drop

CC

V

= 8.5V

EXTVCC

10 20 40

0

CURRENT (mA)

30

LTC3727/LTC3727-1

Internal 7.5V LDO Line Regulation

50

3727 G05

Maximum Current Sense Threshold
vs Duty Factor

150

125

100

(mV)

75

SENSE

V

50

25

0

0

20 40 60 80

DUTY FACTOR (%)

Current Sense Threshold
vs I

Voltage Load Regulation V

TH

150

125

100

75

(mV)

50

SENSE

V

25

0

–25

–50

0.5 1.0 2.0

0

V

ITH

1.5

(V)

3727 G07

3727 G10

100

2.5

Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)

150

135

120

105

90

(mV)

75

SENSE

60

V

45

30

15

0

20

0

PERCENT OF NOMINAL OUTPUT VOLTAGE (%)

0.0

–0.1

(%)

OUT

–0.2

NORMALIZED V

–0.3

–0.4

1

0

LOAD CURRENT (A)

60

40

3

2

80

3727 G08

FCB = 0V

= 15V

V

IN

FIGURE 1

4

3727 G11

100

Maximum Current Sense Threshold
vs V

ITH

2.5
V

OSENSE

2.0

1.5

(V)

ITH

V

1.0

0.5

0

5

0

(Soft-Start)

RUN/SS

vs V

RUN/SS

= 0.7V

234

1

V

RUN/SS

(V)

56

3727 G12

3727fb

5

LTC3727/LTC3727-1

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Dropout Voltage vs Output Current

SENSE Pins Total Source Current

100

50

0

–50

–100

(µA)

–150

SENSE

–200

I

–250

–300

–350

–400

0

V

5

COMMON MODE VOLTAGE (V)

SENSE

10

15

3727 G13

(Figure 13)

1.4
V

= 5V

OUT

1.2

1.0

0.8

0.6

0.4

DROPOUT VOLTAGE (V)

0.2

0

123 5

0

OUTPUT CURRENT (A)

R

R

SENSE

SENSE

= 0.015Ω

= 0.010Ω

4

3727 G14

RUN/SS Current vs Temperature

1.8

1.6

1.4

1.2

1.0

0.8

0.6

RUN/SS CURRENT (µA)

0.4

0.2

0

–50 –25

0 25 125
TEMPERATURE (°C)

75 10050

3727 G15

Soft-Start Up (Figure 12)

I

*

OUT

5A/DIV

V

OUT

5V/DIV

V

RUN/SS

5V/DIV

= 20V 50ms/DIV

V

IN

V

= 12V

OUT

Input Source/Capacitor
Instantaneous Current (Figure 12)

I

IN

1A/DIV

V

SW1

20V/DIV

V

SW2

20V/DIV

3727 G16

V

OUT

200mV/DIV

I

OUT

2A/DIV

V

OUT

20mV/DIV

I

OUT

0.5A/DIV

Load Step (Figure 12)

*

= 15V 50µs/DIV

V

IN

V

= 12V

OUT

LOAD STEP = 0A TO 3A
Burst Mode OPERATION

Burst Mode Operation (Figure 12)

*

3727 G17

V

OUT

200mV/DIV

I

OUT

2A/DIV

V

OUT

20mV/DIV

I

OUT

0.5A/DIV

Load Step (Figure 12)

*

V

= 15V 50µs/DIV

IN

V

= 12V

OUT

LOAD STEP = 0A TO 3A
CONTINUOUS MODE

Constant Frequency (Burst Inhibit)
Operation (Figure 12)

*

3727 G18

V

= 15V 1µs/DIV

IN

V

= 12V

OUT1

V

= 5V

OUT2

= I

I

OUT1

*I

⇒ INDUCTOR CURRENT

OUT

6

OUT2

= 2A

3727 G19

V

= 15V 50µs/DIV

IN

V

= 12V

OUT

V

= OPEN

FCB

= 20mA

I

OUT

3727 G20

V

= 15V 5µs/DIV

IN

V

= 12V

OUT

V

= 7.5V

FCB

= 20mA

I

OUT

3727 G21

3727fb

UW

TEMPERATURE (°C)

–50

400

500

700

25 75

3727 G24

300

200

–25 0

50 100 125

100

0

600

FREQUENCY (kHz)

V

PLLFLTR

= 5V

V

PLLFLTR

= 1.2V

V

PLLFLTR

= 0V

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3727/LTC3727-1

Current Sense Pin Input Current
vs Temperature

35

V

= 5V

OUT

33

31

29

27

CURRENT SENSE INPUT CURRENT (µA)

25

–50 –25

0

TEMPERATURE (°C)

50

25

Undervoltage Lockout
vs Temperature

3.50

3.45

3.40

3.35

3.30

UNDERVOLTAGE LOCKOUT (V)

3.25

3.20
–50

–25 0

75

100

3727 G22

25 75

TEMPERATURE (°C)

10

8

6

4

SWITCH RESISTANCE (Ω)

CC

2

EXTV

125

50 100 125

0

EXTVCC Switch Resistance
vs Temperature

50

25

–50 –25

3727 G25

0

TEMPERATURE (°C)

Oscillator Frequency
vs Temperature

100

125

3727 G23

75

Shutdown Latch Thresholds
vs Temperature

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

SHUTDOWN LATCH THRESHOLDS (V)

LTC3727 ONLY

0

–50 –25

LATCH ARMING

LATCHOFF

THRESHOLD

0 25 125

TEMPERATURE (°C)

75 10050

3727 G26

PI FU CTIO S

RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13): Combina­tion of Soft-Start, Run Control Inputs and Short-Circuit
Detection Timers (LTC3727 only). A capacitor to ground at
each of these pins sets the ramp time to full output current.
Forcing either of these pins back below 1.0V causes the IC
to shut down the circuitry required for that particular
controller. Latchoff overcurrent protection is also invoked
via this pin as described in the Applications Information
section (LTC3727 only).

U

UU

G Package/UH Package

SENSE1+, SENSE2+ (Pins 2, 14/Pins 30, 12): The (+)

Input to the Differential Current Comparators. The ITH pin
voltage and controlled offsets between the SENSE

+

SENSE

pins in conjunction with R

set the current

SENSE

–

and

trip threshold.

SENSE1

–

, SENSE2– (Pins 3, 13/Pins 31, 11): The (–)

Input to the Differential Current Comparators.

V

OSENSE1

, V

OSENSE2

(Pins 4, 12/Pins 1, 9): Receives the

remotely-sensed feedback voltage for each controller from
an external resistive divider across the output.

3727fb

7

LTC3727/LTC3727-1

U

UU

PI FU CTIO S

PLLFLTR (Pin 5/Pin 2): The phase-locked loop’s lowpass
filter is tied to this pin. Alternatively, this pin can be driven
with an AC or DC voltage source to vary the frequency of
the internal oscillator.

PLLIN (Pin 6/Pin 3): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with 50kΩ. The phase-locked loop will force the rising top
gate signal of controller 1 to be synchronized with the
rising edge of the PLLIN signal.

FCB (Pin 7/Pin 4): Forced Continuous Control Input. This
input acts on both controllers and is normally used to
regulate a secondary winding. Pulling this pin below 0.8V
will force continuous synchronous operation. Do not
leave this pin floating.

I

TH1, ITH2

and Switching Regulator Compensation Points. Each as­sociated channels’ current comparator trip point increases
with this control voltage.

SGND (Pin 9/Pin 6): Small Signal Ground. Common
to both controllers; must be routed separately from
high current grounds to the common (–) terminals
of the C

3.3V

of supplying 10mA DC with peak currents as high as
50mA.

(Pins 8, 11/Pins 5, 8): Error Amplifier Outputs

capacitors.

OUT

(Pin 10/Pin 7): Linear Regulator Output. Capable

OUT

EXTVCC (Pin 22/Pin 21): External Power Input to an

Internal Switch Connected to INTV
and supplies V
out regulator, whenever EXTV
EXTV

connection in Applications section. Do not exceed

CC

power, bypassing the internal low drop-

CC

CC

. This switch closes

CC

is higher than 7.3V. See

8.5V on this pin.

BG1, BG2 (Pins 23, 19/Pins 22, 18): High Current Gate
Drives for Bottom (Synchronous) N-Channel MOSFETs.
Voltage swing at these pins is from ground to INTV

V

(Pin 24/Pin 23): Main Supply Pin. A bypass capacitor

IN

CC

.

should be tied between this pin and the signal ground pin.

BOOST1, BOOST2 (Pins 25, 18/Pins 24, 17): Bootstrapped
Supplies to the Top Side Floating Drivers. Capacitors are
connected between the boost and switch pins and Schot­tky diodes are tied between the boost and INTV
Voltage swing at the boost pins is from INTV

CC

).

INTV

CC

pins.

CC

to (VIN +

SW1, SW2 (Pins 26, 17/Pins 25, 15): Switch Node
Connections to Inductors. Voltage swing at these pins is
from a Schottky diode (external) voltage drop below
ground to V

IN

.

TG1, TG2 (Pins 27, 16/Pins 26, 14): High Current Gate
Drives for Top N-Channel MOSFETs. These are the outputs
of floating drivers with a voltage swing equal to INTV

CC

–

0.5V superimposed on the switch node voltage SW.

PGND (Pin 20/Pin 19): Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs, an­odes of the Schottky rectifiers and the (–) terminal(s) of C

INTV

Low Dropout Regulator and the EXTV

(Pin 21/Pin 20): Output of the Internal 7.5V Linear

CC

Switch. The driver

CC

IN

.

and control circuits are powered from this voltage source.
Must be decoupled to power ground with a minimum of 4.7µF
tantalum or other low ESR capacitor.

8

PGOOD (Pin 28/Pin 27): Open-Drain Logic Output. PGOOD
is pulled to ground when the voltage on either V

OSENSE

pin

is not within ±7.5% of its set point.

Exposed Pad (Pin 33, UH Package): Signal Ground. Must
be soldered to the PCB ground for electrical contact and
optimum thermal performance.

3727fb

LTC3727/LTC3727-1

U

U

W

FU CTIO AL DIAGRA

PLLIN

F

IN

PLLFLTR

R

LP

C

LP

PGOOD

V

SEC

R6

FCB

R5

3.3V

V

IN

V

IN

EXTV

INTV

7.5V

+

SGND

50k

0.18µA

OUT

CC

CC

PHASE DET

OSCILLATOR

1.5V

+

–

7.3V

0.8V

CLK1

CLK2

–

0.86V

+

V

OSENSE1

–

+

0.74V

0.86V

–

+

V

OSENSE2

–

+

0.74V

–

7V

+

–

+

+

–

BINH

FCB

V

REF

7.5V
LDO
REG

INTERNAL

SUPPLY

DUPLICATE FOR SECOND
CONTROLLER CHANNEL

0.86V

4(VFB)

SLOPE

COMP

1.2µA

6V

DROP

OUT
DET

BOT

FCB

25k

+

–

+– –+

4(VFB)

SHDN

RST

B

3mV

TOP ON

SHDN

START

–

+

25k

OV

RUN

SOFT

2.4V

SRQ

Q

0.55V

I1 I2

+

–

SWITCH

EA

LOGIC

–

+

+

–

INTV

BOOST

INTV

CC

50k

50k

CC

TG

SW

BG

PGND

SENSE

SENSE

V

OSENSE

I

TH

RUN/SS

+

–

TOP

BOT

INTV

V

FB

0.80V

0.86V

V

CC

IN

D

B

C

B

D

SEC

R2

R1

C

C

C

C2

C

SS

+

C

1

SENSE

IN

C

OUT

+

V

OUT

+

C

SEC

D

R

R

C

Figure 2

U

OPERATIO

Main Control Loop

The LTC3727/LTC3727-1 use a constant frequency, cur­rent mode step-down architecture with the two controller
channels operating 180 degrees out of phase. During
normal operation, each top MOSFET is turned on when the
clock for that channel sets the RS latch, and turned off
when the main current comparator, I1, resets the RS latch.
The peak inductor current at which I1 resets the RS latch
is controlled by the voltage on the I
output of each error amplifier EA. The V

(Refer to Functional Diagram)

pin, which is the

TH

OSENSE

pin receives

3727 F02

the voltage feedback signal, which is compared to the
internal reference voltage by the EA. When the load current
increases, it causes a slight decrease in V

OSENSE

the 0.8V reference, which in turn causes the I

relative to

voltage to

TH

increase until the average inductor current matches the
new load current. After the top MOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current compara­tor I

, or the beginning of the next cycle.

2

3727fb

9

LTC3727/LTC3727-1

U

OPERATIO

(Refer to Functional Diagram)

The top MOSFET drivers are biased from floating boot­strap capacitor C

, which normally is recharged during

B

each off cycle through an external diode when the top
MOSFET turns off. As V

, the loop may enter dropout and attempt to turn on

V

OUT

decreases to a voltage close to

IN

the top MOSFET continuously. The dropout detector de­tects this and forces the top MOSFET off for about 400ns
every tenth cycle to allow CB to recharge.

The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When

reaches 1.5V, the main control loop is enabled with the

C

SS

I

voltage clamped at approximately 30% of its maximum

TH

value. As C

continues to charge, the I

SS

pin voltage is

TH

gradually released allowing normal, full-current opera­tion. When both RUN/SS1 and RUN/SS2 are low, all
LTC3727/LTC3727-1 controller functions are shut down,
including the 7.5V and 3.3V regulators.

Low Current Operation

The FCB pin is a multifunction pin providing two func­tions: 1) to provide regulation for a secondary winding by
temporarily forcing continuous PWM operation on
both controllers; and 2) to select between

two

modes of

low current operation. When the FCB pin voltage is below

0.8V, the controller forces continuous PWM current
mode operation. In this mode, the top and bottom
MOSFETs are alternately turned on to maintain the output
voltage independent of direction of inductor current.
When the FCB pin is below V

INTVCC

– 2V but greater than

0.8V, the controller enters Burst Mode operation. Burst
Mode operation sets a minimum output current level
before inhibiting the top switch and turns off the synchro­nous MOSFET(s) when the inductor current goes nega­tive. This combination of requirements will, at low cur­rents, force the I

pin below a voltage threshold that will

TH

temporarily inhibit turn-on of both output MOSFETs until
the output voltage drops. There is 60mV of hysteresis in
the burst comparator B tied to the ITH pin. This hysteresis
produces output signals to the MOSFETs that turn them
on for several cycles, followed by a variable “sleep”
interval depending upon the load current. The resultant
output voltage ripple is held to a very small value by

having the hysteretic comparator follow the error ampli­fier gain block.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be
synchronized to an external source via the PLLIN pin. The
output of the phase detector at the PLLFLTR pin is also the
DC frequency control input of the oscillator that operates
over a 250kHz to 550kHz range corresponding to a DC
voltage input from 0V to 2.4V. When locked, the PLL
aligns the turn on of the top MOSFET to the rising edge of
the synchronizing signal. When PLLIN is left open, the
PLLFLTR pin goes low, forcing the oscillator to its mini­mum frequency.

Continuous Current (PWM) Operation

Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, current will be
forced back into the main power supply potentially boost­ing the input supply to dangerous voltage levels—
BEWARE!

INTVCC/EXTVCC Power

Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV
When the EXTV
dropout linear regulator supplies INTV

pin is left open, an internal 7.5V low

CC

power. If EXTV

CC

CC

pin.

CC

is taken above 7.3V, the 7.5V regulator is turned off and an
internal switch is turned on connecting EXTV
This allows the INTV

power to be derived from a high

CC

to INTVCC.

CC

efficiency external source such as the output of the regu­lator itself or a secondary winding, as described in the
Applications Information section.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi­tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned on
until the overvoltage condition is cleared.

10

3727fb

OPERATIO

LTC3727/LTC3727-1

U

(Refer to Functional Diagram)

Power Good (PGOOD) Pin

The PGOOD pin is connected to an open drain of an internal
MOSFET. The MOSFET turns on and pulls the pin low when
either output is not within ± 7.5% of the nominal output
level as determined by the resistive feedback divider.
When both outputs meet the ± 7.5% requirement, the
MOSFET is turned off within 10µs and the pin is allowed to
be pulled up by an external resistor to a source of up to 7V.

Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff (LTC3727 Only)

The RUN/SS capacitors are used initially to limit the inrush
current of each switching regulator. After the controller
has been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SS capacitor is used in a short-circuit time-out
circuit. If the output voltage falls to less than 70% of its
nominal output voltage, the RUN/SS capacitor begins
discharging on the assumption that the output is in an
overcurrent and/or short-circuit condition. If the condi­tion lasts for a long enough period as determined by the
size of the RUN/SS capacitor, the controller will be shut
down until the RUN/SS pin(s) voltage(s) are recycled.
This built-in latchoff can be overridden by providing a
>5µA pull-up at a compliance of 5V to the RUN/SS pin(s).
This current shortens the soft start period but also pre­vents net discharge of the RUN/SS capacitor(s) during an
overcurrent and/or short-circuit condition. Foldback cur­rent limiting is also activated when the output voltage falls
below 70% of its nominal level whether or not the short­circuit latchoff circuit is enabled. Even if a short is present
and the short-circuit latchoff is not enabled, a safe, low
output current is provided due to internal current foldback
and actual power wasted is low due to the efficient nature
of the current mode switching regulator.

PART NUMBER FUNCTION

LTC3727 With Latchoff Function Available

LTC3727-1 Latchoff Always Disabled

THEORY AND BENEFITS OF 2-PHASE OPERATION

The LTC3727 dual high efficiency DC/DC controller brings
the considerable benefits of 2-phase operation to portable
applications. Notebook computers, PDAs, handheld ter­minals and automotive electronics will all benefit from the
lower input filtering requirement, reduced electromag­netic interference (EMI) and increased efficiency associ­ated with 2-phase operation.

Why the need for 2-phase operation? Until recently, con­stant-frequency dual switching regulators operated both
channels in phase (i.e., single-phase operation). This
means that both switches turned on at the same time,
causing current pulses of up to twice the amplitude of
those for one regulator to be drawn from the input capaci­tor and battery. These large amplitude current pulses
increased the total RMS current flowing from the input
capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.

With 2-phase operation, the two channels of the dual­switching regulator are operated 180 degrees out of
phase. This effectively interleaves the current pulses
drawn by the switches, greatly reducing the overlap time
where they add together.

The result is a significant reduc­tion in total RMS input current, which in turn allows less
expen

sive input capacitors to be used, reduces shielding
requirements for EMI and improves real world operating
efficiency.

Figure 3 compares the input waveforms for a representa­tive single-phase dual switching regulator to the new
LTC3727 2-phase dual switching regulator. An actual
measurement of the RMS input current under these con­ditions shows that 2-phase operation dropped the input
current from 2.53A
impressive reduction in itself, remember that the power
losses are proportional to I
power wasted is reduced by a factor of 2.66. The reduced
input ripple voltage also means less power is lost in the

to 1.55A

RMS

. While this is an

RMS

2

, meaning that the actual

RMS

3727fb

11

LTC3727/LTC3727-1

U

OPERATIO

(Refer to Functional Diagram)

I

= 2.53A

IN(MEAS)

(a)

Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for
Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input
Ripple with the LTC3727 2-Phase Regulator Allows Less Expensive Input Capacitors,
Reduces Shielding Requirements for EMI and Improves Efficiency

3727 F03a

RMS

5V SWITCH

20V/DIV

3.3V SWITCH
20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

500mV/DIV

I

IN(MEAS)

= 1.55A

(b)

3727 F03b

RMS

input power path, which could include batteries, switches,
trace/connector resistances and protection circuitry. Im­provements in both conducted and radiated EMI also
directly accrue as a result of the reduced RMS input
current and voltage.

Of course, the improvement afforded by 2-phase opera­tion is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
voltage V

(Duty Cycle = V

IN

OUT/VIN

). Figure 4 shows how
the RMS input current varies for single-phase and 2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.

It can readily be seen that the advantages of 2-phase
operation are not just limited to a narrow operating range,
but in fact extend over a wide region. A good rule of thumb
for most applications is that 2-phase operation will reduce
the input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.

A final question: If 2-phase operation offers such an
advantage over single-phase operation for dual switching
regulators, why hasn’t it been done before? The answer is
that, while simple in concept, it is hard to implement.
Constant-frequency current mode switching regulators

require an oscillator derived “slope compensation” signal
to allow stable operation of each regulator at over 50%
duty cycle. This signal is relatively easy to derive in single­phase dual switching regulators, but required the develop­ment of a new and proprietary technique to allow 2-phase
operation. In addition, isolation between the two channels
becomes more critical with 2-phase operation because
switch transitions in one channel could potentially disrupt
the operation of the other channel.

3.0

SINGLE PHASE

2.5

2.0

1.5

1.0

INPUT RMS CURRENT (A)

0.5
VO1 = 5V/3A

= 3.3V/3A

V

O2

0

0

Figure 4. RMS Input Current Comparison

DUAL CONTROLLER

2-PHASE

DUAL CONTROLLER

10 20 30 40

INPUT VOLTAGE (V)

3727 F04

12

3727fb

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APPLICATIO S I FOR ATIO

LTC3727/LTC3727-1

Figure 1 on the first page is a basic LTC3727

/LTC3727-1
application circuit. External component selection is driven
by the load requirement, and begins with the selection of
R
and D1 are selected. Finally, C

and the inductor value. Next, the power MOSFETs

SENSE

and C

IN

are selected.

OUT

The circuit shown in Figure 1 can be configured for
operation up to an input voltage of 28V (limited by the
external MOSFETs).

R

R

Selection For Output Current

SENSE

is chosen based on the required output current.

SENSE

The LTC3727 current comparator has a maximum thresh­old of 135mV/R

and an input common mode range

SENSE

of SGND to 14V. The current comparator threshold sets
the peak of the inductor current, yielding a maximum
average output current I

equal to the peak value less

MAX

half the peak-to-peak ripple current, ∆IL.

Allowing a margin for variations in the LTC3727 and
external component values yields:

mV

R

SENSE

90

=

I

MAX

When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet stability crite­rion for buck regulators operating at greater than 50%
duty factor. A curve is provided to estimate this reducton
in peak output current level depending upon the operating
duty factor.

Operating Frequency

The LTC3727 uses a constant frequency phase-lockable
architecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current plus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to Phase-Locked Loop
and Frequency Synchronization in the Applications Infor­mation section for additional information.

A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure 5. As the operating frequency

2.5

2.0

1.5

1.0

PLLFLTR PIN VOLTAGE (V)

0.5

0

200 250 300 350 550400 450 500

OPERATING FREQUENCY (kHz)

3727 F05

Figure 5. PLLFLTR Pin Voltage vs Frequency

is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 550kHz.

Inductor Value Calculation

The operating frequency and inductor selection are inter­related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.

The inductor value has a direct effect on ripple current. The
inductor ripple current ∆I
tance or frequency and increases with higher V

∆I

1

()( )

fL

V

=

L OUT

decreases with higher induc-

L

⎛

1

–

⎜
⎝

V

OUT

V

IN

⎞
⎟

⎠

IN

:

Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆I

= 0.3(I

L

). The maximum ∆I

MAX

L

occurs at the maximum input voltage.

3727fb

13

LTC3727/LTC3727-1

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APPLICATIO S I FOR ATIO

The inductor value also has secondary effects. The transi­tion to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by R
inductor values (higher ∆I

) will cause this to occur at

L

SENSE

. Lower

lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.

Inductor Core Selection

Once the inductance value is determined, the type of
inductor must be selected. Actual core loss is independent
of core size for a fixed inductor value, but it is very
dependent on inductance selected. As inductance in­creases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper (I2R) losses will increase.

Ferrite designs have very low core loss and are preferred
at high switching frequencies, so designers can concen­trate on reducing I

2

R loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur­rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!

Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate­rials are small and don’t radiate much energy, but gener­ally cost more than powdered iron core inductors with
similar characteristics. The choice of which style inductor
to use mainly depends on the price vs size requirements
and any radiated field/EMI requirements. New designs for
high current surface mount inductors are available from
numerous manufacturers, including Coiltronics, Vishay,
TDK, Pulse, Panasonic, Wuerth, Coilcraft, Toko and Sumida.

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for each
controller in the LTC3727: One N-channel MOSFET for the
top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTV

CC

voltage. This voltage is typically 7.5V during start-up (see
EXTV

Pin Connection). Consequently, logic-level

CC

threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected

< 5V); then, sub-logic level threshold MOSFETs

(V

IN

(V
BV

< 3V) should be used. Pay close attention to the

GS(TH)

specification for the MOSFETs as well; most of the

DSS

logic level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the “ON”
resistance R

, reverse transfer capacitance C

DS(ON)

RSS

,
input voltage and maximum output current. When the
LTC3727 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:

V

Main SwitchDuty Cycle

Synchronous Switch Duty Cycle

OUT

=

V

IN

VV

–

IN OUT

=

V

IN

The MOSFET power dissipations at maximum output
current are given by:

V

P

MAIN

P

SYNC

OUT

=

V

IN

2

kV I C f

()( )( )()

IN MAX RSS

–

VV

IN OUT

=

V

where δ is the temperature dependency of R

2

IR

()

MAX DS ON

IN

+

1 δ

()

2

IR

()

MAX DS ON

+

1 δ

()

+

()

()

DS(ON)

and k

is a constant inversely related to the gate drive current.

Both MOSFETs have I

2

R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V the
high current efficiency generally improves with larger
MOSFETs, while for V
increase to the point that the use of a higher R
with lower C

actually provides higher efficiency. The

RSS

> 20V the transition losses rapidly

IN

device

DS(ON)

synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a

3727fb

14

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APPLICATIO S I FOR ATIO

LTC3727/LTC3727-1

short-circuit when the synchronous switch is on close to
100% of the period.

The term (1+δ) is generally given for a MOSFET in the form
of a normalized R
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. C
FET characteristics. The constant k = 1.7 can be used to
estimate the contributions of the two terms in the main
switch dissipation equation.

The Schottky diode D1 shown in Figure 2 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead­time and requiring a reverse recovery period that could
cost as much as 3% in efficiency at high VIN. A 1A to 3A
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance. Schottky diodes should
be placed in parallel with the synchronous MOSFETs when
operating in pulse-skip mode or in Burst Mode operation.

vs Temperature curve, but

DS(ON)

is usually specified in the MOS-

RSS

the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current • ESR) not only heats up the capacitor but
wastes power from the battery.

Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as
input capacitors, but each has drawbacks: ceramic voltage
coefficients are very high and may have audible piezoelec­tric effects; tantalums need to be surge-rated; OS-CONs
suffer from higher inductance, larger case size and limited
surface-mount applicability; electrolytics’ higher ESR and
dryout possibility require several to be used. Multiphase
systems allow the lowest amount of capacitance overall.
As little as one 22µF or two to three 10µF ceramic capaci-
tors are an ideal choice in a 20W to 35W power supply due
to their extremely low ESR. Even though the capacitance
at 20V is substantially below their rating at zero-bias, very
low ESR loss makes ceramics an ideal candidate for
highest efficiency battery operated systems. Also con­sider parallel ceramic and high quality electrolytic capaci­tors as an effective means of achieving ESR and bulk
capacitance goals.

C

and C

IN

The selection of C
tecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
the highest (V
formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease
the input RMS ripple current from this maximum value
(see Figure 4). The out-of-phase technique typically re­duces the input capacitor’s RMS ripple current by a factor
of 30% to 70% when compared to a single phase power
supply solution.

The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selec­tion process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 22µF to 47µF is usually sufficient
for a 25W output supply operating at 250kHz. The ESR of

Selection

OUT

OUT

is simplified by the multiphase archi-

IN

)(I

) product needs to be used in the

OUT

In continuous mode, the source current of the top N-chan­nel MOSFET is a square wave of duty cycle V
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current of one channel must
be used. The maximum RMS capacitor current is given by:

VVV

()

[]

C quiredI I

Re

IN RMS MAX

This formula has a maximum at VIN = 2V
I

= I

RMS

monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.

/2. This simple worst case condition is com-

OUT

≅

OUT IN OUT

OUT/VIN

−

V

IN

OUT

. To

/

12

, where

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15

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APPLICATIO S I FOR ATIO

The benefit of the LTC3727 multiphase can be calculated
by using the equation above for the higher power control­ler and then calculating the loss that would have resulted
if both controller channels switch on at the same time. The
total RMS power lost is lower when both controllers are
operating due to the interleaving of current pulses through
the input capacitor’s ESR. This is why the input capacitor’s
requirement calculated above for the worst-case control­ler is adequate for the dual controller design. Remember
that input protection fuse resistance, battery resistance
and PC board trace resistance losses are also reduced due
to the reduced peak currents in a multiphase system.

The
overall benefit of a multiphase design will only be fully
realized when the source impedance of the power supply/
battery is included in the efficiency testing.

The drains of
the two top MOSFETS should be placed within 1cm of each
other and share a common C
and C
resonances at V

The selection of C

may produce undesirable voltage and current

IN

.

IN

is driven by the required effective

OUT

(s). Separating the drains

IN

series resistance (ESR). Typically once the ESR require­ment is satisfied the capacitance is adequate for filtering.
The output ripple (∆V

∆∆V I ESR

OUT L

⎛

≅ +

⎜
⎝

Where f = operating frequency, C
tance, and ∆I

= ripple current in the inductor. The output

L

ripple is highest at maximum input voltage since ∆I
increases with input voltage. With ∆IL = 0.3I
output ripple will typically be less than 50mV at max V

) is determined by:

OUT

⎞

1

⎟

fC

OUT

⎠

OUT

8

= output capaci-

OUT(MAX)

the

IN

L

assuming:

C

Recommended ESR < 2 R

OUT

and C

> 1/(8fR

OUT

SENSE

)

SENSE

The first condition relates to the ripple current into the
ESR of the output capacitance while the second term
guarantees that the output capacitance does not signifi­cantly discharge during the operating frequency period
due to ripple current. The choice of using smaller output
capacitance increases the ripple voltage due to the

discharging term but can be compensated for by using
capacitors of very low ESR to maintain the ripple voltage
at or below 50mV. The I

pin OPTI-LOOP compensation

TH

components can be optimized to provide stable, high
performance transient response regardless of the output
capacitors selected.

Manufacturers such as Nichicon, Nippon Chemi-Con and
Sanyo can be considered for high performance through­hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.

In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages. Spe­cial polymer surface mount capacitors offer very low ESR
but have lower storage capacity per unit volume than other
capacitor types. These capacitors offer a very cost-effec­tive output capacitor solution and are an ideal choice when
combined with a controller having high loop bandwidth.
Tantalum capacitors offer the highest capacitance density
and are often used as output capacitors for switching
regulators having controlled soft-start. Several excellent
surge-tested choices are the AVX TPS, AVX TPS Series III
or the KEMET T510 series of surface mount tantalums,
available in case heights ranging from 1.2mm to 4.1mm.
Aluminum electrolytic capacitors can be used in cost­driven applications providing that consideration is given
to ripple current ratings, temperature and long term reli­ability. A typical application will require several to many
aluminum electrolytic capacitors in parallel. A combina­tion of the above mentioned capacitors will often result in
maximizing performance and minimizing overall cost. Other
capacitor types include Nichicon PL series, NEC Neocap,
Cornell Dubilier ESRE and Sprague 595D series. Consult
manufacturers for other specific recommendations.

16

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APPLICATIO S I FOR ATIO

LTC3727/LTC3727-1

INTVCC Regulator

An internal P-channel low dropout regulator produces

7.5V at the INTV

pin from the VIN supply pin. INTV

CC

CC

powers the drivers and internal circuitry within the
LTC3727. The INTV

pin regulator can supply a peak

CC

current of 50mA and must be bypassed to ground with a
minimum of 4.7µF tantalum, 10µF special polymer, or low
ESR type electrolytic capacitor. A 1µF ceramic capacitor
placed directly adjacent to the INTV

and PGND IC pins

CC

is highly recommended. Good bypassing is necessary to
supply the high transient currents required by the MOSFET
gate drivers and to prevent interaction between channels.

Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi­mum junction temperature rating for the LTC3727 to be
exceeded. The system supply current is normally domi­nated by the gate charge current. Additional external
loading of the INTV

and 3.3V linear regulators also

CC

needs to be taken into account for the power dissipation
calculations. The total INTV
either the 7.5V internal linear regulator or by the EXTV

current can be supplied by

CC

CC

input pin. When the voltage applied to the EXTVCC pin is
less than 7.3V, all of the INTV

current is supplied by the

CC

internal 7.5V linear regulator. Power dissipation for the IC
in this case is highest: (V

IN

)(I

), and overall efficiency

INTVCC

is lowered. The gate charge current is dependent on
operating frequency as discussed in the Efficiency Consid­erations section. The junction temperature can be esti­mated by using the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC3727 V

IN

current is limited to less than 24mA from a 24V supply
when not using the EXTV

= 70°C + (24mA)(24V)(95°C/W) = 125°C

T

J

pin as follows:

CC

Use of the EXTVCC input pin reduces the junction tempera­ture to:

T

= 70°C + (24mA)(7.5V)(95°C/W) = 87°C

J

Dissipation should be calculated to also include any added
current drawn from the internal 3.3V linear regulator. To
prevent maximum junction temperature from being ex­ceeded, the input supply current must be checked operat­ing in continuous mode at maximum V

IN

.

EXTV

Connection

CC

The LTC3727 contains an internal P-channel MOSFET
switch connected between the EXTV
When the voltage applied to EXTV

and INTVCC pins.

CC

rises above 7.3V, the

CC

internal regulator is turned off and the switch closes,
connecting the EXTV

pin to the INTV

CC

pin thereby

CC

supplying internal power. The switch remains closed as
long as the voltage applied to EXTV

remains above 7.0V.

CC

This allows the MOSFET driver and control power to be
derived from the output during normal operation (7.2V <
V

< 8.5V) and from the internal regulator when the

OUT

output is out of regulation (start-up, short-circuit). If more
current is required through the EXTV

switch than is

CC

specified, an external Schottky diode can be added be­tween the EXTV
than 8.5V to the EXTV

and INTVCC pins. Do not apply greater

CC

pin and ensure that EXTVCC<VIN.

CC

Significant efficiency gains can be realized by powering
INTV

from the output, since the VIN current resulting

CC

from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 7.5V regulators this
supply means connecting the EXTVCC pin directly to V

OUT

.
However, for 3.3V and other lower voltage regulators,
additional circuitry is required to derive INTV

power

CC

from the output.

The following list summarizes the four possible connec­tions for EXTV

1. EXTVCC Left Open (or Grounded). This will cause INTV

CC:

CC

to be powered from the internal 7.5V regulator resulting in
an efficiency penalty of up to 10% at high input voltages.

2. EXTV

Connected directly to V

CC

. This is the normal

OUT

connection for a 7.5V regulator and provides the highest
efficiency.

3. EXTVCC Connected to an External supply. If an external
supply is available in the 7.5V to 8.5V range, it may be used
to power EXTV

providing it is compatible with the

CC

MOSFET gate drive requirements.

4. EXTV

Connected to an Output-Derived Boost Net-

CC

work. For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater

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17

LTC3727/LTC3727-1

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APPLICATIO S I FOR ATIO

V

N-CH

N-CH

IN

+

C

IN

V

SEC

+

1µF

R

1:N

SENSE

T1

V

OUT

+

C

OUT

3727 F06

OPTIONAL EXTV
CONNECTION

7.5V < V

EXTV

R6

FCB

R5

SGND

Figure 6. Secondary Output Loop & EXTVCC Connection

SEC

LTC3727

CC

< 8.5V

PGND

CC

V

TG1

SW

BG1

IN

than 7.5V. This can be done with the inductive boost
winding as shown in Figure 6.

Topside MOSFET Driver Supply (C

External bootstrap capacitors C

, DB)

B

connected to the BOOST

B

pins supply the gate drive voltages for the topside MOSFETs.
Capacitor C
external diode D

in the functional diagram is charged though

B

from INTVCC when the SW pin is low.

B

When one of the topside MOSFETs is to be turned on, the
driver places the C

voltage across the gate-source of the

B

desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: V
V

IN

+ V

. The value of the boost capacitor CB needs

INTVCC

BOOST

=

to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the exter­nal Schottky diode must be greater than V

IN(MAX)

. When
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and the
input current decreases, then the efficiency has improved.
If there is no change in input current, then there is no
change in efficiency.

Output Voltage

The LTC3727 output voltages are each set by an external
feedback resistive divider carefully placed across the
output capacitor. The resultant feedback signal is
compared with the internal precision 0.800V voltage
reference by the error amplifier. The output voltage is
given by the equation:

R

2

VV

=+

OUT

⎛

08 1

.

⎜
⎝

⎞
⎟

⎠

R

1

where R1 and R2 are defined in Figure 2.

SENSE

+

/SENSE– Pins

The common mode input range of the current comparator
sense pins is from 0V to 14V. Continuous linear operation
is guaranteed throughout this range allowing output volt­age setting from 0.8V to 14V. A differential NPN input
stage is biased with internal resistors from an internal

2.4V source as shown in the Functional Diagram. This
requires that current either be sourced or sunk from the
SENSE pins depending on the output voltage. If the output
voltage is below 2.4V current will flow out of both SENSE
pins to the main output. The output can be easily preloaded
by the V

resistive divider to compensate for the current

OUT

comparator’s negative input bias current. The maximum
current flowing out of each pair of SENSE pins is:

I

SENSE

Since V

+

+ I

OSENSE

–

SENSE

= (2.4V – V

OUT

)/24k

is servoed to the 0.8V reference voltage, we
can choose R1 in Figure 2 to have a maximum value to
absorb this current.

⎛

.

⎜
⎝

.–

24

08

VV

Rk

124

for V

=

MAX

()

< 2.4V

OUT

V

OUT

⎞
⎟

⎠

18

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APPLICATIO S I FOR ATIO

LTC3727/LTC3727-1

Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32K. Note that for an output voltage above

2.4V, R1 has no maximum value necessary to absorb the
sense currents; however, R1 is still bounded by the
V

OSENSE

feedback current.

Soft-Start/Run Function

The RUN/SS1 and RUN/SS2 pins are multipurpose pins
that provide a soft-start function and a means to shut
down the LTC3727. Soft-start reduces the input power
source’s surge currents by gradually increasing the
controller’s current limit (proportional to V

). This pin

ITH

can also be used for power supply sequencing.

An internal 1.2µA current source charges up the C

SS

capacitor. When the voltage on RUN/SS1 (RUN/SS2)
reaches 1.5V, the particular controller is permitted to start
operating. As the voltage on RUN/SS increases from 1.5V
to 3.0V, the internal current limit is increased from 45mV/
R

to 135mV/R

SENSE

. The output current limit ramps

SENSE

up slowly, taking an additional 1.25s/µF to reach full
current. The output current thus ramps up slowly, reduc­ing the starting surge current required from the input
power supply. If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:

V

3.3V OR 5V RUN/SS

*OPTIONAL TO DEFEAT OVERCURRENT
LATCHOFF (NOT NEEDED WITH THE LTC3727-1)

The RUN/SS capacitor, C

IN

RSS*

D1

(7a) (7b)

Figure 7. RUN/SS Pin Interfacing

SS

C

SS

, is used initially to turn on and

INTV

CC

RSS*

RUN/SS

C

SS

3727 F07

limit the inrush current. After the controller has been
started and been given adequate time to charge up the
output capacitor and provide full load current, the RUN/SS
capacitor is used for a short-circuit timer. If the regulator’s
output voltage falls to less than 70% of its nominal value
after C

reaches 4.1V, CSS begins discharging on the

SS

assumption that the output is in an overcurrent condition.
If the condition lasts for a long enough period as deter­mined by the size of the CSS and the specified discharge
current, the controller will be shut down until the RUN/SS
pin voltage is recycled. If the overload occurs during start­up, the time can be approximated by:

t

≅ [CSS(4.1 – 1.5 + 4.1 – 3.5)]/(1.2µA)

LO1

15

.

t

DELAY SS SS

t

IRAMP SS SS

V

=

12

315

=

CsFC

.

A

µ

.

VV

−

12

.

A

µ

125

./

=µ

()

125

CsFC

./

=µ

()

By pulling both RUN/SS pins below 1V, the LTC3727 is
put into low current shutdown (IQ = 20µA). The RUN/SS
pins can be driven directly from logic as shown in Fig­ure 7. Diode D1 in Figure 7 reduces the start delay but
allows CSS to ramp up slowly providing the soft-start
function. Each RUN/SS pin has an internal 6V zener clamp
(See Functional Diagram).

Fault Conditions: Overcurrent Latchoff (LTC3727 Only)

The RUN/SS pins also provide the ability to latch off the
controller(s) when an overcurrent condition is detected.

= 2.7 • 106 (CSS)

If the overload occurs after start-up the voltage on C

SS

will

begin discharging from the zener clamp voltage:

t

≅ [CSS (6 – 3.5)]/(1.2µA) = 2.1 • 106 (CSS)

LO2

This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin as shown
in Figure 7. This resistance shortens the soft-start period
and prevents the discharge of the RUN/SS capacitor
during an over current condition. Tying this pull-up resis­tor to VIN, as in Figure 7a, defeats overcurrent latchoff.
Diode-connecting this pull-up resistor to INTVCC, as in
Figure 7b, eliminates any extra supply current during
controller shutdown while eliminating the INTV

loading

CC

from preventing controller start-up. This pull-up resistor
is not needed in LTC3727-1 designs.

3727fb

19

LTC3727/LTC3727-1

I

mV

R

I

SC

SENSE

LSC

=+

45 1

2

∆

()

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APPLICATIO S I FOR ATIO

Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem
with noise pickup or poor layout causing the protection
circuit to latch off. Defeating this feature will easily allow
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature. If latchoff is
not required, the LTC3727-1 can be used.

The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci­tance is given by:

C

SS

> (C

OUT

)(V

) (10–4) (R

OUT

SENSE

)

The minimum recommended soft-start capacitor of

= 0.1µF will be sufficient for most applications.

C

SS

Fault Conditions: Current Limit and Current Foldback

The LTC3727 current comparator has a maximum sense
voltage of 135mV resulting in a maximum MOSFET cur­rent of 135mV/R
limit generally occurs with the largest V

. The maximum value of current

SENSE

at the highest

IN

ambient temperature, conditions that cause the highest
power dissipation in the top MOSFET.

The LTC3727 includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch described above is overridden. If the
output falls below 70% of its nominal output level, then the
maximum sense voltage is progressively lowered from
135mV to 45mV. Under short-circuit conditions with very
low duty cycles, the LTC3727 will begin cycle skipping in
order to limit the short-circuit current. In this situation the
bottom MOSFET will be dissipating most of the power but
less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time t

ON(MIN)

of
the LTC3727 (less than 200ns), the input voltage and
inductor value:

The resulting short-circuit current is:

Fault Conditions: Overvoltage Protection (Crowbar)

The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow, that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the
controller is operating.

A comparator monitors the output for overvoltage condi­tions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage.
When this condition is sensed, the top MOSFET is turned
off and the bottom MOSFET is turned on until the overvolt­age condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
therefore allow a switching regulator system having a poor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if V

returns to a safe level,

OUT

normal operation automatically resumes. A shorted top
MOSFET will result in a high current condition which will
open the system fuse. The switching regulator will regu­late properly with a leaky top MOSFET by altering the duty
cycle to accommodate the leakage.

Phase-Locked Loop and Frequency Synchronization

The LTC3727 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±50% around the
center frequency f

. A voltage applied to the PLLFLTR pin

O

of 1.2V corresponds to a frequency of approximately
380kHz. The nominal operating frequency range of the
LTC3727 is 250kHz to 550kHz.

∆I

L(SC)

20

= t

ON(MIN)

(VIN/L)

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APPLICATIO S I FOR ATIO

LTC3727/LTC3727-1

The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec­tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆f

, is equal to the capture range, ∆f

H

C:

∆fH = ∆fC = ± 0.5 fO (250kHz-550kHz)

The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin.

If the external frequency (f
lator frequency f

, current is sourced continuously,

0SC

) is greater than the oscil-

PLLIN

pulling up the PLLFLTR pin. When the external frequency
is less than f

, current is sunk continuously, pulling

0SC

down the PLLFLTR pin. If the external and internal fre­quencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time correspond­ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor C

holds the voltage. The

LP

LTC3727 PLLIN pin must be driven from a low impedance
source such as a logic gate located close to the pin. When
using multiple LTC3727s for a phase-locked system, the
PLLFLTR pin of the master oscillator should be biased at
a voltage that will guarantee the slave oscillator(s) ability
to lock onto the master’s frequency. A DC voltage of 0.7V
to 1.7V applied to the master oscillator’s PLLFLTR pin is
recommended in order to meet this requirement. The
resultant operating frequency can range from 310kHz to
470kHz.

The loop filter components (C

, RLP) smooth out the

LP

current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically R

=10kΩ and CLP is 0.01µF to

LP

0.1µF.

Minimum On-Time Considerations

Minimum on-time t

ON(MIN)

is the smallest time duration
that the LTC3727 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that

V

t

()

ON MIN

<

Vf

OUT

IN

()

If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3727 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.

The minimum on-time for the LTC3727 is generally less
than 200ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
300ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger inductor current and output
voltage ripple.

FCB Pin Operation

The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced on
both controllers when the FCB pin drops below 0.8V.
During continuous mode, current flows continuously in
the transformer primary. The secondary winding(s) draw
current only when the bottom, synchronous switch is on.
When primary load currents are low and/or the V

IN/VOUT

ratio is low, the synchronous switch may not be on for a
sufficient amount of time to transfer power from the
output capacitor to the secondary load. Forced continuous
operation will support secondary windings providing there
is sufficient synchronous switch duty factor. Thus, the
FCB input pin removes the requirement that power must

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APPLICATIO S I FOR ATIO

be drawn from the inductor primary in order to extract
power from the auxiliary windings. With the loop in
continuous mode, the auxiliary outputs may nominally be
loaded without regard to the primary output load.

The secondary output voltage V

is normally set as

SEC

shown in Figure 6 by the turns ratio N of the transformer:

≅ (N + 1) V

V

SEC

OUT

However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then V
V

SEC

VV

will droop. An external resistive divider from

SEC

to the FCB pin sets a minimum voltage V

R

6

SEC MIN()

⎛

.≅ +

08 1

⎜
⎝

⎞
⎟

⎠

R

5

SEC(MIN)

:

where R5 and R6 are shown in Figure 2.

If V
temporary continuous switching operation until V

drops below this level, the FCB voltage forces

SEC

SEC

is

again above its minimum.

In order to prevent erratic operation if no external connec­tions are made to the FCB pin, the FCB pin has a 0.18µA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.

loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Voltage positioning can easily be added to
the LTC3727 by loading the I

pin with a resistive divider

TH

having a Thevenin equivalent voltage source equal to the
midpoint operating voltage range of the error amplifier, or

1.2V (see Figure 8).

The resistive load reduces the DC loop gain while main­taining the linear control range of the error amplifier. The
maximum output voltage deviation can theoretically be
reduced to half or alternatively the amount of output
capacitance can be reduced for a particular application. A
complete explanation is included in Design Solutions 10
(see www.Linear.com).

INTV

CC

R

T2

I

TH

R

R

C

T1

C

C

Figure 8. Active Voltage Positioning Applied to the LTC3727

LTC3727

3727 F08

Efficiency Considerations

The following table summarizes the possible states avail­able on the FCB pin:

Table 1

FCB PIN CONDITION

0V to 0.75V Forced Continuous Both Controllers

(Current Reversal Allowed—
Burst Inhibited)

0.85V < V

Feedback Resistors Regulating a Secondary Winding

>7.3V Burst Mode Operation Disabled

< 6.8V Minimum Peak Current Induces

FCB

Burst Mode Operation
No Current Reversal Allowed

Constant Frequency Mode Enabled
No Current Reversal Allowed No
Minimum Peak Current

Voltage Positioning

Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage
of input power.

Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3727 circuits: 1) LTC3727 V
cluding loading on the 3.3V internal regulator), 2) INTV

current (in-

IN

CC

regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.

1. The V

current has two components: the first is the DC

IN

supply current given in the Electrical Characteristics table,

3727fb

22

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APPLICATIO S I FOR ATIO

LTC3727/LTC3727-1

which excludes MOSFET driver and control currents; the
second is the current drawn from the 3.3V linear regulator
output. V

2. INTV

current typically results in a small (<0.1%) loss.

IN

current is the sum of the MOSFET driver and

CC

control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTV
ground. The resulting dQ/dt is a current out of INTV

CC

CC

that

to

is typically much larger than the control circuit current. In
continuous mode, I

GATECHG

=f(QT + QB), where QT and Q

B

are the gate charges of the topside and bottom side
MOSFETs.

Supplying INTV
from an output-derived source will scale the V

power through the EXTVCC switch input

CC

current

IN

required for the driver and control circuits by a factor of
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTVCC current results in approxi­mately 2.5mA of V

current. This reduces the mid-current

IN

loss from 10% or more (if the driver was powered directly
from V

3. I

) to only a few percent.

IN

2

R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R

SENSE

,
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi­mately the same R

, then the resistance of one

DS(ON)

MOSFET can simply be summed with the resistances of L,
R
R

and ESR to obtain I2R losses. For example, if each

SENSE

= 30mΩ, RL = 50mΩ, R

DS(ON)

= 10mΩ and R

SENSE

ESR

= 40mΩ (sum of both input and output capacitance
losses), then the total resistance is 130mΩ. This results in
losses ranging from 3% to 13% as the output current
increases from 1A to 5A for a 5V output, or a 4% to 20%
loss for a 3.3V output. Efficiency varies as the inverse
square of V

for the same external components and

OUT

output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!

4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:

Transition Loss = (1.7) V

2

I

IN

O(MAX) CRSS

f

Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that CIN has
adequate charge storage and very low ESR at the switch­ing frequency. A 25W supply will typically require a mini­mum of 22µF to 47µF of capacitance having a maximum
of 20mΩ to 50mΩ of ESR. The LTC3727 2-phase architec­ture typically halves this input capacitance requirement
over competing solutions. Other losses, including Schot­tky diode conduction losses during dead-time and induc­tor core losses, generally account for less than 2% total
additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ∆I
series resistance of C
discharge C

generating the feedback error signal that

OUT

(ESR), where ESR is the effective

LOAD

OUT

. ∆I

also begins to charge or

LOAD

shifts by an

OUT

forces the regulator to adapt to the current change and
return V
time V

to its steady-state value. During this recovery

OUT

can be monitored for excessive overshoot or

OUT

ringing, which would indicate a stability problem. OPTI­LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values.

The availability of the ITH pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response

. Assuming a pre­dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of

3727fb

23

LTC3727/LTC3727-1

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APPLICATIO S I FOR ATIO

overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I

TH

external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.

The I

series RC-CC filter sets the dominant pole-zero

TH

loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80% of
full-load current having a rise time of 1µs to 10µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
why it is better to look at the ITH pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing RC and the bandwidth of the loop will be
increased by decreasing C
factor that C

is decreased, the zero frequency will be kept

C

. If RC is increased by the same

C

the same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability of
the closed-loop system and will demonstrate the actual
overall supply performance.

approximately 25 • C

. Thus a 10µF capacitor would

LOAD

require a 250µs rise time, limiting the charging current to
about 200mA.

Automotive Considerations: Plugging into the
Cigarette Lighter

As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during opera­tion. But before you connect, be advised: you are plugging
into the supply from Hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load-dump, reverse-battery, and
double-battery.

Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.

The network shown in Figure 9 is the most straight forward
approach to protect a DC/DC converter from the ravages
of an automotive power line. The series diode prevents
current from flowing during reverse-battery, while the
transient suppressor clamps the input voltage during
load-dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamp the input voltage below breakdown of the converter.
Although the LTC3727 has a maximum input voltage of
36V, most applications will be limited to 30V by the
MOSFET BVDSS.

A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C

, causing a rapid drop in V

OUT

. No regulator can

OUT

alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C

LOAD

to C

is greater than 1:50, the switch rise time

OUT

should be controlled so that the load rise time is limited to

24

RATING

50A I

PK

12V

TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT

1.5KA24A

Figure 9. Automotive Application Protection

V

IN

LTC3727

3727 F09

3727fb

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APPLICATIO S I FOR ATIO

LTC3727/LTC3727-1

Design Example

As a design example for one channel, assume V
24V(nominal), V
f = 250kHz.

The inductance value is chosen first based on a 40% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLFLTR pin
to the SGND pin for 250kHz operation. The minimum
inductance for 40% ripple current is:

V

∆I

A 14µH inductor will result in 40% ripple current. The peak
inductor current will be the maximum DC value plus one
half the ripple current, or 6A, for the 14µH value.

The R
maximum current sense voltage specification with some
accommodation for tolerances:

R

Choosing 1% resistors; R1 = 20k and R2 = 280k yields an
output voltage of 12V.

The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Siliconix Si4412DY results
in: R
voltage with T(estimated) = 50°C:

P

MAIN

OUT OUT

=

L

()( )

fL

SENSE

≤≈Ω

SENSE

= 0.042Ω, C

DS(ON)

=

0 042 1 7 30 5 100 250

()

=

= 30V(max), V

IN

⎛

–1

⎜
⎝

resistor value can be calculated by using the

mV

90

A

6

V

12

5 1 0 005 50 25

()

V

30

..

Ω

mW

664

⎞

V

⎟
⎠

V

IN

0 015.

= 100pF. At maximum input

RSS

2

+°°

(. )( – )

[]

+

V A pF kHz

()()( )( )

= 12V, I

OUT

CC

2

MAX

=

IN

= 5A and

A short-circuit to ground will result in a folded back current
of:

mV ns V

I

with a typical value of R
The resulting power dissipated in the bottom MOSFET is:

P

which is less than under full-load conditions.

is chosen for an RMS current rating of at least 3A at

C

IN

temperature assuming only this channel is on. C
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:

V

PC Board Layout Checklist

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3727. These items are also illustrated graphically in
the layout diagram of Figure 10; Figure 11 illustrates the
current waveforms present in the various branches of the
2-phase synchronous regulators operating in continuous
mode. Check the following in your layout:

1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at C
two channels as it can cause a large resonant loop.

45

=

SC

0 015

.

30 12

=

SYNC

284

=

ORIPPLE

IN

= R

? Do not attempt to split the input decoupling for the

⎛

12200 30

+

⎜

Ω

–

VV

30

V

mW

(∆IL) = 0.02Ω(2A) = 40mV

ESR

14

⎝

and δ = (0.005/°C)(20) = 0.1.

DS(ON)

32 11 0042

...

A

()()

⎞

()

⎟

H

µ

⎠

2

()

=

32

.

A

Ω

P–P

OUT

is

3727fb

25

LTC3727/LTC3727-1

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APPLICATIO S I FOR ATIO

2. Are the signal and power grounds kept separate? The
combined LTC3727 signal ground pin and the ground
return of C

INTVCC

must return to the combined C

OUT

(–)
terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the C

capacitor should have short

IN

leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible to the
(–) terminals of the input capacitor by placing the capaci­tors next to each other and away from the Schottky loop
described above.

3. Do the LTC3727 V

OSENSE

nect to the (+) terminals of C
must be connected between the (+) terminal of C

pins resistive dividers con-

? The resistive divider

OUT

and

OUT

signal ground. The R2 and R4 connections should not be

1

RUN/SS1

2

R2

R1

INTV

3.3V

R4R3

3

4

5

f

IN

6

7

CC

8

9

10

11

12

13

14

SENSE1

SENSE1

V

OSENSE1

PLLFLTR

PLLIN

FCB

I

TH1

SGND

3.3V

OUT

I

TH2

V

OSENSE2

SENSE2

SENSE2

+

–

LTC3727

–

+

RUN/SS2

PGOOD

TG1

SW1

BOOST1

V

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

28

27

26

25

24

IN

23

22

CC

21

CC

20

19

18

17

16

15

along the high current input feeds from the input
capacitor(s).

–

4. Are the SENSE

and SENSE+ leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE

+

and SENSE– should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the SENSE resistor.

5. Is the INTVCC decoupling capacitor connected close to
the IC, between

the INTVCC and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1µF ceramic capacitor placed immediately
next to the INTV

and PGND pins can help improve noise

CC

performance substantially.

R

PU

V

PULL-UP

(<7V)

PGOOD

C

B1

C

C

B2

+

INTVCC

M1 M2

R

IN

C

VIN

V

IN

M3 M4

L1

V

R

SENSE

D1

C

OUT1

+

C

IN

+

L2

R

C

OUT2

D2

SENSE

+

OUT1

GND

V

OUT2

26

3727 F10

Figure 10. LTC3727 Recommended Printed Circuit Layout Diagram

3727fb

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APPLICATIO S I FOR ATIO

LTC3727/LTC3727-1

SW1

D1

V

IN

R

IN

+

C

IN

BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH

SW2

D2

L1

L2

R

SENSE1

R

SENSE2

C

C

OUT1

OUT2

V

V

+

+

OUT1

OUT2

3727 F11

R

L1

R

L2

Figure 11. Branch Current Waveforms

6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the LTC3727 and occupy minimum PC trace area.

7. Use a modified “star ground” technique: a low imped­ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV

CC

decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
operating voltage and current range expected in the

3727fb

27

LTC3727/LTC3727-1

U

WUU

APPLICATIO S I FOR ATIO

appli

cation. The frequency of operation should be main­tained over the input voltage range down to dropout and
until the output load drops below the low current opera­tion threshold—typically 10% to 20% of the maximum
designed current level in Burst Mode operation.

The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple­mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation. Over­compensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Only after each controller is checked for its individual
performance should both controllers be turned on at the
same time. A particularly difficult region of operation is
when one controller channel is nearing its current com­parator trip point when the other channel is turning on its
top MOSFET. This occurs around 50% duty cycle on either
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.

Short-circuit testing can be performed to verify proper
overcurrent latchoff, or 5µA can be provided to the RUN/
SS pin(s) by resistors from V
latchoff from occurring.

Reduce V
regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V
monitoring the outputs to verify operation.

from its nominal level to verify operation of the

IN

to prevent the short-circuit

IN

while

IN

Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If prob­lems coincide with high input voltages and low output
currents, look for capacitive coupling between the BOOST,
SW, TG, and possibly BG connections and the sensitive
voltage and current pins. The capacitor placed across the
current sensing pins needs to be placed immediately
adjacent to the pins of the IC. This capacitor helps to
minimize the effects of differential noise injection due to
high frequency capacitive coupling. If problems are en­countered with high current output loading at lower input
voltages, look for inductive coupling between CIN, Schottky
and the top MOSFET components to the sensitive current
and voltage sensing traces. In addition, investigate com­mon ground path voltage pickup between these compo­nents and the SGND pin of the IC.

An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still be
maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.

28

3727fb

TYPICAL APPLICATIO S

1

RUN/SS1

0.1µF

27pF

20k
1%

10k

33pF

15k

33pF

15k

20k
1%

27pF

0.01µF

220pF

220pF

105k

1%

280k

1%

1000pF

1000pF

f

3.3V

1000pF

SYNC

2

3

4

5

6

7

8

9

10

11

12

13

14

SENSE1

SENSE1

V

OSENSE1

PLLFLTR

PLLIN

FCB

I

TH1

SGND

3.3V

I

TH2

V

OSENSE2

SENSE2

SENSE2

U

OUT

+

–

LTC3727

–

+

PGOOD

TG1

SW1

BOOST1

V

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

LTC3727/LTC3727-1

V

PULL-UP

1µF
10V

(<7V)

PGOOD

0.1µF

CMDSH-3

4.7µF

CMDSH-3

0.1µF

L1

M1A M1B

10Ω

0.1µF

8µH

22µF

50V

0.015Ω

D1
MBRM
140T3

C

OUT1

47µF

6.3V

V

OUT1

5V
5A; 6A PEAK

+ +

GND

+

C

100µF 16V

M2A M2B

15µH

OUT2

D2
MBRM
140T3

L2

0.015Ω

V

IN

15V TO
28V

V

OUT2

12V
4A; 5A PEAK

28

27

26

25

24

IN

23

22

CC

21

CC

20

19

18

17

16

15

0.1µF

C

: PANASONIC EEFCDOJ470R

OUT1

C

: SANYO OS-CON 16SVP100M

OUT2

VIN: 15V TO 28V
V

: 5V, 5A/12V, 4A

OUT

SWITCHING FREQUENCY = 250kHz
MI, M2: FAIRCHILD FDS6680A

L1: 8µH SUMIDA CDEP134-8R0
L2: 15µH COILTRONICS UP4B-150

Figure 12. LTC3727 12V/4A, 5V/5A Regulator with External Frequency Synchronization

3727 F12

3727fb

29

LTC3727/LTC3727-1

U

TYPICAL APPLICATIO S

1

RUN/SS1

0.1µF

27pF

20k

1%

33pF

15k

33pF

15k

20k

1%

27pF

105k

220pF

220pF

192.5k

1%

1%

1000pF

3.3V

1000pF

2

3

4

5

6

7

8

9

10

11

12

13

14

SENSE1

SENSE1

V

OSENSE1

PLLFLTR

PLLIN

FCB

I

TH1

SGND

3.3V

OUT

I

TH2

V

OSENSE2

SENSE2

SENSE2

+

–

LTC3727

–

+

PGOOD

TG1

SW1

BOOST1

V

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

V

PULL-UP

1µF
10V

(<7V)

PGOOD

0.1µF

CMDSH-3

4.7µF

CMDSH-3

0.1µF

L1

M1A M1B

10Ω

0.1µF

8µH

22µF

50V

0.015Ω

D1
MBRM
140T3

C

OUT1

47µF

6.3V

V

OUT1

5V
5A; 6A PEAK

+ +

GND

+

C

100µF 16V

M2A M2B

8µH

OUT2

D2
MBRM
140T3

L2

0.015Ω

V

IN

10V TO 15V

V

OUT2

8.5V
3A; 4A PEAK

28

27

26

25

24

IN

23

22

CC

21

CC

20

19

18

17

16

15

0.1µF

C

: PANASONIC EEFCDOJ470R

OUT1

C

: SANYO OS-CON 16SVP100M

OUT2

VIN: 10V TO 15V
V

: 5V, 5A/8.5V, 3A

OUT

Figure 13. LTC3727 8.5V/3A, 5V/5A Regulator

SWITCHING FREQUENCY = 250kHz
MI, M2: FAIRCHILD FDS6680A

3727 F13

L1, L2: 8µH SUMIDA CDEP134-8R0

30

3727fb

PACKAGE DESCRIPTIO

LTC3727/LTC3727-1

U

G Package

28-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

1.25 ±0.12

5.00 – 5.60**
(.197 – .221)

0° – 8°

4.10 ±0.05

3.45 ±0.05

0.55 – 0.95

(.022 – .037)

MILLIMETERS

(INCHES)

(4 SIDES)

0.09 – 0.25

(.0035 – .010)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE
*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

5.50 ±0.05

7.8 – 8.2

0.42 ±0.03

RECOMMENDED SOLDER PAD LAYOUT

0.65

(.0256)

BSC

0.22 – 0.38

(.009 – .015)

TYP

0.65 BSC

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693)

0.70 ±0.05

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

5.3 – 5.7

(.079)

MAX

0.05

(.002)

MIN

G28 SSOP 0204

2.0

12345678 9 10 11 12 1413

2526 22 21 20 19 181716 1523242728

9.90 – 10.50*
(.390 – .413)

7.40 – 8.20

(.291 – .323)

PACKAGE
OUTLINE

0.25 ± 0.05

RECOMMENDED SOLDER PAD LAYOUT

5.00 ± 0.10
(4 SIDES)

PIN 1
TOP MARK
(NOTE 6)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

0.50 BSC

0.75 ± 0.05

0.00 – 0.05

3.45 ± 0.10
(4-SIDES)

0.200 REF

BOTTOM VIEW—EXPOSED PAD

R = 0.115

TYP

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

32

31

0.25 ± 0.05

0.50 BSC

PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER

0.40 ± 0.10

1

2

(UH32) QFN 1004

3727fb

31

LTC3727/LTC3727-1

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≤ 7V

IN

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3.5V ≤ V

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, PGOOD

OUT1

≤ 36V, Fixed Frequency

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150kHz to 300kHz

Wide Input Range Synchronous Step-Down Controller Up to 97% Efficiency, 4V ≤ VIN ≤ 36V,

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0.8V ≤ V

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≤ 14V

Up to 20A

Smaller L and C

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≤ 6V, 4.5V ≤ VIN ≤ 32V, I

OUT

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SENSE

≤ 36V

IN

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≤ 60A,

32

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

3727fb

LT 0106 REV B • PRINTED IN USA

© LINEAR TECHNOLOGY CORPORATION 2001