Datasheet LTC3720 Datasheet (LINEAR TECHNOLOGY)

FEATURES

LTC3720

Single Phase VRM8.5

Current Mode Step-Down Controller

U

DESCRIPTIO

■

5-Bit Programmable Output Voltage:

1.05V to 1.825V (VRM8.5)

■

No Sense Resistor Required

■

2% to 87% Duty Cycle at 200kHz

■

t

ON(MIN)

■

Supports Active Voltage Positioning

■

True Current Mode Control

■

Stable with Ceramic C

■

Dual N-Channel MOSFET Synchronous Drive

■

Power Good Output Voltage Monitor

■

Wide VIN Range: 4V to 36V

■

±1% 0.8V Reference

■

Adjustable Current Limit

■

Adjustable Switching Frequency

■

Forced Continuous Control Pin

■

Programmable Soft-Start

■

Output Overvoltage Protection

■

Optional Short-Circuit Shutdown Timer

■

Micropower Shutdown: IQ < 30µA

■

Available in 28-Lead Narrow SSOP Package

≤ 100ns

OUT

U

APPLICATIO S

■

Power Supplies for Pentium® Processors

■

Notebook Computers and Servers

The LTC®3720 is a synchronous step-down switching
regulator controller for CPU power. An output voltage
between 1.05V and 1.825V is selected by a 5-bit code
(Intel VRM8.5 VID specification). The controller uses a
valley current control architecture to deliver very low duty
cycles without requiring a sense resistor. Operating fre­quency is selected by an external resistor and is compen­sated for variations in VIN and V

OUT

.

Discontinuous mode operation provides high efficiency
operation at light loads. A forced continuous control pin
reduces noise and RF interference and can assist second­ary winding regulation by disabling discontinuous mode
operation when the main output is lightly loaded.

Fault protection is provided by internal foldback current
limiting, an output overvoltage comparator and optional
short-circuit shutdown timer. Soft-start capability for sup­ply sequencing is accomplished using an external timing
capacitor. The regulator current limit level is also user
programmable. Wide supply range allows operation from
4V to 36V at the input.

, LTC and LT are registered trademarks of Linear Technology Corporation.

No R

is a trademark of Linear Technology Corporation.

SENSE

Pentium is a registered trademark of Intel Corporation.

TYPICAL APPLICATIO

470pF

5-BIT VID

0.1µF

20k

LTC3720

PGOOD

RUN/SS

I

TH

BOOST

SGND

INTV

VID4

SENSE

VID3
VID2

PGND

VID1

SENSE¯

VID0

V

OSENSE

Figure 1. High Efficiency Step-Down Converter

330k

I

ON

V

IN

TG

SW

V

CC

CC

+

+

BG

0.33µF

CMDSH-3

4.7µF

U

IRF7811W
×2

IRF7811W
×3

L1

1µH

UPS840

V

IN

5V TO 24V

10µF
×5

V

OUT

1.05V TO 1.825V

C

20A

OUT

+

270µF
2V
×4

C

: CORNELL DUBILIER

OUT

ESRE271M02B

L1: SUMIDA CEP125-IROMC

3720 F01a

Efficiency vs Output Current

100

V

= 1.45V

OUT

L1 = 1µH

95

90

85

80

75

EFFICIENCY (%)

70

65

60

55

0.01

VIN = 5V

VIN = 15V

0.1

1

OUTPUT CURRENT (A)

10

100

3720 F01b

3720f

1

LTC3720

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

Input Supply Voltage

VIN, ION..................................................36V to –0.3V

Boosted Topside Driver Supply Voltage

BOOST.................................................. 42V to –0.3V

SW, SENSE+ Voltages ................................. 36V to – 5V

EXTVCC, (BOOST – SW), RUN/SS, V

VID0-VID4, PGOOD Voltages..................... 7V to –0.3V

FCB, VON, V
ITH, VFB, V

Voltages .......... INTVCC + 0.3V to –0.3V

RNG

Voltages....................... 2.7V to –0.3V

OSENSE

TG, BG, INTVCC, EXTVCC Peak Currents.................... 2A

TG, BG, INTVCC, EXTVCC RMS Currents .............. 50mA

Operating Ambient Temperature Range

LTC3720EGN (Note 2) ........................ –40°C to 85°C

Junction Temperature (Note 3)............................ 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)..................300°C

CC

UU

W

PACKAGE/ORDER I FOR ATIO

TOP VIEW

1

RUN/SS

2

V

ON

3

PGOOD

4

V

RNG

5

FCB

6

I

TH

7

SGND

8

I

ON

9

V

FB

10

SGND

11

V

FB

12

V

OSENSE

13

VID0

14

VID1

GN PACKAGE

28-LEAD NARROW PLASTIC SSOP

T

= 125°C, θJA = 95°C/W

JMAX

BOOST

28

TG

27

SW

26

+

SENSE

25

–

SENSE

24

PGND

23

BG

22

INTV

21

CC

V

20

IN

EXTV

19

CC

V

18

CC

VID4

17

VID3

16

VID2

15

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ORDER PART

NUMBER

LTC3720EGN

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop

I

Q

V

FB

∆V

FB(LINEREG)

∆V

FB(LOADREG)

I

FB

g

m(EA)

V

FCB

I

FCB

t

ON

t

ON(MIN)

t

OFF(MIN)

V

SENSE(MAX)

V

SENSE(MIN)

∆V

FB(OV)

V

FB(UV)

V

RUN/SS(ON)

Input DC Supply Current
Normal 900 2000 µA
Shutdown Supply Current 15 30 µA

Feedback Reference Voltage ITH = 1.2V (Note 4) ● 0.792 0.800 0.808 V
Feedback Voltage Line Regulation VIN = 4V to 30V, ITH = 1.2V (Note 4) 0.002 %/V
Feedback Voltage Load Regulation ITH = 0.5V to 1.9V (Note 4) ● –0.05 –0.3 %
Feedback Pin Input Current –5 ±50 nA
Error Amplifier Transconductance ITH = 1.2V (Note 4) 1.4 1.7 2 mS
Forced Continuous Threshold ● 0.76 0.8 0.84 V
Forced Continuous Pin Current V

= 0.8V –1 –2 µA

FCB

On-Time ION = 60µA, VON = 1.5V 200 250 300 ns

ION = 30µA, VON = 1.5V 425 500 575 ns
Minimum On-Time ION = 180µA, VON = 0V 50 100 ns
Minimum Off-Time ION = 60µA, VON = 1.5V 250 400 ns
Maximum Current Sense Threshold V

V

SENSE

–

– V

SENSE

+

Minimum Current Sense Threshold V
V

SENSE

–

– V

SENSE

+

= 1V, VFB = 0.76V ● 113 133 153 mV

RNG

V

= 0V, VFB = 0.76V ● 79 93 107 mV

RNG

V

= INTVCC, VFB = 0.76V ● 158 186 214 mV

RNG

= 1V, VFB = 0.84V –67 mV

RNG

V

= 0V, VFB = 0.84V –47 mV

RNG

V

= INTVCC, VFB = 0.84V –93 mV

RNG

Output Overvoltage Fault Threshold 5.5 7.5 9.5 %
Output Undervoltage Fault Threshold 520 600 680 mV
RUN Pin Start Threshold ● 0.8 1.5 2 V

3720f

2

LTC3720

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

RUN/SS(LE)

V

RUN/SS(LT)

I

RUN/SS(C)

I

RUN/SS(D)

VIN (UVLO) Undervoltage Lockout VIN Falling ● 3.4 3.9 V

TG R

UP

TG R

DOWN

BG R

UP

BG R

DOWN

TG t

r

TG t

f

BG t

r

BG t

f

Internal VCC Regulator

V

INTVCC

∆V

LDO(LOADREG)

V

EXTVCC

∆V

EXTVCC

∆V

EXTVCC(HYS)

PGOOD Output

∆V

FBH

∆V

FBL

∆V

FB(HYS)

V

PGL

VID DAC

V

CC

V

VID(T)

V

VID(LEAK)

∆V

OSENSE

R

PULLUP

R

VID

I

VCC

RUN Pin Latchoff Enable Threshold RUN/SS Pin Rising 4 4.5 V
RUN Pin Latchoff Threshold RUN/SS Pin Falling 3.5 V
Soft-Start Charge Current –0.5 –1.2 –3 µA
Soft-Start Discharge Current 0.8 1.8 3 µA

VIN Rising ● 3.5 4.0 V

TG Driver Pull-Up On Resistance TG High 2 3 Ω
TG Driver Pull-Down On Resistance TG Low 2 3 Ω
BG Driver Pull-Up On Resistance BG High 3 4 Ω
BG Driver Pull-Down On Resistance BG Low 1 2 Ω
TG Rise Time C
TG Fall Time C
BG Rise Time C
BG Fall Time C

Internal VCC Voltage 6V < VIN < 30V, V
Internal VCC Load Regulation ICC = 0mA to 20mA, V
EXTVCC Switchover Voltage ICC = 20mA, V
EXTVCC Switch Drop Voltage ICC = 20mA, V

= 3300pF 20 ns

LOAD

= 3300pF 20 ns

LOAD

= 3300pF 20 ns

LOAD

= 3300pF 20 ns

LOAD

= 4V ● 4.7 5 5.3 V

EXTVCC

= 4V –0.1 ±2%

EXTVCC

Rising ● 4.5 4.7 V

EXTVCC

= 5V 150 300 mV

EXTVCC

EXTVCC Switchover Hysteresis 200 mV

PGOOD Upper Threshold VFB Rising 5.5 7.5 9.5 %
PGOOD Lower Threshold VFB Falling – 5.5 – 7.5 – 9.5 %
PGOOD Hysteresis VFB Returning 1 2 %
PGOOD Low Voltage I

= 5mA 0.15 0.4 V

PGOOD

Operating Supply Voltage Range 3.1 5.5 V
VID0-VID4 Logic Threshold Voltage VCC = 3.3V 0.4 1.2 2 V
VID0-VID4 Leakage Current V
DAC Output Accuracy V

Pull-Up Resistance on VID V
Resistance from V

OSENSE

to V

FB

VID0-VVID4
OSENSE

1.05V to 1.825V (Note 5), V

DIODE

= V

CC

0.01 ±1 µA

Programmed from –0.25 0 0.25 %

= 5V

CC

= 0.6V (Note 6) 28 40 56 kΩ

61014 kΩ

Supply Current (Note 7) 1 10 µA

Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.

Note 2: The LTC3720E is guaranteed to meet performance specifications from
0°C to 70°C. Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with statistical
process controls.

Note 3: TJ is calculated from the ambient temperature TA and power
dissipation P

LTC3720EGN: T

Note 4: The LTC3720 is tested in a feedback loop that adjusts V
a specified error amplifier output voltage (I

as follows:

D

= TA + (PD • 95°C/W)

J

to achieve

).

TH

FB

Note 5: The LTC3720 VID DAC is tested in a feedback loop that adjusts
V

to achieve a specified feedback voltage (VFB = 0.8V) for each DAC VID

OSENSE

code.
Note 6: Each built-in pull-up resistor attached to VID inputs also has a series

diode connected to VCC to allow input voltages higher than the VCC supply
without damage or clamping. (See Operation section for further details.)

Note 7: Supply current is specified with all VID inputs floating. Due to the
internal pull-ups on the VID pins, the supply current will increase depending
on the number of grounded VID lines. Each grounded VID line will draw
approximately (V

– 0.6V)/40k mA. (See Operation section for further

CC

details.)

3720f

3

LTC3720

TEMPERATURE (°C)

–50

0.78

FEEDBACK REFERENCE VOLTAGE (V)

0.79

0.80

0.81

0.82

–25 0 25 50

3720 G09

75 100 125

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Current Sense Threshold
vs ITH Voltage

300

V

RNG

2V

=

On-Time vs ION Current On-Time vs VON Voltage

10k

V

VON

= 0V

1000

I

ION

= 30µA

200

100

0

–100

CURRENT SENSE THRESHOLD (mV)

–200

0

1.0 1.5 2.0

0.5
ITH VOLTAGE (V)

On-Time vs Temperature

300

I

= 30µA

ION

= 0V

V

VON

250

200

150

ON-TIME (ns)

100

50

1.4V

1V

0.7V

0.5V

2.5 3.0

3720 G01

1k

ON-TIME (ns)

100

10

1

ION CURRENT (µA)

Current Limit Foldback

150

125

100

= 1V

V

RNG

75

50

25

10 100

3720 G02

800

600

400

ON-TIME (ns)

200

0

0

1

VON VOLTAGE (V)

Maximum Current Sense
Threshold vs V

300

250

200

150

100

50

RNG

2

Voltage

3

3720 G02

0

–50

–25 0

Maximum Current Sense
Threshold vs RUN/SS Voltage

150

125

100

MAXIMUM CURRENT SENSE THRESHOLD (mV)

4

= 1V

V

RNG

75

50

25

0

1.5

2 2.5 3 3.5

50 100 125

25 75

TEMPERATURE (°C)

RUN/SS VOLTAGE (V)

3720 G04

3729 G07

MAXIMUM CURRENT SENSE THRESHOLD (mV)

0

0

0.2 0.4 0.6 0.8
VFB (V)

Maximum Current Sense
Threshold vs Temperature

150

V

= 1V

RNG

140

130

120

110

MAXIMUM CURRENT SENSE THRESHOLD (mV)

100

–50 –25

0

TEMPERATURE (°C)

50

25

75

100

3720 G05

3720 G08

125

MAXIMUM CURRENT SENSE THRESHOLD (mV)

0

0.5

0.75

1.0 1.25 1.5
V

VOLTAGE (V)

RNG

1.75 2.0

Feedback Reference Voltage
vs Temperature

3720 G06

3720f

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Input and Shutdown Currents

Error Amplifier gm vs Temperature

2.0

1.8

vs Input Voltage INTVCC Load Regulation

1200

1000

EXTVCC OPEN

LTC3720

60

50

SHUTDOWN CURRENT (µA)

0

–0.1

1.6

(mS)

m

g

1.4

1.2

1.0
–50 –25

25

0

TEMPERATURE (°C)

EXTVCC Switch Resistance
vs Temperature

10

8

6

4

SWITCH RESISTANCE (Ω)

CC

2

EXTV

800

600

400

INPUT CURRENT (µA)

200

50

75

100

125

3720 G10

0

0

510

SHUTDOWN

EXTVCC = 5V

20 30 35

15 25

INPUT VOLTAGE (V)

3720 G11

40

30

20

10

0

–0.2

(%)

CC

–0.3

∆INTV

–0.4

–0.5

10

0

INTVCC LOAD CURRENT (mA)

30

40

20

50

3720 G12

RUN/SS Pin Current

FCB Pin Current vs Temperature

0

–0.25

–0.50

–0.75

–1.00

FCB PIN CURRENT (µA)

–1.25

vs Temperature

3

2

1

0

FCB PIN CURRENT (µA)

–1

PULL-DOWN CURRENT

PULL-UP CURRENT

0

–50 –25

50

25

0

TEMPERATURE (°C)

5.0

4.5

4.0

3.5

RUN/SS THRESHOLD (V)

3.0
–50

100

125

3720 G13

75

–1.50

–50

RUN/SS Latchoff Thresholds
vs Temperature

LATCHOFF ENABLE

LATCHOFF THRESHOLD

–25 0 25 50

TEMPERATURE (°C)

75 100 125

–25 0

3720 G16

50 100 125

25 75

TEMPERATURE (°C)

–2

–50 –25

3720 G14

Undervoltage Lockout Threshold
vs Temperature

4.0

3.5

3.0

2.5

UNDERVOLTAGE LOCKOUT THRESHOLD (V)

2.0
–50

–25 0 25 50

TEMPERATURE (C)

75 100 125

50

25

0

TEMPERATURE (

3720 G17

°C)

100

125

3720 G15

3720f

75

5

LTC3720

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Transient Response
(Forced Continuous Mode)

V

OUT

50mV/DIV

I

L

10A/DIV

3720 G18

U

LOAD STEP = 0A TO 15A
V

= 15V

IN

= 1.5V

V

OUT

FCB = 0V
FIGURE 7 CIRCUIT

20µs/DIV

UU

PI FU CTIO S

RUN/SS (Pin 1): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.

Transient Response
(Discontinuous Mode)

V

OUT

50mV/DIV

I

L

10A/DIV

LOAD STEP = 1A TO 15A
V

= 15V

IN

= 1.5V

V

OUT

FCB = INTV
FIGURE 7 CIRCUIT

I

(Pin 6): Current Control Threshold and Error Amplifier

TH

20µs/DIV 3720 G19

CC

Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 0.8V corresponding to zero sense
voltage (zero current).

VON (Pin 2): On-Time Voltage Input. Voltage trip point for
the on-time comparator. Tying this pin to the output
voltage makes the on-time proportional to V

OUT

. The

comparator input defaults to 0.7V when the pin is grounded,

2.4V when the pin is tied to INTVCC.
PGOOD (Pin 3): Power Good Output. Open drain logic

output that is pulled to ground when the output voltage is
not within ±7.5% of the regulation point.

V

(Pin 4): Sense Voltage Range Input. The voltage at

RNG

this pin is ten times the nominal sense voltage at maxi­mum output current and can be set from 0.5V to 2V by a
resistive divider from INTVCC. The nominal sense voltage
defaults to 70mV when this pin is tied to ground, 140mV
when tied to INTVCC.

FCB (Pin 5): Forced Continuous Input. Tie this pin to
ground to force continuous synchronous operation at low
load or to INTVCC to enable discontinuous mode operation
at low load.

SGND (Pin 7, 10): Signal Ground. All small-signal compo­nents and compensation components should connect to
this ground, which in turn connects to PGND at one point.

ION (Pin 8): On-Time Current Input. Tie a resistor from V

IN

to this pin to set the one-shot timer current and thereby set
the switching frequency.

VFB (Pin 9, 11): Error Amplifier Feedback Input. This pin
connects to both the error amplifier input and to the output
of the internal resistive divider. It can be used to attach
additional compensation components if desired.

V

OSENSE

(Pin 12): Output Voltage Sense. The output

voltage connects here to the input of the internal resistive
feedback divider.

VID0-VID4 (Pins 13, 14, 15, 16, 17): VID Digital Inputs.
The voltage identification (VID) code sets the internal
feedback resistor divider ratio for different output voltages
as shown in Table 1. If unconnected, the pins are pulled
high by internal 40k pull-up resistors.

3720f

6

LTC3720

U

UU

PI FU CTIO S

VCC (Pin 18): Power Supply Voltage for VID. Range is from

3.1V to 5.5V.
EXTVCC (Pin 19): External VCC Input. When EXTVCC ex-

ceeds 4.7V, an internal switch connects this pin to INTV
and shuts down the internal regulator so that controller
and gate drive power is drawn from EXTVCC. Do not exceed
7V at this pin and ensure that EXTVCC < VIN.

VIN (Pin 20): Main Input Supply. Decouple this pin to
PGND with an RC filter (1Ω, 0.1µF).

INTVCC (Pin 21): Internal 5V Regulator Output. The driver
and control circuits are powered from this voltage. De­couple this pin to power ground with a minimum of 4.7µF
low ESR tantalum capacitor.

BG (Pin 22): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.

PGND (Pin 23): Power Ground. Connect this pin closely to
the source of the bottom N-channel MOSFET, the (–)
terminal of C

and the (–) terminal of CIN.

VCC

CC

SENSE– (Pin 24): Current Sense Comparator Input. The
(–) input is normally connected to PGND.

SENSE+ (Pin 25): Current Sense Comparator Input. The
(+) input to the current comparator is normally connected
to the SW node unless using a sense resistor (see Appli­cations Information).

SW (Pin 26): Switch Node. The (–) terminal of the boot­strap capacitor CB connects here. This pin swings from a
diode voltage drop below ground up to VIN.

TG (Pin 27): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superim­posed on the switch node voltage SW.

BOOST (Pin 28): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below INTVCC up to
V

+ INTVCC.

IN

3720f

7

LTC3720

U

U

W

FU CTIO AL DIAGRA

R

ON

0.7V

V

2

1

OST

tON = (10pF)

1.4V

V

RNG

4

0.7V

1

240k

I

THB

+

0.8V

–

×4

ON

2.4V

V

VON

I

ION

I

CMP

Q3

I

8

ON

R
SQ

20k

+

–

×

Q2

Q1

EA

+

+

–

3.3µA

Q4

Q6

–

1µA

I

REV

Q5

–

0.6V

V

IN

V

0.8V
REF

5V

REG

0.74V

0.86V

BOOST

28

TG

27

SW

26

SENSE

25

INTV

21

BG

22

PGND

23

SENSE

24

PGOOD

3

20

IN

+

C

IN

C

B

M1

+

D

B

CC

+

C

VCC

–

R2
10k

×5 (ALL VID PINS)

V

CC

VID

DAC

R1

M2

L1

+

V

OSENSE

40k

C

OUT

12

VID0

13

VID1

14

VID2

15

VID3

16

VID4

17

V

18

CC

FCB

5

–

F

1V

0.8V

4.7V

+

–

+

FCNT

SHDN

ON

OV

19

EXTV

SWITCH

LOGIC

CC

+

UV

–

+

OV

–

SS

–

+

+

RUN

SHDN

1.2µA

6V

8

0.8V

C

I

6

C1

TH

R

C

0.6V

RUN/SS

C

1

V

SS

FB

911

V

FB

10

SGNDSGND

7

3711 FD

3720f

OPERATIO

LTC3720

U

(Refer to Functional Diagram)

Main Control Loop

The LTC3720 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by a
one-shot timer OST. When the top MOSFET is turned off,
the bottom MOSFET is turned on until the current com­parator I
initiating the next cycle. Inductor current is determined
by sensing the voltage between the SENSE– and SENSE
pins using either the bottom MOSFET on-resistance or a
separate sense resistor. The voltage on the ITH pin sets
the comparator threshold corresponding to inductor
valley current. The error amplifier EA adjusts this voltage
by comparing the feedback signal VFB from the output
voltage with an internal 0.8V reference. The feedback
voltage is derived from the output voltage by a resistive
divider DAC that is set by the VID code pins VID0-VID4.
If the load current increases, it causes a drop in the
feedback voltage relative to the reference. The ITH voltage
then rises until the average inductor current again matches
the load current.

trips, restarting the one-shot timer and

CMP

+

Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±7.5% window around the regulation point.
Furthermore, in an overvoltage condition, M1 is turned
off and M2 is turned on and held on until the overvoltage
condition clears.

Foldback current limiting is provided if the output is
shorted to ground. As VFB drops, the buffered current
threshold voltage I
level set by Q4 and Q6. This reduces the inductor valley
current level to one sixth of its maximum value as V
approaches 0V.

Pulling the RUN/SS pin low forces the controller into its
shutdown state, turning off both M1 and M2. Releasing
the pin allows an internal 1.2µA current source to charge
up an external soft-start capacitor CSS. When this voltage
reaches 1.5V, the controller turns on and begins switch­ing, but with the ITH voltage clamped at approximately

0.6V below the RUN/SS voltage. As CSS continues to
charge, the soft-start current limit is removed.

is pulled down by clamp Q3 to a 1V

THB

FB

At low load currents, the inductor current can drop to zero
and become negative. This is detected by current reversal
comparator I
discontinuous operation. Both switches will remain off
with the output capacitor supplying the load current until
the ITH voltage rises above the zero current level (0.8V) to
initiate another cycle. Discontinuous mode operation is
disabled by comparator F when the FCB pin is brought
below 0.8V, forcing continuous synchronous operation.

The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an on­time that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in VIN and V
with an external resistor RON.

which then shuts off M2, resulting in

REV

. The nominal frequency can be adjusted

OUT

INTVCC/EXTVCC Power

Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is re­charged from INTVCC through an external Schottky diode
DB when the top MOSFET is turned off. When the EXTV
pin is grounded, an internal 5V low dropout regulator
supplies the INTVCC power from VIN. If EXTVCC rises
above 4.7V, the internal regulator is turned off, and an
internal switch connects EXTVCC to INTVCC. This allows
a high efficiency source connected to EXTVCC, such as an
external 5V supply or a secondary output from the
converter, to provide the INTVCC power. Voltages up to
7V can be applied to EXTVCC for additional gate drive. If
the input voltage is low and INTVCC drops below 3.5V,
undervoltage lockout circuitry prevents the power
switches from turning on.

CC

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The basic LTC3720 application circuit is shown in
Figure 1. External component selection is primarily de­termined by the maximum load current and begins with
the selection of the sense resistance and power MOSFET
switches. The LTC3720 can use either a sense resistor or
the on-resistance of the synchronous power MOSFET for
determining the inductor current. The desired amount of
ripple current and operating frequency largely deter­mines the inductor value. Finally, CIN is selected for its
ability to handle the large RMS current into the converter
and C

is chosen with low enough ESR to meet the

OUT

output voltage ripple and transient specification.

Maximum Sense Voltage and V

RNG

Pin

Inductor current is determined by measuring the voltage
across a sense resistance that appears between the
and

SENSE+ pins. The maximum sense voltage is set by
the voltage applied to the V
approximately (0.133)V

RNG

pin and is equal to

RNG

. The current mode control

SENSE

–

loop will not allow the inductor current valleys to exceed
(0.133)V

RNG/RSENSE

. In practice, one should allow some
margin for variations in the LTC3720 and external compo­nent values and a good guide for selecting the sense
resistance is:

V

10•

RNG

I

OUT MAX

()

R

SENSE

=

An external resistive divider from INTVCC can be used to
set the voltage of the V

pin between 0.5V and 2V

RNG

resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the V

pin can be tied to SGND or INTV

RNG

CC

in which case the nominal sense voltage defaults to 70mV
or 140mV, respectively. The maximum allowed sense
voltage is about 1.33 times this nominal value.

Connecting the SENSE+ and

SENSE– Pins

The LTC3720 can be used with or without a sense resistor.
When using a sense resistor, it is placed between the
source of the bottom MOSFET M2 and ground. Connect
the

SENSE+ pin to the source of the bottom MOSFET and

the

SENSE– pin to PGND so that the resistor appears

between the

SENSE+ and

SENSE– pins. Kelvin connec­tions at the sense resistor ensure accurate current sens­ing. Using a sense resistor provides a well defined current
limit, but adds cost and reduces efficiency. Alternatively,
one can eliminate the sense resistor and use the bottom
MOSFET as the current sense element by simply connect­ing the SE
the bottom MOSFET and keep
PGND

NSE+ pin to the switch node SW at the drain of

SENSE– connected to

. This improves efficiency, but one must carefully

choose the MOSFET on-resistance as discussed below.

Power MOSFET Selection

The LTC3720 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V
threshold voltage V
transfer capacitance C

, on-resistance R

(GS)TH

and maximum current I

RSS

DS(ON)

(BR)DSS

, reverse

DS(MAX)

,

.

The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3720 applications. If the input voltage is
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be considered.

When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on­resistance. MOSFET on-resistance is typically specified
with a maximum value R

DS(ON)(MAX)

at 25°C. In this case,

additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:

R

R

DS ON MAX

()( )

=

SENSE

ρ

T

The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 2. For a maximum temperature of 100°C, using a
value ρT = 1.3 is reasonable.

The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and

10

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APPLICATIO S I FOR ATIO

LTC3720

2.0

1.5

1.0

0.5

NORMALIZED ON-RESISTANCE

T

ρ

0

–50

Figure 2. R

0

JUNCTION TEMPERATURE (°C)

50

vs. Temperature

DS(ON)

100

150

3720 F02

the load current. When the LTC3720 is operating in
continuous mode, the duty cycles for the MOSFETs are:

V

D

D

TOP

BOT

OUT

=

V

IN

–

VV

IN OUT

=

V

IN

The operating frequency of LTC3720 applications is deter­mined implicitly by the one-shot timer that controls the
on-time tON of the top MOSFET switch. The on-time is set
by the current into the ION pin and the voltage at the V

ON

pin according to:

V

t

ON

VON

= ()10

I

ION

pF

Tying a resistor RON from VIN to the ION pin yields an on­time inversely proportional to VIN. For a step-down con­verter, this results in approximately constant frequency
operation as the input supply varies:

V

f

=

VR pF

OUT

VON ON

()10

Hz

[]

To hold frequency constant during output voltage changes,
tie the VON pin to V

. The VON pin has internal clamps

OUT

that limit its input to the one-shot timer. If the pin is tied
below 0.7V, the input to the one-shot is clamped at 0.7V.
Similarly, if the pin is tied above 2.4V, the input is clamped
at 2.4V.

The resulting power dissipation in the MOSFETs at maxi­mum output current are:

P

P

TOP

BOT

= D

TOP IOUT(MAX)

+ k V

= D

IN

BOT IOUT(MAX)

2

I

2

ρ

T(TOP) RDS(ON)(MAX)

OUT(MAX) CRSS

2

ρ

T(BOT) RDS(ON)(MAX)

f

Both MOSFETs have I2R losses and the top MOSFET
includes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottom MOSFET losses are greatest when the bottom duty
cycle is near 100%, during a short-circuit or at high input
voltage.

Operating Frequency

The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.

Because the voltage at the ION pin is about 0.7V, the
current into this pin is not exactly inversely proportional to
VIN, especially in applications with lower input voltages.
To correct for this error, an additional resistor R

ON2

connected from the ION pin to the 5V INTVCC supply will
further stabilize the frequency.

V

07=.

5

R

V

R

ON ON2

Changes in the load current magnitude will also cause
frequency shift. Parasitic resistance in the MOSFET
switches and inductor reduce the effective voltage across
the inductance, resulting in increased duty cycle as the
load current increases. By lengthening the on-time slightly
as current increases, constant frequency operation can be
maintained. This is accomplished with a resistive divider
from the ITH pin to the VON pin and V

. The values

OUT

required will depend on the parasitic resistances in the
specific application. A good starting point is to feed about
25% of the voltage change at the ITH pin to the VON pin as

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APPLICATIO S I FOR ATIO

R

VON1

30k

V

OUT

R

VON2

100k

R

C

C

C

(3a)

Figure 3. Correcting Frequency Shift with Load Current Changes

C

VON

0.01µF

V

ON

LTC3720

I

TH

3720 F03a

shown in Figure 3a. Place capacitance on the VON pin to
filter out the ITH variations at the switching frequency. The
resistor load on ITH reduces the DC gain of the error amp
and degrades load regulation, which can be avoided by
using the PNP emitter follower of Figure 3b.

Inductor Selection

Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:

∆=

I

L








V



OUT OUT

fL

V

−

1












V



IN

Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.

A reasonable starting point is to choose a ripple current
that is about 40% of I

OUT(MAX)

. The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:



L

V

=



fI

∆



L MAX





OUT




() ()

V

−

1



V



IN MAX

OUT






R

VON1

INTV

OUT

3k

R

VON2

10k

10k

CC

2N5087

Q1

(3b)

V

C

VON

0.01µF

R

C

C

C

V

ON

LTC3720

I

TH

3720 F03b

Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af­ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ® cores. A variety of inductors designed for high
current, low voltage applications are available from manu­facturers such as Sumida, Panasonic, Coiltronics, Coilcraft
and Toko.

Schottky Diode D1 Selection

The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
of the bottom MOSFET from turning on and storing charge
during the dead time, which can cause a modest (about
1%) efficiency loss. The diode can be rated for about one
half to one fifth of the full load current since it is on for only
a fraction of the duty cycle. In order for the diode to be
effective, the inductance between it and the bottom MOSFET
must be as small as possible, mandating that these
components be placed adjacently. The diode can be omit­ted if the efficiency loss is tolerable.

CIN and C

Selection

OUT

The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.

II

≅

RMS OUT MAX

()

V

OUT

V

IN

V

V

IN

OUT

–1

12

Kool Mµ is a registered trademark of Magnetics, Inc.

3720f

VV

R
R

SEC MIN()

.=+











08 1

4
3

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APPLICATIO S I FOR ATIO

LTC3720

This formula has a maximum at VIN = 2V
I

RMS

= I

OUT(MAX)

/2. This simple worst-case condition is

OUT

, where

commonly used for design because even significant
deviations do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often
based on only 2000 hours of life which makes it advisable
to derate the capacitor.

The selection of C

is primarily determined by the ESR

OUT

required to minimize voltage ripple and load step
transients. The output ripple ∆V

is approximately

OUT

bounded by:

∆≤∆ +



V I ESR

OUT L





8

fC

1

OUT






Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.

Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to signifi­cant ringing. When used as input capacitors, care must be
taken to ensure that ringing from inrush currents and
switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5µF to 50µF aluminum electrolytic
capacitor with an ESR in the range of 0.5Ω to 2Ω. High

performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recom­mended to reduce the effect of their lead inductance.

Top MOSFET Driver Supply (CB, DB)

An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode DB from INTV

CC

when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications a 0.1µF to 0.47µF X5R
or X7R dielectric capacitor is adequate.

Discontinuous Mode Operation and FCB Pin

The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.8V threshold enables discontinuous
operation where the bottom MOSFET turns off when
inductor current reverses. The load current at which
current reverses and discontinuous operation begins de­pends on the amplitude of the inductor ripple current and
will vary with changes in VIN. Tying the FCB pin below the

0.8V threshold forces continuous synchronous operation,
allowing current to reverse at light loads and maintaining
high frequency operation.

In addition to providing a logic input to force continuous
operation, the FCB pin provides a means to maintain a
flyback winding output when the primary is operating in
discontinuous mode. The secondary output V

SEC

is nor­mally set as shown in Figure 4 by the turns ratio N of the
transformer. However, if the controller goes into discon­tinuous mode and halts switching due to a light primary
load current, then V
divider from V
V

SEC(MIN)

until V

SEC

SEC

below which continuous operation is forced

has risen above its minimum.

will droop. An external resistor

SEC

to the FCB pin sets a minimum voltage

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V

IN

+

C

V

IN

OPTIONAL

EXTV

CONNECTION

5V < V

CC

< 7V

SEC

Figure 4. Secondary Output Loop and EXTVCC Connection

EXTV

R4

FCB

R3

SGND

LTC3720

CC

SENSE

TG

SW

+

BG

PGND

IN

1N4148

•

•

T1

1:N

V

SEC

+

C

SEC

1µF

V

C

OUT

OUT

3720 F04

+

Fault Conditions: Current Limit and Foldback

The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the LTC3720, the maximum sense voltage is controlled by
the voltage on the V

pin. With valley current control,

RNG

the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:

To further limit current in the event of a short circuit to
ground, the LTC3720 includes foldback current limiting. If
the output falls by more than 25%, then the maximum
sense voltage is progressively lowered to about one sixth
of its full value.

Minimum Off-time and Dropout Operation

The minimum off-time t

OFF(MIN)

is the smallest amount of
time that the LTC3720 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 350ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON + t

OFF(MIN)

). If the maximum duty cycle is reached,
due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:

tt

+

VV

IN MIN OUT

=

()

ON OFF MIN

t

ON

()

Output Voltage Programming

V

SNS MAX

I

=+∆

LIMIT

()

R

DS ON T

()

1

I

*ρ

L

2

The current limit value should be checked to ensure that
I

LIMIT(MIN)

> I

OUT(MAX)

. The minimum value of current limit
generally occurs with the largest VIN at the highest ambi­ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of I

which heats

LIMIT

the MOSFET switches.
Caution should be used when setting the current limit

based upon the R

of the MOSFETs. The maximum

DS(ON)

current limit is determined by the minimum MOSFET on­resistance. Data sheets typically specify nominal and
maximum values for R
reasonable assumption is that the minimum R

, but not a minimum. A

DS(ON)

DS(ON)

lies
the same amount below the typical value as the maximum
lies above it. Consult the MOSFET manufacturer for further
guidelines.

The output voltage is digitally set to levels between 1.05V
and 1.825V using the voltage identification (VID) inputs
VID0-VID4. An internal 5-bit DAC configured as a preci­sion resistive voltage divider sets the output voltage in
increments according to Table 1. The VID codes are com­patible with Intel VRM8.5 processor specifications. Each
VID input is pulled up by an internal 40k pull-up resistor
from the INTVCC supply and includes a series diode to
prevent damage from VID inputs that exceed the supply.

INTVCC Regulator

An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3720. The INTVCC pin can supply up to
50mA RMS and must be bypassed to ground with a
minimum of 4.7µF low ESR capacitor. Good bypassing is
necessary to supply the high transient currents required
by the MOSFET gate drivers. Applications using large
MOSFETs with a high input voltage and high frequency of

*Use R

value if a sense resistor is connected between SENSE+ and SENSE–.

SENSE

14

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LTC3720

Table 1. VID Output Voltage Programming

VID4 VID3 VID2 VID1 VID0 V

000001.250V

000011.275V

000101.200V

000111.225V

001001.150V

001011.175V

001101.100V

001111.125V

010001.050V

010011.075V

010101.800V

010111.825V

011001.750V

011011.775V

011101.700V
01111 1.725V

100001.650V

100011.675V

100101.600V

100111.625V

101001.550V

101011.575V

101101.500V

101111.525V

110001.450V

110011.475V

110101.400V

110111.425V

111001.350V

111011.375V

111101.300V
11111 1.325V

OUT

(V)

operation may cause the LTC3720 to exceed its maximum
junction temperature rating or RMS current rating. Most
of the supply current drives the MOSFET gates unless an
external EXTVCC source is used. In continuous mode
operation, this current is I

GATECHG

= f(Q

g(TOP)

+ Q

g(BOT)

).
The junction temperature can be estimated from the
equations given in Note 3 of the Electrical Characteristics.
For example, the LTC3720EGN is limited to less than
19mA from a 30V supply:

TJ = 70°C + (19mA)(30V)(95°C/W) = 125°C

For larger currents, consider using an external supply with
the EXTVCC pin.

EXTVCC Connection

The EXTVCC pin can be used to provide MOSFET gate drive
and control power from an external source during normal
operation. Whenever the EXTVCC pin is above 4.7V the
internal 5V regulator is shut off and an internal 50mA P­channel switch connects the EXTVCC pin to INTVCC. INTV

CC

power is supplied from EXTVCC until this pin drops below

4.5V. Do not apply more than 7V to the EXTVCC pin and
ensure that EXTVCC ≤ VIN. The following list summarizes
the possible connections for EXTVCC:

1. EXTVCC grounded. INTV

is always powered from the

CC

internal 5V regulator.

2. EXTVCC connected to an external supply. A high effi­ciency supply compatible with the MOSFET gate drive
requirements (typically 5V) can improve overall
efficiency.

3. EXTVCC connected to an output derived boost network.
The low voltage output can be boosted using a charge
pump or flyback winding to greater than 4.7V. The system
will start-up using the internal linear regulator until the
boosted output supply is available.

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External Gate Drive Buffers

The LTC3720 drivers are adequate for driving up to about
60nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
higher frequencies requiring greater RMS currents will
benefit from using external gate drive buffers such as the
LTC1693. Alternately, the external buffer circuit shown in
Figure 5 can be used. Note that the bipolar devices reduce
the signal swing at the MOSFET gate and benefit from an
increased EXTVCC voltage of about 6V.

10Ω

INTV

PGND

CC

Q3
FMMT619

Q4
FMMT720

GATE
OF M2

3720 F05

BOOST

Q1
FMMT619

10Ω

TG

Q2
FMMT720

SW

Figure 5. Optional External Gate Driver

GATE
OF M1

BG

Soft-Start and Latchoff with the RUN/SS Pin

The RUN/SS pin provides a means to shut down the
LTC3720 as well as a timer for soft-start and overcurrent
latchoff. Pulling the RUN/SS pin below 0.8V puts the
LTC3720 into a low quiescent current shutdown
(IQ < 30µA). Releasing the pin allows an internal 1.2µA
current source to charge up the external timing capacitor
CSS. If RUN/SS has been pulled all the way to ground,
there is a delay before starting of about:

15

.

t

DELAY SS SS

V

=

12

CsFC

.

A

µ

13

./

=µ

()

When the voltage on RUN/SS reaches 1.5V, the LTC3720
begins operating with a clamp on ITH of approximately

0.9V. As the RUN/SS voltage rises to 3V, the clamp on I

TH

is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF, during which the load current is folded

INTV

CC

V

3.3V OR 5V RUN/SS

Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated

IN

RSS*

D1

C

SS

(6a) (6b)

RSS*

RUN/SS

D2*

C

SS

3720 F06

*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF

back until the output reaches 75% of its final value. The pin
can be driven from logic as shown in Figure 6. Diode D1
reduces the start delay while allowing CSS to charge up
slowly for the soft-start function.

After the controller has been started and given adequate
time to charge up the output capacitor, CSS is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8µA cur-
rent then begins discharging CSS. If the fault condition
persists until the RUN/SS pin drops to 3.5V, then the con­troller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.

The overcurrent protection timer requires that the soft­start timing capacitor CSS be made large enough to guar­antee that the output is in regulation by the time CSS has
reached the 4V threshold. In general, this will depend upon
the size of the output capacitance, output voltage and load
current characteristic. A minimum soft-start capacitor can
be estimated from:

CSS > C

OUT VOUT RSENSE

(10–4 [F/V s])

Generally 0.1µF is more than sufficient.
Overcurrent latchoff operation is not always needed or

desired. Load current is already limited during a short­circuit by the current foldback circuitry and latchoff

16

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LTC3720

operation can prove annoying during troubleshooting.
The feature can be overridden by adding a pull-up current
greater than 5µA to the RUN/SS pin. The additional
current prevents the discharge of CSS during a fault and
also shortens the soft-start period. Using a resistor to V

IN

as shown in Figure 6a is simple, but slightly increases
shutdown current. Connecting a resistor to INTVCC as
shown in Figure 6b eliminates the additional shutdown
current, but requires a diode to isolate CSS. Any pull-up
network must be able to pull RUN/SS above the 4.5V
maximum threshold that arms the latchoff circuit and
overcome the 4µA maximum discharge current.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3720 circuits:

3. INTVCC current. This is the sum of the MOSFET driver
and control currents. This loss can be reduced by supply­ing INTVCC current through the EXTVCC pin from a high
efficiency source, such as an output derived boost net­work or alternate supply if available.

4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.

Other losses, including C

ESR loss, Schottky diode D1

OUT

conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.

When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.

Checking Transient Response

1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same R

DS(ON)

, then the
resistance of one MOSFET can simply be summed with the
resistances of L and the board traces to obtain the DC I2R
loss. For example, if R

= 0.01Ω and RL = 0.005Ω, the

DS(ON)

loss will range from 1% up to 10% as the output current
varies from 1A to 10A for a 1.5V output.

2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capaci­tance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:

Transition Loss ≅ (1.7A–1) V

IN

2

I

OUT CRSS

f

The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to ∆I
resistance of C
discharge C

(ESR), where ESR is the effective series

LOAD

OUT

generating a feedback error signal used

OUT

by the regulator to return V
During this recovery time, V

immediately shifts by an amount

OUT

. ∆I

also begins to charge or

LOAD

to its steady-state value.

OUT

can be monitored for

OUT

overshoot or ringing that would indicate a stability
problem. The ITH pin external components shown in
Figure 7 will provide adequate compensation for most
applications. For a detailed explanation of switching
control loop theory see Application Note 76.

3720f

17

LTC3720

WUUU

APPLICATIO S I FOR ATIO

Design Example

As a design example, take a supply with the following
specifications: VIN = 7V to 24V (15V nominal), V
to 1.825V with typical at 1.5V, I
First, calculate the timing resistor with VON = V

R

=

ON

300 10

()()

and choose the inductor for about 40% ripple current at
the maximum VIN:

L

300 0 4 15

()()()

Selecting a standard value of 1µH results in a maximum
ripple current of:

∆=

L

300 1

()

Next, choose the synchronous MOSFET switch. Because
of the narrow duty cycle and large current, a single SO-8
MOSFET will have difficulty dissipating the power lost in the
switch. Choosing two IRF7811A (R
= 60pF, θJA = 50°C/W) yields a nominal sense voltage of:

V

SNS(NOM)

Tying V
range for a nominal value of 140mV with current limit
occurring at 186mV. To check if the current limit is
acceptable, assume a junction temperature of about 100°C
above a 50°C ambient with ρ

RNG

1

kHz pF

V

15

.

kHz A

to INTVCC will set the current sense voltage

.

15

.

V

µ

kHz H

()

= (15A)(0.5)(1.3)(0.012Ω) = 117mV

=








1

–





OUT(MAX)

330

−

1

15

.

24

150°C

= 15A, f = 300kHz.

k



V

15

.

=µ

08



V

24





V

47

.

=I



V



= 0.013Ω, C

DS(ON)

= 1.6:

A

.

OUT

OUT

H=

= 1.05V

:

RSS

mV

I

≥

LIMIT

and double check the assumed TJ in the MOSFET:

P

TJ = 50°C + (2.12W)(50°C/W) = 156°C

Because the top MOSFET is on for such a short time, a
single IRF7811A will be sufficient. Checking its power
dissipation at current limit with ρ

P

BOT

TJ = 50°C + (0.84W)(50°C/W) = 92°C

The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.

CIN is chosen for an RMS current rating of about 6A at
temperature. The output capacitors are chosen for a low
ESR of 0.005Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:

∆V

24 1 52421 7

=

BOT

15

=

1 7 24 21 7 60 300

..

()( )( )( )( )

=+=

046 038 084

OUT(RIPPLE)

186

05 16 0012

...

()()

VVVA

V

.

24

V

...

()

–. .

WWW




2



21 7 1 3 0 012

()()

V A pF kHz

= ∆I

= (4.7A) (0.005Ω) = 24mV

2

A

...

2

L(MAX)

1

+

Ω

2



16 0012 212

()





90°C

()

(ESR)

AA

=

47 18

.

()

2

.. .

Ω

()

= 1.3:

Ω

+

W

=

18

3720f

WUUU

APPLICATIO S I FOR ATIO

LTC3720

However, a 0A to 15A load step will cause an output
change of up to:

∆V

OUT(STEP)

= ∆I

(ESR) = (15A) (0.005Ω) = 75mV

LOAD

The complete circuit is shown in Figure 7.

Active Voltage Positioning

Active voltage positioning (also termed load “deregula­tion” or droop) describes a technique where the output
voltage varies with load in a controlled manner. It is useful
in applications where rapid load steps are the main cause
of error in the output voltage. By positioning the output
voltage above the regulation point at zero load, and below
the regulation point at full load, one can use more of the

INT V

CC

100k

POWER GOOD

BOOST

SENSE

SENSE

PGND

INTV

EXTV

VID4

VID3

VID2

V

SW

BG

V

28

27

TG

26

25

+

24

–

23

22

21

CC

20

IN

19

CC

18

CC

17

16

15

C

ION

0.01µF

C

SS

0.1µF

C

C2

100pF

R

C

V

20k

IN

330k

INT V

C

500pF

C1

C

FB

C2 6.8nF

CC

100pF

10

11

12

13

14

1

2

3

4

5

6

7

8

9

RUN/SS

V

ON

PGOOD

V

RNG

FCB

I

TH

SGND

I

ON

V

FB

SGND

V

FB

V

OSENSE

VID0

VID1

LTC3720

error budget for the load step. This allows one to reduce
the number of output capacitors by relaxing the ESR
requirement.

In the design example, Figure 7, five 0.025Ω capacitors
are required in parallel to keep the output voltage within
tolerance. Using active voltage positioning, the same
specification can be met with only three capacitors. In this
case, the load step will cause an output voltage change of:





∆=

OUT STEP()

R

F

10Ω

C

0.33µF

B

D

B

CMDSH-3

1Ω

4.7µF

6.3V

C

F

0.1µF

IRF7811A

IRF7811A

()

V

IN

7V TO 24V

M1

UPS840

M2

×2

1

.15

0 025 125

()





3





C

IN

10µF
50V
×3

L1

1µH

+

3720 F07

V

1.05V TO 1.825V
15A

C

OUT

270µF
2V
×5

SGND

=VA mV

Ω

OUT

Figure 7. 15A CPU Core Voltage Regulator at 300kHz

3720f

19

LTC3720

WUUU

APPLICATIO S I FOR ATIO

By positioning the output voltage 60mV above the regula­tion point at no load, it will only drop 65mV below the
regulation point after the load step, well within the ±100mV
tolerance.

Implementing active voltage positioning requires setting a
precise gain between the sensed current and the output
voltage. Because of the variability of MOSFET on-resis­tance, it is prudent to use a sense resistor with active
voltage positioning. In order to minimize power lost in this
resistor, a low value is chosen of 0.003Ω. The nominal
sense voltage will now be:

V

SNS(NOM)

= (0.003Ω)(15A) = 45mV

To maintain a reasonable current limit, the voltage on the
V

pin is reduced to its minimum value of 0.5V, corre-

RNG

sponding to a 50mV nominal sense voltage.
Next, the gain of the LTC3720 error amplifier must be

determined. The change in ITH voltage for a corresponding
change in the output current is:



I

∆=

TH





=

()



V

12

RI



V



RNG

24 0 003 15 1 08..

()()

∆

SENSE OUT

Ω

AV

=

Solving for this resistance value:

VI

∆

R

VP

OUT TH

=

Vg V

(. )

08

==

(. )(. )( )

08 17 125

∆

m OUT

VV

(. )(. )

15 108

VmS mV

.

953

k

The gain setting resistance RVP is implemented with two
resistors, R

connected from ITH to ground and R

VP1

VP2

connected from ITH to INTVCC. The parallel combination of
these resistors must equal RVP and their ratio determines
nominal value of the ITH pin voltage when the error
amplifier input is zero. To center the load line around the
regulation point, the ITH pin voltage must be set to corre­spond to half the output current. The relation between I

TH

voltage and the output current is:

I

TH NOM

=

=
=











117



12 1

V

RI I V



V



RNG



12

V

0 003 7 5

()



.

05

V



.

V



∆

SENSE OUT L()

..–..

Ω

–.










2

1

AAV

2



+

08







47 08

+





The corresponding change in the output voltage is deter­mined by the gain of the error amplifier and feedback
divider. The LTC3720 error amplifier has a transconduc­tance gm that is constant over both temperature and a wide
± 40mV input range. Thus, by connecting a load resis­tance RVP to the ITH pin, the error amplifier gain can be
precisely set for accurate active voltage positioning.

∆=

TH m VP






08.

V

OUT



V

∆IgR

V

OUT





Solving for the required values of the resistors:

5

==

R

VP

1

12 44

=

===

R

VP

2

V

5

––.

VI

TH NOM

.

k

55

V

I

TH NOM

()

R

()

R

VP

VP

117

.

5

V

5117

VV

V

953 4073

..

kk

V

953

.

k

3720f

20

WUUU

APPLICATIO S I FOR ATIO

LTC3720

The modified circuit is shown in Figure 8. Figures 9 and 10
show the transient response without and with active
voltage positioning. Both circuits easily stay within ±100mV
of the 1.5V output. However, the circuit with active voltage

INT V

CC

100k

C

SS

R

VP2

40.2k

12.4k

V

IN

R

RNG2

45.3k

330k

POWER GOOD

C

C

C

FB

100pF

180pF

10

11

12

13

14

1

2

3

4

5

6

7

8

9

RUN/SS

V

ON

PGOOD

V

RNG

FCB

I

TH

SGND

I

ON

V

FB

SGND

V

FB

V

OSENSE

VID0

VID1

LTC3720

BOOST

SENSE

SENSE

PGND

INTV

EXTV

VID4

VID3

VID2

V

TG

SW

BG

V

28

27

26

25

+

24

–

23

22

21

CC

20

IN

19

CC

18

CC

17

16

15

INT V

0.1pF

R

RNG1

4.99k

CC

R

VP1

C

ION

0.01µF

positioning accomplishes this with only three output ca­pacitors rather than five. Refer to Linear Technology
Design Solutions 10 for additional information about
active voltage positioning.

V

IN

5V TO 24V

R

F

1Ω

+

C

F

0.1µF

0.33µF

C

B

D

B

CMDSH-3

4.7µF

6.3V

M1
IRF7811A

M2
IRF7811A
×2

R

SENSE

0.003Ω

C

IN

10µF
35V
×3

UPS840

L1

1µH

+

3720 F08

V

OUT

1.05V TO 1.825V
15A

C

OUT

270µF
2V
×3

SGND

Figure 8. 15A CPU Core Voltage Regulator with Active Voltage Positioning at 300kHz

V

OUT

100mV/DIV

1.5V

I

L

10A/DIV

= 5 × 270µF20µs/DIV 3720 F09

C

OUT

VIN = 15V
FIGURE 7 CIRCUIT

Figure 9. Normal Transient Response (C

= 5 × 270µF)

OUT

V

OUT

100mV/DIV

1.5V

I

L

10A/DIV

C

= 3 × 270µF20µs/DIV 3720 F10

OUT

VIN = 15V
FIGURE 8 CIRCUIT

Figure 10. Transient Response with Active
Voltage Positioning (C

= 3 × 270µF)

OUT

3720f

21

LTC3720

WUUU

APPLICATIO S I FOR ATIO

PC Board Layout Checklist

When laying out the printed circuit board, use the follow­ing checklist to ensure proper operation of the controller.
These items are also illustrated in Figure 11.

• Segregate the signal and power grounds. All small

signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
source of M2.

• Place M2 as close to the controller as possible, keeping

the SENSE–, BG and SENSE+ traces short.

•

Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current. Minimize the loop area formed by CIN, M1 and
M2.

INT V

CC

POWER GOOD

1

RUN/SS

C

SS

C

C2

R

C

C

ION

R

ON

V

INT V

C

C1

IN

BOLD LINES INDICATE HIGH CURRENT PATHS

2

V

ON

3

PGOOD

4

V

CC

RNG

5

FCB

6

I

TH

7

SGND

8

I

ON

9

V

FB

10

SGND

11

V

FB

12

V

OSENSE

13

VID0

14

VID1

LTC3720

BOOST

SENSE

SENSE

PGND

INTV

EXTV

VID4

VID3

VID2

SW

BG

V

V

TG

+

–

CC

IN

CC

CC

• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.

• Connect the INTVCC decoupling capacitor C

VCC

closely

to the INTVCC and PGND pins.

• Connect the top driver boost capacitor CB closely to the
BOOST and SW pins.

• Connect the VIN pin decoupling capacitor CF closely to
the VIN and PGND pins.

• VID0-VID4 interface circuitry must return to SGND.

V

IN

R

F

10Ω

C

28

27

26

25

24

23

22

21

20

19

18

17

16

15

B

M1

D

B

M2

+

C

F

C

L1

1µH

D1

IN

V

OUT

+

C

OUT

SGND

3720 F11

22

Figure 11. LTC3720 Layout Diagram

3720f

PACKAGE DESCRIPTIO

LTC3720

U

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.254 MIN

.0075 – .0098

(0.191 – 0.249)

.045 ±.005

.150 – .165

.0250 TYP.0165 ±.0015

RECOMMENDED SOLDER PAD LAYOUT

.015

± .004

×

°

(0.38 ± 0.10)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

45

.229 – .244

(5.817 – 6.198)

.053 – .069

(1.351 – 1.748)

.008 – .012

(0.203 – 0.305)

12

.386 – .393*

(9.804 – 9.982)

202122232425262728

19

5

4

3

678 9 10 11 12

.0250

(0.635)

BSC

16

18

15

17

13 14

(0.102 – 0.249)

.033

(0.838)

REF

.150 – .157**
(3.810 – 3.988)

.004 – .009

GN28 (SSOP) 0502

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3720f

23

LTC3720

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Burst Mode is registered trademark of Linear Technology Corporation.

Synchronous Step-Down Controllers No Sense Resistor Required, 4V ≤ VIN ≤ 36V,

SENSE

Capacitors, Integrated MOSFET Drivers

I

OUT

OUT

Current, 16-Pin SSOP Package

≤ 36V

IN

≤ 36V

IN

≤ 36V

IN

≤ 2V, 3.5V ≤ VIN ≤ 36V

OUT

≤ VIN, Synchronizable to 750kHz

OUT

≤ (0.9) V

OUT

OUT

≤ 60A, Integrated MOSFET Drivers

= 1/2 VIN, I

IN

≤ 2V, VIN up to 36V, 24-Pin GN

up to 15A, 3V ≤ VIN ≤ 8V, 700µA Supply

OUT

24

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

3720f

LT/TP 0203 2K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2002