Page 1
FEATURES
No R
Wide Operating Range,
TM
SENSE
Step-Down Controller
DESCRIPTIO
LTC3711
5-Bit Adjustable,
U
■
5-Bit Programmable Output Voltage: 0.925V to 2V
■
No Sense Resistor Required
■
True Current Mode Control
■
2% to 90% Duty Cycle at 200kHz
■
t
ON(MIN)
■
Supports Active Voltage Positioning
■
Extremely Fast Transient Response
■
Stable with Ceramic C
■
Dual N-Channel MOSFET Synchronous Drive
■
Power Good Output Voltage Monitor
■
Wide VIN Range: 4V to 36V
■
±1% 0.8V Reference
■
Adjustable Current Limit
■
Adjustable Switching Frequency
■
Programmable Soft-Start
■
Output Overvoltage Protection
■
Optional Short-Circuit Shutdown Timer
■
Micropower Shutdown: IQ < 30µA
■
Available in 24-Lead Narrow SSOP Package
< 100ns
OUT
U
APPLICATIO S
■
Power Supplies for Mobile Pentium® Processors
■
Notebook and Palmtop Computers, PDAs
The LTC®3711 is a synchronous step-down switching
regulator controller for CPU power. An output voltage
between 0.925V and 2.000V is selected by a 5-bit code
(Intel mobile VID specification). The controller uses a
valley current control architecture to deliver very low duty
cycles without requiring a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in VIN and V
OUT
.
Discontinuous mode operation provides high efficiency
operation at light loads. A forced continuous control pin
reduces noise and RF interference and can assist secondary winding regulation by disabling discontinuous mode
operation when the main output is lightly loaded.
Fault protection is provided by internal foldback current
limiting, an output overvoltage comparator and optional
short-circuit shutdown timer. Soft-start capability for supply sequencing is accomplished using an external timing
capacitor. The regulator current limit level is user programmable. Wide supply range allows operation from 4V
to 36V at the input.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No R
is a trademark of Linear Technology Corporation.
SENSE
Pentium is a registered trademark of Intel Corporation.
TYPICAL APPLICATIO
R
ON
330k
BOOST
LTC3711
INTV
V
OSENSE
I
V
SW
PGND
ON
IN
TG
CB 0.33µF
D
B
CMDSH-3
CC
BG
+
C
VCC
4.7µF
C
500pF
C
5-BIT VID
PGOOD
C
SS
0.1µF
RUN/SS
I
TH
RC 20k
SGND
VID4
VID3
VID2
VID1
VID0
Figure 1. High Efficiency Step-Down Converter
U
M1
IRF7811A
M2
IRF7811A
×2
L1
1µH
D1
UPS840
V
IN
5V TO 24V
C
IN
22µF
50V
V
×3
OUT
1.5V
C
15A
OUT
+
270µF
2V
×4
: UNITED CHEMICON
C
IN
THCR70EIH226ZT
: CORNELL DUBILIER
C
OUT
ESRE271M02B
L1: SUMIDA CEP125-IROMC
3711 F01a
Efficiency vs Load Current
100
V
= 1.5V
OUT
EXTV
= 5V
CC
90
80
EFFICIENCY (%)
70
60
0.01
0.1
LOAD CURRENT (A)
VIN = 5V
VIN = 15V
1
10
3711 F01b
3711f
1
Page 2
LTC3711
WWWU
ABSOLUTE AXI U RATI GS
(Note 1)
Input Supply Voltage
VIN, ION..................................................36V to –0.3V
Boosted Topside Driver Supply Voltage
BOOST.................................................. 42V to –0.3V
SW, SENSE+ Voltages ................................. 36V to – 5V
EXTVCC, (BOOST – SW), RUN/SS,
VID0-VID4, PGOOD Voltages..................... 7V to –0.3V
FCB, VON, V
ITH, VFB, V
TG, BG, INTVCC, EXTVCC Peak Currents.................... 2A
TG, BG, INTVCC, EXTVCC RMS Currents .............. 50mA
Operating Ambient Temperature Range
LTC3711EGN (Note 2) ........................ –40°C to 85°C
Junction Temperature (Note 3)............................ 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
Voltages .......... INTVCC + 0.3V to –0.3V
RNG
OSENSE
Voltages....................... 2.7V to –0.3V
UU
W
PACKAGE/ORDER I FOR ATIO
TOP VIEW
VID2
RUN/SS
V
ON
PGOOD
V
RNG
FCB
I
TH
SGND
I
ON
10
V
FB
V
11
OSENSE
12
VID3
24-LEAD PLASTIC SSOP
T
JMAX
1
2
3
4
5
6
7
8
9
GN PACKAGE
= 125°C, θJA = 130°C/W
VID1
24
VID0
23
BOOST
22
TG
21
SW
20
19
18
17
16
15
14
13
SENSE
PGND
BG
INTV
V
IN
EXTV
VID4
+
CC
CC
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ORDER PART
NUMBER
LTC3711EGN
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
I
Q
V
FB
∆V
FB(LINEREG)
∆V
FB(LOADREG)
I
FB
g
m(EA)
V
FCB
I
FCB
t
ON
t
ON(MIN)
t
OFF(MIN)
V
SENSE(MAX)
V
SENSE(MIN)
∆V
FB(OV)
V
FB(UV)
Input DC Supply Current
Normal 900 2000 µA
Shutdown Supply Current 15 30 µA
Feedback Reference Voltage ITH = 1.2V (Note 4) ● 0.792 0.800 0.808 V
Feedback Voltage Line Regulation VIN = 4V to 30V, ITH = 1.2V (Note 4) 0.002 %/V
Feedback Voltage Load Regulation ITH = 0.5V to 1.9V (Note 4) ● –0.05 –0.3 %
Feedback Input Current VFB = 0.8V –5 ±50 nA
Error Amplifier Transconductance ITH = 1.2V (Note 4) ● 1.4 1.7 2 mS
Forced Continuous Threshold ● 0.76 0.8 0.84 V
Forced Continuous Pin Current V
= 0.8V –1 –2 µA
FCB
On-Time ION = 60µA, VON = 1.5V 212 250 288 ns
I
= 30µA, VON = 1.5V 425 500 575 ns
ON
Minimum On-Time ION = 180µA, VON = 0V 50 100 ns
Minimum Off-Time ION = 60µA, VON = 1.5V 250 400 ns
Maximum Current Sense Threshold V
V
PGND
– V
SENSE
+
Minimum Current Sense Threshold V
V
PGND
– V
SENSE
+
= 1V, VFB = 0.76V 113 133 153 mV
RNG
V
= 0V, VFB = 0.76V ● 79 93 107 mV
RNG
= INTVCC, VFB = 0.76V 158 186 214 mV
V
RNG
= 1V, VFB = 0.84V –67 mV
RNG
V
= 0V, VFB = 0.84V –47 mV
RNG
V
= INTVCC, VFB = 0.84V –93 mV
RNG
Output Overvoltage Fault Threshold 5.5 7.5 9.5 %
Output Undervoltage Fault Threshold 520 600 680 mV
3711f
2
Page 3
LTC3711
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
RUN/SS(ON)
V
RUN/SS(LE)
V
RUN/SS(LT)
I
RUN/SS(C)
I
RUN/SS(D)
V
IN(UVLO)
V
IN(UVLOR)
TG R
UP
TG R
DOWN
BG R
UP
BG R
DOWN
TG t
r
TG t
f
BG t
r
BG t
f
Internal VCC Regulator
V
INTVCC
∆V
LDO(LOADREG)
V
EXTVCC
∆V
EXTVCC
∆V
EXTVCC(HYS)
PGOOD Output
∆V
FBH
∆V
FBL
∆V
FB(HYS)
V
PGL
VID DAC
V
VID(T)
I
VID(PULLUP)
V
VID(PULLUP)
I
VID(LEAK)
R
VID
∆V
OSENSE
RUN Pin Start Threshold ● 0.8 1.5 2 V
RUN Pin Latchoff Enable Threshold RUN/SS Pin Rising 4 4.5 V
RUN Pin Latchoff Threshold RUN/SS Pin Falling 3.5 4.2 V
Soft-Start Charge Current V
Soft-Start Discharge Current V
= 0V –0.5 –1.2 –3 µA
RUN/SS
= 4.5V, VFB = 0V 0.8 1.8 3 µA
RUN/SS
Undervoltage Lockout VIN Falling ● 3.4 3.9 V
Undervoltage Lockout Release VIN Rising ● 3.5 4 V
TG Driver Pull-Up On Resistance TG High 2 3 Ω
TG Driver Pull-Down On Resistance TG Low 2 3 Ω
BG Driver Pull-Up On Resistance BG High 3 4 Ω
BG Driver Pull-Down On Resistance BG Low 1 2 Ω
TG Rise Time C
TG Fall Time C
BG Rise Time C
BG Fall Time C
Internal VCC Voltage 6V < VIN < 30V, V
Internal VCC Load Regulation ICC = 0mA to 20mA, V
EXTVCC Switchover Voltage ICC = 20mA, V
EXTVCC Switch Drop Voltage ICC = 20mA, V
= 3300pF 20 ns
LOAD
= 3300pF 20 ns
LOAD
= 3300pF 20 ns
LOAD
= 3300pF 20 ns
LOAD
= 4V ● 4.7 5 5.3 V
EXTVCC
= 4V –0.1 ±2%
EXTVCC
Rising ● 4.5 4.7 V
EXTVCC
= 5V 150 300 mV
EXTVCC
EXTVCC Switchover Hysteresis 200 mV
PGOOD Upper Threshold VFB Rising 5.5 7.5 9.5 %
PGOOD Lower Threshold VFB Falling – 5.5 – 7.5 – 9.5 %
PGOOD Hysteresis VFB Returning 1 2 %
PGOOD Low Voltage I
= 5mA 0.15 0.4 V
PGOOD
VID0-VID4 Logic Threshold Voltage 0.4 1.2 2 V
VID0-VID4 Pull-Up Current V
VID0-VID4 Pull-Up Voltage V
VID0-VID4 Leakage Current V
Resistance from V
OSENSE
to V
FB
DAC Output Accuracy V
to V
VID0
VID0
VID0
= 0V –2.5 µA
VID4
to V
Open 4.5 V
VID4
to V
VID4
= 5V, V
= 0V 0.01 1 µA
RUN/SS
61014 KΩ
Programmed from –0.25 0 0.25 %
OSENSE
0.925V to 2V (Note 5)
Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.
Note 2: The LTC3711E is guaranteed to meet performance specifications from
0°C to 70°C. Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with statistical
process controls.
Note 3: T
dissipation P
is calculated from the ambient temperature TA and power
J
as follows:
D
LTC3711EGN: T
= TA + (PD • 130°C/W)
J
Note 4: The LTC3711 is tested in a feedback loop that adjusts V
a specified error amplifier output voltage (I
).
TH
to achieve
FB
Note 5: The LTC3711 VID DAC is tested in a feedback loop that adjusts
to achieve a specified feedback voltage (VFB = 0.8V) for each DAC VID
V
OSENSE
code.
3711f
3
Page 4
LTC3711
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Transient Response
V
OUT
50mV/DIV
10A/DIV
Transient Response
I
L
50mV/DIV
(Discontinuous Mode)
V
OUT
I
L
10A/DIV
RUN/SS
2V/DIV
V
OUT
1V/DIV
10A/DIV
Start-Up
I
L
LOAD STEP = 0A TO 15A
V
= 15V
IN
= 1.5V
V
OUT
FCB = 0V
FIGURE 9 CIRCUIT
20µs/DIV
3711 G01
LOAD STEP = 1A TO 15A
V
= 15V
IN
= 1.5V
V
OUT
FCB = INTV
FIGURE 9 CIRCUIT
20µs/DIV 3711 G02
CC
VIN = 15V
V
= 1.5V
OUT
R
= 0.1Ω
LOAD
FIGURE 9 CIRCUIT
50ms/DIV 3711 G03
Efficiency vs Load Current Efficiency vs Input Voltage Frequency vs Load Current
100
90
80
70
EFFICIENCY (%)
60
50
0.001
DISCONTINUOUS
MODE
0.01
0.1
LOAD CURRENT (A)
CONTINUOUS
MODE
VIN = 15V
V
= 1.5V
OUT
= 5V
EXTV
CC
FIGURE 9 CIRCUIT
1
3711 G04
100
FIGURE 9 CIRCUIT
FCB = 5V
95
EXTV
= 5V
CC
90
85
EFFICIENCY (%)
80
75
10
70
I
LOAD
5 10 15 20 25 30
0
INPUT VOLTAGE (V)
= 15A
I
LOAD
= 1.5A
3711 G05
350
300
250
200
150
FREQUENCY (kHz)
100
50
0
2 4 6 8 10
0
CONTINUOUS MODE
DISCONTINUOUS MODE
LOAD CURRENT (A)
Current Sense Threshold
Frequency vs Input Voltage ITH Voltage vs Load Current
350
FIGURE 9 CIRCUIT
FCB = 0V
325
300
275
250
FREQUENCY (kHz)
225
I
I
OUT
OUT
= 15A
= 0A
2.5
FIGURE 9 CIRCUIT
FCB = 0V
2.0
1.5
VOLTAGE (V)
1.0
TH
I
0.5
vs ITH Voltage
300
200
100
0
–100
CURRENT SENSE THRESHOLD (mV)
FIGURE 9 CIRCUIT
3711 G06
RNG
2V
=
1.4V
1V
0.7V
0.5V
V
4
200
5
10 15 20 25
INPUT VOLTAGE (V)
3711 G07
0
5 10 15 20 25
0
LOAD CURRENT (A)
3711 G09
–200
0
1.0 1.5 2.0
0.5
ITH VOLTAGE (V)
2.5 3.0
3711 G10
3711f
Page 5
UW
TEMPERATURE (°C)
–50
ON-TIME (ns)
200
250
300
25 75
3711 G13
150
100
–25 0
50 100 125
50
0
I
ION
= 30µA
V
VON
= 0V
RUN/SS VOLTAGE (V)
1.5
0
MAXIMUM CURRENT SENSE THRESHOLD (mV)
25
50
75
100
125
150
V
RNG
= 1V
2 2.5 3 3.5
3711 G16
TYPICAL PERFOR A CE CHARACTERISTICS
LTC3711
On-Time vs ION Current
10k
1k
ON-TIME (ns)
100
10
1
ION CURRENT (µA)
Current Limit Foldback
150
125
100
= 1V
V
RNG
75
V
= 0V
VON
10 100
3711 G11
On-Time vs VON Voltage
1000
ON-TIME (ns)
800
600
400
200
= 30µA
I
ION
0
0
1
VON VOLTAGE (V)
Maximum Current Sense
Threshold vs V
300
250
200
150
RNG
2
Voltage
On-Time vs Temperature
3
3711 G12
Maximum Current Sense
Threshold vs RUN/SS Voltage
50
25
MAXIMUM CURRENT SENSE THRESHOLD (mV)
0
0
0.2 0.4 0.6 0.8
VFB (V)
Maximum Current Sense
Threshold vs Temperature
150
V
= 1V
RNG
140
130
120
110
MAXIMUM CURRENT SENSE THRESHOLD (mV)
100
–50 –25
0
TEMPERATURE (°C)
100
50
MAXIMUM CURRENT SENSE THRESHOLD (mV)
3711 G14
0
0.5
0.75
1.0 1.25 1.5
V
VOLTAGE (V)
RNG
1.75 2.0
3711 G15
Feedback Reference Voltage
vs Temperature
0.82
0.81
0.80
0.79
FEEDBACK REFERENCE VOLTAGE (V)
50
25
75
100
125
3711 G17
0.78
–50
–25 0 25 50
TEMPERATURE (°C)
75 100 125
3711 G18
3711f
5
Page 6
LTC3711
TEMPERATURE (
°C)
–50 –25
–2
FCB PIN CURRENT (µA)
0
3
0
50
75
3711 G24
–1
2
1
25
100
125
PULL-UP CURRENT
PULL-DOWN CURRENT
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Input and Shutdown Currents
Error Amplifier gm vs Temperature
2.0
1.8
vs Input Voltage
1200
1000
EXTVCC OPEN
INTVCC Load Regulation
60
50
SHUTDOWN CURRENT (µA)
0
–0.1
1.6
(mS)
m
g
1.4
1.2
1.0
–50 –25
25
0
TEMPERATURE (°C)
EXTVCC Switch Resistance
vs Temperature
10
8
6
4
SWITCH RESISTANCE (Ω)
CC
2
EXTV
800
600
400
INPUT CURRENT (µA)
200
0
50
75
100
125
3711 G19
0
510
SHUTDOWN
EXTVCC = 5V
20 30 35
15 25
INPUT VOLTAGE (V)
3711 G20
40
30
20
10
0
–0.2
(%)
CC
–0.3
∆INTV
–0.4
–0.5
10
0
INTVCC LOAD CURRENT (mA)
30
40
20
50
3711 G21
RUN/SS Pin Current
FCB Pin Current vs Temperature
0
–0.25
–0.50
–0.75
–1.00
FCB PIN CURRENT (µA)
–1.25
vs Temperature
0
–50 –25
RUN/SS THRESHOLD (V)
6
0
TEMPERATURE (°C)
75
100
50
25
RUN/SS Latchoff Thresholds
vs Temperature
5.0
4.5
LATCHOFF ENABLE
4.0
3.5
3.0
–50
LATCHOFF THRESHOLD
–25 0 25 50
TEMPERATURE (°C)
125
3711 G22
75 100 125
3711 G25
–1.50
–50
–25 0
50 100 125
25 75
TEMPERATURE (°C)
3711 G23
Undervoltage Lockout Threshold
vs Temperature
4.0
3.5
3.0
2.5
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
2.0
–50
–25 0 25 50
TEMPERATURE (C)
75 100 125
3711 G26
3711f
Page 7
LTC3711
U
UU
PI FU CTIO S
VID0-VID4 (Pins 23, 24, 1, 12, 13): VID Digital Inputs.
The voltage identification (VID) code sets the internal
feedback resistor divider ratio for different output voltages
as shown in Table 1. If unconnected, the pins are pulled
high by internal 2.5µA current sources.
RUN/SS (Pin 2): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.
VON (Pin 3): On-Time Voltage Input. Voltage trip point for
the on-time comparator. Tying this pin to the output
voltage makes the on-time proportional to V
comparator input defaults to 0.7V when the pin is grounded,
2.4V when the pin is tied to INTVCC.
PGOOD (Pin 4): Power Good Output. Open drain logic
output that is pulled to ground when the output voltage is
not within ±7.5% of the regulation point.
V
(Pin 5): Sense Voltage Range Input. The voltage at
RNG
this pin is ten times the nominal sense voltage at maximum output current and can be set from 0.5V to 2V by a
resistive divider from INTVCC. The nominal sense voltage
defaults to 70mV when this pin is tied to ground, 140mV
when tied to INTVCC.
OUT
. The
VFB (Pin 10): Error Amplifier Feedback Input. This pin
connects to both the error amplifier input and to the output
of the internal resistive divider. It can be used to attach
additional compensation components if desired.
V
voltage connects here to the input of the internal resistive
feedback divider.
EXTVCC (Pin 14): External VCC Input. When EXTVCC ex-
ceeds 4.7V, an internal switch connects this pin to INTV
and shuts down the internal regulator so that controller
and gate drive power is drawn from EXTVCC. Do not exceed
7V at this pin and ensure that EXTVCC < VIN.
VIN (Pin 15): Main Input Supply. Decouple this pin to
PGND with an RC filter (1Ω, 0.1µF).
INTVCC (Pin 16): Internal 5V Regulator Output. The driver
and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum of 4.7µF
low ESR tantalum capacitor.
BG (Pin 17): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.
PGND (Pin 18): Power Ground. Connect this pin closely to
the source of the bottom N-channel MOSFET, the (–)
terminal of C
(Pin 11): Output Voltage Sense. The output
OSENSE
and the (–) terminal of CIN.
VCC
CC
FCB (Pin 6): Forced Continuous Input. Tie this pin to
ground to force continuous synchronous operation at low
load, to INTVCC to enable discontinuous mode operation
at low load or to a resistive divider from a secondary output
when using a secondary winding.
I
(Pin 7): Current Control Threshold and Error Amplifier
TH
Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 0.8V corresponding to zero sense
voltage (zero current).
SGND (Pin 8): Signal Ground. All small-signal components and compensation components should connect to
this ground, which in turn connects to PGND at one point.
ION (Pin 9): On-Time Current Input. Tie a resistor from V
to this pin to set the one-shot timer current and thereby set
the switching frequency.
IN
SENSE+ (Pin 19): Current Sense Comparator Input. The
(+) input to the current comparator is normally connected
to the SW node unless using a sense resistor (see Applications Information).
SW (Pin 20): Switch Node. The (–) terminal of the bootstrap capacitor CB connects here. This pin swings from a
diode voltage drop below ground up to VIN.
TG (Pin 21): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superimposed on the switch node voltage SW.
BOOST (Pin 22): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below INTVCC up to
V
+ INTVCC.
IN
3711f
7
Page 8
LTC3711
U
U
W
FU CTIO AL DIAGRA
R
ON
0.7V
V
3
1
OST
tON = (10pF)
1.4V
V
RNG
5
0.7V
ON
2.4V
V
VON
I
ION
I
CMP
I
9
ON
R
SQ
20k
+
–
+
–
×
I
1µA
REV
V
IN
V
0.8V
REF
5V
REG
BOOST
22
TG
21
SW
20
SENSE
19
INTV
16
BG
17
PGND
18
PGOOD
4
15
IN
+
C
IN
C
B
M1
+
D
B
CC
L1
+
C
C
VCC
M2
OUT
FCB
6
–
F
0.8V
+
4.7V
+
–
FCNT
SHDN
ON
OV
14
EXTV
SWITCH
LOGIC
CC
1
240k
I
THB
+
–
×4
0.8V
3.3µA
V
OSENSE
11
0.74V
Q2
Q4
Q6
Q3
Q1
EA
–
+
0.8V
1V
Q5
0.6V
RUN
SHDN
2
RUN/SS
SS
–
+
+
–
0.6V
C
I
7
C1
TH
R
C
UV
OV
1.2µA
+
–
+
0.86V
–
6V
C
SS
FB
R2
10k
×5 (ALL VID PINS)
INTV
CC
VID
DAC
10 8
R1
2.5µA
23
24
1
12
13
SGNDV
3711 FD
VID0
VID1
VID2
VID3
VID4
3711f
8
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OPERATIO
LTC3711
U
Main Control Loop
The LTC3711 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by a
one-shot timer OST. When the top MOSFET is turned off,
the bottom MOSFET is turned on until the current comparator I
initiating the next cycle. Inductor current is determined
by sensing the voltage between the PGND and SENSE
pins using either the bottom MOSFET on-resistance or an
optional sense resistor. The voltage on the ITH pin sets the
comparator threshold corresponding to inductor valley
current. The error amplifier EA adjusts this voltage by
comparing the feedback signal VFB from the output
voltage with an internal 0.8V reference. The feedback
voltage is derived from the output voltage by a resistive
divider DAC that is set by the VID code pins VID0-VID4.
If the load current increases, it causes a drop in the
feedback voltage relative to the reference. The ITH voltage
then rises until the average inductor current again matches
the load current.
trips, restarting the one-shot timer and
CMP
+
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±7.5% window around the regulation point.
Furthermore, in an overvoltage condition, M1 is turned
off and M2 is turned on and held on until the overvoltage
condition clears.
Foldback current limiting is provided if the output is
shorted to ground. As VFB drops, the buffered current
threshold voltage I
level set by Q4 and Q6. This reduces the inductor valley
current level to one sixth of its maximum value as V
approaches 0V.
Pulling the RUN/SS pin low forces the controller into its
shutdown state, turning off both M1 and M2. Releasing
the pin allows an internal 1.2µA current source to charge
up an external soft-start capacitor CSS. When this voltage
reaches 1.5V, the controller turns on and begins switching, but with the ITH voltage clamped at approximately
0.6V below the RUN/SS voltage. As CSS continues to
charge, the soft-start current limit is removed.
is pulled down by clamp Q3 to a 1V
THB
FB
At low load currents, the inductor current can drop to zero
and become negative. This is detected by current reversal
comparator I
discontinuous operation. Both switches will remain off
with the output capacitor supplying the load current until
the ITH voltage rises above the zero current level (0.8V) to
initiate another cycle. Discontinuous mode operation is
disabled by comparator F when the FCB pin is brought
below 0.8V, forcing continuous synchronous operation.
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in VIN and V
with an external resistor RON.
which then shuts off M2, resulting in
REV
. The nominal frequency can be adjusted
OUT
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is recharged from INTVCC through an external Schottky diode
DB when the top MOSFET is turned off. When the EXTV
pin is grounded, an internal 5V low dropout regulator
supplies the INTVCC power from VIN. If EXTVCC rises
above 4.7V, the internal regulator is turned off, and an
internal switch connects EXTVCC to INTVCC. This allows
a high efficiency source connected to EXTVCC, such as an
external 5V supply or a secondary output from the
converter, to provide the INTVCC power. Voltages up to
7V can be applied to EXTVCC for additional gate drive. If
the input voltage is low and INTVCC drops below 3.5V,
undervoltage lockout circuitry prevents the power
switches from turning on.
CC
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APPLICATIO S I FOR ATIO
The basic LTC3711 application circuit is shown in
Figure 1. External component selection is primarily determined by the maximum load current and begins with
the selection of the sense resistance and power MOSFET
switches. The LTC3711 can use either a sense resistor or
the on-resistance of the synchronous power MOSFET for
determining the inductor current. The desired amount of
ripple current and operating frequency largely determines the inductor value. Finally, CIN is selected for its
ability to handle the large RMS current into the converter
and C
is chosen with low enough ESR to meet the
OUT
output voltage ripple and transient specification.
Maximum Sense Voltage and V
RNG
Pin
Inductor current is determined by measuring the voltage
across a sense resistance that appears between the PGND
and
SENSE+ pins. The maximum sense voltage is set by
the voltage applied to the V
approximately (0.133)V
RNG
pin and is equal to
RNG
. The current mode control
loop will not allow the inductor current valleys to exceed
(0.133)V
RNG/RSENSE
. In practice, one should allow some
margin for variations in the LTC3711 and external component values and a good guide for selecting the sense
resistance is:
V
R
SENSE
=
10 •
RNG
I
OUT MAX
()
An external resistive divider from INTVCC can be used to
set the voltage of the V
pin between 0.5V and 2V
RNG
resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the V
pin can be tied to SGND or INTV
RNG
CC
in which case the nominal sense voltage defaults to 70mV
or 140mV, respectively. The maximum allowed sense
voltage is about 1.33 times this nominal value.
Connecting the SENSE+ Pin
The LTC3711 can be used with or without a sense resistor.
When using a sense resistor, it is placed between the
source of the bottom MOSFET M2 and ground. Connect
the
SENSE+ pin to the source of the bottom MOSFET so
that the resistor appears between the
SENSE+ and PGND
pins. Using a sense resistor provides a well defined
current limit, but adds cost and reduces efficiency. Alternatively, one can eliminate the sense resistor and use the
bottom MOSFET as the current sense element by simply
connecting the SE
NSE+ pin to the switch node SW at the
drain of the bottom MOSFET. This improves efficiency, but
one must carefully choose the MOSFET on-resistance as
discussed below.
Power MOSFET Selection
The LTC3711 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V
threshold voltage V
transfer capacitance C
, on-resistance R
(GS)TH
and maximum current I
RSS
DS(ON)
(BR)DSS
, reverse
DS(MAX)
,
.
The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3711 applications. If the input voltage is
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be considered.
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its onresistance. MOSFET on-resistance is typically specified
with a maximum value R
DS(ON)(MAX)
at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
R
R
DS ON MAX
()( )
=
SENSE
ρ
T
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 2. For a maximum temperature of 100°C, using a
value ρT = 1.3 is reasonable.
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
the load current. When the LTC3711 is operating in
continuous mode, the duty cycles for the MOSFETs are:
V
D
D
TOP
BOT
OUT
=
V
IN
–
VV
IN OUT
=
V
IN
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APPLICATIO S I FOR ATIO
2.0
1.5
LTC3711
Tying a resistor RON from VIN to the ION pin yields an ontime inversely proportional to VIN. For a step-down converter, this results in approximately constant frequency
operation as the input supply varies:
1.0
0.5
NORMALIZED ON-RESISTANCE
T
ρ
0
–50
Figure 2. R
0
JUNCTION TEMPERATURE (°C)
50
vs. Temperature
DS(ON)
100
150
3711 F02
The resulting power dissipation in the MOSFETs at maximum output current are:
P
P
TOP
BOT
= D
TOP IOUT(MAX)
+ k V
= D
IN
BOT IOUT(MAX)
2
I
2
ρ
T(TOP) RDS(ON)(MAX)
OUT(MAX) CRSS
2
ρ
T(BOT) RDS(ON)(MAX)
f
Both MOSFETs have I2R losses and the top MOSFET
includes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottom MOSFET losses are greatest when the bottom duty
cycle is near 100%, during a short-circuit or at high input
voltage.
V
f
=
VR pF
OUT
VON ON
()10
Hz
[]
To hold frequency constant during output voltage changes,
tie the VON pin to V
. Figure 3 shows how frequency
OUT
varies with RON in this case. The VON pin has internal
clamps that limit its input to the one-shot timer. If the pin
is tied below 0.7V, the input to the one-shot is clamped at
0.7V. Similarly, if the pin is tied above 2.4V, the input is
clamped at 2.4V.
1000
SWITCHING FREQUENCY (kHz)
10
100
RON (kΩ)
Figure 3. Switching Frequency vs RON with VON Tied to V
1000
3711 F03
OUT
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The operating frequency of LTC3711 applications is determined implicitly by the one-shot timer that controls the
on-time tON of the top MOSFET switch. The on-time is set
by the current into the ION pin and the voltage at the V
ON
pin according to:
V
t
ON
VON
= ()10
I
ION
pF
Because the voltage at the ION pin is about 0.7V, the
current into this pin is not exactly inversely proportional to
VIN, especially in applications with lower input voltages.
To correct for this error, an additional resistor R
ON2
connected from the ION pin to the 5V INTVCC supply will
further stabilize the frequency.
V
07=.
5
R
V
R
ON ON2
Changes in the load current magnitude will also cause
frequency shift. Parasitic resistance in the MOSFET
switches and inductor reduce the effective voltage across
the inductance, resulting in increased duty cycle as the
load current increases. By lengthening the on-time slightly
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LTC3711
∆=
−
I
V
fL
V
V
L
OUT OUT
IN
1
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APPLICATIO S I FOR ATIO
R
VON1
30k
V
OUT
R
VON2
100k
R
C
C
C
C
VON
0.01µF
V
ON
LTC3711
I
TH
3711 F04a
(4a)
Figure 4. Correcting Frequency Shift with Load Current Changes
as current increases, constant frequency operation can be
maintained. This is accomplished with a resistive divider
from the ITH pin to the VON pin and V
. The values
OUT
required will depend on the parasitic resistances in the
specific application. A good starting point is to feed about
25% of the voltage change at the ITH pin to the VON pin as
shown in Figure 4a. Place capacitance on the VON pin to
filter out the ITH variations at the switching frequency. The
resistor load on ITH reduces the DC gain of the error amp
and degrades load regulation, which can be avoided by
using the PNP emitter follower of Figure 4b.
Minimum Off-time and Dropout Operation
R
VON1
V
INTV
OUT
3k
R
VON2
10k
10k
CC
Q1
2N5087
C
VON
0.01µF
R
C
C
C
V
ON
LTC3711
I
TH
3711 F04b
(4b)
2.0
1.5
1.0
0.5
SWITCHING FREQUENCY (MHz)
0
0 0.25 0.50 0.75
DUTY CYCLE (V
DROPOUT
REGION
OUT/VIN
)
1.0
3711 F05
Figure 5. Maximum Switching Frequency vs Duty Cycle
The minimum off-time t
OFF(MIN)
is the smallest amount of
time that the LTC3711 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 250ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON + t
OFF(MIN)
). If the maximum duty cycle is reached,
due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:
tt
+
VV
IN MIN OUT
=
()
ON OFF MIN
t
ON
()
A plot of maximum duty cycle vs frequency is shown in
Figure 5.
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
Lower ripple current reduces cores losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
A reasonable starting point is to choose a ripple current
that is about 40% of I
OUT(MAX)
. The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:
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APPLICATIO S I FOR ATIO
LTC3711
L
V
=
fI
∆
OUT
() ()
L MAX
V
−
1
V
IN MAX
OUT
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ® cores. A variety of inductors designed for high
current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft
and Toko.
Schottky Diode D1 Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
of the bottom MOSFET from turning on and storing charge
during the dead time, which can cause a modest (about
1%) efficiency loss. The diode can be rated for about one
half to one fifth of the full load current since it is on for only
a fraction of the duty cycle. In order for the diode to be
effective, the inductance between it and the bottom MOSFET
must be as small as possible, mandating that these
components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable.
CIN and C
Selection
OUT
The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
V
II
≅
RMS OUT MAX
()
OUT
V
IN
This formula has a maximum at VIN = 2V
I
RMS
= I
OUT(MAX)
/2. This simple worst-case condition is
V
V
IN
OUT
–1
OUT
, where
commonly used for design because even significant
deviations do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often
based on only 2000 hours of life which makes it advisable
to derate the capacitor.
Kool Mµ is a registered trademark of Magnetics, Inc.
The selection of C
is primarily determined by the ESR
OUT
required to minimize voltage ripple and load step
transients. The output ripple ∆V
is approximately
OUT
bounded by:
∆≤∆ +
V I ESR
OUT L
8
fC
1
OUT
Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to significant ringing. When used as input capacitors, care must be
taken to ensure that ringing from inrush currents and
switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5µF to 50µF aluminum electrolytic
capacitor with an ESR in the range of 0.5Ω to 2Ω. High
performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance.
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode DB from INTV
CC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises
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APPLICATIO S I FOR ATIO
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications a 0.1µF to 0.47µF X5R
or X7R dielectric capacitor is adequate.
Discontinuous Mode Operation and FCB Pin
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.8V threshold enables discontinuous
operation where the bottom MOSFET turns off when
inductor current reverses. The load current at which
current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and
will vary with changes in VIN. Tying the FCB pin below the
0.8V threshold forces continuous synchronous operation,
allowing current to reverse at light loads and maintaining
high frequency operation.
In addition to providing a logic input to force continuous
operation, the FCB pin provides a means to maintain a
flyback winding output when the primary is operating in
discontinuous mode. The secondary output V
SEC
is normally set as shown in Figure 6 by the turns ratio N of the
transformer. However, if the controller goes into discontinuous mode and halts switching due to a light primary
load current, then V
divider from V
V
OUT2(MIN)
until V
OUT2
VV
OUT MIN2
OPTIONAL
EXTV
CONNECTION
5V < V
OUT2
OUT2
below which continuous operation is forced
has risen above its minimum.
()
CC
< 7V
08 1
EXTV
R4
FCB
R3
SGND
will droop. An external resistor
OUT2
to the FCB pin sets a minimum voltage
R
4
.=+
LTC3711
CC
SENSE
PGND
V
SW
BG
R
3
V
IN
+
C
IN
TG
+
IN
1N4148
V
•
•
T1
+
1:N
OUT2
+
C
OUT2
1µF
V
OUT
C
OUT
3711 F06
Fault Conditions: Current Limit and Foldback
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the LTC3711, the maximum sense voltage is controlled by
the voltage on the V
pin. With valley current control,
RNG
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
V
SNS MAX
I
=+∆
LIMIT
()
R
DS ON T
()
ρ12
I
L
The current limit value should be checked to ensure that
I
LIMIT(MIN)
> I
OUT(MAX)
. The minimum value of current limit
generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of I
which heats
LIMIT
the MOSFET switches.
Caution should be used when setting the current limit
based upon the R
of the MOSFETs. The maximum
DS(ON)
current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and
maximum values for R
reasonable assumption is that the minimum R
, but not a minimum. A
DS(ON)
DS(ON)
lies
the same amount below the typical value as the maximum
lies above it. Consult the MOSFET manufacturer for further
guidelines.
To further limit current in the event of a short circuit to
ground, the LTC3711 includes foldback current limiting. If
the output falls by more than 25%, then the maximum
sense voltage is progressively lowered to about one sixth
of its full value.
Figure 6. Secondary Output Loop and EXTVCC Connection
14
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LTC3711
Output Voltage Programming
The output voltage is digitally set to levels between 0.900V
and 2.000V using the voltage identification (VID) inputs
VID0-VID4. An internal 5-bit DAC configured as a precision resistive voltage divider sets the output voltage in
increments according to Table 1. The VID codes are
compatible with Intel Mobile Pentium III processor specifications. Each VID input is pulled up by an internal 2.5µA
current source from the INTVCC supply and includes a
series diode to prevent damage from VID inputs that
exceed the supply.
INTVCC Regulator
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3711. The INTVCC pin can supply up to
50mA RMS and must be bypassed to ground with a
minimum of 4.7µF low ESR tantalum capacitor. Good
bypassing is necessary to supply the high transient currents required by the MOSFET gate drivers. Applications
using large MOSFETs with a high input voltage and high
frequency of operation may cause the LTC3711 to exceed
its maximum junction temperature rating or RMS current
rating. Most of the supply current drives the MOSFET
gates unless an external EXTVCC source is used. In continuous mode operation, this current is I
+ Q
). The junction temperature can be estimated
g(BOT)
GATECHG
= f(Q
g(TOP)
from the equations given in Note 2 of the Electrical
Characteristics. For example, the LTC3711CGN is limited
to less than 14mA from a 30V supply:
TJ = 70°C + (14mA)(30V)(130°C/W) = 125°C
For larger currents, consider using an external supply with
the EXTVCC pin.
Table 1. VID Output Voltage Programming
VID4 VID3 VID2 VID1 VID0 V
000002.000V
000011.950V
000101.900V
000111.850V
001001.800V
001011.750V
001101.700V
001111.650V
010001.600V
010011.550V
010101.500V
010111.450V
011001.400V
011011.350V
011101.300V
01111 *
100001.275V
100011.250V
100101.225V
100111.200V
101001.175V
101011.150V
101101.125V
101111.100V
110001.075V
110011.050V
110101.025V
110111.000V
111000.975V
111010.950V
111100.925V
11111 **
Note: *, ** represent codes without a defined output voltage as specified by
Intel. The LTC3711 interprets these codes as valid inputs and
voltages as follows: [01111] = 1.250V, [11111] = 0.900V.
produces output
OUT
(V)
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EXTVCC Connection
The EXTVCC pin can be used to provide MOSFET gate drive
and control power from the output or another external
source during normal operation. Whenever the EXTV
pin is above 4.7V the internal 5V regulator is shut off and
an internal 50mA P-channel switch connects the EXTV
pin to INTVCC. INTVCC power is supplied from EXTVCC until
this pin drops below 4.5V. Do not apply more than 7V to
the EXTVCC pin and ensure that EXTVCC ≤ VIN. The following list summarizes the possible connections for EXTVCC:
1. EXTVCC grounded. INTV
internal 5V regulator.
2. EXTVCC connected to an external supply. A high efficiency supply compatible with the MOSFET gate drive
requirements (typically 5V) can improve overall
efficiency.
3. EXTVCC connected to an output derived boost network.
The low voltage output can be boosted using a charge
pump or flyback winding to greater than 4.7V. The system
will start-up using the internal linear regulator until the
boosted output supply is available.
is always powered from the
CC
CC
CC
15
V
t
DELAY SS SS
When the voltage on RUN/SS reaches 1.5V, the LTC3711
begins operating with a clamp on ITH of approximately
0.9V. As the RUN/SS voltage rises to 3V, the clamp on I
is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF, during which the load current is folded
back until the output reaches 75% of its final value. The pin
can be driven from logic as shown in Figure 8. Diode D1
reduces the start delay while allowing CSS to charge up
slowly for the soft-start function.
After the controller has been started and given adequate
time to charge up the output capacitor, CSS is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8µA cur-
rent then begins discharging CSS. If the fault condition
persists until the RUN/SS pin drops to 3.5V, then the controller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.
=
.
12
.
µ
=µ
CsFC
A
13
./
()
TH
External Gate Drive Buffers
The LTC3711 drivers are adequate for driving up to about
30nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
frequencies requiring greater RMS currents will benefit
from using external gate drive buffers such as the LTC1693.
Alternately, the external buffer circuit shown in Figure 7
can be used. Note that the bipolar devices reduce the
signal swing at the MOSFET gate and benefit from an
increased EXTVCC voltage of about 6V.
Soft-Start and Latchoff with the RUN/SS Pin
The RUN/SS pin provides a means to shut down the
LTC3711 as well as a timer for soft-start and overcurrent
latchoff. Pulling the RUN/SS pin below 0.8V puts the
LTC3711 into a low quiescent current shutdown
(IQ < 30µA). Releasing the pin allows an internal 1.2µA
current source to charge up the external timing capacitor
CSS. If RUN/SS has been pulled all the way to ground,
there is a delay before starting of about:
The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has
reached the 4V threshold. In general, this will depend upon
the size of the output capacitance, output voltage and load
current characteristic. A minimum soft-start capacitor can
be estimated from:
CSS > C
Generally 0.1µF is more than sufficient.
Overcurrent latchoff operation is not always needed or
desired. Load current is already limited during a shortcircuit by the current foldback circuitry and latchoff
operation can prove annoying during troubleshooting.
The feature can be overridden by adding a pull-up current
greater than 5µA to the RUN/SS pin. The additional
current prevents the discharge of CSS during a fault and
also shortens the soft-start period. Using a resistor to V
as shown in Figure 8a is simple, but slightly increases
shutdown current. Connecting a resistor to INTVCC as
shown in Figure 8b eliminates the additional shutdown
OUT VOUT RSENSE
(10–4 [F/V s])
IN
3711f
16
Page 17
WUUU
APPLICATIO S I FOR ATIO
LTC3711
current, but requires a diode to isolate CSS. Any pull-up
network must be able to pull RUN/SS above the 4.2V
maximum threshold of the latchoff circuit and overcome
the 4µA maximum discharge current.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3711 circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same R
DS(ON)
, then the
resistance of one MOSFET can simply be summed with the
resistances of L and the board traces to obtain the DC I2R
loss. For example, if R
= 0.01Ω and RL = 0.005Ω, the
DS(ON)
loss will range from 1% up to 10% as the output current
varies from 1A to 10A for a 1.5V output.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
Transition Loss ≅ (1.7A–1) V
IN
2
I
OUT CRSS
f
3. INTVCC current. This is the sum of the MOSFET driver
and control currents. This loss can be reduced by supplying INTVCC current through the EXTVCC pin from a high
efficiency source, such as an output derived boost network or alternate supply if available.
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including C
ESR loss, Schottky diode D1
OUT
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to ∆I
resistance of C
discharge C
(ESR), where ESR is the effective series
LOAD
OUT
generating a feedback error signal used
OUT
by the regulator to return V
During this recovery time, V
immediately shifts by an amount
OUT
. ∆I
also begins to charge or
LOAD
to its steady-state value.
OUT
can be monitored for
OUT
overshoot or ringing that would indicate a stability
problem. The ITH pin external components shown in
INTV
CC
V
IN
RSS*
D1
C
SS
10Ω
INTV
PGND
CC
Q3
FMMT619
Q4
FMMT720
3.3V OR 5V RUN/SS
GATE
OF M2
3711 F07
Figure 8. RUN/SS Pin Interfacing with Latchoff Defeated
BOOST
Q1
FMMT619
10Ω
TG
Q2
FMMT720
SW
Figure 7. Optional External Gate Driver
GATE
OF M1
BG
RSS*
RUN/SS
D2*
C
SS
3711 F08
*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF
(8b)(8a)
3711f
17
Page 18
LTC3711
WUUU
APPLICATIO S I FOR ATIO
Figure 9 will provide adequate compensation for most
applications. For a detailed explanation of switching
control loop theory see Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: VIN = 7V to 24V (15V nominal), V
±100mV, I
timing resistor with VON = V
R
and choose the inductor for about 40% ripple current at
the maximum VIN:
L
Selecting a standard value of 1µH results in a maximum
ripple current of:
∆=
OUT(MAX)
=
ON
300 10
()()
kHz A
300 0 4 15
()()()
L
300 1
()
= 15A, f = 300kHz. First, calculate the
:
OUT
1
kHz pF
V
15
.
.
15
.
V
kHz H
1
µ
()
=
–
330
−
1
15
.
24
k
15
.
24
V
V
V
V
47
=I
=µ
08
.
A
= 1.5V
OUT
H=
.
–. .
VVVA
P
TJ = 50°C + (2.12W)(50°C/W) = 156°C
Because the top MOSFET is on for such a short time, a
single IRF7811A will be sufficient. Checking its power
dissipation at current limit with ρ
P
BOT
TJ = 50°C + (0.84W)(50°C/W) = 92°C
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
CIN is chosen for an RMS current rating of about 6A at
temperature. The output capacitors are chosen for a low
ESR of 0.005Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
24 1 52421 7
=
BOT
15
.
V
=
24
V
1 7 24 21 7 60 300
..
()( )( )( )( )
046 038 084
...
WWW
=+=
21 7 1 3 0 012
()()
V A pF kHz
2
...
A
2
2
.. .
16 0012 212
()
2
90°C
Ω
()
Ω
()
= 1.3:
+
W
=
Next, choose the synchronous MOSFET switch. Because
of the narrow duty cycle and large current, a single SO-8
MOSFET will have difficulty dissipating the power lost in
the switch. Choosing two IRF7811A (R
C
= 60pF, θJA = 50°C/W) yields a nominal sense voltage
RSS
of:
V
SNS(NOM)
Tying V
range for a nominal value of 140mV with current limit
occurring at 186mV. To check if the current limit is
acceptable, assume a junction temperature of about 100°C
above a 50°C ambient with ρ
I
LIMIT
and double check the assumed TJ in the MOSFET:
= (15A)(0.5)(1.3)(0.012Ω) = 117mV
to INTVCC will set the current sense voltage
RNG
= 1.6:
150°C
mV
≥
186
05 16 0012
...
()()
()
Ω
1
+
47 18
.
()
2
= 0.013Ω,
DS(ON)
AA
=
∆V
OUT(RIPPLE)
However, a 0A to 15A load step will cause an output
change of up to:
∆V
OUT(STEP)
The complete circuit is shown in Figure 9.
Active Voltage Positioning
Active voltage positioning (also termed load “deregulation” or droop) describes a technique where the output
voltage varies with load in a controlled manner. It is useful
in applications where rapid load steps are the main cause
of error in the output voltage. By positioning the output
voltage above the regulation point at zero load, and below
the regulation point at full load, one can use more of the
error budget for the load step. This allows one to reduce
the number of output capacitors by relaxing the ESR
requirement.
= ∆I
= (4.7A) (0.005Ω) = 24mV
= ∆I
LOAD
(ESR)
L(MAX)
(ESR) = (15A) (0.005Ω) = 75mV
3711f
18
Page 19
WUUU
APPLICATIO S I FOR ATIO
LTC3711
In the design example, Figure 9, five 0.025Ω capacitors
are required in parallel to keep the output voltage within
tolerance. Using active voltage positioning, the same
specification can be met with only three capacitors. In this
case, the load step will cause an output voltage change of:
∆=
OUT STEP()
()
1
.15
0 025 125
()
3
=VA mV
Ω
By positioning the output voltage 60mV above the regulation point at no load, it will only drop 65mV below the
regulation point after the load step, well within the ±100mV
tolerance.
Implementing active voltage positioning requires setting a
precise gain between the sensed current and the output
voltage. Because of the variability of MOSFET on-resistance, it is prudent to use a sense resistor with active
C
SS
0.1µF
C
C1
470pF
R
20k
C
R
330k
1
VID2
2
RUN/SS
3
V
R
PG
100k
C
C2
100pF
C
100pF
FB
C2
6.8nF
ON
ON
4
PGOOD
5
V
RNG
6
FCB
LTC3711
7
I
TH
8
SGND
9
I
ON
10
V
FB
11
V
OSENSE
12
VID3
VID1
VID0
BOOST
SENSE
PGND
INTV
EXTV
VID4
SW
V
TG
BG
24
23
22
C
21
20
19
+
18
17
16
CC
15
IN
14
CC
13
0.33µF
C
4.7µF
C
0.1µF
voltage positioning. In order to minimize power lost in this
resistor, a low value is chosen of 0.003Ω. The nominal
sense voltage will now be:
V
SNS(NOM)
= (0.003Ω)(15A) = 45mV
To maintain a reasonable current limit, the voltage on the
V
pin is reduced to its minimum value of 0.5V, corre-
RNG
sponding to a 50mV nominal sense voltage.
Next, the gain of the LTC3711 error amplifier must be
determined. The change in ITH voltage for a corresponding
change in the output current is:
CMDSH-3
B
VCC
F
I
∆=
TH
=
D
B
R
F
1Ω
()
V
12
RI
V
RNG
24 0 003 15 1 08..
()()
M1
IRF7811A
M2
IRF7811A
×2
∆
SENSE OUT
Ω
AV
L1
1µH
D1
UPS840
=
V
IN
7V TO 24V
C
IN
22µF
50V
V
OUT
OUT
1.5V
15A
×3
C
+
270µF
2V
×5
C
: UNITED CHEMICON THCR70EIH226ZT
IN
: CORNELL DUBILIER ESRE271M02B
C
OUT
L1: SUMIDA CEP125-IR0MC-H
3711 F09
Figure 9. CPU Core Voltage Regulator 1.5V/15A at 300kHz
3711f
19
Page 20
LTC3711
WUUU
APPLICATIO S I FOR ATIO
The corresponding change in the output voltage is determined by the gain of the error amplifier and feedback
divider. The LTC3711 error amplifier has a transconductance gm that is constant over both temperature and a wide
± 40mV input range. Thus, by connecting a load resistance RVP to the ITH pin, the error amplifier gain can be
precisely set for accurate active voltage positioning.
∆=
TH m VP
08.
V
OUT
V
∆IgR
V
OUT
Solving for this resistance value:
VI
∆
R
=
VP
==
OUT TH
Vg V
(. )
08
(. )(. )( )
08 17 125
∆
m OUT
VV
(. )(. )
15 108
VmS mV
.
953
k
The gain setting resistance RVP is implemented with two
resistors, R
connected from ITH to ground and R
VP1
VP2
connected from ITH to INTVCC. The parallel combination of
these resistors must equal RVP and their ratio determines
nominal value of the ITH pin voltage when the error
amplifier input is zero. To center the load line around the
regulation point, the ITH pin voltage must be set to correspond to half the output current. The relation between I
TH
voltage and the output current is:
The modified circuit is shown in Figure 10. Figures 11
and␣ 12 show the transient response without and with
active voltage positioning. Both circuits easily stay within
±100mV of the 1.5V output. However, the circuit with
active voltage positioning accomplishes this with only
three output capacitors rather than five. Refer to Design
Solutions 10 for additional information about active voltage positioning.
PC Board Layout Checklist
When laying out the printed circuit board, use the following checklist to ensure proper operation of the controller.
These items are also illustrated in Figure 11.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
source of M2.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SENSE+ traces short.
•
Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current.
• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the INTVCC decoupling capacitor C
VCC
closely
to the INTVCC and PGND pins.
I
TH NOM
=
=
=
117
12 1
V
RI I V
V
RNG
12
V
0 003 7 5
()
.
05
V
.
V
∆
SENSE OUT L()
..–..
Ω
–.
2
1
AAV
2
+
08
47 08
Solving for the required values of the resistors:
5
==
R
VP
1
5
12 44
=
===
R
VP
2
V
––.
VI
TH NOM
.
k
55
V
I
TH NOM
()
R
()
R
VP
VP
117
.
5
V
5117
VV
V
953 4073
..
kk
V
953
.
20
• Connect the top driver boost capacitor CB closely to the
BOOST and SW pins.
• Connect the VIN pin decoupling capacitor CF closely to
+
the VIN and PGND pins.
• VID0-VID4 interface circuitry must return to SGND.
k
3711f
Page 21
WUUU
APPLICATIO S I FOR ATIO
LTC3711
C
0.1µF
R
RNG1
4.99k
1
SS
R
RNG2
45.3k
R
330k
ON
R
VP2
40.2k
R
VP1
12.4k
C
100k
FB
R
PG
100pF
C
180pF
VID2
2
RUN/SS
3
V
ON
4
PGOOD
5
V
RNG
LTC3711
6
FCB
7
I
TH
C1
8
SGND
9
I
ON
10
V
FB
11
V
OSENSE
12
VID3
VID1
VID0
BOOST
SENSE
PGND
INTV
EXTV
VID4
SW
BG
V
24
23
22
21
TG
20
19
+
18
17
16
CC
15
IN
14
CC
13
C
B
0.33µF
C
VCC
4.7µF
C
F
0.1µF
D
B
CMDSH-3
1Ω
V
IN
7V TO 24V
C
IN
M1
IRF7811A
M2
IRF7811A
×2
R
SENSE
0.003Ω
R
F
L1
1µH
D1
UPS840
22µF
50V
×3
C
OUT
270µF
2V
×3
V
1.5V
15A
OUT
C
: UNITED CHEMICON THCR70EIH226ZT
IN
: CORNELL DUBILIER ESRE271M02B
C
OUT
L1: SUMIDA CEP125-IR0MC-H
Figure 10. CPU Core Voltage Regulator with Active Voltage Positioning 1.5V/15A at 300kHz
3711 F010
3711f
21
Page 22
LTC3711
WUUU
APPLICATIO S I FOR ATIO
V
OUT
100mV/DIV
10A/DIV
1.5V
I
L
C
= 5 × 270µF20µs/DIV 3711 F09
OUT
VIN = 15V
FIGURE 7 CIRCUIT
Figure 11. Normal Transient Response
1
C
SS
C
C1
R
C
C
R
ON
VID2
2
RUN/SS
3
V
ON
4
PGOOD
5
V
RNG
6
FCB
LTC3711
7
I
TH
C
C2
8
SGND
9
I
ON
FB
10
V
FB
11
V
OSENSE
12
VID3
VID1
VID0
BOOST
SENSE
PGND
INTV
EXTV
VID4
SW
BG
V
V
OUT
100mV/DIV
1.5V
I
L
10A/DIV
C
= 3 × 270µF20µs/DIV 3711 F10
OUT
VIN = 15V
FIGURE 8 CIRCUIT
Figure 12. Transient Response with Active Voltage Positioning
24
23
C
22
21
TG
20
19
+
18
17
16
CC
15
IN
14
CC
13
B
D
B
M2
C
VCC
C
R
F
F
L
M1
D1
C
IN
+
V
IN
–
–
C
OUT
V
OUT
+
22
BOLD LINES INDICATE HIGH CURRENT PATHS
3711 F13
Figure 13. LTC3711 Layout Diagram
3711f
Page 23
PACKAGE DESCRIPTIO
U
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 ±.005
.337 – .344*
(8.560 – 8.738)
LTC3711
.033
161718192021222324
15
14
(0.838)
13
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.007 – .0098
(0.178 – 0.249)
.016 – .050
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
(0.406 – 1.270)
INCHES
(MILLIMETERS)
.150 – .165
.015
± .004
(0.38 ± 0.10)
0° – 8° TYP
.229 – .244
(5.817 – 6.198)
5
12
.0250 TYP.0165 ±.0015
× 45°
.053 – .068
(1.351 – 1.727)
.008 – .012
(0.203 – 0.305)
4
3
678 9 10 11 12
.0250
(0.635)
BSC
.150 – .157**
(3.810 – 3.988)
.004 – .0098
(0.102 – 0.249)
GN24 (SSOP) 0502
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
3711f
23
Page 24
LTC3711
TYPICAL APPLICATIO
U
1
C
SS
0.1µF
R
PG
100k
C
C1
R
2.2nF
C
4.7k
C
C2
100pF
C
100pF
FB
R
ON
330k
: UNITED CHEMICON THCR70EIH226ZT
C
IN
: TAIYO YUDEN LMK550BJ476MM, 1.5V/15A ALL CERAMIC
C
OUT
L1: SUMIDA CEP125-IR0MC-H
VID2
2
RUN/SS
3
V
4
PGOOD
5
V
6
FCB
7
I
TH
8
SGND
9
I
ON
10
V
11
V
12
VID3
1.5V/15A All Ceramic C
24
VID1
23
VID0
22
BOOST
ON
21
TG
20
LTC3711
SENSE
PGND
INTV
EXTV
VID4
SW
19
+
18
17
BG
16
CC
15
V
IN
14
CC
13
RNG
FB
OSENSE
C
B
0.33µF
C
VCC
4.7µF
C
F
0.1µF
D
B
CMDSH-3
OUT
V
IN
7V TO 24V
C
IN
M1
IRF7811A
M2
IRF7811A
×2
R
F
1Ω
1µH
L1
D1
UPS840
3711 TA01
22µF
50V
V
OUT
×3
1.5V
15A
C
OUT
+
47µF
10V
×8
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●
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LINEAR TECHNOLOGY CORPORATION 2001
≤ 3.5V
3711f
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