Datasheet LTC2912ITS8-3, LTC2912 Datasheet (Linear Technology)

LTC2912

Single UV/OV

Voltage Monitor

FEATURES

■

Monitors Single Voltage

■

Adjustable UV and OV Trip Values

■

Guaranteed Threshold Accuracy: ±1.5%

■

Power Supply Glitch Immunity

■

Adjustable Reset Timeout with Timeout Disable

■

29μA Quiescent Current

■

Open-Drain OV and UV Outputs

■

Guaranteed OV and UV for VCC ≥ 1V

■

Available in 8-Lead ThinSOTTM and (3mm × 2mm)

DFN Packages

APPLICATIONS

■

Desktop and Notebook Computers

■

Network Servers

■

Core, I/O Voltage Monitors

DESCRIPTION

The LTC®2912 voltage monitor is designed to detect power
supply undervoltage and overvoltage events. The VL and
VH monitor inputs include fi ltering to reject brief glitches,
thereby ensuring reliable reset operation without false or
noisy triggering. An adjustable timer defi nes the duration of
the overvoltage and under voltage reset outputs which func­tion independently. While the LTC2912 operates directly
from 2.3V to 6V supplies, an internal V
coupled with low supply current demand allows operation
from higher voltages such as 12V, 24V or 48V.

Three output confi gurations are available: the LTC2912­1 has a latch control for the OV output; the LTC2912-2
has an OV and UV output disable feature for margining
applications; the LTC2912-3 is identical to the LTC2912-1
but with a noninverting, OV output.

The LTC2912 provides a precise, versatile, space-conscious
micropower solution for voltage monitoring.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.

shunt regulator

CC

TYPICAL APPLICATION

Single OV/UV Supply Monitor, 3.3V ±10% Tolerance Reset Time-Out Period vs Capacitance

POWER
SUPPLY

3.3V

27.4k

1k

4.53k

0.1μF

V

CC

VH

LTC2912-1

VL

LATCH

GND TMR

OV

UV

22nF

SYSTEM

2912 TA01a

TIMEOUT = 200ms

10000

(ms)

1000

UOTO

100

10

UV/OV TIMEOUT PERIOD, t

1

0.1 10 100 1000

1

TMR PIN CAPACITANCE, C

TMR

(nF)

2912 G08

2912fa

1

LTC2912

(

(

(

ABSOLUTE MAXIMUM RATINGS

Terminal Voltages

VCC (Note 3) ............................................. –0.3V to 6V

OV, UV, OV ............................................ –0.3V to 16V

TMR ..........................................–0.3V to (VCC + 0.3V)

VH, VL, LATCH, DIS .............................. –0.3V to 7.5V

Terminal Currents
I
I

....................................................................10mA

VCC

, IOV, IOV ........................................................10mA

UV

(Note 1)

Operating Temperature Range

LTC2912C ................................................ 0°C to 70°C

LTC2912I.............................................. –40°C to 85°C

LTC2912H .......................................... –40°C to 125°C

Storage Temperature Range

TSOT .................................................. –65°C to 125°C

DFN .................................................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

TSOT ................................................................. 300°C

PACKAGE/ORDER INFORMATION

TOP VIEW

TOP VIEW

LATCH 1

UV 2
OV 3

GND 4

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

T

= 150°C, θJA = 195°C/W

JMAX

8 V
7 VH
6 VL
5 TMR

CC

EXPOSED PAD (PIN 9) IS GND, CONNECTION TO PCB OPTIONAL

CC

VH

VL

TMR

3mm × 2mm) PLASTIC DFN

8-LEAD

T

= 150°C, θJA = 76°C/W

JMAX

ORDER PART NUMBER TS8 PART MARKING* ORDER PART NUMBER DDB PART MARKING*

LTC2912CTS8-1
LTC2912ITS8-1
LTC2912HTS8-1

DIS 1

UV 2
OV 3

GND 4

T

JMAX

TOP VIEW

8 V
7 VH
6 VL
5 TMR

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

= 150°C, θJA = 195°C/W

LTCJW
LTCJW
LTCJW

CC

LTC2912CDDB-1
LTC2912IDDB-1
LTC2912HDDB-1

CC

VH

VL

TMR

3mm × 2mm) PLASTIC DFN

8-LEAD

T

= 150°C, θJA = 76°C/W

EXPOSED PAD (PIN 9) IS GND, CONNECTION TO PCB OPTIONAL

JMAX

ORDER PART NUMBER TS8 PART MARKING* ORDER PART NUMBER DDB PART MARKING*

LTC2912CTS8-2
LTC2912ITS8-2
LTC2912HTS8-2

LATCH 1

GND 4

T

JMAX

TOP VIEW

UV 2
OV 3

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

= 150°C, θJA = 195°C/W

8 V
7 VH
6 VL
5 TMR

LTCJX
LTCJX
LTCJX

CC

LTC2912CDDB-2
LTC2912IDDB-2
LTC2912HDDB-2

1V

CC

VH

2

VL

3

TMR

4

DDB PACKAGE

3mm × 2mm) PLASTIC DFN

8-LEAD

T

= 150°C, θJA = 76°C/W

EXPOSED PAD (PIN 9) IS GND, CONNECTION TO PCB OPTIONAL

JMAX

ORDER PART NUMBER TS8 PART MARKING* ORDER PART NUMBER DDB PART MARKING*

LTC2912CTS8-3
LTC2912ITS8-3
LTC2912HTS8-3

Order Options

Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/

LTCJY
LTCJY
LTCJY

*The temperature grade is identifi ed by a label on the shipping container.

LTC2912CDDB-3
LTC2912IDDB-3
LTC2912HDDB-3

1V

2

9

3

4

DDB PACKAGE

TOP VIEW

1V

2

9

3

4

DDB PACKAGE

TOP VIEW

9

8

LATCH
UV

7

OV

6

GND

5

LCJZ
LCJZ
LCJZ

8

DIS

UV

7

OV

6

GND

5

LCKB
LCKB
LCKB

8

LATCH
UV

7

OV

6

GND

5

LCKC
LCKC
LCKC

2912fa

2

LTC2912

ELECTRICAL CHARACTERISTICS

The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, VL = 0.45V, VH = 0.55V, LATCH = VCC unless otherwise
noted. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

SHUNT

ΔV

SHUNT

V

CC

V

CCR(MIN)

V

CC(UVLO)

ΔV

CC(UVHYST)

I

CC

V

UOT

t

UOD

VCC Shunt Regulator Voltage ICC = 5mA

–40°C < T

A

VCC Shunt Regulator Load Regulation ICC = 2mA to 10mA

Supply Voltage (Note 3)

Minimum VCC Output Valid DIS = 0V

Supply Undervoltage Lockout DIS = 0V, VCC Rising

Supply Undervoltage Lockout Hysteresis DIS = 0V

Supply Current VCC = 2.3V to 6V

Undervoltage/Overvoltage Threshold

Undervoltage/Overvoltage Threshold to

VHn = V

UOT

Output Delay

I

VHL

t

UOTO

V

LATCH(VIH)

V

LATCH(VIL)

I

LATCH

I

DIS

V

DIS(VIH)

V

DIS(VIL)

I

TMR(UP)

I

TMR(DOWN)

V

TMR(DIS)

V

OH

V

OL

VH, VL Input Current

–40°C < T

UV/OV Time-Out Period C

–40°C < T

TMR

A

= 1nF

A

OV Latch Clear Input High

OV Latch Clear Input Low
LATCH Input Current V

DIS Input Current V

LATCH

> 0.5V

DIS

> 0.5V

DIS Input High

DIS Input Low

TMR Pull-Up Current V

TMR Pull-Down Current V

= 0V

TMR

–40°C < T

= 1.6V

TMR

–40°C < T

A

A

Timer Disable Voltage Referenced to V
Output Voltage High UV/OV/OV VCC = 2.3V, I
Output Voltage Low UV/OV/OV VCC = 2.3V, I

V

= 1V, IUV = 100μA

CC

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.

< 125°

– 5mV or VLn = V

UOT

+ 5mV

< 125°

< 125°

< 125°

< 125°

CC

= –1μA

UV/OV

= 2.5mA

UV/OV

Note 3: VCC maximum pin voltage is limited by input current. Since the
V

pin has an internal 6.5V shunt regulator, a low impedance supply that

CC

exceeds 6V may exceed the rated terminal current. Operation from higher
voltage supplies requires a series dropping resistor. See Applications
Information.

●

6.2 6.6 7.2 V

●

6.2 6.6 7.3 V

●

●

2.3 V

●

●

1.9 2 2.1 V

●

52550 mV

●

●

492 500 508 mV

●

50 125 500 μs

●

●

●

6 8.5 12.5 ms

●

6 8.5 14 ms

●

1.2 V

●

●

●

1 2 3.3 μA

●

1.2 V

●

●

–1.3 –2.1 –2.8 μA

●

–1.2 –2.1 –2.8 μA

●

1.3 2.1 2.8 μA

●

1.2 2.1 2.8 μA

●

–180 –270 mV

●

1V

●

●

200 300 mV

SHUNT

1V

29 70 μA

±15 nA

±30 nA

0.8 V

±1 μA

0.8 V

0.10

0.01

0.30

0.15

V

V
V

2912fa

3

LTC2912

)

TIMING DIAGRAMS

VH Monitor Timing

V

VH

UOT

t

UOD

UV

1V

VH Monitor Timing (TMR Pin Strapped to V

V

VH

UOT

t

UOD

UV

1V

t

UOD

t

UOTO

2912 TD01

CC

2912 TD03

)

TYPICAL PERFORMANCE CHARACTERISTICS

Input Threshold Voltage
vs Temperature

0.505

0.504

0.503

(V)

UOT

0.502

0.501

0.500

0.499

0.498

0.497

THRESHOLD VOLTAGE, V

0.496

0.495
–50

–25

TEMPERATURE (°C)

0

25 50

75

100

2912 G01

Supply Current vs Temperature

45

40

VCC = 5V

VCC = 3.3V

VCC = 2.3V

–25 0 25 50

TEMPERATURE (°C)

(μA)

CC

I

35

30

25

20

15

–50

VL Monitor Timing

V

VL

UOT

t

UOD

1V

OV

t

UOTO

2912 TD02

VL Monitor Timing (TMR Pin Strapped to VCC)

V

VL

UOT

t

UOD

OV

1V

t

UOD

2912 TD04

VCC Shunt Voltage
vs Temperature

6.8

10mA

5mA

2mA

1mA

200μA

75 100

2912 G02

(V)

CC

V

6.7

6.6

6.5

6.4

6.3

6.2
–50

02550

–25

TEMPERATURE (°C)

75 100

2912 G03

4

VCC Shunt Voltage vs I

6.75

6.65

6.55

(V)

CC

V

6.45
–40°C

6.35
25°C

85°C

6.25
–2 0

2

Typical Transient Duration vs

CC

6

4

I

CC

8

(mA)

10

12

2912 G04

Comparator Overdrive

700

600

500

400

300

200

100

TYPICAL TRANSIENT DURATION (μs)

VCC = 2.3V

50

0.1

COMPARATOR OVERDRIVE PAST THRESHOLD (%

RESET OCCURS

ABOVE CURVE

VCC = 6V

1 10 100

2912 G05

UV Output Voltage vs V

0.8

0.6

0.4

UV VOLTAGE (V)

0.2

0

0

UV WITHOUT

PULL-UP

0.2
SUPPLY VOLTAGE, V

0.4

V

CC

CC

UV WITH
10k PULL-UP

0.6

CC

(V)

0.8

1

2912 G06

2912fa

TYPICAL PERFORMANCE CHARACTERISTICS

Reset Time-Out Period

UV Output Voltage vs V

5

VH = 0.55V
SEL = V

CC

4

3

2

UV VOLTAGE (V)

1

0

1

0

SUPPLY VOLTAGE, VCC (V)

CC

3

4

2

5

2912 G07

vs Capacitance

10000

(ms)

1000

UOTO

100

10

UV/OV TIMEOUT PERIOD, t

1

0.1 10 100 1000

1

TMR PIN CAPACITANCE, C

TMR

(nF)

2912 G08

UV, I

5

4

(mA)

UV

3

2

1

PULL-DOWN CURRENT, I

0

0

vs V

SINK

VH = 0.45V
SEL = V

CC

UV AT 150mV

1

SUPPLY VOLTAGE, VCC (V)

LTC2912

CC

UV AT 50mV

3

2

4

5

2912 G09

UV/OV, Voltage Output Low
vs Output Sink Current

1.0

(mA)

25°C85°C

–40°C

25

30

1912 G10

0.8

(V)

0.6

OL

0.4

UV/OV, V

0.2

0

0

PIN FUNCTIONS

10 15 20

5

I

UV/OV

(DFN/TSOT Packages)

DIS (Pin 8/Pin 1, LTC2912-2): Output Disable Input.

Disables the OV and UV output pins. When DIS is pulled
high, the OV and UV pins are not asserted except during a
UVLO condition. Pin has a weak (2μA) internal pull-down
to GND. Leave pin open if unused.

Exposed Pad (Pin 9, DDB Package): Exposed Pad may
be left open or connected to device ground.

GND (Pin 5/Pin 4): Device Ground.

Reset Timeout Period
vs Temperature

12

C

= 1nF

TMR

11

(ms)

OUTO

10

9

8

7

UV/OV TIMEOUT PERIOD, t

6

–50

02550

–25

TEMPERATURE (°C)

75 100

2912 G11

is cleared. While held high, OV/OV has a similar delay and
output characteristic as UV.

OV (Pin 6/Pin 3, LTC2912-1, LTC2912-2): Overvoltage
Logic Output. Asserts low when the VL input voltage is
above threshold. Latched low (LTC2912-1). Held low for
programmed delay time after VL input is valid (LTC2912-2).
Pin has a weak pull-up to V

and may be pulled above VCC

CC

using an external pull-up. Leave pin open if unused.

LATCH (Pin 8/Pin 1, LTC2912-1, LTC2912-3): OV/OV
Latch Clear/Bypass Input. When pulled high, OV/OV latch

2912fa

5

LTC2912

PIN FUNCTIONS

(DFN/TSOT Packages)

OV (Pin 6/Pin 3, LTC2912-3): Overvoltage Logic Output.

Asserts high with a weak internal pull-up to V

when the

CC

VL input is above threshold. Latches high. May be pulled
above V

using an external pull-up. Leave pin open if

CC

unused.

TMR (Pin 4/Pin 5): Reset Delay Timer. Attach an external
capacitor (C

) of at least 10pF to GND to set a reset

TMR

delay time of 9ms/nF. A 1nF capacitor will generate an

8.5ms reset delay time. Tie pin to V

to bypass timer.

CC

UV (Pin 7/Pin 2): Undervoltage Logic Output. Asserts low
when the VH input voltage is below threshold. Held low for
a programmed delay time after the VH input is valid. Pin
has a weak pull-up to V

and may be pulled above VCC

CC

using an external pull-up. Leave pin open if unused.

BLOCK DIAGRAM

1

CC

(Pin 1/Pin 8): Supply Voltage. Bypass this pin to

V

CC

GND with a 0.1μF (or greater) capacitor. Operates as a
direct supply input for voltages up to 6V. Operates as a
shunt regulator for supply voltages greater than 6V and
should have a resistance between the pin and the supply
to limit input current to no greater than 10mA. When used
without a current-limiting resistance, pin voltage must
not exceed 6V.

VH (Pin 2/Pin 7): Voltage High Input. When the voltage
on this pin is below 0.5V, an undervoltage condition is
triggered. Tie pin to V

if unused.

CC

VL (Pin 3/Pin 6): Voltage Low Input. When the voltage on
this pin is above 0.5V, an overvoltage condition is triggered.
Tie pin to GND if unused.

4

TMRV

OSCILLATOR

V

CC

400k

VH

VL

GND

0.5V

–
+

UVLO

UVLO

–
+

+

2V

V

–

CC

LTC2912-1, LTC2912-3

LTC2912-2

UV PULSE

GENERATOR

DISABLE

OV PULSE

GENERATOR

DISABLE

OV LATCH

CLEAR/BYPASS

+
–

–
+

LTC2912-1
LTC2912-2

LTC2912-3

1V

1V

2

3

5

UV

7

V

CC

400k

OV/OV

6

LATCH

8

DIS

8

2μA

2912 BD

2912fa

6

APPLICATIONS INFORMATION

LTC2912

Voltage Monitoring

The LTC2912 is a low power voltage monitoring circuit
with an undervoltage and an overvoltage input. A timeout
period that holds OV and UV asserted after a fault has
cleared is adjustable using an external capacitor and may
be externally disabled. When confi gured to monitor a posi­tive voltage V

using the 3-resistor circuit confi guration

n

shown in Figure 1, VH will be connected to the high side
tap of the resistive divider and VL will be connected to the
low side tap of the resistive divider.

3-Step Design Procedure

The following 3-step design procedure allows selecting
appropriate resistances to obtain the desired UV and OV
trip points for the voltage monitor circuit in Figure 1.

For supply monitoring, V
ing voltage, I
resistive divider, V
and V

UV

1. Choose R

is chosen to set the desired trip point for the

R

A

is the desired nominal current through the

n

OV

is the desired undervoltage trip point.

to obtain the desired OV trip point

A

is the desired nominal operat-

n

is the desired overvoltage trip point

overvoltage monitor.

V

V

05.

R

=

A

I

n

V

n

R

C

•

n

V

OV

LTC2912

VH

(1)

–

2. Choose R

Once R

to obtain the desired UV trip point

B

is known, RB is chosen to set the desired trip

A

point for the undervoltage monitor.

05.

R

=

B

I

n

3. Choose R

Once R

and RB are known, RC is determined by:

A

V

R

n

= ––

C

I

n

If any of the variables V

n

•–

to complete the design

C

RR

AB

R

V

UV

A

, In, VUV or VOV change, then each

n

(2)

(3)

V

V

step must be recalculated.

Voltage Monitor Example

A typical voltage monitor application is shown in Figure 2.
The monitored voltage is a 5V ±10% supply. Nominal cur­rent in the resistive divider is 10μA.

1. Find R

R

to set the OV trip point of the monitor.

A

V

•

V

55

.

k

45 3

.

V

05105

.

= ≈

A

µA

2. Find RB to set the UV trip point of the monitor.

V

•

V

5

45 3 10 2

–. .

V

45

.

kk

05

R

.

= ≅

B

10

µA

3. Determine RC to complete the design.

+

R

B

R

A

Figure 1. 3-Resistor Positive UV/OV Monitoring Confi guration

+

0.5V

–

–

VL

+

UV

OV

2912 F01

V

R

5

= −≈

C

µA

10

Figure 2. Typical Supply Monitor

kkk

45 3 10 2 442–. .

V1

5V ±10%

R

C

442k

R

B

10.2k

R

A

45.3k

VH1

LTC2912-1

VL1

V

5V

V

GND

CC

CC

OV

UV

2912 F02

2912fa

7

LTC2912

APPLICATIONS INFORMATION

Power-Up/Power-Down

As soon as V
asserts low and the OV output weakly pulls to V

reaches 1V during power up, the UV output

CC

.

CC

The LTC2912 is guaranteed to assert UV low, OV high
(LTC2912-1, LTC2912-2) and OV low (LTC2912-3) under
conditions of low V

, down to VCC = 1V. Above VCC = 2V

CC

(2.1V maximum), the VH and VL inputs take control.

Once the VH input and V

become valid an internal timer

CC

is started. After an adjustable delay time, UV weakly pulls
high.

Threshold Accuracy

Reset threshold accuracy is important in a supply-sensitive
system. Ideally, such a system resets only if supply voltages
fall outside the exact thresholds for a specifi ed margin.
Both LTC2912 inputs have a relative threshold accuracy
of ±1.5% over the full operating temperature range.

For example, when the LTC2912 is programmed to moni­tor a 5V input with a 10% tolerance, the desired UV trip
point is 4.5V. Because of the ±1.5% relative accuracy of
the LTC2912, the UV trip point can be anywhere between

4.433V and 4.567V which is 4.5V ±1.5%.

Likewise, the accuracy of the resistances chosen for R

and RC can affect the UV and OV trip points as well.

R

B

,

A

Using the example just given, if the resistances used to
set the UV trip point have 1% accuracy, the UV trip range
is between 4.354V and 4.650V. This is illustrated in the
following calculations.

The UV trip point is given as:

VUV= 0.5V 1+






RA+ R



R

C





B

The two extreme conditions, with a relative accuracy of

1.5% and resistance accuracy of 1%, result in:

V

UV(MIN)

= 0.5V •0.985 • 1+






• 0.99

R

C

R

+ R

()

A

B

• 1.01






and

V

UV(MAX)

= 0.5V •1.015 • 1+




For a desired trip point of 4.5V,



•1.01

R

C

R

+ R

()

A

B

R

C

RA+ R

= 8

B

•0.99






Therefore,

V

UV(MIN)

= 0.5V •0.985 • 1+ 8




0.99

1.01



= 4.354V



and

V

UV(MAX)

= 0.5V •1.015 • 1+ 8




1.01

0.99



= 4.650V



Glitch Immunity

In any supervisory application, noise riding on the moni­tored DC voltage causes spurious resets. To solve this
problem without adding hysteresis, which causes a new
error term in the trip voltage, the LTC2912 lowpass fi lters
the output of the fi rst stage comparator at each input. This
fi lter integrates the output of the comparator before as­serting the UV or OV logic. A transient at the input of the
comparator of suffi cient magnitude and duration triggers
the output logic. The Typical Performance Characteristics
show a graph of the Transient Duration vs Comparator
Overdrive.

8

UV/OV Timing

The LTC2912 has an adjustable timeout period (t

UOTO

) that

holds OV, OV or UV asserted after each fault has cleared.
This delay assures a minimum reset pulse width allowing
settling time for the monitored voltage after it has entered
the “valid” region of operation.

2912fa

APPLICATIONS INFORMATION

LTC2912

When the VH input drops below its designed threshold,
the UV pin asserts low. When the input recovers above
its designed threshold, the UV output timer starts. If the
input remains above the designed threshold when the
timer fi nishes, the UV pin weakly pulls high. However, if
the input falls below its designed threshold during this
timeout period, the timer resets and restarts when the
input is above the designed threshold. The OV and OV
outputs behave as the UV output when LATCH is high
(LTC2912-1, LTC2912-3).

Selecting the UV/OV Timing Capacitor

The UV and OV timeout period (t

) for the LTC2912

UOTO

is adjustable to accommodate a variety of applications.
Connecting a capacitor, C

, between the TMR pin and

TMR

ground sets the timeout period. The value of capacitor
needed for a particular timeout period is:

C

TMR

= t

• 115 • 10–9 [F/s]

UOTO

The Reset Timeout Period vs Capacitance graph found in
the Typical Performance Characteristics shows the desired
delay time as a function of the value of the timer capacitor
that must be used. The TMR pin must have a minimum
10pF load or be tied to V

. For long timeout periods, the

CC

only limitation is the availability of a large value capaci­tor with low leakage. Capacitor leakage current must not
exceed the minimum TMR charging current of 1.3μA.Tying
the TMR pin to V

bypasses the timeout period.

CC

Undervoltage Lockout

When V

falls below 2V, the LTC2912 asserts an

CC

undervoltage lockout (UVLO) condition. During UVLO, UV
is asserted and pulled low while OV and OV are cleared
and blocked from asserting. When V

rises above 2V, UV

CC

follows the same timing procedure as an undervoltage
condition on the VH input.

have a resistance R

between the supply and the VCC pin

Z

to limit the current to no greater than 10mA.

When choosing this resistance value, select an appropriate
location on the I-V curve shown in the Typical Performance
Characteristics to accommodate any variations in V
to changes in current through R

.

Z

CC

due

UV, OV and OV Output Characteristics

The DC characteristics of the UV, OV and 0V pull-up and
pull-down strength are shown in the Typical Performance
Characteristics. Each pin has a weak internal pull-up to

and a strong pull-down to ground. This arrangement

V

CC

allows these pins to have open-drain behavior while pos­sessing several other benefi cial characteristics. The weak
pull-up eliminates the need for an external pull-up resistor
when the rise time on the pin is not critical. On the other
hand, the open-drain confi guration allows for wired-OR
connections, and is useful when more than one signal
needs to pull down on the output. V
a maximum V

= 1V, the weak pull-up current on OV is barely turned

At V

CC

= 0.15V at UV.

OL

of 1V guarantees

CC

on. Therefore, an external pull-up resistor of no more than
100k is recommended on the OV pin if the state and pull-up
strength of the OV pin is crucial at very low V

CC

.

Note however, by adding an external pull-up resistor, the
pull-up strength on the OV pin is increased. Therefore, if
it is connected in a wired-OR connection, the pull-down
strength of any single device must accommodate this
additional pull-up strength.

Output Rise and Fall Time Estimation

The UV, OV and OV outputs have strong pull-down capa-
bility. The following formula estimates the output fall time
(90% to 10%) for a particular external load capacitance

LOAD

):

(C

Shunt Regulator

The LTC2912 has an internal shunt regulator. The V

CC

pin
operates as a direct supply input for voltages up to 6V. Under
this condition, the quiescent current of the device remains
below a maximum of 70μA. For V

voltages higher than

CC

6V, the device operates as a shunt regulator and should

t

≈ 2.2 • RPD • C

FALL

LOAD

where RPD is the on-resistance of the internal pull-down
transistor, typically 50Ω at V
perature (25°C). C

is the external load capacitance

LOAD

> 1V and at room tem-

CC

on the pin. Assuming a 150pF load capacitance, the fall
time is 16.5ns.

2912fa

9

LTC2912

APPLICATIONS INFORMATION

The rise time on the UV, OV and 0V pins is limited by a
400k pull-up resistance to V

. A similar formula esti-

CC

mates the output rise time (10% to 90%) at the UV, OV
and OV pins:

t

≈ 2.2 • RPU • C

RISE

LOAD

where RPU is the pull-up resistance.

OV/OV Latch (LTC2912-1, LTC2912-3)

With the LATCH pin held low, the OV pin latches low
(LTC2912-1) and the OV pin latches high (LTC2912-3)
when an OV condition is detected. The latch is cleared
by raising the LATCH pin high. If an OV condition clears
while LATCH is held high, the latch is bypassed and the
OV and OV pins behave the same as the UV pin with a

TYPICAL APPLICATIONS

Dual UV/OV Supply Monitor, 3.3V ±10% Tolerance

3.3V

POWER
SUPPLY

R

C

27.4k

R

B

1k

R

A

4.53k

C

BYP

2

VH

3

VL

0.1μF

1

V

CC

LTC2912-1

LATCH

GND TMR

OV

UV

45

C

TMR

22nF

6

7

8

TIMEOUT = 200ms

SYSTEM

2912 TA02

similar timeout period at the output. If LATCH is pulled
low while the timeout period is active, the OV and OV pins
latch as before.

Disable (LTC2912-2)

The LTC2912-2 allows disabling the UV and OV outputs
via the DIS pin. Pulling DIS high forces both outputs to
remain weakly pulled high, regardless of any faults that
occur on the inputs. However, if a UVLO condition oc­curs, UV asserts and pulls low, but the timeout function
is bypassed. UV pulls high as soon as the UVLO condition
is cleared.

DIS has a weak 2μA (typical) internal pull-down current
guaranteeing normal operation with the pin left open.

48V Supply Monitor (<±10% = Powergood)

48V

POWER
SUPPLY

R

C

37.4M

R

B

80.6k

R

A

357k

2

3

R

C

BYP

200k

0.1μF

1

V

CC

VH

LTC2912-2

VL

GND TMR

Z

R

PG

30k

6

OV

7

UV

DIS

45

C
10nF

2912 TA03

8

TMR

POWERGOOD
LED

TIMEOUT = 85ms

10

Dual UV Supply Monitor, 3.3V, 2.5V, 10% Tolerance

3.3V

POWER

SUPPLIES

2.5V

R

54.9k

R

39.2k

C

0.1μF

BYP

1

B1

B2

R
11k

R
11k

V

2

V

H

A1

3

V

L

A2

CC

LTC2912-2

GND

5

TMR

4

OV

UV

DIS

R
10k

6

7

8

R

UV

10k

OV

SYSTEM

2912 TA04

2912fa

PACKAGE DESCRIPTION

LTC2912

DDB Package

8-Lead Plastic DFN (3mm × 2mm)

(Reference LTC DWG # 05-08-1702 Rev B)

0.61 ±0.05
(2 SIDES)

0.70 ±0.05

2.55 ±0.05

1.15 ±0.05

PACKAGE
OUTLINE

0.25 ± 0.05

0.50 BSC

2.20 ±0.05
(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 BAR

TOP MARK

(SEE NOTE 6)

0.200 REF

3.00 ±0.10
(2 SIDES)

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637)

0.52

MAX

0.65
REF

2.00 ±0.10
(2 SIDES)

0.75 ±0.05

R = 0.05

0 – 0.05

TYP

0.56 ± 0.05
(2 SIDES)

2.90 BSC
(NOTE 4)

R = 0.115

TYP

0.25 ± 0.05

2.15 ±0.05
(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

0.40 ± 0.10

85

14

0.50 BSC

PIN 1
R = 0.20 OR

0.25 × 45°
CHAMFER

(DDB8) DFN 0905 REV B

3.85 MAX

2.62 REF

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.20 BSC

DATUM ‘A’

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

1.22 REF

1.4 MIN

0.30 – 0.50 REF

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

2.80 BSC

0.09 – 0.20
(NOTE 3)

1.50 – 1.75
(NOTE 4)

PIN ONE ID

0.65 BSC

0.80 – 0.90

1.00 MAX

1.95 BSC

0.22 – 0.36
8 PLCS (NOTE 3)

0.01 – 0.10

TS8 TSOT-23 0802

2912fa

11

LTC2912

TYPICAL APPLICATION

Single UV/OV Supply Monitor with 3.3V ±10%

POWER
SUPPLY

12V

3.3V

27.4k

1k

4.53k

0.1μF

V

CC

VH

LTC2912-3

VL

LATCH

GND TMR

OV

UV

22nF

Q1

10k

SYSTEM

2912 TA05

TIMEOUT = 200ms

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12

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone] ● www.linear.com

2912fa

LT 1007 REV A • PRINTED IN USA

© LINEAR TECHNOLOGY CORPORATION 2006