Datasheet LTC2499 Datasheet (LINEAR TECHNOLOGY)

SCL

SDA

F

O

REF

+

V

CC

MUXOUT/
ADCIN

MUXOUT/
ADCIN

2.7V TO 5.5V

10µF

1.7k

COM

REF

–

24-BIT ∆Σ ADC

WITH EASY DRIVE

16-CHANNEL

MUX

TEMPERATURE

SENSOR

IN

+

IN

–

2499 TA01

2-WIRE
I2C INTERFACE

CH0
CH1

•

•

•

•

•

•

CH7
CH8

CH15

0.1µF

OSC

TEMPERATURE (°C)

–55 –30 –5

ABSOLUTE ERROR (°C)

5

4

3

2

1

–4

–3

–2

–1

0

12095704520

2499 TA02

–5

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

No Latency DS and Easy Drive are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.

DS

LTC2499

24-Bit 8-/16-Channel

ADC with Easy Drive Input Current

Cancellation and I

2

C Interface

FeaTures

■

Up to Eight Differential or 16 Single-Ended Inputs

■

Easy DriveTM Technology Enables Rail-to-Rail

Inputs with Zero Differential Input Current

■

Directly Digitizes High Impedance Sensors with

Full Accuracy

■

2-Wire I2C Interface with 27 Addresses Plus One

Global Address for Synchronization

■

600nV RMS Noise

■

Integrated High Accuracy Temperature Sensor

■

GND to VCC Input/Reference Common Mode Range

■

Programmable 50Hz, 60Hz or Simultaneous 50Hz/

60Hz Rejection Mode

■

2ppm INL, No Missing Codes

■

1ppm Offset and 15ppm Full-Scale Error

■

2x Speed/Reduced Power Mode (15Hz Using Internal

Oscillator and 80µA at 7.5Hz Output)

■

No Latency: Digital Filter Settles in a Single Cycle,

Even After a New Channel Is Selected

■

Single Supply 2.7V to 5.5V Operation (0.8mW)

■

Internal Oscillator

■

Tiny 5mm × 7mm QFN Package

applicaTions

■

Direct Sensor Digitizer

■

Direct Temperature Measurement

■

Instrumentation

■

Industrial Process Control

DescripTion

The LTC®2499 is a 16-channel (eight differential), 24-bit,
No Latency DSTM ADC with Easy Drive technology and a
2-wire, I2C interface. The patented sampling scheme elimi­nates dynamic input current errors and the shortcomings
of on-chip buffering through automatic cancellation of
differential input current. This allows large external source
impedances and rail-to-rail input signals to be directly
digitized while maintaining exceptional DC accuracy.

The LTC2499 includes a high accuracy, temperature
sensor and an integrated oscillator. This device can be
configured to measure an external signal (from combi­nations of 16 analog input channels operating in single­ended or differential modes) or its internal temperature
sensor. The integrated temperature sensor offers 1/30th
°C resolution and 2°C absolute accuracy.

The LTC2499 allows a wide common mode input range
(0V to VCC), independent of the reference voltage. Any
combination of single-ended or differential inputs can
be selected and the first conversion, after a new channel
is selected, is valid. Access to the multiplexer output en­ables optional external amplifiers to be shared between all
analog inputs and auto calibration continuously removes
their associated offset and drift.

Typical applicaTion

Data Acquisition System with Temperature Compensation

Integrated High Performance Temperature Sensor

2499fa

1

LTC2499

13 14 15 16

TOP VIEW

39

UHF PACKAGE

38-LEAD (5mm × 7mm) PLASTIC QFN

17 18 19

38 37 36 35 34 33 32

24

25

26

27

28

29

30

31

8

7

6

5

4

3

2

1GND

SCL

SDA

GND

NC

GND

COM

CH0

CH1

CH2

CH3

CH4

GND

REF

–

REF

+

V

CC

MUXOUTN

ADCINN

ADCINP

MUXOUTP

CH15

CH14

CH13

CH12

CA2

CA1

CA0

FOGND

GND

GND

CH5

CH6

CH7

CH8

CH9

CH10

CH11

23

22

21

20

9

10

11

12

(Notes 1, 2)

Supply Voltage (VCC) ................................... –0.3V to 6V

Analog Input Voltage

(CH0-CH15, COM) ....................–0.3V to (V

+

REF
ADCINN, ADCINP, MUXOUTP,

, REF– ...............................–0.3V to (V

MUXOUTN ................................–0.3V to (V

Digital Input Voltage ......................–0.3V to (V

Digital Output Voltage ...................–0.3V to (V

Operating Temperature Range

LTC2499C .................................................

LTC2499I ..............................................

–40ºC to 85ºC

Storage Temperature Range ....................–65ºC to 150ºC

+ 0.3V)

CC

+ 0.3V)

CC

+ 0.3V)

CC

+ 0.3V)

CC

+ 0.3V)

CC

0ºC to 70ºC

package/orDer inFormaTionabsoluTe maximum raTings

T

= 125°C, θJA = 34°C/W

EXPOSED PAD (PIN #39) IS GND, MUST BE SOLDERED TO PCB

JMAX

ORDER PART NUMBER QFN PART MARKING*

LTC2499CUHF

2499

LTC2499IUHF

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is defined by a label on the shipping container.

2499fa

2

LTC2499

elecTrical characTerisTics (normal speeD)

The ● denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 0.1V ≤ V
Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, V

2.7V ≤ VCC ≤ 5.5V, V
Offset Error 2.5V ≤ V
Offset Error Drift 2.5V ≤ V
Positive Full-Scale Error 2.5V ≤ V
Positive Full-Scale Error Drift 2.5V ≤ V
Negative Full-Scale Error 2.5V ≤ V
Negative Full-Scale Error Drift 2.5V ≤ V
Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, V

5V ≤ VCC ≤ 5.5V, V

2.7V ≤ VCC ≤ 5.5V, V
Output Noise 2.7V < VCC < 5.5V, 2.5V ≤ V

GND ≤ IN+ = IN– ≤ VCC (Note 12)
Internal PTAT Signal TA = 27°C (Note 13) 27.8 28.0 28.2 mV
Internal PTAT Temperature Coefficient 93.5 µV/°C

≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 24 Bits

REF

= 5V, V

REF

= 2.5V, V

REF

≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13)

REF

≤ VCC, GND ≤ IN+ = IN– ≤ V

REF

≤ VCC, IN+ = 0.75V

REF

≤ VCC, IN+ = 0.75V

REF

≤ VCC, IN+ = 0.25V

REF

≤ VCC, IN+ = 0.25V

REF

= 2.5V, V

REF

= 5V, V

REF

= 2.5V, V

REF

IN(CM)

IN(CM)

REF

IN(CM)

REF

REF

REF

REF

IN(CM)

IN(CM)

≤ VCC,

= 2.5V (Note 6)

= 1.25V (Note 6)

CC

, IN– = 0.25V
, IN– = 0.25V
, IN– = 0.75V
, IN– = 0.75V

= 1.25V

= 2.5V

= 1.25V

REF

REF

REF

REF

●

●

●

●

●

2
1

10 ppm of V

ppm of V

0.5 2.5 µV
10 nV/°C

25 ppm of V

0.1 ppm of V

25 ppm of V

0.1 ppm of V
15

15
15

ppm of V
ppm of V
ppm of V

0.6 µV

REF

REF

REF
REF

REF

/°C

REF

/°C

REF
REF
REF

RMS

elecTrical characTerisTics (2x speeD)

The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 0.1V ≤ V
Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, V

2.7V ≤ VCC ≤ 5.5V, V
Offset Error 2.5V ≤ V
Offset Error Drift 2.5V ≤ V
Positive Full-Scale Error 2.5V ≤ V
Positive Full-Scale Error Drift 2.5V ≤ V
Negative Full-Scale Error 2.5V ≤ V
Negative Full-Scale Error Drift 2.5V ≤ V
Output Noise 5V ≤ VCC ≤ 5.5V, V

converTer characTerisTics

The ● denotes the specifications which apply over the full operating

≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 24 Bits

REF

= 5V, V

REF

= 2.5V, V

REF

≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13)

REF

≤ VCC, GND ≤ IN+ = IN– ≤ V

REF

≤ VCC, IN+ = 0.75V

REF

≤ VCC, IN+ = 0.75V

REF

≤ VCC, IN+ = 0.25V

REF

≤ VCC, IN+ = 0.25V

REF

= 5V, GND ≤ IN+ = IN– ≤ V

REF

= 2.5V (Note 6)

IN(CM)

IN(CM)

, IN– = 0.25V

REF

, IN– = 0.25V

REF

, IN– = 0.75V

REF

, IN– = 0.75V

REF

= 1.25V (Note 6)

CC

REF

REF

REF

REF

CC

●

●

●

●

2
1

10 ppm of V

ppm of V

0.2 2 mV

100 nV/°C

25 ppm of V

0.1 ppm of V
25 ppm of V

0.1 ppm of V

0.85 µV

REF

REF

REF
REF

REF

/°C

REF

/°C

RMS

temperature range, otherwise specifications are at TA = 25°C. (Note 3)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Common Mode Rejection DC 2.5V ≤ V
Input Common Mode Rejection 50Hz ±2% 2.5V ≤ V
Input Common Mode Rejection 60Hz ±2% 2.5V ≤ V
Input Normal Mode Rejection 50Hz ±2% 2.5V ≤ V
Input Normal Mode Rejection 60Hz ±2% 2.5V ≤ V
Input Normal Mode Rejection 50Hz/60Hz ±2% 2.5V ≤ V
Reference Common Mode Rejection DC 2.5V ≤ V
Power Supply Rejection DC V
Power Supply Rejection, 50Hz ±2%, 60Hz ±2% V

= 2.5V, IN+ = IN– = GND 120 dB

REF

= 2.5V, IN+ = IN– = GND (Notes 7, 8, 9) 120 dB

REF

≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)

REF

≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7)

REF

≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8)

REF

≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7)

REF

≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8)

REF

≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 9)

REF

≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)

REF

●

140 dB

●

140 dB

●

140 dB

●

110 120 dB

●

110 120 dB

●

87 dB

●

120 140 dB

2499fa

3

LTC2499

analog inpuT anD reFerence

The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

+

IN

–

IN

V

IN

FS Full Scale of the Differential Input (IN+ – IN–)
LSB Least Significant Bit of the Output Code

+

REF

–

REF
V

REF

CS(IN+) IN+ Sampling Capacitance 11 pF
CS(IN–) IN– Sampling Capacitance 11 pF
CS(V

REF

I

DC_LEAK(IN+)

I

DC_LEAK(IN–)

I

DC_LEAK(REF+)

I

DC_LEAK(REF–)

t

OPEN

QIRR MUX Off Isolation VIN = 2V

Absolute/Common Mode IN+ Voltage

GND – 0.3V VCC + 0.3V V

(IN+ Corresponds to the Selected Positive Input Channel)
Absolute/Common Mode IN– Voltage

GND – 0.3V VCC + 0.3V V

(IN– Corresponds to the Selected Negative Input Channel)

CC

●

●

●

●

●

●

●

●

●

●

–FS +FS V

0.5V

REF

24

FS/2

0.1 V

GND REF+ – 0.1V V

0.1 V

–10 1 10 nA

–10 1 10 nA
–100 1 100 nA
–100 1 100 nA

Input Differential Voltage Range (IN+ – IN–)

Absolute/Common Mode REF+ Voltage
Absolute/Common Mode REF– Voltage
Reference Voltage Range (REF+ – REF–)

) V

Sampling Capacitance 11 pF

REF

IN+ DC Leakage Current Sleep Mode, IN+ = GND
IN– DC Leakage Current Sleep Mode, IN– = GND
REF+ DC Leakage Current Sleep Mode, REF+ = V
REF– DC Leakage Current Sleep Mode, REF– = GND
MUX Break-Before-Make 50 ns

DC to 1.8MHz 120 dB

P-P

CC

CC

V

V

V

i2c inpuTs anD DigiTal ouTpuTs

The ● denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CC

●

0.7V

CC

●

●

●

●

●

●

●

●

●

●

●

●

0.05V

0.95V

CC

10 kW

2 MW

–10 10 µA

0.05V

CC

V

0.4 V

20 + 0.1C

B

0.3V

V

10 kW

250 ns

1 µA

10 pF

CC

CC

V

IH

V

IL

V

IHA

V

ILA

R

INH

High Level Input Voltage
Low Level Input Voltage
Low Level Input Voltage for Address Pins CA0, CA1, CA2
High Level Input Voltage for Address Pins CA0, CA1, CA2
Resistance from CA0, CA1, CA2 to VCC to Set Chip Address

Bit to 1

R

INL

Resistance from CA0, CA1, CA2 to GND to Set Chip Address
Bit to 0

R

INF

Resistance from CA0, CA1, CA2 to GND or VCC to Set Chip
Address Bit to Float

I

I

V

HYS

V

OL

t

OF

Digital Input Current
Hysteresis of Schmitt Trigger Inputs (Note 5)
Low Level Output Voltage (SDA) I = 3mA
Output Fall Time V

IH(MIN)

to V

IL(MAX)

Bus Load CB 10pF to
400pF (Note 14)

I

IN

C

CAX

Input Leakage 0.1VCC ≤ VIN ≤ V
External Capacitative Load on Chip Address Pins (CA0, CA1,

CA2) for Valid Float

V
V
V

4

2499fa

LTC2499

power requiremenTs

The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

CC

I

CC

Supply Voltage
Supply Current Conversion Current (Note 11)

Temperature Measurement (Note 11)
Sleep Mode (Note 11)

DigiTal inpuTs anD DigiTal ouTpuTs

The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

EOSC

t

HEO

t

LEO

t

CONV_1

t

CONV_2

External Oscillator Frequency Range (Note 16)
External Oscillator High Period
External Oscillator Low Period
Conversion Time for 1x Speed Mode 50Hz Mode

60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)

Conversion Time for 2x Speed Mode 50Hz Mode

60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)

●

2.7 5.5 V

●

●

●

●

10 4000 kHz

●

0.125 100 µs

●

0.125 100 µs

●

157.2

●

131

●

144.1
41036/f

●

78.7

●

65.6

●

72.2
20556/f

160
200

1

160.3

133.6

146.9

EOSC

80.3

66.9

73.6

EOSC

275
300

2

163.5

136.3

149.9

(in kHz)

81.9

68.2

75.1

(in kHz)

ms
ms
ms
ms

ms
ms
ms
ms

µA
µA
µA

i2c Timing characTerisTics

The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3, 15)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

SCL

t

HD(SDA)

t

LOW

t

HIGH

t

SU(STA)

t

HD(DAT)

t

SU(DAT)

t

r

t

f

t

SU(STO)

t

BUF

SCL Clock Frequency
Hold Time (Repeated) Start Condition
Low Period of the SCL Pin
High Period of the SCL Pin
Set-Up Time for a Repeated Start Condition
Data Hold Time
Data Set-Up Time
Rise Time for SDA Signals (Note 14)
Fall Time for SDA Signals (Note 14)
Set-Up Time for Stop Condition
Bus Free Time Between a Second Start Condition

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: All voltage values are with respect to GND.
Note 3: Unless otherwise specified: VCC = 2.7V to 5.5V

= V

V

REFCM

VIN = IN+ – IN–, V
where IN+ and IN– are the selected input channels.

/2, FS = 0.5V

REF

IN(CM)

REF

= (IN+ – IN–)/2,

Note 4: Use internal conversion clock or external conversion clock source
with f

= 307.2kHz unless otherwise specified.

EOSC

Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.

Note 7: 50Hz mode (internal oscillator) or f
Note 8: 60Hz mode (internal oscillator) or f
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or f

280kHz ±2% (external oscillator).
Note 10: The external oscillator is connected to the FO pin. The external

oscillator frequency, f

Note 11: The converter uses its internal oscillator.
Note 12: The output noise includes the contribution of the internal

calibration operations.

Note 13: Guaranteed by design and test correlation.
Note 14: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF).
Note 15: All values refer to V
Note 16: Refer to Applications Information section for Performance vs

Data Rate graphs.

●

●

●

●

●

●

●

●

●

●

●

0 400 kHz

0.6 µs

1.3 µs

0.6 µs

0.6 µs
0 0.9 µs

100 ns
20 + 0.1C
20 + 0.1C

0.6 µs

1.3 µs

, is expressed in kHz.

EOSC

IH(MIN)

B

B

= 256kHz ±2% (external oscillator).

EOSC

= 307.2kHz ±2% (external oscillator).

EOSC

and V

IL(MAX)

levels.

300 ns
300 ns

=

EOSC

2499fa

5

LTC2499

INPUT VOLTAGE (V)

–3

INL (ppm of V

REF

)

–1

1

3

–2

0

2

–1.5 –0.5 0.5 1.5

2499 G01

2.5–2–2.5 –1 0 1 2

VCC = 5V
V

REF

= 5V

V

IN(CM)

= 2.5V

FO = GND

85°C

–45°C

25°C

INPUT VOLTAGE (V)

–3

INL (ppm of V

REF

)

–1

1

3

–2

0

2

–0.75 –0.25 0.25 0.75

2499 G02

1.25–1.25

VCC = 5V
V

REF

= 2.5V

V

IN(CM)

= 1.25V

FO = GND

–45°C, 25°C, 85°C

INPUT VOLTAGE (V)

–3

INL (ppm of V

REF

)

–1

1

3

–2

0

2

–0.75 –0.25 0.25 0.75

2499 G03

1.25–1.25

VCC = 2.7V
V

REF

= 2.5V

V

IN(CM)

= 1.25V

FO = GND

–45°C, 25°C, 85°C

INPUT VOLTAGE (V)

–12

TUE (ppm of V

REF

)

–4

4

12

–8

0

8

–1.5 –0.5 0.5 1.5

2499 G04

2.5–2–2.5 –1 0 1 2

VCC = 5V
V

REF

= 5V

V

IN(CM)

= 2.5V

FO = GND

85°C

25°C

–45°C

INPUT VOLTAGE (V)

–12

TUE (ppm of V

REF

)

–4

4

12

–8

0

8

–0.75 –0.25 0.25 0.75

2499 G05

1.25–1.25

VCC = 5V
V

REF

= 2.5V

V

IN(CM)

= 1.25V

FO = GND

85°C

25°C

–45°C

INPUT VOLTAGE (V)

–12

TUE (ppm of V

REF

)

–4

4

12

–8

0

8

–0.75 –0.25 0.25 0.75

2499 G06

1.25–1.25

VCC = 2.7V
V

REF

= 2.5V

V

IN(CM)

= 1.25V

FO = GND

85°C

25°C

–45°C

OUTPUT READING (µV)

–3

NUMBER OF READINGS (%)

8

10

12

0.6

2499 G07

6

4

–1.8 –0.6

–2.4 1.2

–1.2 0 1.8

2

0

14

10,000 CONSECUTIVE
READINGS
VCC = 5V
V

REF

= 5V
VIN = 0V
TA = 25°C

RMS = 0.60µV

AVERAGE = –0.69µV

OUTPUT READING (µV)

–3

NUMBER OF READINGS (%)

8

10

12

0.6

2499 G08

6

4

–1.8 –0.6

–2.4 1.2

–1.2 0 1.8

2

0

14

10,000 CONSECUTIVE
READINGS
VCC = 2.7V
V

REF

= 2.5V
VIN = 0V
TA = 25°C

RMS = 0.59µV

AVERAGE = –0.19µV

TIME (HOURS)

0

–5

ADC READING (µV)

–3

–1

1

10

20

30 40

2499 G09

50

3

5

–4

–2

0

2

4

60

VCC = 5V
V

REF

= 5V
VIN = 0V
V

IN(CM)

= 2.5V

TA = 25°C
RMS NOISE = 0.60µV

Typical perFormance characTerisTics

Integral Nonlinearity
(VCC = 5V, V

REF

= 5V)

Total Unadjusted Error
(VCC = 5V, V

REF

= 5V)

Integral Nonlinearity
(VCC = 5V, V

= 2.5V)

REF

Total Unadjusted Error
(VCC = 5V, V

= 2.5V)

REF

Integral Nonlinearity
(VCC = 2.7V, V

REF

= 2.5V)

Total Unadjusted Error
(VCC = 2.7V, V

REF

= 2.5V)

6

Noise Histogram (6.8sps)

Noise Histogram (7.5sps)

Long-Term ADC Readings

2499fa

Typical perFormance characTerisTics

INPUT DIFFERENTIAL VOLTAGE (V)

0.4

RMS NOISE (µV)

0.6

0.8

1.0

0.5

0.7

0.9

–1.5 –0.5 0.5 1.5

2499 G10

2.5–2–2.5 –1 0 1 2

VCC = 5V
V

REF

= 5V

V

IN(CM)

= 2.5V
TA = 25°C
FO = GND

V

IN(CM)

(V)

–1

RMS NOISE (µV)

0.8

0.9

1.0

2 4

2499 G11

0.7

0.6

0 1

3 5 6

0.5

0.4

VCC = 5V
V

REF

= 5V
VIN = 0V
TA = 25°C
FO = GND

TEMPERATURE (°C)

–45

0.4

RMS NOISE (µV)

0.5

0.6

0.7

0.8

1.0

–30 –15 15

0 30 45 60

2499 G12

75 90

0.9

VCC = 5V
V

REF

= 5V
VIN = 0V
V

IN(CM)

= GND

FO = GND

VCC (V)

2.7

RMS NOISE (µV)

0.8

0.9

1.0

3.9 4.7

2499 G13

0.7

0.6

3.1 3.5

4.3 5.1 5.5

0.5

0.4

V

REF

= 2.5V
VIN = 0V
V

IN(CM)

= GND
TA = 25°C
FO = GND

V

REF

(V)

0

0.4

RMS NOISE (µV)

0.5

0.6

0.7

0.8

0.9

1.0

1 2 3 4

2499 G14

5

VCC = 5V
VIN = 0V
V

IN(CM)

= GND
TA = 25°C
FO = GND

V

IN(CM)

(V)

–1

OFFSET ERROR (ppm of V

REF

)

0.1

0.2

0.3

2 4

2499 G15

0

–0.1

0 1

3 5 6

–0.2

–0.3

VCC = 5V
V

REF

= 5V
VIN = 0V
TA = 25°C
FO = GND

TEMPERATURE (°C)

–45

–0.3

OFFSET ERROR (ppm of V

REF

)

–0.2

0

0.1

0.2

–15

15

30 90

2499 G16

–0.1

–30 0

45

60

75

0.3
VCC = 5V

V

REF

= 5V
VIN = 0V
V

IN(CM)

= GND

FO = GND

VCC (V)

2.7

OFFSET ERROR (ppm of V

REF

)

0.1

0.2

0.3

3.9 4.7

2499 G17

0

–0.1

3.1 3.5

4.3 5.1 5.5

–0.2

–0.3

REF+ = 2.5V
REF– = GND
VIN = 0V
V

IN(CM)

= GND
TA = 25°C
FO = GND

V

REF

(V)

0

–0.3

OFFSET ERROR (ppm of V

REF

)

–0.2

–0.1

0

0.1

0.2

0.3

1 2 3 4

2499 G18

5

VCC = 5V
REF– = GND
VIN = 0V
V

IN(CM)

= GND
TA = 25°C
FO = GND

LTC2499

RMS Noise
vs Input Differential Voltage

RMS Noise vs V

CC

RMS Noise vs V

RMS Noise vs V

IN(CM)

REF

RMS Noise vs Temperature (TA)

Offset Error vs V

IN(CM)

Offset Error vs Temperature

Offset Error vs V

CC

Offset Error vs V

REF

2499fa

7

LTC2499

TEMPERATURE (°C)

–45 –30

300

FREQUENCY (kHz)

304

310

–15

30

45

2499 G19

302

308

306

150

60 75

90

VCC = 4.1V
V

REF

= 2.5V
VIN = 0V
V

IN(CM)

= GND

FO = GND

VCC (V)

2.5

300

FREQUENCY (kHz)

302

304

306

308

310

3.0

3.5 4.0 4.5

2499 G20

5.0 5.5

V

REF

= 2.5V
VIN = 0V
V

IN(CM)

= GND
FO = GND
TA = 25°C

FREQUENCY AT VCC (Hz)

1

0

–20

–40

–60

–80

–100

–120

–140

1k 100k

2499 G21

10 100

10k 1M

REJECTION (dB)

VCC = 4.1V DC
V

REF

= 2.5V
IN+ = GND
IN– = GND
FO = GND
TA = 25°C

FREQUENCY AT VCC (Hz)

0

–140

REJECTION (dB)

–120

–80

–60

–40

0

20

100

140

2499 G22

–100

–20

80

180

220200

40

60

120 160

VCC = 4.1V DC ±1.4V
V

REF

= 2.5V
IN+ = GND
IN– = GND
FO = GND
TA = 25°C

FREQUENCY AT VCC (Hz)

30600

–60

–40

0

30750

2499 G23

–80

–100

30650 30700 30800

–120

–140

–20

REJECTION (dB)

VCC = 4.1V DC ±0.7V
V

REF

= 2.5V
IN+ = GND
IN– = GND
FO = GND
TA = 25°C

TEMPERATURE (°C)

–45

100

CONVERSION CURRENT (µA)

120

160

180

200

–15

15

30 90

2499 G24

140

–30 0

45

60

75

VCC = 5V

VCC = 2.7V

FO = GND

TEMPERATURE (°C)

–45

0

SLEEP MODE CURRENT (µA)

0.2

0.6

0.8

1.0

2.0

1.4

–15

15

30 90

2499 G25

0.4

1.6

1.8

1.2

–30 0

45

60

75

VCC = 5V

VCC = 2.7V

FO = GND

OUTPUT DATA RATE (READINGS/SEC)

0

SUPPLY CURRENT (µA)

500

450

400

350

300

250

200

150

100

80

2499 G26

20 40 60 1007010 30 50 90

VCC = 5V

VCC = 3V

V

REF

= V

CC

IN+ = GND
IN– = GND
FO = EXT OSC
TA = 25°C

INPUT VOLTAGE (V)

–3

INL (µV)

–1

1

3

–2

0

2

–1.5 –0.5 0.5 1.5

2499 G27

2.5–2–2.5 –1 0 1 2

VCC = 5V
V

REF

= 5V

V

IN(CM)

= 2.5V

FO = GND

25°C, 90°C

–45°C

Typical perFormance characTerisTics

On-Chip Oscillator Frequency
vs Temperature

PSRR vs Frequency at V

CC

On-Chip Oscillator Frequency
vs V

CC

PSRR vs Frequency at V

CC

PSRR vs Frequency at V

Conversion Current
vs Temperature

CC

8

Sleep Mode Current
vs Temperature

Conversion Current
vs Output Data Rate

Integral Nonlinearity (2x Speed
Mode; VCC = 5V, V

REF

= 5V)

2499fa

Typical perFormance characTerisTics

INPUT VOLTAGE (V)

–3

INL (ppm OF V

REF

)

–1

1

3

–2

0

2

–0.75 –0.25 0.25 0.75

2499 G28

1.25–1.25

VCC = 5V
V

REF

= 2.5V

V

IN(CM)

= 1.25V

FO = GND

85°C

–45°C, 25°C

INPUT VOLTAGE (V)

–3

INL (ppm OF V

REF

)

–1

1

3

–2

0

2

–0.75 –0.25 0.25 0.75

2499 G29

1.25–1.25

VCC = 2.7V
V

REF

= 2.5V

V

IN(CM)

= 1.25V

FO = GND

85°C

–45°C, 25°C

OUTPUT READING (µV)

179

NUMBER OF READINGS (%)

8

10

12

186.2

2499 G30

6

4

181.4 183.8 188.6

2

0

16

14

10,000 CONSECUTIVE
READINGS
VCC = 5V
V

REF

= 5V
VIN = 0V
TA = 25°C

RMS = 0.85µV

AVERAGE = 0.184mV

V

REF

(V)

0

RMS NOISE (µV)

0.6

0.8

1.0

4

2499 G31

0.4

0.2

0

1

2

3

5

VCC = 5V
VIN = 0V
V

IN(CM)

= GND
FO = GND
TA = 25°C

V

IN(CM)

(V)

–1

180

OFFSET ERROR (µV)

182

186

188

190

200

194

1

3

4

2499 G32

184

196

198

192

0

2

5

6

VCC = 5V
V

REF

= 5V
VIN = 0V
FO = GND
TA = 25°C

TEMPERATURE (°C)

–45

OFFSET ERROR (µV)

200

210

220

75

2499 G33

190

180

160

–15

15

45

–30 90

0

30

60

170

240

230

VCC = 5V
V

REF

= 5V
VIN = 0V
V

IN(CM)

= GND

FO = GND

LTC2499

Integral Nonlinearity (2x Speed
Mode; VCC = 5V, V

RMS Noise vs V

REF

REF

= 2.5V)

(2x Speed Mode)

Integral Nonlinearity (2x Speed
Mode; VCC = 2.7V, V

Offset Error vs V

REF

IN(CM)

= 2.5V)

(2x Speed Mode)

Noise Histogram
(2x Speed Mode)

Offset Error vs Temperature
(2x Speed Mode)

2499fa

9

LTC2499

VCC (V)

2 2.5

0

OFFSET ERROR (µV)

100

250

3

4

4.5

2499 G34

50

200

150

3.5

5

5.5

V

REF

= 2.5V
VIN = 0V
V

IN(CM)

= GND
FO = GND
TA = 25°C

V

REF

(V)

0

OFFSET ERROR (µV)

190

200

210

3

5

2499 G35

180

170

160

1 2 4

220

230

240

VCC = 5V
VIN = 0V
V

IN(CM)

= GND
FO = GND
TA = 25°C

FREQUENCY AT VCC (Hz)

1

0

–20

–40

–60

–80

–100

–120

–140

1k 100k

2499 G36

10 100

10k 1M

REJECTION (dB)

VCC = 4.1V DC
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C

FREQUENCY AT VCC (Hz)

0

–140

RREJECTION (dB)

–120

–80

–60

–40

0

20

100

140

2499 G37

–100

–20

80

180

220200

40

60

120 160

VCC = 4.1V DC ±1.4V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C

FREQUENCY AT VCC (Hz)

30600

–60

–40

0

30750

2499 G38

–80

–100

30650 30700 30800

–120

–140

–20

REJECTION (dB)

VCC = 4.1V DC ±0.7V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C

Typical perFormance characTerisTics

Offset Error vs VCC
(2x Speed Mode)

PSRR vs Frequency at V
(2x Speed Mode)

Offset Error vs V
(2x Speed Mode)

CC

REF

PSRR vs Frequency at V

CC

(2x Speed Mode)

PSRR vs Frequency at V

CC

(2x Speed Mode)

pin FuncTions

GND (Pins 1, 4, 6, 31, 32, 33, 34): Ground. Multiple
ground pins internally connected for optimum ground cur­rent flow and VCC decoupling. Connect each one of these
pins to a common ground plane through a low impedance
connection. All seven pins must be connected to ground
for proper operation.

SCL (Pin 2): Serial Clock Pin of the I2C Interface. The
LTC2499 can only act as a slave and the SCL pin only ac­cepts an external serial clock. Data is shifted into the SDA

10

pin on the rising edges of the SCL clock and output through
the SDA pin on the falling edges of the SCL clock.

SDA (Pin 3): Bidirectional Serial Data Line of the I2C Inter-
face. In the transmitter mode (Read), the conversion result
is output through the SDA pin, while in the receiver mode
(Write), the device channel select and configuration bits
are input through the SDA pin. The pin is high impedance
during the data input mode and is an open drain output
(requires an appropriate pull-up device to VCC) during the
data output mode.

2499fa

pin FuncTions

AUTOCALIBRATION

AND CONTROL

DIFFERENTIAL

3RD ORDER

∆Σ MODULATOR

DECIMATING FIR

ADDRESS

INTERNAL

OSCILLATOR

I2C

2-WIRE

INTERFACE

GND

V

CC

CH0
CH1

•

•

•

CH15

COM

MUX

SDA

REF

+

REF

–

ADCINNMUXOUTN

ADCINPMUXOUTP

SCL

F

O

(INT/EXT)

2499 BD

+

–

TEMP

SENSOR

LTC2499

NC (Pin 5): No Connect. This pin can be left floating or
tied to GND.

COM (Pin 7): The Common Negative Input (IN–) for All
Single-Ended Multiplexer Configurations. The voltage on
CH0-CH15 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN– ) provide a bipolar input
range (VIN = IN+ – IN– ) from –0.5 • V

to 0.5 • V

REF

REF

.
Outside this input range, the converter produces unique
over-range and under-range output codes.

CH0 to CH15 (Pin 8-Pin 23): Analog Inputs. May be pro­grammed for single-ended or differential mode.

MUXOUTP (Pin 24): Positive Multiplexer Output. Connect
to the input of external buffer/amplifier or short directly
to ADCINP.

ADCINP (Pin 25): Positive ADC Input. Connect to the
output of a buffer/amplifier driven by MUXOUTP or short
directly to MUXOUTP.

ADCINN (Pin 26): Negative ADC Input. Connect to the
output of a buffer/amplifier driven by MUXOUTN or short
directly to MUXOUTN

MUXOUTN (Pin 27): Negative Multiplexer Output. Con­nect to the input of an external buffer/amplifier or short
directly to ADCINN.

VCC (Pin 28): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor as close to the part as possible.

REF+, REF– (Pin 29, Pin 30): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 0.1V. The differential voltage (V

REF

= REF+

– REF–) sets the full-scale range for all input channels.

FO (Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock rate. When FO is
connected to GND, the converter uses its internal oscil­lator running at 307.2kHz. The conversion clock may
also be overridden by driving the FO pin with an external
clock in order to change the output rate and the digital
filter rejection null.

CA0, CA1, CA2 (Pins 36, 37, 38): Chip Address Control
Pins. These pins are configured as a three-state (LOW,
HIGH, Floating) address control bits for the device I2C
address.

Exposed Pad (Pin 39): Ground. This pin is ground and
must be soldered to the PCB ground plane. For prototyping
purposes, this pin may remain floating.

FuncTional block Diagram

2499fa

11

LTC2499

CONVERSION

SLEEP

2499 F01

YES

NO

ACKNOWLEDGE

YES

NO

STOP

OR READ

32 BITS

DATA OUTPUT/INPUT

POWER-ON RESET

DEFAULT CONFIGURATION:

IN+ = CH0, IN– = CH1

50Hz/60Hz REJECTION

1X OUTPUT

applicaTions inFormaTion

CONVERTER OPERATION

Converter Operation Cycle

The LTC2499 is a multichannel, low power, delta-sigma
analog-to-digital converter with a 2-wire, I2C interface.
Its operation is made up of four states (see Figure 1).
The converter operating cycle begins with the conver­sion, followed by the sleep state and ends with the data
input/output cycle .

Initially, at power-up, the LTC2499 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in the sleep state, power consumption is
reduced by two orders of magnitude. The part remains in
the sleep state as long it is not addressed for a read/write
operation. The conversion result is held indefinitely in a
static shift register while the part is in the sleep state.

The device will not acknowledge an external request dur­ing the conversion state. After a conversion is finished,
the device is ready to accept a read/write request. Once
the LTC2499 is addressed for a read operation, the device
begins outputting the conversion result under the control
of the serial clock (SCL). There is no latency in the conver­sion result. The data output is 32 bits long and contains a
24-bit plus sign conversion result. Data is updated on the
falling edges of SCL allowing the user to reliably latch data
on the rising edge of SCL. A new conversion is initiated
by a stop condition following a valid write operation or an
incomplete read operation. The conversion automatically
begins at the conclusion of a complete read cycle (all 32
bits read out of the device).

Ease of Use

The LTC2499 data output has no latency, filter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straightforward. Each conver­sion, immediately following a newly selected input or
mode, is valid and accurate to the full specifications of
the device.

The LTC2499 automatically performs offset and full-scale
calibration every conversion cycle independent of the input
channel selected. This calibration is transparent to the user

12

Figure 1. State Transition Table

and has no effect on the operation cycle described above.
The advantage of continuous calibration is extreme stability
of offset and full-scale readings with respect to time, supply
voltage variation, input channel, and temperature drift.

Easy Drive Input Current Cancellation

The LTC2499 combines a high precision, delta-sigma ADC
with an automatic, differential, input current cancellation
front end. A proprietary front end passive sampling network
transparently removes the differential input current. This
enables external RC networks and high impedance sen­sors to directly interface to the LTC2499 without external
amplifiers. The remaining common mode input current
is eliminated by either balancing the differential input im­pedances or setting the common mode input equal to the
common mode reference (see the Automatic Differential
Input Current Cancellation section). This unique architec­ture does not require on-chip buffers, thereby enabling
signals to swing beyond ground and VCC. Moreover, the

2499fa

applicaTions inFormaTion

LTC2499

cancellation does not interfere with the transparent offset
and full-scale auto-calibration and the absolute accuracy
(full scale + offset + linearity + drift) is maintained even
with external RC networks.

Power-Up Sequence

The LTC2499 automatically enters an internal reset state
when the power supply voltage VCC drops below approxi­mately 2.0V. This feature guarantees the integrity of the
conversion result and input channel selection.

When VCC rises above this threshold, the converter creates
an internal power-on-reset (POR) signal with a duration
of approximately 4ms. The POR signal clears all internal
registers. The conversion immediately following a POR
cycle is performed on the input channel IN+ = CH0, IN– =
CH1 with simultaneous 50Hz/60Hz rejection and 1x output
rate. The first conversion following a POR cycle is accurate
within the specification of the device if the power supply
voltage is restored to (2.7V to 5.5V) before the end of the
POR interval. A new input channel, rejection mode, speed
mode, or temperature selection can be programmed into
the device during this first data input/output cycle.

Reference Voltage Range

This converter accepts a truly differential external reference
voltage. The absolute/common mode voltage range for
REF+ and REF– pins covers the entire operating range of
the device (GND to VCC). For correct converter operation,
V

must be positive (REF+ > REF–).

REF

The LTC2499 differential reference input range is 0.1V to
VCC. For the simplest operation, REF+ can be shorted to
VCC and REF– can be shorted to GND. The converter out­put noise is determined by the thermal noise of the front
end circuits and, as such, its value in nanovolts is nearly
constant with reference voltage. A decrease in reference
voltage will not significantly improve the converter’s effec­tive resolution. On the other hand, a decreased reference
will improve the converter’s overall INL performance.

Input Voltage Range

The analog inputs are truly differential with an absolute,
common mode range for the CH0-CH15 and COM input
pins extending from GND – 0.3V to V
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase rapidly.
Within these limits, the LTC2499 converts the bipolar dif­ferential input signal VIN = IN+ – IN– (where IN+ and IN– are
the selected input channels), from – FS = – 0.5 • V
to + FS = 0.5 • V
this range, the converter indicates the overrange or the
underrange condition using distinct output codes (see
Table 1).

Signals applied to the input (CH0-CH15, COM) may extend
300mV below ground and above VCC. In order to limit
any fault current, resistors of up to 5kW may be added in
series with the input. The effect of series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent error due to input leakage current. A 1nA input
leakage current will develop a 1ppm offset error on a 5k
resistor if V
perature dependency.

MUXOUT/ADCIN

The outputs of the multiplexer (MUXOUTP/MUXOUTN) and
the inputs to the ADC (ADCINP/ADCINN) can be used to
perform input signal conditioning on any of the selected
input channels or simply shorted together for direct
digitization. If an external amplifier is used, the LTC2499
automatically calibrates both the offset and drift of this
circuit and the Easy Drive sampling scheme enables a
wide variety of amplifiers to be used.

In order to achieve optimum performance, if an external
amplifier is not used, short these pins directly together
(ADCINP to MUXOUTP and ADCINN to MUXOUTN) and
minimize their capacitance to ground.

REF

where V

REF

= 5V. This error has a very strong tem-

= REF+ - REF–. Outside

REF

+ 0.3V. Outside

CC

REF

2499fa

13

LTC2499

SDA

SCL

S Sr P S

t

HD(SDA)

t

HD(DAT)

t

SU(STA)

t

SU(STO)

t

SU(DAT)

t

LOW

t

HD(SDA)

t

SP

t

BUF

t

r

t

f

t

r

t

f

t

HIGH

2499 F02

applicaTions inFormaTion

I2C INTERFACE

The LTC2499 communicates through an I2C interface. The
I2C interface is a 2-wire open-drain interface supporting
multiple devices and multiple masters on a single bus. The
connected devices can only pull the data line (SDA) low
and can never drive it high. SDA is required to be externally
connected to the supply through a pull-up resistor. When
the data line is not being driven, it is high. Data on the
I2C bus can be transferred at rates up to 100kbits/s in the
standard mode and up to 400kbits/s in the fast mode.

Each device on the I2C bus is recognized by a unique
address stored in that device and can operate either as a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when perform­ing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals
to permit that transfer. Devices addressed by the master
are considered a slave.

The LTC2499 can only be addressed as a slave. Once
addressed, it can receive configuration bits (channel
selection, rejection mode, speed mode) or transmit the
last conversion result. The serial clock line, SCL, is always
an input to the LTC2499 and the serial data line SDA is
bidirectional. The device supports the standard mode and
the fast mode for data transfer speeds up to 400kbits/s.
Figure 2 shows the definition of the I2C timing.

The Start and Stop Conditions

A Start (S) condition is generated by transitioning SDA from
high to low while SCL is high. The bus is considered to be
busy after the Start condition. When the data transfer is

finished, a Stop (P) condition is generated by transitioning
SDA from low to high while SCL is high. The bus is free
after a Stop is generated. Start and Stop conditions are
always generated by the master.

When the bus is in use, it stays busy if a Repeated Start
(Sr) is generated instead of a Stop condition. The repeated
Start timing is functionally identical to the Start and is
used for writing and reading from the device before the
initiation of a new conversion.

Data Transferring

After the Start condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit.
The master releases the SDA line during the ninth SCL
clock cycle. The slave device can issue an ACK by pulling
SDA low or issue a Not Acknowledge (NAK) by leaving
the SDA line high impedance (the external pull-up resistor
will hold the line high). Change of data only occurs while
the clock line (SCL) is low.

DATA FORMAT

After a Start condition, the master sends a 7-bit address
followed by a read/write (R/W) bit. The R/W bit is 1 for a
read request and 0 for a write request. If the 7-bit address
matches the hard wired LTC2499’s address (one of 27
pin-selectable addresses) the device is selected. When
the device is addressed during the conversion state, it will
not acknowledge R/W requests and will issue a NAK by
leaving the SDA line high. If the conversion is complete,
the LTC2499 issues an ACK by pulling the SDA line low.

Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus

14

2499fa

applicaTions inFormaTion

LTC2499

The LTC2499 has two registers. The output register (32
bits long) contains the last conversion result. The input
register (16 bits long) sets the input channel, selects the
temperature sensor, rejection mode, and speed mode.

DATA OUTPUT FORMAT

The output register contains the last conversion result.
After each conversion is completed, the device automati­cally enters the sleep state where the supply current is
reduced to 1µA. When the LTC2499 is addressed for a read
operation, it acknowledges (by pulling SDA low) and acts
as a transmitter. The master/receiver can read up to four
bytes from the LTC2499. After a complete read operation
(4 bytes), a new conversion is initiated. The device will
NAK subsequent read operations while a conversion is
being performed.

The data output stream is 32 bits long and is shifted out
on the falling edges of SCL (see Figure 3a). The first bit
is the conversion result sign bit (SIG) (see Tables 1 and

2). This bit is high if VIN ≥ 0 and low if VIN < 0 (where VIN
corresponds to the selected input signal IN+ – IN–). The
second bit is the most significant bit (MSB) of the result.
The first two bits (SIG and MSB) can be used to indicate
over and under range conditions (see Table 2). If both bits

are HIGH, the differential input voltage is equal to or above
+FS. If both bits are set low, the input voltage is below –FS.
The function of these bits is summarized in Table 2. The
24 bits following the MSB bit are the conversion result in
binary two’s, complement format. The remaining six bits
are sub LSBs below the 24-bit level.

As long as the voltage on the selected input channels (IN+
and IN–) remains between –0.3V and VCC + 0.3V (absolute
maximum operating range) a conversion result is gener­ated for any differential input voltage VIN from –FS = –0.5

• V

to +FS = 0.5 • V

REF

. For differential input voltages

REF

greater than +FS, the conversion result is clamped to the
value corresponding to +FS. For differential input voltages
below –FS, the conversion result is clamped to the value
–FS – 1LSB.

Table 2. LTC2499 Status Bits

Input Range

VIN ≥ FS 1 1
0V ≤ VIN < FS 1 0
–FS ≤ VIN < 0V 0 1
VIN < –FS 0 0

Bit 31

SIG

Bit 30

MSB

Table 1. Output Data Format

Differential Input Voltage
VIN*

VIN* ≥ FS** 1 1 0 0 0 … 0 00000
FS** – 1LSB 1 0 1 1 1 … 1 XXXXX

0.5 • FS** 1 0 1 0 0 … 0 XXXXX

0.5 • FS** – 1LSB 1 0 0 1 1 … 1 XXXXX
0 1 0 0 0 0 … 0 XXXXX
–1LSB 0 1 1 1 1 … 1 XXXXX
–0.5 • FS** 0 1 1 0 0 … 0 XXXXX
–0.5 • FS** – 1LSB 0 1 0 1 1 … 1 XXXXX
–FS** 0 1 0 0 0 … 0 XXXXX
VIN* < –FS** 0 0 1 1 1 … 1 11111

*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • V
*** Sub LSBs are below the 24-bit level. They may be included in averaging, or discarded without loss of resolution.

Bit 31

SIG

Bit 30

MSB

Bit 29 Bit 28 Bit 27 … Bit 6

.

REF

LSB

Bits 5-0

Sub LSBs***

2499fa

15

LTC2499

SLEEP DATA OUTPUT

ACK BY

LTC2499

ACK BY

MASTER

SUB LSBs

START BY

MASTER

NAK BY

MASTER

LSBR MSBSGN

DIS

7 … …8 9 1 2 9

1 2 3 4 5 6 7 8 9

1

7-BIT

ADDRESS

2499 F03a

SLEEP DATA INPUT

ACK BY

LTC2499

ACK

LTC2499

ACK

LTC2499

(OPTIONAL 2ND BYTE)

START BY

MASTER

SGL ODD

W

01

SCL

SDA

EN A2 A1 A0

7 … 8 9 12 9

1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9

1

7-BIT ADDRESS

2499 F03b

IM FAEN2 FB SPD

applicaTions inFormaTion

INPUT DATA FORMAT

The serial input word to the LTC2499 is 13 bits long and
is written into the device input register in two 8-bit words.
The first word (SGL, ODD, A2, A1, A0) is used to select
the input channel. The second word of data (IM, FA, FB,
SPD) is used to select the frequency rejection, speed
mode (1x, 2x), and temperature measurement.

After power-up, the device initiates an internal reset cycle
which sets the input channel to CH0-CH1 (IN+ = CH0, IN– =
CH1), the frequency rejection to simultaneous 50Hz/60Hz,
and 1x output rate (auto-calibration enabled). The first
conversion automatically begins at power-up using this
default configuration. Once the conversion is complete,
up to two words may be written into the device.

The first three bits of the first input word consist of two
preamble bits and one enable bit. Valid settings for these
three bits are 000, 100, and 101. Other combinations
should be avoided.

If the first three bits are 000 or 100, the following data
is ignored (don’t care) and the previously selected input
channel remains valid for the next conversion

If the first three bits shifted into the device are 101, then
the next five bits select the input channel for the next
conversion cycle (see Table 3).

The first input bit (SGL) following the 101 sequence de­termines if the input selection is differential (SGL = 0) or
single-ended (SGL = 1). For SGL = 0, two adjacent chan­nels can be selected to form a differential input. For SGL
= 1, one of 16 channels is selected as the positive input.
The negative input is COM for all single-ended operations.
The remaining four bits (ODD, A2, A1, A0) determine
which channel(s) is/are selected and the polarity (for a
differential input).

Once the first word is written into the device, a second
word may be input in order to select a configuration mode.

16

Figure 3a. Timing Diagram for Reading from the LTC2499

Figure 3b. Timing Diagram for Writing to the LTC2499

2499fa

LTC2499

applicaTions inFormaTion

Table 3. Channel Selection

MUX ADDRESS CHANNEL SELECTION

ODD/

SGL

SIGN A2 A1 A0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 COM

*0

0 0 0 0 IN+IN
0 0 0 0 1 IN+IN
0 0 0 1 0 IN+IN
0 0 0 1 1 IN+IN
0 0 1 0 0 IN+IN
0 0 1 0 1 IN+IN
0 0 1 1 0 IN+IN
0 0 1 1 1 IN+IN
0 1 0 0 0 IN–IN
0 1 0 0 1 IN–IN
0 1 0 1 0 IN–IN
0 1 0 1 1 IN–IN
0 1 1 0 0 IN–IN
0 1 1 0 1 IN–IN
0 1 1 1 0 IN–IN
0 1 1 1 1 IN–IN
1 0 0 0 0 IN
1 0 0 0 1 IN
1 0 0 1 0 IN
1 0 0 1 1 IN
1 0 1 0 0 IN
1 0 1 0 1 IN
1 0 1 1 0 IN
1 0 1 1 1 IN
1 1 0 0 0 IN
1 1 0 0 1 IN
1 1 0 1 0 IN
1 1 0 1 1 IN
1 1 1 0 0 IN
1 1 1 0 1 IN
1 1 1 1 0 IN
1 1 1 1 1 IN+IN

*Default at power up

–

–

–

–

–

–

–

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

–

+

–

IN

–

IN

–

IN

–

IN

–

IN

–

IN

–

IN

–

IN

–

IN

–

IN

–

IN

–

IN

–

IN

–

IN

–

IN

–

2499fa

17

LTC2499

applicaTions inFormaTion

The first bit of the second word is the enable bit for the
conversion configuration (EN2). If this bit is set to 0, then
the next conversion is performed using the previously
selected converter configuration.

A new configuration can be loaded into the device by
setting EN2 = 1 (see Table 4). The first bit (IM) is used

up to 15Hz with no latency). When IM = 1 (temperature
measurement) SPD will be ignored and the device will
operate in 1x mode.

The configuration remains valid until a new input word with
EN = 1 (the first three bits are 101 for the first word) and EN2
= 1 (for the second write byte) is shifted into the device.

to select the internal temperature sensor. If IM = 1, the
following conversion will be performed on the internal
temperature sensor rather than the selected input channel.
The next two bits (FA and FB) are used to set the rejection
frequency. The final bit (SPD) is used to select either the
1x output rate if SPD = 0 (auto-calibration is enabled and
the offset is continuously calibrated and removed from
the final conversion result) or the 2x output rate if SPD
= 1 (offset calibration disabled, multiplexing output rates

Table 4. Converter Configuration

1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD CONVERTER CONFIGURATION

1 0 0 X X X X X X X X X X Keep Previous
1 0 1 X X X X X 0 X X X X Keep Previous
0 0 1 X X X X X X X X X X Keep Previous
1 0 1 X X X X X 1 0 0 0 0 External Input (See Table 3)

1 0 1 X X X X X 1 0 0 1 0 External Input (See Table 3)

1 0 1 X X X X X 1 0 1 0 0 External Input (See Table 3)

1 0 1 X X X X X 1 0 0 0 1 External Input (See Table 3)

1 0 1 X X X X X 1 0 0 1 1 External Input (See Table 3)

1 0 1 X X X X X 1 0 1 0 1 External Input (See Table 3)

1 0 1 X X X X X 1 1 0 0 X Measure Temperature

1 0 1 X X X X X 1 1 0 1 X Measure Temperature

1 0 1 X X X X X 1 1 1 0 X Measure Temperature

1 0 1 X X X X X 1 X 1 1 X Reserved, Do Not Use

Rejection Mode (FA, FB)

The LTC2499 includes a high accuracy on-chip oscillator
with no required external components. Coupled with an
integrated fourth order digital low pass filter, the LTC2499
rejects line frequency noise. In the default mode, the
LTC2499 simultaneously rejects 50Hz and 60Hz by at least
87dB. If more rejection is required, the LTC2499 can be
configured to reject 50Hz or 60Hz to better than 110dB.

50Hz/60Hz Rejection, 1x

50Hz Rejection, 1x

60Hz Rejection, 1x

50Hz/60Hz Rejection, 2x

50Hz Rejection, 2x

60Hz Rejection, 2x

50Hz/60Hz Rejection, 1x

50Hz Rejection, 1x

60Hz Rejection, 1x

18

2499fa

T

DATAOUT

in Kelvin

K

=

24

314

T

DATAOUT

V

in Kelvin

K

REF

=

24

1570

•

SLOPE

DATAOUT

T

N

=

24

T

DATAOUT

SLOPE

K

=

24

TEMPERATURE (K)

0

DATAOUT

24

60000

80000

100000

120000

140000

400

2499 F04

40000

0

300200100

20000

VCC = 5V
V

REF

= 5V

SLOPE = 314 LSB24/K

TEMPERATURE (°C)

–55 –30 –5

ABSOLUTE ERROR (°C)

5

4

3

2

1

–4

–3

–2

–1

0

12095704520

2499 F05

–5

applicaTions inFormaTion

LTC2499

Speed Mode (SPD)

Every conversion cycle, two conversions are combined
to remove the offset (default mode). This result is free
from offset and drift. In applications where the offset is
not critical, the auto-calibration feature can be disabled
with the benefit of twice the output rate.

While operating in the 2x mode (SPD = 1), the linearity
and full-scale errors are unchanged from the 1x mode
performance. In both the 1x and 2x mode there is no
latency. This enables input steps or multiplexer changes
to settle in a single conversion cycle, easing system over­head and increasing the effective conversion rate. During
temperature measurements, the 1x mode is always used
independent of the value of SPD.

Temperature Sensor

The LTC2499 includes an integrated temperature sen­sor. The temperature sensor is selected by setting
IM = 1. During temperature readings, MUXOUTN/
MUXOUTP remains connected to the selected input chan­nel. The ADC internally connects to the temperature sensor
and performs a conversion.

(see Figures 4 and 5). Slope calibration is not required if
the reference voltage (V

) is known. A 5V reference has

REF

a slope of 314 LSBs24/ºC. The temperature is calculated
from the output code (where DATAOUT24 is the decimal
representation of the 24-bit result) for a 5V reference using
the following formula:

If a different value of V

is used, the temperature

REF

output is:

If the value of V

is not known, the slope is determined

REF

by measuring the temperature sensor at a known tempera­ture TN (in K) and using the following formula:

This value of slope can be used to calculate further tem­perature readings using:

The digital output is proportional to the absolute tem­perature of the device. This feature allows the converter
to perform cold junction compensation for external
thermocouples or continuously remove the temperature
effects of external sensors.

The internal temperature sensor output is 28mV at 27ºC
(300ºK), with a slope of 93.5µV/ºC independent of V

Figure 4. Internal PTAT Digital Output vs Temperature Figure 5. Absolute Temperature Error

REF

All Kelvin temperature readings can be converted to TC
(ºC) using the fundamental equation:

= TK – 273

T

C

2499fa

19

LTC2499

applicaTions inFormaTion

Initiating a New Conversion

When the LTC2499 finishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device is
ready for a read operation. After the device acknowledges
a read request, the device exits the sleep state and enters
the data output state. The data output state concludes
and the LTC2499 starts a new conversion once a Stop
condition is issued by the master or all 32 bits of data are
read out of the device.

During the data read cycle, a Stop command may be issued
by the master controller in order to start a new conversion
and abort the data transfer. This Stop command must be
issued during the ninth clock cycle of a byte read when
the bus is free (the ACK/NAK cycle).

LTC2499 Address

The LTC2499 has three address pins (CA0, CA1, CA2).
Each may be tied high, low, or left floating enabling one
of 27 possible addresses (see Table 5).

In addition to the configurable addresses listed in Table
5, the LTC2499 also contains a global address (1110111)
which may be used for synchronizing multiple LTC2499s or
other LTC24XX delta-sigma I2C devices (see Synchronizing
Multiple LTC2499s with a Global Address Call section).

Operation Sequence

The LTC2499 acts as a transmitter or receiver, as shown
in Figure 6. The device may be programmed to perform
several functions. These include input channel selection,
measure the internal temperature, selecting the line fre­quency rejection (50Hz, 60Hz, or simultaneous 50Hz and
60Hz), and a 2x speed mode.

Continuous Read

In applications where the input channel/configuration does
not need to change for each cycle, the conversion can be
continuously performed and read without a write cycle
(see Figure 7). The configuration/input channel remains
unchanged from the last value written into the device. If
the device has not been written to since power up, the
configuration is set to the default value. At the end of a
read operation, a new conversion automatically begins.
At the conclusion of the conversion cycle, the next result

Table 5. Address Assignment

CA2 CA1 CA0 ADDRESS

LOW LOW LOW 0010100
LOW LOW HIGH 0010110
LOW LOW FLOAT 0010101
LOW HIGH LOW 0100110
LOW HIGH HIGH 0110100
LOW HIGH FLOAT 0100111
LOW FLOAT LOW 0010111
LOW FLOAT HIGH 0100101

LOW FLOAT FLOAT 0100100
HIGH LOW LOW 1010110
HIGH LOW HIGH 1100100
HIGH LOW FLOAT 1010111
HIGH HIGH LOW 1110100
HIGH HIGH HIGH 1110110
HIGH HIGH FLOAT 1110101
HIGH FLOAT LOW 1100101
HIGH FLOAT HIGH 1100111
HIGH FLOAT FLOAT 1100110

FLOAT LOW LOW 0110101
FLOAT LOW HIGH 0110111
FLOAT LOW FLOAT 0110110
FLOAT HIGH LOW 1000111
FLOAT HIGH HIGH 1010101
FLOAT HIGH FLOAT 1010100
FLOAT FLOAT LOW 1000100
FLOAT FLOAT HIGH 1000110
FLOAT FLOAT FLOAT 1000101

may be read using the method described above. If the
conversion cycle is not concluded and a valid address
selects the device, the LTC2499 generates a NAK signal
indicating the conversion cycle is in progress.

Continuous Read/Write

Once the conversion cycle is concluded, the LTC2499 can
be written to and then read from using the Repeated Start
(Sr) command.

Figure 8 shows a cycle which begins with a data Write, a
repeated Start, followed by a Read and concluded with a
Stop command. The following conversion begins after all

2499fa

20

S ACK DATA Sr DATA TRANSFERRING P

SLEEP DATA INPUT/OUTPUT CONVERSIONCONVERSION

7-BIT ADDRESS

R/W

2499 F05

7-BIT ADDRESS

CONVERSION CONVERSION

CONVERSION

SLEEP SLEEPDATA OUTPUT DATA OUTPUT

7-BIT ADDRESSS SR RACK ACKREAD READP P

2499 F07

7-BIT ADDRESS

CONVERSION CONVERSIONADDRESSSLEEP DATA OUTPUTDATA INPUT

7-BIT ADDRESSS RW ACK ACKWRITE Sr PREAD

2499 F08

7-BIT ADDRESS

CONVERSION CONVERSIONSLEEP DATA INPUT

S W ACK WRITE (OPTIONAL) P

2499 F09

applicaTions inFormaTion

Figure 6. Conversion Sequence

Figure 7. Consecutive Reading with the Same Input/Configuration

LTC2499

Figure 8. Write, Read, Start Conversion

Figure 9. Start a New Conversion Without Reading Old Conversion Result

2499fa

21

LTC2499

I IN I IN

V V

R

AVG AVG

IN CM REF CM

EQ

+

( )=( )

=

−

•

–

( ) ( )

.0 5

II REF

V V V

R

AVG

REF REF CM IN CM

+

( )

≈

+

( )

1 5

0 5

. –

. •

( ) ( )

EEQ

IN

REF EQ

REF

REF CM

V

V R

where

V REF REF

V

–

•

:

(

2

= −

+ −

))

–

,

=















= −

+ −

+ − +

REF REF

V IN IN WHEREIN AN

IN

2

DDIN ARE THE SELECTED INPUTCHANNELS

V

IN

IN CM

−

+

=

( )

––.IN

R M INTERNAL OSCILLATOR

EQ

−















=22 71 6W 00Hz MODE

R 2.98 M INTERNAL OSCILLATOR 50Hz/60

EQ

= W HHz MODE

R 0.833 10 /f EXTERNAL OSCIL

EQ

12

EOSC

= •

( )

LLATOR

IN

+

IN

–

10kΩ

INTERNAL

SWITCH

NETWORK

10kΩ

C

EQ

12µF

10kΩ

I

IN

–

REF

+

I

REF

+

I

IN

+

I

REF

–

2499 F11

SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 • f

EOSC

EXTERNAL OSCILLATOR

REF

–

10kΩ

100Ω

INPUT

MULTIPLEXER

EXTERNAL

CONNECTION

100Ω

MUXOUTP ADCINP

EXTERNAL

CONNECTION

MUXOUTN ADCINN

GLOBAL ADDRESS

SCL

SDA

LTC2499 LTC2499 LTC2499…

ALL LTC2499s IN SLEEP CONVERSION OF ALL LTC2499s

DATA INPUT

S W ACK WRITE (OPTIONAL) P

2499 F10

applicaTions inFormaTion

32 bits are read out of the device or after a Stop command.
The following conversion will be performed using the
newly programmed data. In cases where the same speed
(1x/2x mode) and rejection frequency (50Hz, 60Hz, 50Hz
and 60Hz) is used but the channel is changed, a Stop or
Repeated Start may be issued after the first byte (channel
selection data) is written into the device.

Discarding a Conversion Result and Initiating a New
Conversion with Optional Write

At the conclusion of a conversion cycle, a write cycle
can be initiated. Once the write cycle is acknowledged, a
Stop command will start a new conversion. If a new input
channel or conversion configuration is required, this data
can be written into the device and a Stop command will
initiate the next conversion (see Figure 9).

Synchronizing Multiple LTC2499s with a Global
Address Call

In applications where several LTC2499s (or other I2C
delta-sigma ADCs from Linear Technology Corporation)
are used on the same I2C bus, all converters can be syn­chronized through the use of a global address call. Prior
to issuing the global address call, all converters must have
completed a conversion cycle. The master then issues a
Start, followed by the global address 1110111, and a write
request. All converters will be selected and acknowledge
the request. The master then sends a write byte (optional)
followed by the Stop command. This will update the chan­nel selection (optional) converter configuration (optional)
and simultaneously initiate a start of conversion for all
delta-sigma ADCs on the bus (see Figure 10). In order

Figure 10. Synchronize Multiple LTC2499s with a Global Address Call

22

Figure 11. Equivalent Analog Input Circuit

2499fa

applicaTions inFormaTion

LTC2499

to synchronize multiple converters without changing
the channel or configuration, a Stop may be issued after
acknowledgement of the global write command. Global
read commands are not allowed and the converters will
NAK a global read request.

Driving the Input and Reference

The input and reference pins of the LTC2499 are connected
directly to a switched capacitor network. Depending on
the relationship between the differential input voltage and
the differential reference voltage, these capacitors are
switched between these four pins. Each time a capacitor
is switched between two of these pins, a small amount
of charge is transferred. A simplified equivalent circuit is
shown in Figure 11.

When using the LTC2499’s internal oscillator, the input
capacitor array is switched at 123kHz. The effect of the
charge transfer depends on the circuitry driving the in­put/reference pins. If the total external RC time constant
is less than 580ns the errors introduced by the sampling
process are negligible since complete settling occurs.

Typically, the reference inputs are driven from a low
impedance source. In this case, complete settling occurs
even with large external bypass capacitors. The inputs
(CH0-CH15, COM), on the other hand, are typically driven
from larger source resistances. Source resistances up
to 10k may interface directly to the LTC2499 and settle
completely; however, the addition of external capacitors
at the input terminals in order to filter unwanted noise
(antialiasing) results in incomplete settling.

The LTC2499 offers two methods of removing these
errors. The first is an automatic differential input current
cancellation (Easy Drive) and the second is the insertion
of an external buffer between the MUXOUT and ADCIN
pins, thus isolating the input switching from the source
resistance.

Automatic Differential Input Current Cancellation

In applications where the sensor output impedance is
low (up to 10kW with no external bypass capacitor or up
to 500W with 0.001µF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization is possible.

For many applications, the sensor output impedance
combined with external input bypass capacitors produces
RC time constants much greater than the 580ns required
for 1ppm accuracy. For example, a 10kW bridge driving a

0.1µF capacitor has a time constant an order of magnitude
greater than the required maximum.

The LTC2499 uses a proprietary switching algorithm
that forces the average differential input current to zero
independent of external settling errors. This allows direct
digitization of high impedance sensors without the need
for buffers.

The switching algorithm forces the average input current
on the positive input (I
current on the negative input (I

+

) to be equal to the average input

IN

–

). Over the complete

IN

conversion cycle, the average differential input current

+

(I

IN

zero, the common mode input current (I

–

– I

) is zero. While the differential input current is

IN

IN

+

+ I

IN

–

)/2 is
proportional to the difference between the common mode
input voltage (V
voltage (V

REF(CM)

) and the common mode reference

IN(CM)

).

In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balanced bridge, both the differential and com­mon mode input current are zero. The accuracy of the
converter is not compromised by settling errors.

In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between V

IN(CM)

and V

REF(CM)

. For a reference
common mode voltage of 2.5V and an input common mode
of 1.5V, the common mode input current is approximately

0.74µA (in simultaneous 50Hz/60Hz rejection mode). This
common mode input current does not degrade the accuracy
if the source impedances tied to IN+ and IN– are matched.
Mismatches in source impedance lead to a fixed offset
error but do not effect the linearity or full-scale reading. A
1% mismatch in a 1kW source resistance leads to a 74µV
shift in offset voltage.

In applications where the common mode input voltage
varies as a function of the input signal level (single-ended
type sensors), the common mode input current varies
proportionally with input voltage. For the case of balanced

2499fa

23

LTC2499

–

+

–

+

1/2 LTC6078

1/2 LTC6078

1

2

3

5

6

7

∆Σ ADC

WITH

EASY DRIVE

INPUTS

INPUT

MUX

MUXOUTP

MUXOUTN

17

2499 F12

LTC2499

ANALOG

INPUTS

SCL

SDA

0.1µF

1kΩ

1kΩ

0.1µF

applicaTions inFormaTion

input impedances, the common mode input current effects
are rejected by the large CMRR of the LTC2499, leading
to little degradation in accuracy. Mismatches in source
impedances lead to gain errors proportional to the dif­ference between the common mode input and common
mode reference. 1% mismatches in 1k source resistances
lead to gain errors on the order of 15ppm. Based on the
stability of the internal sampling capacitors and the ac­curacy of the internal oscillator, a one-time calibration will
remove this error.

In addition to the input sampling current, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1µV typical and a 10µV maximum offset voltage.

Automatic Offset Calibration of External Buffers/
Amplifiers

In addition to the Easy Drive input current cancellation,
the LTC2499 allows an external amplifier to be inserted
between the multiplexer output and the ADC input (see
Figure 12). This is useful in applications where balanced

source impedances are not possible. One pair of external
buffers/amplifiers can be shared between all 17 analog
inputs. The LTC2499 performs an internal offset calibration
every conversion cycle in order to remove the offset and
drift of the ADC. This calibration is performed through a
combination of front end switching and digital process­ing. Since the external amplifier is placed between the
multiplexer and the ADC, it is inside this correction loop.
This results in automatic offset correction and offset drift
removal of the external amplifier.

The LTC6078 is an excellent amplifier for this function.
It operates with supply voltages as low as 2.7V and its
noise level is 18nV/√Hz. The Easy Drive input technology
of the LTC2499 enables an RC network to be added directly
to the output of the LTC6078. The capacitor reduces the
magnitude of the current spikes seen at the input to the
ADC and the resistor isolates the capacitor load from the
op-amp output enabling stable operation. The LTC6078
can also be biased at supply rails beyond those used by
the LTC2499. This allows the external sensor to swing rail­to-rail (–0.3V to V

+ 0.3V) without the need of external

CC

level shift circuitry.

24

Figure 12. External Buffers Provide High Impedance Inputs
and Amplifier Offsets are Automatically Cancelled.

2499fa

applicaTions inFormaTion

R

SOURCE

(Ω)

0

+FS ERROR (ppm)

50

70

90

10k

2499 F13

30

10

40

60

80

20

0

–10

10

100

1k

100k

VCC = 5V
V

REF

= 5V

V

IN

+

= 3.75V

V

IN

–

= 1.25V
FO = GND
TA = 25°C

C

REF

= 0.01µF

C

REF

= 0.001µF

C

REF

= 100pF

C

REF

= 0pF

R

SOURCE

(Ω)

0

–FS ERROR (ppm)

–30

–10

10

10k

2499 F14

–50

–70

–40

–20

0

–60

–80

–90

10

100

1k

100k

VCC = 5V
V

REF

= 5V

V

IN

+

= 1.25V

V

IN

–

= 3.75V

FO = GND
TA = 25°C

C

REF

= 0.01µF

C

REF

= 0.001µF

C

REF

= 100pF

C

REF

= 0pF

R

SOURCE

(Ω)

0

+FS ERROR (ppm)

300

400

500

800

2499 F15

200

100

0

200

400

600

1000

VCC = 5V
V

REF

= 5V

V

IN

+

= 3.75V
V

IN

–

= 1.25V
FO = GND
TA = 25°C

C

REF

= 1µF, 10µF

C

REF

= 0.1µF

C

REF

= 0.01µF

R

SOURCE

(Ω)

0

–FS ERROR (ppm)

–200

–100

0

800

2499 F16

–300

–400

–500

200

400

600

1000

VCC = 5V
V

REF

= 5V

V

IN

+

= 1.25V

V

IN

–

= 3.75V

FO = GND
TA = 25°C

C

REF

= 1µF, 10µF

C

REF

= 0.1µF

C

REF

= 0.01µF

LTC2499

Reference Current

Similar to the analog inputs, the LTC2499 samples the
differential reference pins (REF+ and REF–) transferring
small amounts of charge to and from these pins, thus
producing a dynamic reference current. If incomplete set­tling occurs (as a function the reference source resistance
and reference bypass capacitance) linearity and gain errors
are introduced.

For relatively small values of external reference capacitance
(C

< 1nF), the voltage on the sampling capacitor settles

REF

for reference impedances of many kW (if C

= 100pF up

REF

to 10kW will not degrade the performance (see Figures
13 and 14)).

In cases where large bypass capacitors are required on
the reference inputs (C

> .01µF), full-scale and linear-

REF

ity errors are proportional to the value of the reference
resistance. Every ohm of reference resistance produces
a full-scale error of approximately 0.5ppm (while operat­ing in simultaneous 50Hz/60Hz mode (see Figures 15
and 16)). If the input common mode voltage is equal to

Figure 13. +FS Error vs R

Figure 15. +FS Error vs R

SOURCE

SOURCE

at V

at V

(Small C

REF

(Large C

REF

) Figure 14. –FS Error vs R

REF

) Figure 16. –FS Error vs R

REF

SOURCE

SOURCE

at V

at V

(Small C

REF

(Large C

REF

)

REF

)

REF

25

2499fa

LTC2499

VIN/V

REF

–0.5

INL (ppm OF V

REF

)

2

6

10

0.3

2499 F17

–2

–6

0

4

8

–4

–8

–10

–0.3

–0.1

0.1

0.5

VCC = 5V
V

REF

= 5V

V

IN(CM)

= 2.5V
TA = 25°C
C

REF

= 10µF

R = 1k

R = 100Ω

R = 500Ω

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

0 fS2fS3fS4fS5fS6fS7fS8fS9fS10fS11fS12f

S

INPUT NORMAL MODE REJECTION (dB)

2499 F18

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

0 f

S

INPUT NORMAL MODE REJECTION (dB)

2499 F19

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

2fS3fS4fS5fS6fS7fS8fS9fS10f

S

applicaTions inFormaTion

Figure 17. INL vs Differential Input Voltage and
Reference Source Resistance for C

the reference common mode voltage, a linearity error of
approximately 0.67ppm per 100W of reference resistance
results (see Figure 17). In applications where the input
and reference common mode voltages are different, the
errors increase. A 1V difference in between common mode
input and common mode reference results in a 6.7ppm
INL error for every 100W of reference resistance.

REF

> 1µF

When using the internal oscillator, the LTC2499 is de­signed to reject line frequencies. As shown in Figure
20, rejection nulls occur at multiples of frequency fN,
where fN is determined by the input control bits FA and
FB (fN = 50Hz or 60Hz or 55Hz for simultaneous rejec­tion). Multiples of the modulator sampling rate (fS = fN

• 256) only reject noise to 15dB (see Figure 21); if noise
sources are present at these frequencies antialiasing will
reduce their effects.

In addition to the reference sampling charge, the reference
ESD protection diodes have a temperature dependent leak­age current. This leakage current, nominally 1nA (±10nA
max) results in a small gain error. A 100W reference
resistance will create a 0.5µV full-scale error.

Normal Mode Rejection and Antialiasing

One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversample ratio, the LTC2499 significantly
simplifies antialiasing filter requirements. Additionally,
the input current cancellation feature allows external low
pass filtering without degrading the DC performance of
the device.

The SINC4 digital filter provides excellent normal mode
rejection at all frequencies except DC and integer multiples
of the modulator sampling frequency (fS) (see Figures
18 and 19). The modulator sampling frequency is fS =
15,360Hz while operating with its internal oscillator and
fS = f
of frequency f

26

/20 when operating with an external oscillator

EOSC

EOSC

.

Figure 18. Input Normal Mode Rejection, Internal
Oscillator and 50Hz Rejection Mode

Figure 19. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Rejection Mode

2499fa

applicaTions inFormaTion

INPUT SIGNAL FREQUENCY (Hz)

INPUT NORMAL MODE REJECTION (dB)

2499 F20

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

fN0 2fN3fN4fN5fN6fN7fN8f

N

fN = f

EOSC/5120

INPUT SIGNAL FREQUENCY (Hz)

250fN252fN254fN256fN258fN260fN262f

N

INPUT NORMAL MODE REJECTION (dB)

2499 F21

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

fN = f

EOSC/5120

LTC2499

The user can expect to achieve this level of performance
using the internal oscillator, as shown in Figures 22, 23,
and 24. Measured values of normal mode rejection are
shown superimposed over the theoretical values in all
three rejection modes.

Traditional high order delta-sigma modulators suffer
from potential instabilities at large input signal levels. The
proprietary architecture used for the LTC2499 third order

modulator resolves this problem and guarantees stability
with input signals 150% of full scale. In many industrial
applications, it is not uncommon to have microvolt level
signals superimposed over unwanted error sources with
several volts if peak-to-peak noise. Figures 25 and 26 show
measurement results for the rejection of a 7.5V peak-to-peak
noise source (150% of full scale) applied to the LTC2499.
These curves show that the rejection performance is
maintained even in extremely noisy environments.

Figure 20. Input Normal Mode Rejection at DC

Figure 21. Input Normal Mode Rejection at fS = 256 • f

N

2499fa

27

LTC2499

INPUT FREQUENCY (Hz)

0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

NORMAL MODE REJECTION (dB)

2498 F23

0

–20

–40

–60

–80

–100

–120

VCC = 5V
V

REF

= 5V

V

IN(CM)

= 2.5V

V

IN(P-P)

= 5V

TA = 25°C

MEASURED DATA
CALCULATED DATA

INPUT FREQUENCY (Hz)

0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

NORMAL MODE REJECTION (dB)

2498 F24

0

–20

–40

–60

–80

–100

–120

VCC = 5V
V

REF

= 5V

V

IN(CM)

= 2.5V

V

IN(P-P)

= 5V

TA = 25°C

MEASURED DATA
CALCULATED DATA

INPUT FREQUENCY (Hz)

0 20 40 60 80 100 120 140 160 180 200 220

NORMAL MODE REJECTION (dB)

2498 F25

0

–20

–40

–60

–80

–100

–120

VCC = 5V
V

REF

= 5V

V

IN(CM)

= 2.5V

V

IN(P-P)

= 5V

TA = 25°C

MEASURED DATA
CALCULATED DATA

INPUT FREQUENCY (Hz)

0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

NORMAL MODE REJECTION (dB)

2498 F26

0

–20

–40

–60

–80

–100

–120

VCC = 5V
V

REF

= 5V

V

IN(CM)

= 2.5V

TA = 25°C

V

IN(P-P)

= 5V

V

IN(P-P)

= 7.5V

(150% OF FULL SCALE)

INPUT FREQUENCY (Hz)

0

NORMAL MODE REJECTION (dB)

2498 F27

0

–20

–40

–60

–80

–100

–120

VCC = 5V
V

REF

= 5V

V

IN(CM)

= 2.5V

TA = 25°C

V

IN(P-P)

= 5V

V

IN(P-P)

= 7.5V

(150% OF FULL SCALE)

12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

applicaTions inFormaTion

Figure 22. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (60Hz Notch)

Figure 24. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz/60Hz Notch)

Figure 23. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz Notch)

Figure 25. Measure Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 150% (60Hz Notch)

28

Figure 26. Measure Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 150% (50Hz Notch)

2499fa

applicaTions inFormaTion

INPUT SIGNAL FREQUENCY (fN)

INPUT NORMAL REJECTION (dB)

2499 F27

0

–20

–40

–60

–80

–100

–120

0

fN2fN3fN4fN5fN6fN7fN8f

N

INPUT SIGNAL FREQUENCY (fN)

INPUT NORMAL REJECTION (dB)

2499 F28

0

–20

–40

–60

–80

–100

–120

250248 252 254 256 258 260 262 264

LTC2499

Using the 2X speed mode of the LTC2499 alters the
rejection characteristics around DC and multiples of fS.
The device bypasses the offset calibration in order to
increase the output rate. The resulting rejection plots are
shown in Figures 27 and 28. 1x type frequency rejection
can be achieved using the 2x mode by performing a run­ning average of the previoius two conversion results (see
Figure 29).

Output Data Rate

When using its internal oscillator, the LTC2499 produces
up to 7.5 samples per second (sps) with a notch frequency
of 60Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insignificantly short. When
operating with an external conversion clock (fO connected
to an external oscillator), the LTC2499 output data rate
can be increased. The duration of the conversion cycle is
41036/f

EOSC

. If f

= 307.2kHz, the converter behaves

EOSC

as if the internal oscillator is used.
An increase in f

over the nominal 307.2kHz will trans-

EOSC

late into a proportional increase in the maximum output
data rate (up to a maximum of 100sps). The increase in
output rate leads to degradation in offset, full-scale error,

and effective resolution as well as a shift in frequency rejec­tion. When using the integrated temperature sensor, the
internal oscillator should be used or an external oscillator
f

= 307.2kHz maximum.

EOSC

A change in f

results in a proportional change in the

EOSC

internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
rejection of line frequencies remains unchanged, thus fully
differential input signals with a high degree of symmetry
on both the IN+ and IN– pins will continue to reject line
frequency noise.

An increase in f

also increases the effective dynamic

EOSC

input and reference current. External RC networks will
continue to have zero differential input current, but the
time required for complete settling (580ns for f

EOSC

=

307.2kHz) is reduced, proportionally.
Once the external oscillator frequency is increased

above 1MHz (a more than 3x increase in output rate)
the effectiveness of internal auto calibration circuits
begins to degrade. This results in larger offset errors,
full-scale errors, and decreased resolution, as seen in
Figures 30-37.

Figure 27. Input Normal Mode Rejection 2x Speed Mode Figure 28. Input Normal Mode Rejection 2x Speed Mode

2499fa

29

LTC2499

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

48

–70

–80

–90

–100

–110

–120

–130

–140

54 58

2499 F29

50 52

56 60 62

NORMAL MODE REJECTION (dB)

NO AVERAGE

WITH
RUNNING
AVERAGE

OUTPUT DATA RATE (READINGS/SEC)

–10

OFFSET ERROR (ppm OF V

REF

)

10

30

50

0

20

40

20 40 60 80

2499 F30

100100 30 50 70 90

V

IN(CM)

= V

REF(CM)

VCC = V

REF

= 5V
VIN = 0V
FO = EXT CLOCK

TA = 85°C

TA = 25°C

OUTPUT DATA RATE (READINGS/SEC)

0

0

+FS ERROR (ppm OF V

REF

)

500

1500

2000

2500

3500

10

50

70

2499 F31

1000

3000

40

90

100

20

30

60 80

V

IN(CM)

= V

REF(CM)

VCC = V

REF

= 5V

FO = EXT CLOCK

TA = 85°C

TA = 25°C

OUTPUT DATA RATE (READINGS/SEC)

0

–3500

–FS ERROR (ppm OF V

REF

)

–3000

–2000

–1500

–1000

0

10

50

70

2499 F32

–2500

–500

40

90

100

20

30

60 80

V

IN(CM)

= V

REF(CM)

VCC = V

REF

= 5V

FO = EXT CLOCK

TA = 85°C

TA = 25°C

OUTPUT DATA RATE (READINGS/SEC)

0

10

RESOLUTION (BITS)

12

16

18

20

24

10

50

70

2499 F33

14

22

40

90

100

20

30

60 80

V

IN(CM)

= V

REF(CM)

VCC = V

REF

= 5V
VIN = 0V
FO = EXT CLOCK
RES = LOG 2 (V

REF

/NOISE

RMS

)

TA = 85°C

TA = 25°C

OUTPUT DATA RATE (READINGS/SEC)

0

10

RESOLUTION (BITS)

12

16

18

22

10

50

70

2499 F34

14

20

40

90

100

20

30

60 80

TA = 85°C

TA = 25°C

V

IN(CM)

= V

REF(CM)

VCC = V

REF

= 5V
FO = EXT CLOCK
RES = LOG 2 (V

REF

/INL

MAX

)

OUTPUT DATA RATE (READINGS/SEC)

0

–10

OFFSET ERROR (ppm OF V

REF

)

–5

5

10

20

10

50

70

2499 F35

0

15

40

90

100

20

30

60 80

VCC = 5V, V

REF

= 2.5V

VCC = V

REF

= 5V

V

IN(CM)

= V

REF(CM)

VIN = 0V
FO = EXT CLOCK
TA = 25°C

OUTPUT DATA RATE (READINGS/SEC)

0

10

RESOLUTION (BITS)

12

16

18

20

24

10

50

70

2499 F36

14

22

40

90

100

20

30

60 80

V

IN(CM)

= V

REF(CM)

VIN = 0V
FO = EXT CLOCK
TA = 25°C
RES = LOG 2 (V

REF

/NOISE

RMS

)

VCC = 5V, V

REF

= 2.5V

VCC = V

REF

= 5V

OUTPUT DATA RATE (READINGS/SEC)

0

10

RESOLUTION (BITS)

12

16

18

22

10

50

70

2499 F37

14

20

40

90

100

20

30

60 80

VCC = 5V, V

REF

= 2.5V

VCC = V

REF

= 5V

V

IN(CM)

= V

REF(CM)

VIN = 0V
REF– = GND
FO = EXT CLOCK
TA = 25°C
RES = LOG 2 (V

REF

/INL

MAX

)

applicaTions inFormaTion

Figure 29. Input Normal Mode
Rejection 2x Speed Mode with and
Without Running Averaging

Figure 32.–FS Error vs Output Data
Rate and Temperature

Figure 30. Offset Error vs Output Data
Rate and Temperature

Figure 33. Resolution (Noise

≤ 1LSB)

RMS

vs Output Data Rate and Temperature

Figure 31. +FS Error vs Output Data
Rate and Temperature

Figure 34. Resolution (INL

≤ 1LSB)

MAX

vs Output Data Rate and Temperature

30

Figure 35. Offset Error vs Output
Data Rate and Temperature

Figure 36. Resolution (Noise

≤ 1LSB)

RMS

vs Output Data Rate and Temperature

Figure 37. Resolution (INL

≤ 1LSB)

MAX

vs Output Data Rate and Temperature

2499fa

package DescripTion

5.00 ± 0.10

(2 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

PIN 1
TOP MARK
(SEE NOTE 6)

0.40 ± 0.10

37

1

2

38

BOTTOM VIEW—EXPOSED PAD

5.15 ± 0.10

(2 SIDES)

7.00 ± 0.10

(2 SIDES)

0.75 ± 0.05

R = 0.115
TYP

0.25 ± 0.05

(UH) QFN 0205

0.50 BSC

0.200 REF

0.200 REF

0.00 – 0.05

RECOMMENDED SOLDER PAD LAYOUT

3.15 ± 0.10

(2 SIDES)

0.40 ±0.10

0.00 – 0.05

0.75 ± 0.05

0.70 ± 0.05

0.50 BSC

5.15 ± 0.05 (2 SIDES)

3.15 ± 0.05

(2 SIDES)

4.10 ± 0.05

(2 SIDES)

5.50 ± 0.05

(2 SIDES)

6.10 ± 0.05 (2 SIDES)

7.50 ± 0.05 (2 SIDES)

0.25 ± 0.05

PACKAGE
OUTLINE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 NOTCH
R = 0.30 TYP OR

0.35 × 45° CHAMFER

LTC2499

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-1701)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

2499fa

31

LTC2499

–

+

–

+

1/2 LTC6078

1/2 LTC6078

1

2

3

5

6

7

∆Σ ADC

WITH

EASY DRIVE

INPUTS

INPUT

MUX

MUXOUTP

MUXOUTN

17

2499 TA03

LTC2499

ANALOG

INPUTS

SCL

SDA

1kΩ

1kΩ

0.1µF

0.1µF

Typical applicaTion

External Buffers Provide High Impedance Inputs and

Amplifier Offsets are Automatically Cancelled

relaTeD parTs

PART NUMBER DESCRIPTION COMMENTS

LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460 Micropower Series Reference 0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LT1790 Micropower SOT-23 Low Dropout Reference Family 0.05% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400 24-Bit, No Latency DS ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410 24-Bit, No Latency DS ADC with Differential Inputs 0.8µV
LTC2411/

LTC2411-1

24-Bit, No Latency DS ADCs with Differential Inputs in MSOP 1.45µV

Rejection (LTC2411-1)

LTC2413 24-Bit, No Latency DS ADC with Differential Inputs Simultaneous 50Hz/60Hz Rejection, 800nV
LTC2440 24-Bit, High Speed, Low Noise DS ADC 3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs
LTC2442 24-Bit, High Speed, 2-/4-Channel DS ADC with Integrated

Amplifier

8kHz Output Rate, 200nV Noise, Simultaneous 50Hz/60Hz
Rejection

LTC2449 24-Bit, High Speed, 8-/16-Channel DS ADC 8kHz Output Rate, 200nV Noise, Simultaneous 50Hz/60Hz

Rejection
Pin Compatible with 16-Bit and 24-Bit Versions

Pin Compatible with 16-Bit and 24-Bit Versions

Pin-Compatible with LTC2498/LTC2449

Pin-Compatible with LTC2499

Pin-Compatible with LTC2496/LTC2449

LTC2480/LTC2482/
LTC2484

LTC2481/LTC2483/
LTC2485

16-Bit/24-Bit DS ADCs with Easy Drive Inputs, 600nV Noise,
Programmable Gain, and Temperature Sensor

16-Bit/24-Bit DS ADCs with Easy Drive Inputs, 600nV Noise,
I2C Interface, Programmable Gain, and Temperature Sensor

LTC2496 16-Bit 8-/16-Channel DS ADC with Easy Drive Inputs and

SPI Interface

LTC2497 16-Bit 8-/16-Channel DS ADC with Easy Drive Inputs and

I2C Interface

LTC2498 24-Bit 8-/16-Channel DS ADC with Easy Drive Inputs and

SPI Interface, Temperature Sensor

Noise, 2ppm INL

RMS

Noise, 4ppm INL, Simultaneous 50Hz/60Hz

RMS

RMS

Noise

32

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

2499fa

LT/CGRAFX 0407 REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2006