Datasheet LTC2482 Datasheet (LINEAR TECHNOLOGY)

LTC2482

16-Bit ∆Σ ADC with

FEATURES

■

Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current

■

Directly Digitizes High Impedance Sensors with
Full Accuracy

■

600nV RMS Noise, Independent of V

■

Operates with a Reference as Low as 100mV with

REF

16-Bit Resolution

■

GND to VCC Input/Reference Common Mode Range

■

Simultaneous 50Hz/60Hz Rejection Mode

■

2ppm INL, No Missing Codes

■

1ppm Offset and 15ppm Total Unadjusted Error

■

No Latency: Digital Filter Settles in a Single Cycle

■

Single Supply 2.7V to 5.5V Operation

■

Internal Oscillator

■

Available in a Tiny (3mm × 3mm) 10-Lead
DFN Package

U

APPLICATIO S

■

Direct Sensor Digitizer

■

Weight Scales

■

Direct Temperature Measurement

■

Strain Gauge Transducers

■

Instrumentation

■

Industrial Process Control

■

DVMs and Meters

Easy Drive Input

Current

Cancellation

U

DESCRIPTIO

The LTC®2482 combines a 16-bit plus sign No Latency
∆Σ™ analog-to-digital converter with patented Easy Drive™
technology. The patented sampling scheme eliminates
dynamic input current errors and the shortcomings of on­chip buffering through automatic cancellation of differen­tial input current. This allows large external source
impedances and input signals with rail-to-rail input range
to be directly digitized while maintaining exceptional DC
accuracy.

The LTC2482 allows a wide common mode input range
(0V to V
reference can be as low as 100mV or can be tied directly
to VCC. The noise level is 600nV RMS independent of V
This allows direct digitization of low level signals with 16­bit accuracy. The LTC2482 includes an on-chip trimmed
oscillator, eliminating the need for external crystals or
oscillators and provides 87dB rejection of 50Hz and 60Hz
line frequency noise. Absolute accuracy and low drift are
automatically maintained through continuous, transpar­ent, offset and full-scale calibration.

, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ and Easy Drive are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Patent pending.

) independent of the reference voltage. The

CC

REF

.

TYPICAL APPLICATIO

V

CC

SENSE

10k

10k

I

DIFF

= 0

1µF

V

IN

V

IN

V

REF

+

LTC2482

–

GND F

U

+FS Error vs R

80

VCC = 5V

= 5V

V

REF

60

+

= 3.75V

V

IN

–

= 1.25V

V

IN

1µF

V

CC

SDO

SCK

3-WIRE
SPI INTERFACE

CS

O

2482 TA01

40

= GND

F

O

= 25°C

T

A

20

0

–20

+FS ERROR (ppm)

–40

–60

–80

10 100 10k

1

SOURCE

R

SOURCE

at IN+ and IN

CIN = 1µF

1k

(Ω)

–

100k

2482 TA02

2482f

1

LTC2482

PACKAGE/ORDER I FOR ATIO

UU

W

TOP VIEW

11

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

10

9

6

7

8

4

5

3

2

1

F

O

SCK

GND

SDO

CS

*GND

V

CC

V

REF

IN

+

IN

–

WWWU

ABSOLUTE AXI U RATI GS

(Notes 1, 2)

Supply Voltage (VCC) to GND...................... – 0.3V to 6V

Analog Input Voltage to GND ....... –0.3V to (V

+ 0.3V)

CC

ORDER PART

NUMBER

Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V)

Digital Input Voltage to GND ........ –0.3V to (V

Digital Output Voltage to GND ..... –0.3V to (V

+ 0.3V)

CC

+ 0.3V)

CC

LTC2482CDD
LTC2482IDD

Operating Temperature Range

LTC2482C ................................................... 0°C to 70°C

LTC2482I ................................................ –40°C to 85°C

Storage Temperature Range ................ –65°C to 125°C

T

= 125°C, θJA = 43°C/ W

JMAX

EXPOSED PAD (PIN 11) IS GND

MUST BE SOLDERED TO PCB

*PIN 1 MAY BE DRIVEN WITH A DIGITAL

SIGNAL IN ORDER TO REMAIN PIN

COMPATIBLE WITH THE LTC2480/LTC2484

Consult LTC Marketing for parts specified with wider operating temperature ranges.
**The temperature grade is indicated by a label on the shipping container.

DD PART MARKING**

LBSQ

UW

ELECTRICAL CHARACTERISTICS ( OR AL SPEED)

over the full operating temperature range, otherwise specifications are TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 0.1 ≤ V
Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, V

2.7V ≤ VCC ≤ 5.5V, V
Offset Error 2.5V ≤ V
Offset Error Drift 2.5V ≤ V
Positive Full-Scale Error 2.5V ≤ V
Positive Full-Scale Error Drift 2.5V ≤ V

Negative Full-Scale Error 2.5V ≤ V
Negative Full-Scale Error Drift 2.5V ≤ V

Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, V

5V ≤ VCC ≤ 5.5V, V

2.7V ≤ VCC ≤ 5.5V, V
Output Noise 5V ≤ VCC ≤ 5.5V, V

≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) ● 16 Bits

REF

= 5V, V

REF

= 2.5V, V

REF

≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14) ● 0.5 5 µV

REF

≤ VCC, GND ≤ IN+ = IN– ≤ V

REF

≤ VCC, IN+ = 0.75V

REF

≤ VCC, IN+ = 0.75V

REF

≤ VCC, IN+ = 0.75V

REF

≤ VCC, IN+ = 0.75V

REF

= 2.5V, V

REF

= 5V, V

REF

= 2.5V, V

REF

= 5V, GND ≤ IN– = IN+ ≤ VCC (Note 13) 0.6 µV

REF

= 2.5V (Note 6) ● 2 20 ppm of V

IN(CM)

IN(CM)

= 1.25V (Note 6) 1 ppm of V

IN(CM)

CC

, IN– = 0.25V

REF

, IN– = 0.25V

REF

, IN– = 0.25V

REF

, IN– = 0.25V

REF

= 1.25V 15 ppm of V

IN(CM)

REF

REF

REF

REF

= 2.5V ppm of V

= 1.25V ppm of V

IN(CM)

The ● denotes specifications which apply

REF
REF

10 nV/°C

● 32 ppm of V

0.1 ppm of

● 32 ppm of V

0.1 ppm of

REF

V

/°C

REF

REF

/°C

V

REF

REF
REF
REF

RMS

2

2482f

LTC2482

U

CO VERTER CHARACTERISTICS

temperature range, otherwise specifications are at T

PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Common Mode Rejection DC 2.5V ≤ V
Input Common Mode Rejection 2.5V ≤ V

50Hz ±2%
Input Common Mode Rejection 2.5V ≤ V

60Hz ±2%
Input Normal Mode Rejection 2.5V ≤ V

50Hz ±2%
Input Normal Mode Rejection 2.5V ≤ V

60Hz ±2%
Input Normal Mode Rejection 2.5V ≤ V

50Hz/60Hz ±2%
Reference Common Mode 2.5V ≤ V

Rejection DC

Power Supply Rejection DC V

Power Supply Rejection, 50Hz ±2% V

Power Supply Rejection, 60Hz ±2% V

REF

REF

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

= 2.5V, IN– = IN+ = GND 120 dB

= 2.5V, IN– = IN+ = GND (Note 7) 120 dB

= 2.5V, IN– = IN+ = GND (Note 8) 120 dB

The ● denotes specifications which apply over the full operating

= 25°C. (Notes 3, 4)

A

(Note 5) ● 140 dB

CC

(Note 5) ● 140 dB

CC

(Note 5) ● 140 dB

CC

(Notes 5, 7) ● 110 120 dB

CC

(Notes 5, 8) ● 110 120 dB

CC

(Notes 5, 9) ● 87 dB

CC

(Note 5) ● 120 140 dB

CC

UUU

A ALOG I PUT AUD REFERE CE

temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

+

IN

–

IN

FS Full Scale of the Differential Input (IN+ – IN–) ● 0.5V

LSB Least Significant Bit of the Output Code ● FS/2

V

IN

V

REF

CS (IN+)IN

CS (IN–)IN

CS (V

)V

REF

I

(IN+)IN+ DC Leakage Current Sleep Mode, IN+ = GND ● –10 1 10 nA

DC_LEAK

I

(IN–)IN– DC Leakage Current Sleep Mode, IN– = GND ● –10 1 10 nA

DC_LEAK

I

(V

DC_LEAK

Absolute/Common Mode IN+ Voltage GND – 0.3V VCC + 0.3V V

Absolute/Common Mode IN– Voltage GND – 0.3V VCC + 0.3V V

Input Differential Voltage Range (IN+ – IN–) ● –FS +FS V

Reference Voltage Range ● 0.1 V

+

Sampling Capacitance 11 pF

–

Sampling Capacitance 11 pF

Sampling Capacitance 11 pF

REF

)V

REF

Leakage Current Sleep Mode, V

REF

The ● denotes specifications which apply over the full operating

REF

16

CC

REF

= V

CC

● –100 1 100 nA

V

V

2482f

3

LTC2482

UU

DIGITAL I PUTS A D DIGITAL OUTPUTS

operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

V

IH

V

IL

I

IN

I

IN

C

IN

C

IN

V

OH

V

OL

V

OH

V

OL

I

OZ

High Level Input Voltage 2.7V ≤ VCC ≤ 5.5V ● VCC – 0.5 V
CS, F

O

Low Level Input Voltage 2.7V ≤ VCC ≤ 5.5V ● 0.5 V
CS, F

O

High Level Input Voltage 2.7V ≤ VCC ≤ 5.5V (Note 10) ● VCC – 0.5 V
SCK

Low Level Input Voltage 2.7V ≤ VCC ≤ 5.5V (Note 10) ● 0.5 V
SCK

Digital Input Current 0V ≤ VIN ≤ V
CS, F

O

Digital Input Current 0V ≤ VIN ≤ VCC (Note 10) ● –10 10 µA
SCK

Digital Input Capacitance 10 pF
CS, F

O

Digital Input Capacitance 10 pF
SCK

High Level Output Voltage IO = –800µA ● VCC – 0.5 V
SDO

Low Level Output Voltage IO = 1.6mA ● 0.4 V
SDO

High Level Output Voltage IO = –800µA ● VCC – 0.5 V
SCK

Low Level Output Voltage IO = 1.6mA ● 0.4 V
SCK

Hi-Z Output Leakage ● –10 10 µA
SDO

CC

The ● denotes specifications which apply over the full

● –10 10 µA

WU

POWER REQUIRE E TS

otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

CC

I

CC

Supply Voltage ● 2.7 5.5 V

Supply Current Conversion Mode (Note 12) ● 160 250 µA

The ● denotes specifications which apply over the full operating temperature range,

Sleep Mode (Note 12)

● 12 µA

2482f

4

LTC2482

WU

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

EOSC

t

HEO

t

LEO

t

CONV_1

f

ISCK

D

ISCK

f

ESCK

t

LESCK

t

HESCK

t

DOUT_ISCK

t

DOUT_ESCK

t

1

t2 CS↑ to SDO High Z ● 0 200 ns
t3 CS↓ to SCK↓ (Note 10) ● 0 200 ns
t4 CS↓ to SCK↑ (Note 10) ● 50 ns

t

KQMAX

t

KQMIN

t

5

t

6

Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.

Note 2: All voltage values are with respect to GND.
Note 3: V

V

REFCM

VIN = IN+ – IN–, V

Note 4: Use internal conversion clock or external conversion clock source
with f

EOSC

Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.

Note 7: f

EOSC

Note 8: f

EOSC

External Oscillator Frequency Range (Note 15) ● 10 4000 kHz

External Oscillator High Period ● 0.125 100 µs

External Oscillator Low Period ● 0.125 100 µs

Conversion Time Simultaneous 50Hz/60Hz ● 144.1 146.9 149.9 ms

Internal SCK Frequency Internal Oscillator (Note 10) 38.4 kHz

Internal SCK Duty Cycle (Note 10) ● 45 55 %

External SCK Frequency Range (Note 10) ● 4000 kHz

External SCK Low Period (Note 10) ● 125 ns

External SCK High Period (Note 10) ● 125 ns

Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12) ● 0.61 0.625 0.64 ms

External SCK 24-Bit Data Output Time (Note 10) ● 24/f
CS↓ to SDO Low ● 0 200 ns

SCK↓ to SDO Valid ● 200 ns
SDO Hold After SCK↓ (Note 5) ● 15 ns
SCK Set-Up Before CS↓ ● 50 ns
SCK Hold After CS↓ ● 50 ns

= 2.7V to 5.5V unless otherwise specified.

CC

= V

/2, FS = 0.5V

REF

IN(CM)

REF

= (IN+ + IN–)/2

= 307.2kHz unless otherwise specified.

= 256kHz ±2% (external oscillator).
= 307.2kHz ±2% (external oscillator).

The ● denotes specifications which apply over the full operating temperature

External Oscillator

● 41036/f

External Oscillator (Notes 10, 11) f

External Oscillator (Notes 10, 11)

● 192/f

Note 9: Simultaneous 50Hz/60Hz rejection (internal oscillator) or

= 280kHz ±2% (external oscillator).

f

EOSC

Note 10: The SCK can be configured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as digital input and the
driving clock is f

. In internal SCK mode, the SCK pin is used as digital

ESCK

output and the output clock signal during the data output is f
Note 11: The external oscillator is connected to the FO pin. The external

oscillator frequency, f

, is expressed in kHz.

EOSC

Note 12: The converter uses the internal oscillator.
Note 13: The output noise includes the contribution of the internal

calibration operations.

Note 14: Guaranteed by design and test correlation.
Note 15: Refer to Applications Information section for performance vs

data rate graphs.

(in kHz) ms

EOSC

/8 kHz

EOSC

(in kHz) ms

EOSC

(in kHz) ms

ESCK

ISCK

.

2482f

5

LTC2482

INPUT VOLTAGE (V)

–3

INL (ppm OF V

REF

)

–1

1

3

–2

0

2

–0.75 –0.25 0.25 0.75

2482 G03

1.25–1.25

VCC = 2.7V
V

REF

= 2.5V

V

IN(CM)

= 1.25V

F

O

= GND

–45°C, 25°C, 90°C

INPUT VOLTAGE (V)

–12

TUE (ppm OF V

REF

)

–4

4

12

–8

0

8

–0.75 –0.25 0.25 0.75

2482 G06

1.25–1.25

VCC = 2.7V
V

REF

= 2.5V

V

IN(CM)

= 1.25V

F

O

= GND

85°C

25°C

–45°C

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Integral Nonlinearity
(VCC = 5V, V

3

VCC = 5V
V

REF

2

V

IN(CM)

= GND

F

O

)

–45°C

1

REF

0

85°C

–1

INL (ppm OF V

–2

–3

= 5V

REF

= 2.5V

–1.5 –0.5 0.5 1.5

INPUT VOLTAGE (V)

Total Unadjusted Error
(VCC = 5V, V

12

VCC = 5V
V

8

V
F

)

4

REF

0

= 5V

REF
IN(CM)

= GND

O

REF

= 2.5V

25°C

= 5V)

= 5V)

25°C

85°C

–45°C

2482 G01

Integral Nonlinearity
(VCC = 5V, V

3

VCC = 5V

= 2.5V

V

REF

2

)

1

REF

0

–1

INL (ppm OF V

–2

2.5–2–2.5 –1 0 1 2

–3

= 1.25V

V

IN(CM)

= GND

F

O

–0.75 –0.25 0.25 0.75

= 2.5V)

REF

–45°C, 25°C, 90°C

INPUT VOLTAGE (V)

1.25–1.25

2482 G02

Total Unadjusted Error
(VCC = 5V, V

12

VCC = 5V
V

8

V
F

)

4

REF

0

REF
IN(CM)

= GND

O

= 5V

= 1.25V

= 2.5V)

REF

85°C

25°C

–45°C

Integral Nonlinearity
(VCC = 2.7V, V

= 2.5V)

REF

Total Unadjusted Error
(VCC = 2.7V, V

= 2.5V)

REF

–4

TUE (ppm OF V

–8

–12

–1.5 –0.5 0.5 1.5

INPUT VOLTAGE (V)

Offset Error vs V

0.3
VCC = 5V

= 5V

V

REF

)

REF

OFFSET ERROR (ppm OF V

0.2

0.1

–0.1

–0.2

–0.3

V
T

0

–1

= 0V

IN

= 25°C

A

01

–4

TUE (ppm OF V

–8

2.5–2–2.5 –1 0 1 2

2482 G04

–12

IN(CM)

356

24

V

(V)

IN(CM)

2482 G07

–0.75 –0.25 0.25 0.75

INPUT VOLTAGE (V)

0.3

0.2

)

REF

0.1

0

–0.1

OFFSET ERROR (ppm OF V

–0.2

–0.3

1.25–1.25

2482 G05

Offset Error vs Temperature

VCC = 5V

= 5V

V

REF

= 0V

V

IN

= GND

V

IN(CM)

= GND

F

O

–30 0

–45

–15

TEMPERATURE (°C)

30 90

45

15

60

75

2482 G08

6

2482f

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2482

Offset Error vs V

0.3
REF+ = 2.5V

–

= GND

REF

)

REF

OFFSET ERROR (ppm OF V

–0.3

0.2

0.1

–0.1

–0.2

0

2.7

= 0V

V

IN

V

IN(CM)

= 25°C

T

A

3.1 3.5

= GND

CC

4.3 5.1 5.5

3.9 4.7
VCC (V)

On-Chip Oscillator Frequency
vs Temperature

310

308

306

2482 G09

Offset Error vs V

0.3

0.2

)

REF

0.1

0

–0.1

OFFSET ERROR (ppm OF V

–0.2

–0.3

0

1234

REF

V

(V)

REF

On-Chip Oscillator Frequency
vs V

CC

310

308

306

VCC = 5V

–

= GND

REF

= 0V

V

IN

V

IN(CM)

= 25°C

T

A

V

= 2.5V

REF

= 0V

V

IN

V

IN(CM)

= GND

F

O

= GND

5

2482 G10

= GND

304

FREQUENCY (kHz)

VCC = 4.1V

= 2.5V

V

REF

302

= 0V

V

IN

= GND

V

IN(CM)

= GND

F

O

300

–45 –30

–15

TEMPERATURE (°C)

PSRR vs Frequency at V

0

VCC = 4.1V DC

= 2.5V

V

REF

–20

+

= GND

IN

–

= GND

IN

–40

= GND

F

O

= 25°C

T

A

–60

–80

REJECTION (dB)

–100

–120

–140

0

10 100

FREQUENCY AT VCC (Hz)

30

150

45

CC

10k 1M

1k 100k

60 75

2482 G11

2482 G13

304

FREQUENCY (kHz)

302

300

90

2.5

3.5 4.0 4.5

3.0
VCC (V)

PSRR vs Frequency at V

0

VCC = 4.1V DC ±1.4V

= 2.5V

V

REF

–20

+

= GND

IN

–

= GND

IN

–40

= GND

F

O

= 25°C

T

A

–60

–80

REJECTION (dB)

–100

–120

–140

0

60

80

40

20

FREQUENCY AT VCC (Hz)

100

120 160

140

CC

5.0 5.5

2482 G12

180

2482 G14

220200

2482f

7

LTC2482

UW

TYPICAL PERFOR A CE CHARACTERISTICS

PSRR vs Frequency at V

0

VCC = 4.1V DC ±0.7V

= 2.5V

V

REF

–20

+

= GND

IN

–

= GND

IN

–40

= GND

F

O

= 25°C

T

A

–60

–80

REJECTION (dB)

–100

–120

CC

200

180

160

140

CONVERSION CURRENT (µA)

120

Conversion Current
vs Temperature

FO = GND
CS = GND
SCK = NC
SDO = NC

VCC = 5V

VCC = 2.7V

–140

30600

30650 30700 30800

FREQUENCY AT VCC (Hz)

Sleep Mode Current
vs Temperature

2.0
FO = GND

1.8

CS = V

CC

SCK = NC

1.6
SDO = NC

1.4

1.2

1.0

0.8

0.6

SLEEP MODE CURRENT (µA)

0.4

0.2

0

–30 0

–45

–15

VCC = 5V

VCC = 2.7V

30 90

45

15

TEMPERATURE (°C)

30750

2482 G15

100

–45

–30 0

–15

TEMPERATURE (°C)

15

60

30 90

75

45

2482 G16

Conversion Current
vs Data Output Rate

500

V

= V

REF

CC

IN+ = GND

450

–

= GND

IN
SCK = NC

400

SDO = NC
CS = GND

350

= EXT OSC

F

O

= 25°C

T

A

300

250

SUPPLY CURRENT (µA)

200

150

100

0

60

75

2482 G17

20 40 60 1007010 30 50 90

OUTPUT DATA RATE (READINGS/SEC)

VCC = 5V

VCC = 3V

80

2482 G18

8

2482f

LTC2482

U

UU

PI FU CTIO S

GND (Pin 1): Ground. This pin should be tied to ground;
however, in order to remain pin compatible with the
LTC2480/LTC2484, this pin may be driven HIGH or LOW.

VCC (Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 8) with a 1µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor as close to the part as possible.

V

(Pin 3): Positive Reference Input. The voltage on this

REF

pin can have any value between 0.1V and V
reference input is GND (Pin 8).

+

IN

(Pin 4), IN– (Pin 5): Differential Analog Inputs.

The voltage on these pins can have any value between GND
– 0.3V and VCC + 0.3V. Within these limits the converter
bipolar input range (VIN = IN+ – IN–) extends from
–0.5 • V
converter produces unique overrange and underrange
output codes.

CS (Pin 6): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as long
as CS is HIGH. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.

to 0.5 • V

REF

. Outside this input range the

REF

. The negative

CC

GND (Pin 8): Ground. Shared pin for analog ground,
digital ground and reference ground. Should be connected
directly to a ground plane through a minimum impedance.

SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as the digital input for the external serial inter­face clock during the Data Output period. A weak internal
pull-up is automatically activated in Internal Serial Clock
Operation mode. The Serial Clock Operation mode is de­termined by the logic level applied to the SCK pin at power
up or during the most recent falling edge of CS.

FO (Pin 10): Frequency Control Pin. Digital input that
controls the conversion clock. When FO is connected to
GND the converter uses its internal oscillator running at

307.2kHz. The conversion clock may also be overridden
by driving the FO pin with an external clock in order to
change the output rate or the digital filter rejection null.

Exposed Pad (Pin 11): This pin is ground and should be
soldered to the PCB, GND plane. For prototyping purposes
this pin may remain floating.

SDO (Pin 7): Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = VCC), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.

2482f

9

LTC2482

1.69k

SDO

2482 TC02

Hi-Z TO V

OL

VOH TO V

OL

VOL TO Hi-Z

C

LOAD

= 20pF

V

CC

UU

W

FU CTIO AL BLOCK DIAGRA

V

REF

3

+

IN

4

–

IN

5

GND

+

IN

3RD ORDER

∆Σ ADC

–

IN

–

REF

AUTOCALIBRATION

AND CONTROL

8

REF

2

V

CC

1

+

SERIAL

INTERFACE

INTERNAL

OSCILLATOR

GND

SCK

SD0

CS

F

2482 FD

9

7

6

O

10

TEST CIRCUITS

SDO

1.69k

Hi-Z TO V
VOL TO V

OH

VOH TO Hi-Z

= 20pF

C

LOAD

OH

2482 TC01

10

2482f

WUW

TI I G DIAGRA S

CS

LTC2482

Timing Diagram Using Internal SCK

SDO

SCK

SDO

SCK

SLEEP

t

1

t

t

3

KQMIN

t

KQMAX

t

2

CONVERSIONDATA OUT

2482 TD1

Timing Diagram Using External SCK

CS

SLEEP

t

1

t

5

t

6

t

4

t

KQMIN

t

KQMAX

t

2

CONVERSIONDATA OUT

2482 TD2

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APPLICATIO S I FOR ATIO

CONVERTER OPERATION

Converter Operation Cycle

The LTC2482 is a low power, delta-sigma analog-to­digital converter with an easy to use 3-wire serial interface
and automatic differential input current cancellation. Its
operation is made up of three states. The converter oper­ating cycle begins with the conversion, followed by the low
power sleep state and ends with the data output (see
Figure 1). The 3-wire interface consists of serial data
output (SDO), serial clock (SCK) and chip select (CS).

Initially, the LTC2482 performs a conversion. Once the
conversion is complete, the device enters the sleep state.

CONVERT

SLEEP

FALSE

CS = LOW

AND

SCK

TRUE

DATA OUTPUT

2482 F01

Figure 1. LTC2482 State Transition Diagram

2482f

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APPLICATIO S I FOR ATIO

While in this sleep state, power consumption is reduced by
two orders of magnitude. The part remains in the sleep
state as long as CS is HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.

Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data output state and start a new
conversion. The conversion result is shifted out of the
device through the serial data output pin (SDO) on the
falling edge of the serial clock (SCK) (see Figure 2).

Through timing control of the CS and SCK pins, the
LTC2482 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program­ming configuration registers; moreover, they do not dis­turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.

Easy Drive Input Current Cancellation

The LTC2482 combines a high precision delta-sigma ADC
with an automatic differential input current cancellation
front end. A proprietary front-end passive sampling
network transparently removes the differential input cur-

rent. This enables external RC networks and high imped­ance sensors to directly interface to the LTC2482 without
external amplifiers. The remaining common mode input
current is eliminated by either balancing the differential
input impedances or setting the common mode input
equal to the common mode reference (see Automatic
Input Current Cancellation section). This unique architec­ture does not require on-chip buffers enabling input sig­nals to swing all the way to ground and up to V

CC

.
Furthermore, the cancellation does not interfere with the
transparent offset and full-scale autocalibration and the
absolute accuracy (full scale + offset + linearity) is main­tained with external RC networks.

Output Data Format

The LTC2482 serial output data stream is 24 bits long. The
first 3 bits represent status information indicating the sign
and conversion state. The next 17 bits are the conversion
result, MSB first. The remaining 4 bits are always zero.
Bit 21 and Bit 20 together are also used to indicate an
underrange condition (the differential input voltage is
below –FS) or an overrange condition (the differential
input voltage is above +FS).

In applications where a processor generates 32 clock cycles,
or to remain compatible with higher resolution converters,
the LTC2482’s digital interface will ignore extra clock edges
seen during the next conversion period after the 24th and
output “1” for the extra clock cycles. Furthermore, CS may
be pulled high prior to outputting all 24 bits, aborting the
data out transfer and initiating a new conversion.

SDO

SCK

12

CS

BIT 21 BIT 20 BIT 19 BIT 18 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0BIT 22BIT 23

EOC

Hi-Z

SLEEP DATA OUTPUT

DMY MSB B16

SIG

CONVERSION RESULT

Figure 2. Output Data Timing

LSB

CONVERSION

2482 F02

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APPLICATIO S I FOR ATIO

LTC2482

Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.

Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.

Bit 21 (third output bit) is the conversion result sign indi­cator (SIG). If V

is >0, this bit is HIGH. If VIN is <0, this

IN

bit is LOW.

Bit 20 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 21 also
provides the underrange or overrange indication. If both
Bit 21 and Bit 20 are HIGH, the differential input voltage is
above +FS. If both Bit 21 and Bit 20 are LOW, the
differential input voltage is below –FS.

The function of these bits is summarized in Table 1.

Table 1. LTC2482 Status Bits

BIT 23 BIT 22 BIT 21 BIT 20

INPUT RANGE EOC DMY SIG MSB

VIN ≥ 0.5 • V
0V ≤ VIN < 0.5 • V

–0.5 • V

VIN < – 0.5 • V

REF

≤ VIN < 0V 0001

REF

REF

REF

0011

0010

0000

Bits 20-4 are the 16-bit plus sign conversion result MSB
first.

Data is shifted out of the SDO pin under control of the serial
clock (SCK) (see Figure 2). Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.

In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes in real time
from HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the first
rising edge of SCK. Bit 22 is shifted out of the device on the
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 23rd SCK and may be latched
on the rising edge of the 24th SCK pulse. On the falling
edge of the 24th SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 23) for the next conversion cycle. Table 2 summarizes
the output data format.

As long as the voltage on the IN+ and IN– pins is
maintained within the –0.3V to (V

+ 0.3V) absolute

CC

maximum operating range, a conversion result is
generated for any differential input voltage VIN from
–FS = –0.5 • V

to +FS = 0.5 • V

REF

. For differential input

REF

voltages greater than +FS, the conversion result is clamped
to the value corresponding to the +FS + 1LSB. For
differential input voltages below –FS, the conversion re­sult is clamped to the value corresponding to –FS – 1LSB.

Bits 3-0 are always low and are included to maintain
software compatibility with the LTC2480.

Table 2. LTC2482 Output Data Format

DIFFERENTIAL INPUT VOLTAGE BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 … BIT 4

* EOC DMY SIG MSB

V

IN

VIN* ≥ FS** 00110 0 0…0 0
FS** – 1LSB 0 0101 1 1…1 0

0.5 • FS** 0 0101 0 0…0 0

0.5 • FS** – 1LSB 0 0100 1 1…1 0
0 0 0100 0 0…0 0
–1LSB 0 0011 1 1…1 0
–0.5 • FS** 0 0011 0 0…0 0
–0.5 • FS** – 1LSB 0 0010 1 1…1 0
–FS** 0 0010 0 0…0 0
VIN* < –FS** 0 0001 1 1…1 0

*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • V

REF

.

BITS 3-0

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Conversion Clock

A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a SINC or Comb filter). For high
resolution, low frequency applications, this filter is typically
designed to reject line frequencies of 50Hz or 60Hz plus their
harmonics. The filter rejection performance is directly
related to the accuracy of the converter system clock.
The LTC2482 incorporates a highly accurate on-chip
oscillator. This eliminates the need for external frequency
setting components such as crystals or oscillators.

Frequency Rejection Selection (FO)

The LTC2482 internal oscillator provides better than 87dB
normal mode rejection at the line frequency and all its
harmonics (up to the 255th) for the frequency range 48Hz
to 62.4Hz.

When a fundamental rejection frequency different from 50Hz/
60Hz is required, when more than 87dB rejection is needed
for 50Hz/60Hz, or when the converter must be synchronized
with an outside source, the LTC2482 can operate with an
external conversion clock. The converter automatically de­tects the presence of an external clock signal at the FO pin and
turns off the internal oscillator. The frequency f

EOSC

of the
external signal must be at least 10kHz to be detected. The
external clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and low
periods t

HEO

and t

are observed.

LEO

While operating with an external conversion clock of a
frequency f

, the LTC2482 provides better than 110dB

EOSC

normal mode rejection in a frequency range of f

EOSC

/5120
± 4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f

EOSC

/5120
is shown in Figure 3.

–80

–85

–90

–95

–100

–105

–110

–115

–120

–125

NORMAL MODE REJECTION (dB)

–130

–135

–140

–12–8–404812

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DEVIATION FROM NOTCH FREQUENCY f

Figure 3. LTC2482 Normal Mode Rejection When Using
an External Oscillator

EOSC

/5120(%)

2480 F03

Whenever an external clock is not present at the FO pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2482
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.

Table 3 summarizes the duration of each state and the
achievable output data rate as a function of FO.

Table 3. LTC2482 State Duration

STATE OPERATING MODE DURATION

CONVERT Internal Oscillator 50Hz/60Hz Rejection 147ms, Output Data Rate ≤ 6.8 Readings/s

External Oscillator FO = External Oscillator 41036/f

with Frequency f
(f

/5120 Rejection)

EOSC

SLEEP As Long As CS = HIGH, After a Conversion is Complete
DATA OUTPUT Internal Serial Clock FO = LOW/HIGH As Long As CS = LOW But Not Longer Than 0.62ms

(Internal Oscillator) (24 SCK Cycles)
FO = External Oscillator with As Long As CS = LOW But Not Longer Than 192/f

Frequency f

External Serial Clock with As Long As CS = LOW But Not Longer Than 24/f
Frequency f

kHz (24 SCK Cycles)

SCK

EOSC

kHz

EOSC

kHz (24 SCK Cycles)

s, Output Data Rate ≤ f

EOSC

/41036 Readings/s

EOSC

EOSC

SCK

ms

ms

14

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LTC2482

Ease of Use

The

LTC2482
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.

The LTC2482 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to time,
supply voltage change and temperature drift.

Power-Up Sequence

The LTC2482 automatically enters an internal reset
state when the power supply voltage VCC drops below
approximately 2V. This feature guarantees the integrity of
the conversion result and of the serial interface mode
selection. (See the 2-wire I/O sections in the Serial Inter­face Timing Modes section.)

When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 4ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2482 starts a normal conversion cycle and
follows the succession of states described in Figure 1. The
first conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.

Reference Voltage Range

The LTC2482 external reference voltage range is 0.1V to
VCC. The converter output noise is determined by the
thermal noise of the front-end circuits, and as such, its
value in nanovolts is nearly constant with reference volt­age. Since the transition noise (600nV) is much less than
the quantization noise (V

data output has no latency, filter settling

/217), a decrease in the refer-

REF

ence voltage will increase the converter resolution. A
reduced reference voltage will improve the converter
performance when operated with an external conversion
clock (external FO signal) at substantially higher output
data rates (see the Output Data Rate section).

The negative reference input to the converter is internally
tied to GND. GND (Pin 8) should be connected to a ground
plane through as short a trace as possible to minimize
voltage drop. The LTC2482 has an average operational
current of 160µA and for 1Ω parasitic resistance, the
voltage drop of 160µV causes a gain error of 2LSB for

= 5V.

V

REF

Input Voltage Range

The analog input is truly differential with an absolute/
common mode range for the IN
extending from GND – 0.3V to VCC + 0.3V. Outside these
limits, the ESD protection devices begin to turn on and the
errors due to input leakage current increase rapidly. Within
these limits, the LTC2482 converts bipolar differential
input signal, VIN = IN+ – IN–, from – FS to +FS where
FS = 0.5 • V
indicates the overrange or the underrange condition using
distinct output codes. Since the differential input current
cancellation does not rely on an on-chip buffer,
current cancellation as well as DC performance is
maintained rail-to-rail.

Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the perfor­mance of the devices. The effect of the series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sec­tions. In addition, series resistors will introduce a tem­perature dependent offset error due to the input leakage
current. A 1nA input leakage current will develop a 1ppm
offset error on a 5k resistor if V
very strong temperature dependency.

. Outside this range, the converter

REF

+

and IN– input pins

= 5V. This error has a

REF

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APPLICATIO S I FOR ATIO

SERIAL INTERFACE TIMING MODES

The LTC2482’s 3-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock,
2- or 3-wire I/O, single cycle or continuous conversion.
The following sections describe each of these serial inter­face timing modes in detail. In all these cases, the con­verter can use the internal oscillator (FO = LOW or FO =
HIGH) or an external oscillator connected to the F
Refer to Table 4 for a summary.

External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 4.

The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.

The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. Independent of CS, the
device automatically enters the low power sleep state once
the conversion is complete.

pin.

O

When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK
is seen while CS is LOW. The output data is shifted out of
the SDO pin on each falling edge of SCK
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 24th rising edge of SCK. On the 24th falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress. In
applications where the processor generates 32 clock
cycles, or to remain compatible with higher resolution
converters, the LTC2482’s digital interface will ignore
extra clock edges seen during the next conversion period
after the 24th and outputs “1” for the extra clock cycles.

At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.

Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the 24th
falling edge of SCK (see Figure 5). On the rising edge of CS,
the device aborts the data output state and immediately
initiates a new conversion. This is useful for systems not
requiring all 24 bits of output data, aborting an invalid con­version cycle or synchronizing the start of a conversion.

. This enables

Table 4. LTC2482 Interface Timing Modes

CONVERSION DATA CONNECTION

SCK CYCLE OUTPUT and

CONFIGURATION SOURCE CONTROL CONTROL WAVEFORMS

External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 4, 5

External SCK, 2-Wire I/O External SCK SCK Figure 6
Internal SCK, Single Cycle Conversion Internal CS↓ CS↓ Figures 7, 8

Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 9

16

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REFERENCE

0.1V TO V

TEST EOC

(OPTIONAL)

CS

SDO

SCK

(EXTERNAL)

TEST EOC

CONVERSION

SLEEPSLEEP

BIT 23

EOC

Figure 4. External Serial Clock, Single Cycle Operation

2.7V TO 5.5V

1µF

VOLTAGE

ANALOG

INPUT

MSBSIG

210

V

F

CC

O

LTC2482

3

V

REF

CC

4

+

IN

5

–

IN

9

SCK

7

SDO

6

CS

8,1

GND

DATA OUTPUT CONVERSION

INT/EXT CLOCK

3-WIRE
SPI INTERFACE

BIT 4BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22

LSB

LTC2482

BIT 0

TEST EOC

Hi-ZHi-ZHi-Z

2482 F04

SDO

SCK

(EXTERNAL)

2.7V TO 5.5V

1µF

210

V

F

CC

LTC2482

INPUT

3

V

REF

CC

4

5

SCK

SDO

+

IN

CS

–

IN

GND

MSBSIG

REFERENCE

VOLTAGE

0.1V TO V

ANALOG

TEST EOC

(OPTIONAL)

CS

DATA

OUTPUT

EOC

TEST EOC

Hi-Z

CONVERSIONSLEEP

SLEEP

Hi-Z Hi-ZHi-Z

SLEEP

BIT 23BIT 0

EOC

O

7

8,1

INT/EXT CLOCK

9

6

DATA OUTPUT

3-WIRE
SPI INTERFACE

BIT 8BIT 19 BIT 18 BIT 17 BIT 16 BIT 9BIT 20BIT 21BIT 22

TEST EOC

CONVERSION

2482 F05

Figure 5. External Serial Clock, Reduced Data Output Length

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External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter­nally generated serial clock (SCK) signal (see Figure 6). CS
may be permanently tied to ground, simplifying the user
interface or transmission over an isolation barrier.

The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
typically 4ms after V

exceeds approximately 2V. The level

CC

applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.

Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. The output data is shifted out of the SDO pin
on each falling edge of SCK. EOC can be latched on the
first rising edge of SCK. On the 24th falling edge of SCK,
SDO goes HIGH (EOC = 1) indicating a new conversion
has begun. In applications where the processor generates

32 clock cycles, or to remain compatible with higher
resolution converters, the LTC2482’s digital interface will
ignore extra clock edges seen during the next conversion
period after the 24th and outputs “1” for the extra clock
cycles.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle (see Figure 7).

In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto­matically selected if SCK is not externally driven.

The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.

CS

SDO

SCK

(EXTERNAL)

18

CONVERSION

BIT 23

EOC

2.7V TO 5.5V

1µF

210

V

F

CC

LTC2482

REFERENCE

VOLTAGE

0.1V TO V

3

V

REF

CC

4

ANALOG

5

INPUT

MSBSIG LSB

SCK

SDO

+

IN

CS

–

IN

GND

DATA OUTPUT CONVERSION

INT/EXT CLOCK

O

9

2-WIRE
SPI INTERFACE

7

6

8,1

Figure 6. External Serial Clock, CS = 0 Operation

BIT 4BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22

2482 F06

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LTC2482

When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the low power mode during the EOC
test. In order to allow the device to return to the low power
sleep state, CS must be pulled HIGH before the first rising
edge of SCK. In the internal SCK timing mode, SCK goes
HIGH and the device begins outputting data at time t
after the falling edge of CS (if EOC = 0) or t

EOCtest

EOCtest

after EOC
goes LOW (if CS is LOW during the falling edge of EOC).
The value of t
oscillator. If F
frequency f

EOSC

is pulled HIGH before time t

is 12µs if the device is using its internal

EOCtest

is driven by an external oscillator of

O

, then t

EOCtest

is 3.6/f

EOCtest

in seconds. If CS

EOSC

, the device returns to
the sleep state and the conversion result is held in the
internal static shift register.

If CS remains LOW longer than t

, the first rising

EOCtest

edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 24th rising edge. The output data is shifted out of
the SDO pin on each falling edge of SCK. The internally
generated serial clock is output to the SCK pin. This signal
may be used to shift the conversion result into external
circuitry. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result on the 24th rising
edge of SCK. After the 24th rising edge, SDO goes HIGH
(EOC = 1), SCK stays HIGH and a new conversion starts.

Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 24th rising edge of
SCK (see Figure 8). On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 24 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.

Whenever SCK is LOW, the LTC2482’s internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2482’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH once
the external driver goes Hi-Z. On the next CS falling edge,
the device will remain in the internal SCK timing mode.

SDO

SCK

(INTERNAL)

2.7V TO 5.5V

1µF

210

V

F

CC

LTC2482

INPUT

BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22

3

V

REF

CC

4

5

DATA OUTPUT CONVERSIONCONVERSION

SCK

SDO

+

IN

CS

–

IN

GND

REFERENCE

VOLTAGE

0.1V TO V

TEST EOC

CS

Hi-Z Hi-Z Hi-Z Hi-Z

SLEEP

SLEEP

<t

EOCtest

BIT 23

EOC

ANALOG

MSBSIG

INT/EXT CLOCK

O

9

3-WIRE

7

SPI INTERFACE

6

8,1

V

CC

10k

BIT 4

LSB

BIT 0

Figure 7. Internal Serial Clock, Single Cycle Operation

TEST EOC

2482 F07

2482f

19

LTC2482

WUUU

APPLICATIO S I FOR ATIO

A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver­sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as t

), the internal pull-up is

EOCtest

activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.

Internal Serial Clock, 2-Wire I/O,
Continuous Conversion

This timing mode uses a 2-wire (output only) interface. The
conversion result is shifted out of the device by an inter­nally generated serial clock (SCK) signal (see Figure 9).
CS may be permanently tied to ground, simplifying the
user interface or transmission over an isolation barrier.

The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2V. An internal weak

pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).

During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data input/
output cycle begins on the first rising edge of SCK and
ends after the

24th

rising edge. The output data is shifted
out of the SDO pin on each falling edge of SCK. The
internally generated serial clock is output to the SCK pin.
This signal may be used to shift the conversion result into
external circuitry. EOC can be latched on the first rising
edge of SCK and the last bit of the conversion result can
be latched on the

24th

rising edge of SCK. After the

24th
rising edge, SDO goes HIGH (EOC = 1) indicating a new
conversion is in progress. SCK remains HIGH during the
conversion.

SDO

SCK

(INTERNAL)

2.7V TO 5.5V

1µF

210

V

F

CC

LTC2482

ANALOG

INPUT

3

V

REF

CC

4

5

SCK

SDO

+

IN

CS

–

IN

GND

BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22

MSBSIG

REFERENCE

VOLTAGE

0.1V TO V

TEST EOC

TEST EOC

(OPTIONAL)

<t

EOCtest

BIT 23

EOC

SLEEPSLEEP

>t

EOCtest

CS

BIT 0

EOC

Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

DATA

OUTPUT

O

9

7

6

8,1

DATA OUTPUT

INT/EXT CLOCK

3-WIRE
SPI INTERFACE

V

CC

10k

BIT 8

Figure 8. Internal Serial Clock, Reduce Data Output Length

CONVERSIONCONVERSIONSLEEP

TEST EOC

2482 F08

2482f

20

WUUU

APPLICATIO S I FOR ATIO

CS

SDO

SCK

(INTERNAL)

BIT 23

EOC

Figure 9. Internal Serial Clock, CS = 0 Continuous Operation

2.7V TO 5.5V

1µF

REFERENCE

VOLTAGE

0.1V TO V

ANALOG

INPUT

210

V

F

CC

O

LTC2482

3

V

REF

CC

4

+

IN

5

–

IN

9

SCK

7

SDO

6

CS

8,1

GND

DATA OUTPUT CONVERSIONCONVERSION

INT/EXT CLOCK

2-WIRE
SPI INTERFACE

LTC2482

V

CC

10k

BIT 4 BIT 0BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22

LSBMSBSIG

2482 F09

PRESERVING THE CONVERTER ACCURACY

The LTC2482 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturba­tions and so on. Nevertheless, in order to preserve the
extreme accuracy capability of this part, some simple
precautions are required.

Digital Signal Levels

The LTC2482’s digital interface is easy to use. Its digital
inputs (FO, CS and SCK in External SCK mode of operation)
accept standard CMOS logic levels and the internal hyster­esis receivers can tolerate edge transition times as slow as
100µs. However, some considerations are required to take
advantage of the exceptional accuracy and low supply
current of this converter.

The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.

While a digital input signal is in the range 0.5V to
(VCC– 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (FO, CS and
SCK in External SCK mode of operation) is within
this range, the power supply current may increase even
if the signal in question is at a valid logic level.

For micropower operation, it is recommended to
drive all digital input signals to full CMOS levels
[VIL < 0.4V and VOH > (VCC – 0.4V)].

During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins can
severely disturb the analog to digital conversion process.
Undershoot and overshoot occur because of the imped­ance mismatch of the circuit board trace at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver to
the LTC2482

. For reference, on a regular FR-4 board,
signal propagation velocity is approximately 183ps/inch
for internal traces and 170ps/inch for surface traces.
Thus, a driver generating a control signal with a minimum
transition time of 1ns must be connected to the converter
pin through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
are used and multiple reflections may occur. The solution
is to carefully terminate all transmission lines close to
their characteristic impedance.

Parallel termination near the LTC2482 pin will eliminate
this problem but will increase the driver power dissipa­tion. A series resistor between 27Ω and 56Ω placed near
the driver output pin will also eliminate this problem
without additional power dissipation. The actual resistor
value depends upon the trace impedance and connection
topology.

2482f

21

LTC2482

IIN IIN

VV

R

I REF

VV V

RVR

VD
R

VV V

R

V

VR

where

AVG AVG

IN CM REF CM

EQ

AVG

REF INCM REFCM

EQ REF EQ

REF T

EQ

REF REF CM IN CM

EQ

IN

REF EQ

+

+

()=()

=

−

•

()

=

• − +

•

−

•

−≅

+

()

–

() ()

() ()

.

.

.

.• •

.–

.•

–

•

05

15

05

05

15

05

2

::

V

VININ

V

IN IN

REFCM

IN

INCM

=

= −

=

+

⎛

⎝

⎜

⎞

⎠

⎟

= Ω

=•

()

+ −

+ −

2

R 2.98M INTERNAL OSCILLATOR

R 0.915 10 / f EXTERNAL OSCILLATOR

D IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT

EQ

EQ

12

EOSC

T

WHERE REF– IS INTERNALLY TIED TO GND

WUUU

APPLICATIO S I FOR ATIO

An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The differential input architec­ture reduces the converter’s sensitivity to ground
currents.

Particular attention must be given to the connection of the
FO signal when the LTC2482 is used with an external
conversion clock. This clock is active during the conver­sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals can result in DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals can result in a DC offset error. Such
perturbations can occur due to asymmetric capacitive
coupling between the FO signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the FO signal trace and the input/reference sig­nals. When the FO signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the FO connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer­ence. In this situation, the user must reduce to a minimum

the loop area for the FO signal as well as the loop area for
the differential input and reference connections. Even
when F

is not driven, other nearby signals pose similar

0

EMI threats which will be minimized by following good
layout practices.

Driving the Input and Reference

The input and reference pins of the LTC2482 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these ca­pacitors are switching between these four pins transfer­ring small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 10.

For a simple approximation, the source impedance R
driving an analog input pin (IN+, IN–, V

+

or GND) can be

REF

S

considered to form, together with RSW and CEQ (see
Figure 10), a first order passive network with a time
constant τ = (RS + RSW) • CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst­case circumstances, the errors may add.

V

CC

+

I

REF

+

V

REF

+

I

IN

+

V

IN

–

I

IN

–

V

IN

–

I

REF

GND

SWITCHING FREQUENCY

= 123kHz INTERNAL OSCILLATOR

f

SW

= 0.4 • f

f

SW

22

I

LEAK

I

LEAK

V

CC

V

CC

I

LEAK

I

LEAK

V

CC

EXTERNAL OSCILLATOR

EOSC

RSW (TYP)

10k

RSW (TYP)

I

LEAK

10k

I

LEAK

RSW (TYP)

10k

I

LEAK

I

LEAK

10k

2482 F10

RSW (TYP)

2

V

IN

C

EQ

12pF
(TYP)

⎛

V

REF

⎜
⎝

+

⎞
⎟

2

⎠

Figure 10. LTC2482 Equivalent Analog Input Circuit

2482f

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APPLICATIO S I FOR ATIO

LTC2482

When using the internal oscillator, the LTC2482’s front­end switched-capacitor network is clocked at 123kHz
corresponding to an 8.1µs sampling period. Thus, for
settling errors of less than 1ppm, the driving source
impedance should be chosen such that τ ≤ 8.1µs/14 =
580ns. When an external oscillator of frequency f
used, the sampling period is 2.5/f
error of less than 1ppm, τ ≤ 0.178/f

and, for a settling

EOSC

.

EOSC

EOSC

is

Automatic Differential Input Current Cancellation

In applications where the sensor output impedance is low
(up to 10kΩ with no external bypass capacitor or up to
500Ω with 0.001µF bypass), complete settling of the input
occurs. In this case, no errors are introduced and direct
digitization of the sensor is possible.

For many applications, the sensor output impedance com­bined with external bypass capacitors produces RC time
constants much greater than the 580ns required for 1ppm
accuracy. For example, a 10kΩ bridge driving a 0.1µF
bypass capacitor has a time constant an order of magni­tude greater than the required maximum. Historically,
settling issues were solved using buffers. These buffers led
to increased noise, reduced DC performance (Offset/Drift),
limited input/output swing (cannot digitize signals near
ground or VCC), added system cost and increased power.
The LTC2482 uses a proprietary switching algorithm that
forces the average differential input current to zero inde­pendent of external settling errors. This allows accurate
direct digitization of high impedance sensors without the
need for buffers. Additional errors resulting from mis­matched leakage currents must also be taken into account.

The switching algorithm forces the average input current
on the positive input (I
current on the negative input (I

+

) to be equal to the average input

IN

–

). Over the complete

IN

conversion cycle, the average differential input current
(I

IN+

zero, the common mode input current (I

–

– I

) is zero. While the differential input current is

IN

IN

+

+ I

IN

–

)/2 is
proportional to the difference between the common mode
input voltage (V
voltage (V

REFCM

) and the common mode reference

INCM

).

In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balance bridge type application, both the differ­ential and common mode input current are zero. The

accuracy of the converter is unaffected by settling errors.
Mismatches in source impedances between IN+ and IN

–

also do not affect the accuracy.

In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between V

INCM

and V

. For a reference

REFCM

common mode of 2.5V and an input common mode of

1.5V, the common mode input current is approximately

0.74µA. This common mode input current has no effect on
the accuracy if the external source impedances tied to IN

+

and IN– are matched. Mismatches in these source imped­ances lead to a fixed offset error but do not affect the
linearity or full-scale reading. A 1% mismatch in 1kΩ
source resistances leads to a 1LSB shift (74µV) in offset
voltage.

In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the
common mode input current varies proportionally with
input voltage. For the case of balanced input impedances,
the common mode input current effects are rejected by the
large CMRR of the LTC2482 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errors proportional to the difference between the common
mode input voltage and the common mode reference
voltage. 1% mismatches in 1kΩ source resistances lead
to gain worst-case gain errors on the order of 1LSB (for 1V
differences in reference and input common mode volt­age). Table 5 summarizes the effects of mismatched
source impedance and differences in reference/input com­mon mode voltages.

Table 5. Suggested Input Configuration for LTC2482

BALANCED INPUT UNBALANCED INPUT
RESISTANCES RESISTANCES

Constant CIN > 1nF at Both CIN > 1nF at Both IN
V

– V

IN(CM)

Varying CIN > 1nF at Both IN
V

IN(CM)

– V

REF(CM)

REF(CM)

IN+ and IN–. Can Take and IN–. Can Take Large
Large Source Resistance Source Resistance.
with Negligible Error Unbalanced Resistance

Results in an Offset
Which Can be Calibrated

+

Minimize IN+ and IN
and IN–. Can Take Large Capacitors and Avoid
Source Resistance with Large Source Impedance
Negligible Error (<5k Recommended)

+

–

2482f

23

LTC2482

WUUU

APPLICATIO S I FOR ATIO

R

SOURCE

V

V

INCM

INCM

+ 0.5V

– 0.5V

IN

R

SOURCE

IN

C

IN

C

IN

Figure 11. An RC Network at IN+ and IN

80

VCC = 5V

= 5V

V

REF

60

+

= 3.75V

V

IN

–

= 1.25V

V

IN

40

= GND

F

O

= 25°C

T

A

20

0

–20

+FS ERROR (ppm)

–40

–60

–80

1

CIN = 1nF, 0.1µF, 1µF

10 100 10k

R

SOURCE

Figure 12. +FS Error vs R

80

VCC = 5V

= 5V

V

REF

60

+

= 1.25V

V

IN

–

= 3.75V

V

IN

40

= GND

F

O

= 25°C

T

A

20

0

–20

–FS ERROR (ppm)

–40

–60

–80

1

10 100 10k

CIN = 1nF, 0.1µF, 1µF

R

SOURCE

Figure 13. –FS Error vs R

CIN = 0pF

C

IN

1k

(Ω)

SOURCE

CIN = 100pF

1k

(Ω)

SOURCE

C

PAR

≅20pF

C

PAR

≅20pF

= 100pF

at IN+ or IN

CIN = 0pF

at IN+ or IN

2482 F12

2482 F13

IN

LTC2482

IN

100k

100k

+

–

–

2482 F11

–

–

The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and

–

, the expected drift of the dynamic current and offset

IN
will be insignificant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.

In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1µV typical and 10µV maximum offset voltage.

Reference Current

In a similar fashion, the LTC2482 samples the differential
reference pins V

+

and GND transferring small amount

REF

of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in two distinct situations.

For relatively small values of the external reference capaci­tors (C

< 1nF), the voltage on the sampling capacitor

REF

settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C

will deteriorate the converter offset and

REF

gain performance without significant benefits of reference
filtering and the user is advised to avoid them.

Larger values of reference capacitors (C

> 1nF) may be

REF

required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con­stant reference differential impedance.

24

In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator (50Hz/60Hz rejection), the differential refer-

2482f

WUUU

APPLICATIO S I FOR ATIO

LTC2482

ence resistance is 1.1MΩ and the resulting full-scale
error is 0.46ppm for each ohm of source resistance
driving the V
oscillator with a frequency f

pin. When FO is driven by an external

REF

(external conversion

EOSC

clock operation), the typical differential reference resis-

12

tance is 0.33 • 10

/f
resistance driving the V
f

ppm gain error. The typical +FS and –FS errors for

EOSC

Ω and each ohm of source

EOSC

pin will result in 1.53 • 10–6 •

REF

various combinations of source resistance seen by the
V

pin and external capacitance connected to that pin

REF

are shown in Figures 14-17.

In addition to this gain error, the converter INL perfor­mance is degraded by the reference source impedance.

90

VCC = 5V

80

= 5V

V

REF

+

= 3.75V

V

IN

70

–

= 1.25V

V

IN

= GND

F

O

60

= 25°C

T

A

50

40

30

+FS ERROR (ppm)

20

10

–10

C

= 0.01µF

REF

= 0.001µF

C

REF

= 100pF

C

REF

= 0pF

C

REF

0

10

0

100
R

SOURCE

1k

(Ω)

10k

100k

2482 F14

The INL is caused by the input dependent terms –V
(V

• REQ) – (0.5 • V

REF

• DT)/REQ in the reference pin

REF

IN

2

/

current as expressed in Figure 10. When using internal
oscillator with 50Hz/60Hz rejection, every 100Ω of refer­ence source resistance translates into about 0.61ppm
additional INL error. When F
oscillator with a frequency f
resistance driving V

• f

ppm additional INL error. Figure 18 shows the

EOSC

translates into about 1.99 • 10

REF

is driven by an external

O

, every 100Ω of source

EOSC

–6

typical INL error due to the source resistance driving the
V

pin when large C

REF

values are used. The user is

REF

advised to minimize the source impedance driving the
V

pin.

REF

10

0

C

C

REF

VCC = 5V

= 5V

V

REF

+

= 1.25V

V

IN

–

= 3.75V

V

IN

= GND

F

O

= 25°C

T

A

= 0.01µF

REF

= 0.001µF

= 100pF

C

REF

C

REF

10

= 0pF

100
R

SOURCE

1k

(Ω)

10k

100k

2482 F15

–10

–20

–30

–40

–50

–FS ERROR (ppm)

–60

–70

–80

–90

0

Figure 14. +FS Error vs R

500

VCC = 5V

= 5V

V

REF

+

= 3.75V

V

IN

400

–

= 1.25V

V

IN

= GND

F

O

= 25°C

T

A

300

200

+FS ERROR (ppm)

100

0

200

0

400

R

SOURCE

Figure 16. +FS Error vs R

SOURCE

C

= 1µF, 10µF

REF

600

(Ω)

SOURCE

at V

C

REF

C

REF

at V

REF

= 0.1µF

= 0.01µF

800

REF

(Small C

1000

2482 F16

(Large C

REF

REF

)

)

Figure 15. –FS Error vs R

0

–100

–200

C

= 1µF, 10µF

REF

–300

VCC = 5V

–FS ERROR (ppm)

–400

–500

0

V

REF

V

IN

V

IN

F

O

T

A

= 5V

+

= 1.25V

–

= 3.75V
= GND
= 25°C

200

400
R

SOURCE

Figure 17. –FS Error vs R

SOURCE

600

(Ω)

SOURCE

at V

C

REF

C

REF

at V

(Small C

REF

= 0.01µF

= 0.1µF

800

2482 F17

(Large C

REF

1000

REF

REF

)

)

2482f

25

LTC2482

WUUU

APPLICATIO S I FOR ATIO

10

VCC = 5V

8

= 5V

V

REF

= 2.5V

V

IN(CM)

6

= 25°C

T

A

= 10µF

C

)

REF

4

REF

2

0

–2

INL (ppm OF V

–4

–6

–8

–10

Figure 18. INL vs Differential Input Voltage and
Reference Source Resistance for C

–0.5

–0.3

–0.1

VIN/V

REF

0.1

(V)

R = 1k

R = 500Ω

R = 100Ω

0.3

REF

0.5

2482 F18

> 1µF

In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (V

REFCM

– V

) and a 5V reference,

INCM

each Ohm of reference source resistance introduces an
extra (V

REFCM

– V

INCM

)/(V

• REQ) full-scale gain error

REF

which is 0.067ppm when using the internal oscillator
(50Hz/60Hz rejection). If an external clock is used, the
corresponding extra gain error is 0.22 • 10–6 • f

EOSC

ppm.

The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci­tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typically better
than 0.5%. Such a specification can also be easily achieved
by an external clock. When relatively stable resistors
(50ppm/°C) are used for the external source impedance
seen by V

+

and GND, the expected drift of the dynamic

REF

current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.

In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05µV typical and 0.5µV maxi-
mum full-scale error.

Output Data Rate

When using its internal oscillator, the LTC2482 produces

6.8ps with a notch frequency of 55Hz, for simultaneous
50Hz/60Hz rejection. The actual output data rate will
depend upon the length of the sleep and data output
phases which are controlled by the user and which can be
made insignificantly short. When operated with an exter­nal conversion clock (FO connected to an external oscilla­tor), the LTC2482 output data rate can be increased as
desired. The duration of the conversion phase is 41036/
f

.

EOSC

An increase in f

over the nominal 307.2kHz will

EOSC

translate into a proportional increase in the maximum
output data rate. The increase in output rate is neverthe­less accompanied by three potential effects, which must
be carefully considered.

First, a change in f

will result in a proportional change

EOSC

in the internal notch position and in a reduction of the
converter differential mode rejection at the power
line frequency. In many applications, the subsequent
performance degradation can be substantially reduced by
relying upon the LTC2482’s exceptional common mode
rejection and by carefully eliminating common mode to
differential mode conversion sources in the input circuit.
The user should avoid single-ended input filters and
should maintain a very high degree of matching and
symmetry in the circuits driving the IN+ and IN– pins.

Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, C

) are used, the

REF

previous section provides formulae for evaluating the
effect of the source resistance upon the converter perfor­mance for any value of f
reference capacitors (CIN, C

. If small external input and/or

EOSC

) are used, the effect of the

REF

external source resistance upon the LTC2482 typical
performance can be inferred from Figures 12, 13, 14 and
15 in which the horizontal axis is scaled by 307200/f

EOSC

.

Third, an increase in the frequency of the external oscilla­tor above 1MHz (a more than 3× increase in the output data
rate) will start to decrease the effectiveness of the internal
autocalibration circuits. This will result in a progressive

2482f

26

WUUU

APPLICATIO S I FOR ATIO

50

V

= V

IN(CM)

VCC = V

40

V

)

F

REF

30

20

10

OFFSET ERROR (ppm OF V

0

–10

REF(CM)

= 5V

REF

= 0V

IN

= EXT CLOCK

O

TA = 85°C

TA = 25°C

20 40 60 80

OUTPUT DATA RATE (READINGS/SEC)

10010030507090

2482 F19

3500

V

= V

IN(CM)

VCC = V

3000

)

REF

2500

2000

1500

1000

+FS ERROR (ppm OF V

500

0

REF

F

= EXT CLOCK

O

0

20

10

OUTPUT DATA RATE (READINGS/SEC)

REF(CM)

= 5V

30

TA = 85°C

50

40

T

= 25°C

A

70

60 80

LTC2482

100

90

2482 F20

Figure 19. Offset Error vs Output Data Rate and Temperature

0

–500

)

REF

–1000

–1500

–2000

–2500

–FS ERROR (ppm OF V

V

= V

IN(CM)

–3000

VCC = V

REF

= EXT CLOCK

F

O

–3500

0

20

10

OUTPUT DATA RATE (READINGS/SEC)

TA = 85°C

REF(CM)

= 5V

30

40

50

60 80

T

A

= 25°C

70

90

2482 F21

100

Figure 21. –FS Error vs Output Data Rate and Temperature

20

V

= V

IN(CM)

VIN = 0V
F

)

15

T

REF

10

5

0

OFFSET ERROR (ppm OF V

–5

–10

0

REF(CM)

= EXT CLOCK

O

= 25°C

A

VCC = V

VCC = 5V, V

20

10

OUTPUT DATA RATE (READINGS/SEC)

REF

30

40

= 2.5V

50

60 80

REF

= 5V

70

90

2482 F23

100

Figure 20. +FS Error vs Output Data Rate and Temperature

22

V

= V

IN(CM)

VCC = V
F

20

RES = LOG 2 (V

18

16

14

RESOLUTION (BITS)

12

10

0

Figure 22. Resolution (INL

REF(CM)

= 5V

REF

= EXT CLOCK

O

10

20

OUTPUT DATA RATE (READINGS/SEC)

/INL

40

MAX

TA = 85°C

50

60 80

)

TA = 25°C

70

REF

30

MAX

100

90

2482 F22

≤ 1LSB)

vs Output Data Rate and Temperature

22

V

= V

IN(CM)

VIN = 0V
REF

20

F
T

18

RES = LOG 2 (V

16

14

RESOLUTION (BITS)

12

10

0

REF(CM)

–

= GND

= EXT CLOCK

O

= 25°C

A

VCC = 5V, V

20

10

OUTPUT DATA RATE (READINGS/SEC)

/INL

= 2.5V

40

MAX

50

)

VCC = V

70

60 80

REF

REF

30

REF

= 5V

90

2482 F24

100

Figure 23. Offset Error vs Output
Data Rate and Reference Voltage

Figure 24. Resolution (INL

≤ 1LSB) vs

MAX

Output Data Rate and Reference Voltage

2482f

27

LTC2482

WUUU

APPLICATIO S I FOR ATIO

degradation in the converter accuracy and linearity. Typi­cal measured performance curves for output data rates up
to 100 readings per second are shown in Figures 19 to 24.
In order to obtain the highest possible level of accuracy from
this converter at output data rates above 20 readings per
second, the user is advised to maximize the power supply
voltage used and to limit the maximum ambient operating
temperature. In certain circumstances, a reduction of the
differential reference voltage may be beneficial.

Input Bandwidth

The combined effect of the internal SINC4 digital filter and
of the analog and digital autocalibration circuits deter­mines the LTC2482 input bandwidth. When the internal
oscillator is used the 3dB input bandwidth is 3.3Hz. If an
external conversion clock generator of frequency f

EOSC

is

connected to the FO pin, the 3dB input bandwidth is

10.7 • 10–6 • f

EOSC

.

Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2482 input bandwidth is shown in
Figure 25. When an external oscillator of frequency f

EOSC

is used, the shape of the LTC2482 input bandwidth can be
derived from Figure 25 in which the horizontal axis is
scaled by f

EOSC

/307200.

The conversion noise (600nV

typical for V

RMS

REF

= 5V)

can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is 47nV√Hz
for an infinite bandwidth source and 64nV√Hz for a single

0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in order
to reduce the output referred noise and relatively high
bandwidth (at least 500kHz) necessary to drive the input
switched-capacitor network. A possible solution is a high
gain, low bandwidth amplifier stage followed by a high
bandwidth unity-gain buffer.

When external amplifiers are driving the LTC2482, the
ADC input referred system noise calculation can be sim­plified by Figure 26. The noise of an amplifier driving the
LTC2482 input pin can be modeled as a band limited white
noise source. Its bandwidth can be approximated by the
bandwidth of a single pole lowpass filter with a corner
frequency fi. The amplifier noise spectral density is ni.
From Figure 26, using fi as the x-axis selector, we can find
on the y-axis the noise equivalent bandwidth freqi of the
input driving amplifier. This bandwidth includes the band
limiting effects of the ADC internal calibration and filter­ing. The noise of the driving amplifier referred to the
converter input and including all these effects can be
calculated as N = ni • √freqi. The total system noise

0

–1

–2

–3

–4

–5

INPUT SIGNAL ATTENUATION (dB)

–6

Figure 25. Input Signal Bandwidth Using the Internal Oscillator

1

0

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

3

2

4

2482 F25

5

28

100

10

1

INPUT REFERRED NOISE

EQUIVALENT BANDWIDTH (Hz)

0.1

0.1 1 10 100 1k 10k 100k 1M
INPUT NOISE SOURCE SINGLE POLE

EQUIVALENT BANDWIDTH (Hz)

Figure 26. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source

2482 F26

2482f

WUUU

APPLICATIO S I FOR ATIO

LTC2482

(referred to the LTC2482 input) can now be obtained by
summing as square root of sum of squares the three ADC
input referred noise sources: the LTC2482 internal noise,
the noise of the IN+ driving amplifier and the noise of the

–

IN

driving amplifier.

If the FO pin is driven by an external oscillator of frequency
f

, Figure 26 can still be used for noise calculation if the

EOSC

x-axis is scaled by f
ratio f

/307200, the Figure 26 plot accuracy begins to

EOSC

/307200. For large values of the

EOSC

decrease, but at the same time the LTC2482 noise floor
rises and the noise contribution of the driving amplifiers
lose significance.

Normal Mode Rejection and Antialiasing

One of the advantages delta-sigma ADCs offer over con­ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2482 significantly
simplifies antialiasing filter requirements. Additionally,
the input current cancellation feature of the LTC2482
allows external lowpass filtering without degrading the DC
performance of the device.

The SINC

4

digital filter provides greater than 120dB nor­mal mode rejection at all frequencies except DC and
integer multiples of the modulator sampling frequency
(fS). The LTC2482’s autocalibration circuits further sim­plify the antialiasing requirements by additional normal
mode signal filtering both in the analog and digital domain.
Independent of the operating mode, fS = 256 • fN = 2048

• f

OUTMAX

where fN is the notch frequency and f

OUTMAX

is

the maximum output data rate. In the internal oscillator

with 50Hz/60Hz rejection, fS = 13960Hz. In the

mode
external oscillator mode, f

S

= f

EOSC

/20.

The regions of low rejection occurring at integer multiples

have a very narrow bandwidth. Magnified details of

of f

S

the normal mode rejection curves are shown in Figure 27
(rejection near DC) and Figure 28 (rejection at f
where f

represents the notch frequency. These curves

N

= 256fN)

S

have been derived for the external oscillator mode but they
can be used in all operating modes by appropriately
selecting the fN value.

The user can expect to achieve this level of performance
using the internal oscillator as it is demonstrated by
Figure 29. Typical measured values of the normal mode
rejection of the LTC2482 operating with an internal
oscillator (50Hz/60Hz rejection) is shown in Figure 29.

As a result of these remarkable normal mode specifica­tions, minimal (if any) antialias filtering is required in front
of the LTC2482. If passive RC components are placed in
front of the LTC2482, the input dynamic current should be
considered (see Input Current section). In this case, the
differential input current cancellation feature of the
LTC2482 allows external RC networks without significant
degradation in DC performance.

Traditional high order delta-sigma modulators, while pro­viding very good linearity and resolution, suffer from
potential instabilities at large input signal levels. The

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

INPUT NORMAL MODE REJECTION (dB)

–110

–120

Figure 27. Input Normal Mode Rejection at DC

fN0 2fN3fN4fN5fN6fN7fN8f

INPUT SIGNAL FREQUENCY (Hz)

fN = f

EOSC

/5120

N

2482 F27

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

INPUT NORMAL MODE REJECTION (dB)

–110

–120

250f

252fN254fN256fN258fN260fN262f

N

INPUT SIGNAL FREQUENCY (Hz)

Figure 28. Input Normal Mode Rejection at fS = 256f

N

2482 F28

29

N

2482f

LTC2482

WUUU

APPLICATIO S I FOR ATIO

0

–20

–40

–60

–80

NORMAL MODE REJECTION (dB)

–100

–120

0

20 40 60 80 100 120 140 160 180 200 220

Figure 29. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale

INPUT FREQUENCY (Hz)

MEASURED DATA
CALCULATED DATA

proprietary architecture used for the LTC2482 third order
modulator resolves this problem and guarantees a predict­able stable behavior at input signal levels of up to 150% of
full scale. In many industrial applications, it is not uncom­mon to have to measure microvolt level signals superim­posed over volt level perturbations and the LTC2482 is
eminently suited for such tasks. When the perturbation is
differential, the specification of interest is the normal mode
rejection for large input signal levels. With a reference
voltage V

= 5V, the LTC2482 has a full-scale differential

REF

input range of 5V peak-to-peak.

Remote Sensing with Easy Drive Input Current
Cancellation

One problem faced by designers of high performance data
acquisition systems is achieving data sheet specified per­formance in a real world environment. One advantage delta
sigma type ADCs offer over the alternatives is on-chip digi­tal filtering (noise suppression). The disadvantage (solved
by Easy Drive technology) is the drive requirements inher­ent in delta sigma ADC architectures. In order to demon­strate the full potential of the Easy Drive technology, a
practical test case was characterized (see Figure 30).

Precise measurements of offset, noise and linearity were
measured under extreme test conditions. A remote sensor
was digitized through 100 meters of cable applied to an RC
network with low accuracy 1% resistors. A remote sensor
voltage was swept from 0 to 2.5 with less than 1LSB
linearity error (see Figure 31). Noise levels of 650nV RMS
and offsets below 5µV were measured (see Figure 32).

VCC = 5V
V

= 5V

REF

V

IN(CM)

V

IN(P-P)

T

= 25°C

A

= 2.5V
= 5V

2482 F29

Fundamentally, an oversampled data converter (∆Σ ADC)
directly connected to a long cable and a low precision RC
network leads to many problems greatly limiting the
accuracy of the system. These include transmission line
effects, noise and DC settling errors.

The sampling network of ∆Σ ADCs injects high frequency
current spikes into the cable. The resulting voltage spikes
are reflected through the long wire and result in excessive
noise and reduced accuracy. This problem is solved by
placing a bypass capacitor across the input to the ADC.
This capacitor serves as a charge reservoir for the ADC’s
sampling network and reduces the voltage spikes by the
ratio of internal sampling capacitor to external bypass
capacitor. A 1µF bypass capacitor reduces the voltage
spikes generated by the sampling network by a factor of
50,000 (1V spikes are reduced to 18µV) and is sufficient
to achieve data sheet specified noise and accuracy.

The addition the large external bypass capacitor results in
input settling errors. Typical 24-bit high resolution delta
sigma ADCs sample at time intervals on the order of 10µs.
In order to fully settle with a 1µF bypass capacitor, the
source impedance must be lower than 1Ω. Source imped­ances greater than 1Ω result in offset and full-scale errors
due to the accumulation of charge settling errors over the
complete conversion cycle. Easy Drive technology auto­matically removes the differential component of this
error. The remaining common mode error is reduced to a
fixed offset as a function of the external resistor matching
seen at the plus and minus input of the ADC. In this
extreme case, 1k external resistors with 1% matching
result in a 3.5µV offset while the linearity and noise are
unaffected.

The signal path contains a 100 meter wire connected to
a low voltage source in a very noisy environment. Line
frequency noise is rejected by the on chip digital filter
and guaranteed by the high accuracy on chip oscillator.
High frequency noise is rejected by the external lowpass
filter formed by the input bypass capacitor and external
resistors.

30

2482f

PACKAGE DESCRIPTIO

LTC2482

U

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698)

0.675 ±0.05

3.50 ±0.05

1.65 ±0.05
(2 SIDES)2.15 ±0.05

PACKAGE
OUTLINE

0.25 ± 0.05

2.38 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

PIN 1

TOP MARK

(SEE NOTE 5)

0.200 REF

0.50
BSC

(2 SIDES)

3.00 ±0.10
(4 SIDES)

0.75 ±0.05

0.00 – 0.05

1.65 ± 0.10
(2 SIDES)

R = 0.115

TYP

2.38 ±0.10
(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

0.38 ± 0.10

106

15

0.25 ± 0.05

0.50 BSC

(DD10) DFN 0403

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

2482f

31

LTC2482

TYPICAL APPLICATIO

Figure 30. Differential Input Current Cancellation Enables Direct Digitization of Remote Sensors

REMOTE
SENSOR

U

100

METERS

1kΩ

1%

1µF

1kΩ

1%

5V

C8

C7

1µF

0.1µF

V

REF

CC

GND

SCK

SDO

CS

F

O

2482 F30

+

V

IN

LTC2482

–

V

IN

GND

5

INTEGRAL NONLINEARITY

4

THROUGH 100 METERS OF
WIRE AND A 1kΩ, 1µF RC

3

NETWORK

2

1

0

INL (LSB)

–1

–2

–3

–4

–5

0.5

0

1.5

1

INPUT VOLTAGE (V)

2

2.5

2482 F31

Figure 31. Input Current Cancellation Enables Precise DC
Measurements Under Extreme Conditions

Figure 32. Input Current Cancellation Enables Low Noise/
Low Offset Measurements under Extreme Conditions

12

RMS NOISE = 630nV
AVERAGE = –3.5µV
2500 CONSECUTIVE

10

READINGS

8

6

4

NUMBER OF READINGS (%)

2

0

–5.25

–4.65 –4.05

OUTPUT READING (µV)

–2.85 –1.65

–3.45 –2.25

2482 F32

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1050 Precision Chopper Stabilized Op Amp No External Components 5µV Offset, 1.6µV

LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max Initial Accuracy, 5ppm/°C Drift

LT1460 Micropower Series Reference 0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400 24-Bit, No Latency ∆Σ ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ∆Σ ADCs in MSOP 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency ∆Σ ADCs 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

with Differential Inputs

LTC2410 24-Bit, No Latency ∆Σ ADC with Differential Inputs 0.8µV
LTC2411/LTC2411-1 24-Bit, No Latency ∆Σ ADCs with Differential Inputs in MSOP 1.45µV

Noise, 2ppm INL

RMS

Noise, 4ppm INL,

RMS

Simultaneous 50Hz/60Hz Rejection (LTC2411-1)

LTC2413 24-Bit, No Latency ∆Σ ADC with Differential Inputs Simultaneous 50Hz/60Hz Rejection, 800nV
LTC2415/ 24-Bit, No Latency ∆Σ ADCs with 15Hz Output Rate Pin Compatible with the LTC2410

LTC2415-1
LTC2414/LTC2418 8-/16-Channel 24-Bit, No Latency ∆Σ ADCs 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200µA
LTC2420 20-Bit, No Latency ∆Σ ADC in SO-8 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2430/LTC2431 20-Bit, No Latency ∆Σ ADCs with Differential Inputs 2.8µV Noise, SSOP-16/MSOP Package
LTC2435/LTC2435-1 20-Bit, No Latency ∆Σ ADCs with 15Hz Output Rate 3ppm INL, Simultaneous 50Hz/60Hz Rejection
LTC2440 High Speed, Low Noise 24-Bit ∆Σ ADC 3.5kHz Output Rate, 200mV Noise, 24.6 ENOBs
LTC2480 16-Bit, No Latency ∆Σ ADC with PGA and Temperature Sensor Pin Compatible with LTC2482
LTC2484 16-Bit, No Latency ∆Σ ADC with Temperature Sensor Pin Compatible with LTC2482

LT/TP 0405 500 • PRINTED IN THE USA

© LINEAR TECHNOLOGY CORPORATION 2005

32

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

P-P

RMS

Noise

Noise

2482f