Datasheet LTC2480 Datasheet (LINEAR TECHNOLOGY)

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FEATURES

■

Easy Drive Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current

■

Directly Digitizes High Impedance Sensors with Full Accuracy

■

Programmable Gain from 1 to 256

■

Integrated Temperature Sensor

■

GND to VCC Input/Reference Common Mode Range

■

Programmable 50Hz, 60Hz or Simultaneous 50Hz/60Hz Rejection Mode

■

2ppm (0.25LSB) INL, No Missing Codes

■

1ppm Offset and 15ppm Full-Scale Error

■

Selectable 2x Speed Mode (15Hz Using Internal Oscillator)

■

No Latency: Digital Filter Settles in a Single Cycle

■

Single Supply 2.7V to 5.5V Operation

■

Internal Oscillator

■

Available in a Tiny (3mm × 3mm) 10-Lead DFN Package

APPLICATIO S

■

Direct Sensor Digitizer

■

Weight Scales

■

Direct Temperature Measurement

■

Strain Gauge Transducers

■

Instrumentation

■

Industrial Process Control

■

DVMs and Meters

LTC2480

16-Bit ∆Σ ADC with Easy Drive

Input Current Cancellation

DESCRIPTIO

The LTC®2480 combines a 16-bit plus sign No Latency ∆Σ analog-to-digital converter with patented Easy DriveTM technology. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances and input signals, with rail-to-rail input range to be directly digitized while maintaining exceptional DC accuracy.

The LTC2480 includes on-chip programmable gain, a temperature sensor and an oscillator. The LTC2480 can be configured to provide a programmable gain from 1 to 256 in 8 steps, measure an external signal or internal temperature sensor and reject line frequencies. 50Hz, 60Hz or simultaneous 50Hz/60Hz line frequency rejection can be selected as well as a 2x speed-up mode.

The LTC2480 allows a wide common mode input range (0V to V reference can be as low as 100mV or can be tied directly to VCC. The LTC2480 includes an on-chip trimmed oscillator eliminating the need for external crystals or oscillators. Absolute accuracy and low drift are automatically maintained through continuous, transparent, offset and full-scale calibration.

, LTC and LT are registered trademarks of Linear Technology Corporation. No Latency ∆Σ and Easy Drive are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent Pending.

) independent of the reference voltage. The

TYPICAL APPLICATIO

SENSE

10k

DIFF

= 0

1µF

REF

LTC2480

–

GND F

+FS Error vs R

VCC = 5V

= 5V

REF

= 3.75V

–

= 1.25V

= GND

1µF

SDI

SDO

4-WIRE

SCK

SPI INTERFACE

2480 TA01

= 25°C

–20

+FS ERROR (ppm)

–40

–60

–80

10 100 10k

SOURCE

CIN = 1µF

SOURCE

at IN+ and IN

(Ω)

–

100k

2480 TA04

2480f

LTC2480

PACKAGE/ORDER I FOR ATIO

WWWU

ABSOLUTE AXI U RATI GS

(Notes 1, 2)

Supply Voltage (VCC) to GND...................... – 0.3V to 6V

Analog Input Voltage to GND ....... –0.3V to (V

+ 0.3V)

Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V)

Digital Input Voltage to GND ........ –0.3V to (V

Digital Output Voltage to GND ..... –0.3V to (V

+ 0.3V)

Operating Temperature Range

LTC2480C ................................................... 0°C to 70°C

LTC2480I ................................................ –40°C to 85°C

Storage Temperature Range ................ –65°C to 125°C

SDI

REF

10-LEAD (3mm × 3mm) PLASTIC DFN

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

TOP VIEW

–

DD PACKAGE

= 125°C, θJA = 43°C/ W

JMAX

EXPOSED PAD (PIN 11) IS GND

MUST BE SOLDERED TO PCB

SCK

GND

SDO

ORDER PART

NUMBER

LTC2480CDD LTC2480IDD

DD PART MARKING*

LBJY

ELECTRICAL CHARACTERISTICS ( OR AL SPEED)

over the full operating temperature range, otherwise specifications are TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 0.1 ≤ V Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, V

2.7V ≤ VCC ≤ 5.5V, V Offset Error 2.5V ≤ V Offset Error Drift 2.5V ≤ V Positive Full-Scale Error 2.5V ≤ V Positive Full-Scale Error Drift 2.5V ≤ V

Negative Full-Scale Error 2.5V ≤ V Negative Full-Scale Error Drift 2.5V ≤ V

Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, V

5V ≤ VCC ≤ 5.5V, V

2.7V ≤ VCC ≤ 5.5V, V Output Noise 5V ≤ VCC ≤ 5.5V, V Internal PTAT Signal TA = 27°C 420 mV Internal PTAT Temperature Coefficient 1.4 mV/°C Programmable Gain ● 1 256

≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) ● 16 Bits

REF

= 5V, V

REF

= 2.5V, V

REF

≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14) ● 0.5 2.5 µV

REF

≤ VCC, GND ≤ IN+ = IN– ≤ V

REF

≤ VCC, IN+ = 0.75V

REF

≤ VCC, IN+ = 0.75V

REF

≤ VCC, IN+ = 0.75V

REF

≤ VCC, IN+ = 0.75V

REF

= 2.5V, V

REF

= 5V, V

REF

= 2.5V, V

REF

= 5V, GND ≤ IN– = IN+ ≤ VCC (Note 13) 0.6 µV

REF

= 2.5V (Note 6) ● 2 10 ppm of V

IN(CM)

= 1.25V (Note 6) 1 ppm of V

IN(CM)

, IN– = 0.25V

REF

, IN– = 0.25V

REF

, IN– = 0.25V

REF

, IN– = 0.25V

REF

= 1.25V 15 ppm of V

IN(CM)

= 2.5V ppm of V

IN(CM)

REF

= 1.25V ppm of V

The ● denotes specifications which apply

REF REF

10 nV/°C

● 25 ppm of V

0.1 ppm of

● 25 ppm of V

0.1 ppm of

REF

/°C

REF

/°C

REF

REF REF REF

RMS

2480f

LTC2480

ELECTRICAL CHARACTERISTICS (2x SPEED)

The ● denotes specifications which apply over the full

operating temperature range, otherwise specifications are TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 0.1 ≤ V Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, V

2.7V ≤ VCC ≤ 5.5V, V Offset Error 2.5V ≤ V Offset Error Drift 2.5V ≤ V Positive Full-Scale Error 2.5V ≤ V Positive Full-Scale Error Drift 2.5V ≤ V

Negative Full-Scale Error 2.5V ≤ V Negative Full-Scale Error Drift 2.5V ≤ V

Output Noise 5V ≤ VCC ≤ 5.5V, V

≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) ● 16 Bits

REF

= 5V, V

REF

= 2.5V, V

REF

≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14) ● 0.5 2 mV

REF

≤ VCC, GND ≤ IN+ = IN– ≤ V

REF

≤ VCC, IN+ = 0.75V

REF

≤ VCC, IN+ = 0.75V

REF

≤ VCC, IN+ = 0.75V

REF

≤ VCC, IN+ = 0.75V

REF

= 5V, GND ≤ IN– = IN+ ≤ VCC (Note 13) 0.84 µV

REF

= 2.5V (Note 6) ● 2 10 ppm of V

IN(CM)

= 1.25V (Note 6) 1

IN(CM)

, IN– = 0.25V

REF

, IN– = 0.25V

REF

, IN– = 0.25V

REF

, IN– = 0.25V

REF

100 nV/°C

● 25 ppm of V

0.1 ppm of

● 25 ppm of V

0.1 ppm of

REF

/°C

REF

/°C

REF

RMS

Programmable Gain (Note 15) ● 1 128

CO VERTER CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Common Mode Rejection DC 2.5V ≤ V Input Common Mode Rejection 2.5V ≤ V

50Hz ±2% Input Common Mode Rejection 2.5V ≤ V

60Hz ±2% Input Normal Mode Rejection 2.5V ≤ V

50Hz ±2% Input Normal Mode Rejection 2.5V ≤ V

60Hz ±2% Input Normal Mode Rejection 2.5V ≤ V

50Hz/60Hz ±2% Reference Common Mode 2.5V ≤ V

Rejection DC

Power Supply Rejection DC V

Power Supply Rejection, 50Hz ± 2% V

Power Supply Rejection, 60Hz ± 2% V

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

≤ VCC, GND ≤ IN– = IN+ ≤ V

REF

= 2.5V, IN– = IN+ = GND 120 dB

= 2.5V, IN– = IN+ = GND (Notes 7, 9) 120 dB

= 2.5V, IN– = IN+ = GND (Notes 8, 9) 120 dB

The ● denotes specifications which apply over the full operating

(Note 5) ● 140 dB

(Notes 5, 7) ● 110 120 dB

(Notes 5, 8) ● 110 120 dB

(Notes 5, 9) ● 87 dB

(Note 5) ● 120 140 dB

UUU

A ALOG I PUT AUD REFERE CE

temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

–

FS Full Scale of the Differential Input (IN+ – IN–) ● 0.5V

LSB Least Significant Bit of the Output Code ● FS/2

REF

Absolute/Common Mode IN+ Voltage GND – 0.3V VCC + 0.3V V

Absolute/Common Mode IN– Voltage GND – 0.3V VCC + 0.3V V

Input Differential Voltage Range (IN+ – IN–) ● –FS +FS V

Reference Voltage Range ● 0.1 V

The ● denotes specifications which apply over the full operating

/GAIN V

REF

2480f

LTC2480

UUU

A ALOG I PUT AUD REFERE CE

temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CS (IN+)IN

CS (IN–)IN

CS (V

REF

(IN+)IN+ DC Leakage Current Sleep Mode, IN+ = GND ● –10 1 10 nA

DC_LEAK

(IN–)IN– DC Leakage Current Sleep Mode, IN– = GND ● –10 1 10 nA

DC_LEAK

DC_LEAK (VREF

Sampling Capacitance 11 pF

–

Sampling Capacitance 11 pF

REF

DC Leakage Current Sleep Mode, V

REF

The ● denotes specifications which apply over the full operating

REF

= V

● –100 1 100 nA

DIGITAL I PUTS A D DIGITAL OUTPUTS

operating temperature range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

High Level Input Voltage 2.7V ≤ VCC ≤ 5.5V ● VCC – 0.5 V

, SDI

CS, F

Low Level Input Voltage 2.7V ≤ VCC ≤ 5.5V ● 0.5 V

, SDI

CS, F

High Level Input Voltage 2.7V ≤ VCC ≤ 5.5V (Note 10) ● VCC – 0.5 V SCK

Low Level Input Voltage 2.7V ≤ VCC ≤ 5.5V (Note 10) ● 0.5 V SCK

Digital Input Current 0V ≤ VIN ≤ V

, SDI

CS, F

Digital Input Current 0V ≤ VIN ≤ VCC (Note 10) ● –10 10 µA SCK

Digital Input Capacitance 10 pF CS, F

, SDI

Digital Input Capacitance 10 pF SCK

High Level Output Voltage IO = –800µA ● VCC – 0.5 V SDO

Low Level Output Voltage IO = 1.6mA ● 0.4 V SDO

High Level Output Voltage IO = –800µA ● VCC – 0.5 V SCK

Low Level Output Voltage IO = 1.6mA ● 0.4 V SCK

Hi-Z Output Leakage ● –10 10 µA SDO

= 25°C. (Note 3)

The ● denotes specifications which apply over the full

● –10 10 µA

POWER REQUIRE E TS

otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage ● 2.7 5.5 V

Supply Current Conversion Mode (Note 12) ● 160 250 µA

The ● denotes specifications which apply over the full operating temperature range,

Sleep Mode (Note 12)

● 12 µA

2480f

LTC2480

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

EOSC

HEO

LEO

CONV_1

CONV_2

ISCK

ESCK

LESCK

HESCK

DOUT_ISCK

DOUT_ESCK

KQMAX

KQMIN

External Oscillator Frequency Range (Note 15) ● 10 4000 kHz

External Oscillator High Period ● 0.125 100 µs

External Oscillator Low Period ● 0.125 100 µs

Conversion Time for 1x Speed Mode 50Hz Mode ● 157.2 160.3 163.5 ms

Conversion Time for 2x Speed Mode 50Hz Mode ● 78.7 80.3 81.9 ms

Internal SCK Frequency Internal Oscillator (Note 10) 38.4 kHz

Internal SCK Duty Cycle (Note 10) ● 45 55 %

External SCK Frequency Range (Note 10) ● 4000 kHz

External SCK Low Period (Note 10) ● 125 ns

External SCK High Period (Note 10) ● 125 ns

Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12) ● 0.61 0.625 0.64 ms

External SCK 24-Bit Data Output Time (Note 10) ● 24/f CS↓ to SDO Low ● 0 200 ns CS↑ to SDO High Z ● 0 200 ns CS↓ to SCK↓ Internal SCK Mode ● 0 200 ns CS↓ to SCK↑ External SCK Mode ● 50 ns SCK↓ to SDO Valid ● 200 ns SDO Hold After SCK↓ (Note 5) ● 15 ns SCK Set-Up Before CS↓ ● 50 ns SCK Hold After CS↓ ● 50 ns SDI Setup Before SCK↑ (Note 5) ● 100 ns SDI Hold After SCK↑ (Note 5) ● 100 ns

The ● denotes specifications which apply over the full operating temperature

60Hz Mode Simultaneous 50Hz/60Hz Mode External Oscillator

External Oscillator (Notes 10, 11) f

External Oscillator (Notes 10, 11)

● 131.0 133.6 136.3 ms

● 144.1 146.9 149.9 ms

● 41036/f

● 65.6 66.9 68.2 ms

● 72.2 73.6 75.1 ms

● 20556/f

● 192/f

(in kHz) ms

EOSC

(in kHz) ms

EOSC

/8 kHz

EOSC

(in kHz) ms

EOSC

(in kHz) ms

ESCK

Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired.

Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified.

= V

REFCM

/2, FS = 0.5V

REF

VIN = IN+ – IN–, V

IN(CM)

/GAIN

REF

= (IN+ + IN–)/2

Note 4: Use internal conversion clock or external conversion clock source with f

= 307.2kHz unless otherwise specified.

EOSC

Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.

Note 7: 50Hz mode (internal oscillator) or f

= 256kHz ±2% (external

EOSC

oscillator).

Note 8: 60Hz mode (internal oscillator) or f

= 307.2kHz ±2% (external

EOSC

oscillator). Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or f

EOSC

280kHz ±2% (external oscillator). Note 10: The SCK can be configured in external SCK mode or internal SCK

mode. In external SCK mode, the SCK pin is used as digital input and the driving clock is f output and the output clock signal during the data output is f

Note 11: The external oscillator is connected to the F oscillator frequency, f

. In internal SCK mode, the SCK pin is used as digital

ESCK

, is expressed in kHz.

EOSC

pin. The external

ISCK

Note 12: The converter uses the internal oscillator. Note 13: The output noise includes the contribution of the internal

calibration operations.

Note 14: Guaranteed by design and test correlation. Note 15: Refer to Applications Information section for performance vs

data rate graphs.

2480f

LTC2480

INPUT VOLTAGE (V)

–12

TUE (ppm OF V

REF

)

–4

–8

–0.75 –0.25 0.25 0.75

2480 G03

1.25–1.25

VCC = 2.7V V

REF

= 2.5V

IN(CM)

= 1.25V

= GND

85°C

25°C

–45°C

INPUT VOLTAGE (V)

–3

INL (ppm OF V

REF

)

–1

–2

–0.75 –0.25 0.25 0.75

2480 G06

1.25–1.25

VCC = 2.7V V

REF

= 2.5V

IN(CM)

= 1.25V

= GND

–45°C, 25°C, 90°C

TYPICAL PERFOR A CE CHARACTERISTICS

Integral Nonlinearity (VCC = 5V, V

VCC = 5V

= 5V

REF

)

REF

–1

INL (ppm OF V

–2

–3

= 2.5V

IN(CM)

= GND

–45°C

85°C

–1.5 –0.5 0.5 1.5

INPUT VOLTAGE (V)

Total Unadjusted Error (VCC = 5V, V

VCC = 5V

= 5V

REF

)

REF

IN(CM)

= 2.5V

= GND

REF

25°C

REF

= 5V)

25°C

85°C

–45°C

2480 G04

Integral Nonlinearity (VCC = 5V, V

VCC = 5V

= 2.5V

REF

)

REF

–1

INL (ppm OF V

–2

2.5–2–2.5 –1 0 1 2

–3

= 1.25V

IN(CM)

= GND

–0.75 –0.25 0.25 0.75

= 2.5V)

REF

–45°C, 25°C, 90°C

INPUT VOLTAGE (V)

1.25–1.25

2480 G05

Total Unadjusted Error (VCC = 5V, V

VCC = 5V V

V F

)

REF

REF IN(CM)

= GND

= 5V

= 1.25V

= 2.5V)

REF

85°C

25°C

–45°C

Integral Nonlinearity (VCC = 2.7V, V

= 2.5V)

REF

Total Unadjusted Error (VCC = 2.7V, V

= 2.5V)

REF

–4

TUE (ppm OF V

–8

–12

–1.5 –0.5 0.5 1.5

INPUT VOLTAGE (V)

2.5–2–2.5 –1 0 1 2

2480 G01

Noise Histogram (6.8sps) Long-Term ADC Readings

10,000 CONSECUTIVE READINGS

= 5V

REF

= 0V

GAIN = 256

= 25°C

NUMBER OF READINGS (%)

–3

–1.8 –0.6

–2.4 1.2

–1.2 0 1.8

OUTPUT READING (µV)

RMS = 0.60µV

AVERAGE = –0.69µV

0.6

2480 G07

–4

TUE (ppm OF V

–8

–12

–0.75 –0.25 0.25 0.75

INPUT VOLTAGE (V)

Noise Histogram (7.5sps)

10,000 CONSECUTIVE READINGS

= 2.7V

= 2.5V

REF

= 0V

GAIN = 256

= 25°C

NUMBER OF READINGS (%)

–3

–1.8 –0.6

–2.4 1.2

–1.2 0 1.8

OUTPUT READING (µV)

2480 G02

RMS = 0.59µV

AVERAGE = –0.19µV

0.6

2480 G08

1.25–1.25

–1

ADC READING (µV)

–2

–3

–4

–5

VCC = 5V, V GAIN = 256, T

= 5V, VIN = 0V, V

REF

= 25°C, RMS NOISE = 0.60µV

TIME (HOURS)

30 40

IN(CM)

= 2.5V

2480 G09

2480f

REF

(V)

–0.3

OFFSET ERROR (ppm OF V

REF

)

–0.2

–0.1

0.1

0.2

0.3

1234

2480 G18

VCC = 5V REF

–

= GND

= 0V

IN(CM)

= GND GAIN = 256 T

= 25°C

TYPICAL PERFOR A CE CHARACTERISTICS

RMS Noise vs Input Differential Voltage RMS Noise vs V

)

REF

1.0

0.9

0.8

VCC = 5V

= 5V

REF

GAIN = 256

= 2.5V

IN(CM)

= 25°C

1.0

0.9

0.8

VCC = 5V

= 5V

REF

= 0V

IN(CM)

GAIN = 256

= 25°C

= GND

IN(CM)

LTC2480

RMS Noise vs Temperature (TA)

1.0 VCC = 5V

= 5V

REF

0.9

= 0V

= GND

IN(CM)

GAIN = 256

0.8

0.7

0.6

RMS NOISE (ppm OF V

0.5

0.4 –1.5 –0.5 0.5 1.5

INPUT DIFFERENTIAL VOLTAGE (V)

RMS Noise vs V

1.0

= 2.5V

REF

= 0V

= GND

0.9

IN(CM)

GAIN = 256

= 25°C

0.8

0.7

RMS NOISE (µV)

0.6

0.5

0.4

2.7

3.1 3.5

4.3 5.1 5.5

3.9 4.7 VCC (V)

2480 G10

2480 G13

0.7

RMS NOISE (µV)

0.6

0.5

2.5–2–2.5 –1 0 1 2

0.4 –1

RMS Noise vs V

1.0

VCC = 5V

= 0V

0.9

IN(CM)

GAIN = 256

= 25°C

0.8

0.7

RMS NOISE (µV)

0.6

0.5

0.4

356

(V)

IN(CM)

2480 G11

REF

= GND

1234

(V)

REF

2480 G14

0.7

RMS NOISE (µV)

0.6

0.5

0.4 –45

–30 –15 15

0 304560

TEMPERATURE (°C)

Offset Error vs V

0.3 VCC = 5V

= 5V

REF

)

REF

–0.1

OFFSET ERROR (ppm OF V

–0.3

0.2

0.1

–0.2

V GAIN = 256 T

–1

= 0V

= 25°C

75 90

2480 G12

IN(CM)

356

(V)

IN(CM)

2480 G15

Offset Error vs Temperature

0.3 VCC = 5V

0.2

)

REF

0.1

–0.1

OFFSET ERROR (ppm OF V

–0.2

–0.3

–45

= 5V

REF

= 0V

= GND

IN(CM)

= GND

–30 0

–15

30 90

TEMPERATURE (°C)

Offset Error vs V

0.3 REF+ = 2.5V

–

= GND

REF

)

REF

OFFSET ERROR (ppm OF V

2480 G16

0.2

0.1

–0.1

–0.2

–0.3

V V GAIN = 256 T

2.7

= 0V

IN IN(CM)

= 25°C

3.1 3.5

= GND

4.3 5.1 5.5

3.9 4.7 VCC (V)

2480 G17

Offset Error vs V

REF

2480f

LTC2480

TEMPERATURE (°C)

–45 –30

300

FREQUENCY (kHz)

304

310

–15

2480 G26

302

308

306

150

60 75

VCC = 4.1V V

REF

= 2.5V

= 0V

IN(CM)

= GND

TEMPERATURE (°C)

–45

SLEEP MODE CURRENT (µA)

0.2

0.6

0.8

1.0

2.0

1.4

–15

30 90

2480 G32

0.4

1.6

1.8

1.2

–30 0

VCC = 5V

VCC = 2.7V

FO = GND CS = V

SCK = NC SDO = NC SDI = GND

TYPICAL PERFOR A CE CHARACTERISTICS

Temperature Sensor vs Temperature

0.40 VCC = 5V

= 1.4V

REF

= GND

0.35

(V)

REF

0.30

PTAT

0.25

0.20

–60

30090–30 60

TEMPERATURE (°C)

On-Chip Oscillator Frequency vs V

310

308

306

REF

IN(CM)

= 2.5V

= 0V

= GND

2480 G24

= GND

120

Temperature Sensor Error vs Temperature

VCC = 5V

= GND

–1

–2

TEMPERATURE ERROR (°C)

–3

–4

–5

–30

–60

TEMPERATURE (°C)

PSRR vs Frequency at V

VCC = 4.1V DC

= 2.5V

REF

–20

= GND

–

= GND

–40

= GND

= 25°C

–60

On-Chip Oscillator Frequency vs Temperature

= 1.4V

REF

120

2480 G25

PSRR vs Frequency at V

VCC = 4.1V DC ±1.4V

= 2.5V

REF

–20

= GND

–

= GND

–40

= GND

= 25°C

–60

FREQUENCY (kHz)

REJECTION (dB)

–100

–120

–140

304

302

300

2.5

3.5 4.0 4.5

3.0 VCC (V)

PSRR vs Frequency at V

VCC = 4.1V DC ±0.7V

= 2.5V

REF

–20

= GND

–

= GND

–40

= GND

= 25°C

–60

–80

30600

30650 30700 30800

FREQUENCY AT VCC (Hz)

30750

5.0 5.5

2480 G27

2480 G30

–80

REJECTION (dB)

–100

–120

–140

10 100

FREQUENCY AT VCC (Hz)

Conversion Current vs Temperature

200

FO = GND CS = GND SCK = NC

180

SDO = NC SDI = GND

160

140

CONVERSION CURRENT (µA)

120

100

–30 0

–15

–45

10k 1M

1k 100k

VCC = 5V

VCC = 2.7V

30 90

TEMPERATURE (°C)

–80

REJECTION (dB)

–100

–120

2480 G28

–140

100

120 160

140

FREQUENCY AT VCC (Hz)

180

220200

2480 G29

Sleep Mode Current vs Temperature

2480 G31

2480f

INPUT VOLTAGE (V)

–3

INL (ppm OF V

REF

)

–1

–2

–0.75 –0.25 0.25 0.75

2480 G35

1.25–1.25

VCC = 5V V

REF

= 2.5V

IN(CM)

= 1.25V

= GND

90°C

–45°C, 25°C

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2480

Conversion Current vs Output Data Rate

500

= V

REF

IN+ = GND

450

–

= GND

IN SCK = NC

400

SDO = NC SDI = GND

350

CS GND

= EXT OSC

300

= 25°C

250

SUPPLY CURRENT (µA)

200

150

100

20 40 60 1007010 30 50 90

OUTPUT DATA RATE (READINGS/SEC)

VCC = 5V

Integral Nonlinearity (2x Speed Mode; VCC = 2.7V, V

VCC = 2.7V

= 2.5V

REF

)

REF

–1

INL (ppm OF V

–2

–3

= 1.25V

IN(CM)

= GND

90°C

–45°C, 25°C

–0.75 –0.25 0.25 0.75

INPUT VOLTAGE (V)

REF

VCC = 3V

= 2.5V)

2480 G33

2480 G36

Integral Nonlinearity (2x Speed Mode; V

)

REF

–1

INL (ppm OF V

–2

–3

= 5V, V

–1.5 –0.5 0.5 1.5

INPUT VOLTAGE (V)

= 5V)

REF

VCC = 5V V

REF

IN(CM)

25°C, 90°C

–45°C

= 5V

= GND

= 2.5V

2.5–2–2.5 –1 0 1 2

2480 G34

Noise Histogram (2x Speed Mode)

10,000 CONSECUTIVE READINGS

= 5V

REF

= 0V

GAIN = 256

= 25°C

NUMBER OF READINGS (%)

1.25–1.25

179

181.4 183.8 188.6 OUTPUT READING (µV)

RMS = 0.86µV

AVERAGE = 0.184mV

186.2

2480 G37

Integral Nonlinearity (2x Speed Mode; V

RMS Noise vs V

= 5V, V

REF

(2x Speed Mode)

1.0

0.8

0.6

0.4

RMS NOISE (µV)

VCC = 5V

= 0V

0.2

IN(CM)

= GND = 25°C

= GND

(V)

REF

= 2.5V)

2480 G38

200

198

196

194

192

190

188

186

OFFSET ERROR (µV)

184

182

180

–1

Offset Error vs V (2x Speed Mode)

VCC = 5V

= 5V

REF

= 0V

= GND

= 25°C

IN(CM)

(V)

Offset Error vs Temperature (2x Speed Mode)

240

VCC = 5V

= 5V

REF

230

= 0V

= GND

IN(CM)

220

= GND

210

200

190

OFFSET ERROR (µV)

180

170

2480 G39

160

–30 90

–45

–15

TEMPERATURE (°C)

2480 G40

2480f

LTC2480

FREQUENCY AT VCC (Hz)

–20

–40

–60

–80

–100

–120

–140

1k 100k

2480 G43

10 100

10k 1M

REJECTION (dB)

VCC = 4.1V DC REF

= 2.5V

REF

–

= GND

–

= GND

= 25°C

TYPICAL PERFOR A CE CHARACTERISTICS

Offset Error vs V (2x Speed Mode)

250

= 2.5V

REF

= 0V

IN(CM)

200

= GND

= 25°C

150

100

OFFSET ERROR (µV)

2 2.5

= GND

3.5 VCC (V)

4.5

2480 G41

PSRR vs Frequency at V (2x Speed Mode)

VCC = 4.1V DC ±1.4V

= 2.5V

REF

–20

–

= GND

REF

= GND

–

–40

= GND

= 25°C

–60

5.5

Offset Error vs V (2x Speed Mode)

240

VCC = 5V

= 0V

230

IN(CM)

= GND

220

= 25°C

210

200

190

OFFSET ERROR (µV)

180

170

160

REF

= GND

12 4

(V)

REF

2480 G42

PSRR vs Frequency at V (2x Speed Mode)

VCC = 4.1V DC ±0.7V REF

–20

REF IN

–40

IN F

–60

= 2.5V

–

= GND

–

= GND = GND = 25°C

PSRR vs Frequency at V (2x Speed Mode)

PI FU CTIO S

SDI (Pin 1): Serial Data Input. This pin is used to select the GAIN, line frequency rejection, input, temperature sensor and 2x speed mode. Data is shifted into the SDI pin on the rising edge of serial clock (SCK).

VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 8) with a 1µF tantalum capacitor in parallel with 0.1µF ceramic capacitor as close to the part as possible.

pin can have any value between 0.1V and VCC. The negative reference input is GND (Pin 8).

–80

RREJECTION (dB)

–100

–120

–140

(Pin 3): Positive Reference Input. The voltage on this

REF

FREQUENCY AT VCC (Hz)

100

120 160

140

180

220200

2480 G44

–80

REJECTION (dB)

–100

–120

–140

30600

30650 30700 30800

FREQUENCY AT VCC (Hz)

30750

2480 G45

IN+ (Pin 4), IN– (Pin 5): Differential Analog Inputs. The voltage on these pins can have any value between GND –

0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ – IN–) extends from –0.5 • V

/GAIN to 0.5 • V

REF

/GAIN. Outside this input range the

REF

converter produces unique overrange and underrange output codes.

CS (Pin 6): Active LOW Chip Select. A LOW on this pin enables the digital input/output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long

2480f

LTC2480

PI FU CTIO S

as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion.

SDO (Pin 7): Three-State Digital Output. During the Data Output period, this pin is used as the serial data output. When the chip select CS is HIGH (CS = V is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW.

GND (Pin 8): Ground. Shared pin for analog ground, digital ground and reference ground. Should be connected directly to a ground plane through a minimum impedance.

SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as the digital output for the internal serial interface clock during the Data

), the SDO pin

Input/Output period. In External Serial Clock Operation mode, SCK is used as the digital input for the external serial interface clock during the Data Output period. A weak internal pull-up is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS.

(Pin 10): Frequency Control Pin. Digital input that

controls the conversion clock. When FO is connected to GND the converter uses its internal oscillator running at

307.2kHz. The conversion clock may also be overridden by driving the FO pin with an external clock in order to change the output rate or the digital filter rejection null.

Exposed Pad (Pin 11): This pin is ground and should be soldered to the PCB ground plane. For prototyping purposes, this pin may remain floating.

FU CTIO AL BLOCK DIAGRA

REF

–

TEMP

SENSOR

MUX

TEST CIRCUITS

SDO

1.69k

LOAD

= 20pF

–

REF

AUTOCALIBRATION

GND

REF

3RD ORDER

∆Σ ADC

(1-256)

–

AND CONTROL

GAIN

SDI

SCK

SERIAL

INTERFACE

INTERNAL

OSCILLATOR

SDO

SD0

2480 FD

1.69k

= 20pF

LOAD

Hi-Z TO V VOL TO V VOH TO Hi-Z

2480 TA02

Hi-Z TO V VOH TO V VOL TO Hi-Z

2480 TA03

2480f

LTC2480

WUW

TI I G DIAGRA S

Timing Diagram Using Internal SCK

SDO

SCK

SDI

SDO

SCK

SDI

SLEEP

KQMIN

KQMAX

2480 TD1

CONVERSIONDATA IN/OUT

Timing Diagram Using External SCK

SLEEP

KQMIN

KQMAX

2480 TD2

CONVERSIONDATA IN/OUT

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APPLICATIO S I FOR ATIO

CONVERTER OPERATION

Converter Operation Cycle

The LTC2480 is a low power, delta-sigma analog-todigital converter with an easy to use 4-wire serial interface and automatic differential input current cancellation. Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 1). The 4-wire interface consists of serial data output (SDO), serial clock (SCK), chip select (CS) and serial data input (SDI).

Initially, the LTC2480 performs a conversion. Once the conversion is complete, the device enters the sleep state.

CONVERT

SLEEP

FALSE

CS = LOW

AND

SCK

TRUE

DATA OUTPUT

CONFIGURATION INPUT

2480 F01

Figure 1. LTC2480 State Transition Diagram

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APPLICATIO S I FOR ATIO

LTC2480

While in this sleep state, power consumption is reduced by two orders of magnitude. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state.

Once CS is pulled LOW, the device exits the low power mode and enters the data output state. If CS is pulled HIGH before the first rising edge of SCK, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. If CS remains LOW after the first rising edge of SCK, the device begins outputting the conversion result. Taking CS high at this point will terminate the data input and output state and start a new conversion. The conversion result is shifted out of the device through the serial data output pin (SDO) on the falling edge of the serial clock (SCK) (see Figure 2). The LTC2480 includes a serial data input pin (SDI) in which data is latched by the device on the rising edge of SCK (Figure 2). The bit stream applied to this pin can be used to select various features of the LTC2480, including an on-chip temperature sensor, programmable GAIN, line frequency rejection and output data rate. Alternatively, this pin may be tied to ground and the part will perform conversions in a default state. In the default state (SDI grounded) the device simply performs conversions on the user applied input with a GAIN of 1 and simultaneous rejection of 50Hz and 60Hz line frequencies.

Through timing control of the CS and SCK pins, the LTC2480 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section.

Easy Drive Input Current Cancellation

The LTC2480 combines a high precision delta-sigma ADC with an automatic differential input current cancellation front end. A proprietary front-end passive sampling

network transparently removes the differential input current. This enables external RC networks and high impedance sensors to directly interface to the LTC2480 without external amplifiers. The remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see Automatic Input Current Cancellation section). This unique architecture does not require on-chip buffers enabling input signals to swing all the way to ground and up to VCC. Furthermore, the cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full scale + offset + linearity) is maintained even with external RC networks.

Accessing the Special Features of the LTC2480

The LTC2480 combines a high resolution, low noise ∆Σ analog-to-digital converter with an on-chip selectable temperature sensor, programmable gain, programmable digital filter and output rate control. These special features are selected through a single 8-bit serial input word during the data input/output cycle (see Figure 2).

The LTC2480 powers up in a default mode commonly used for most measurements. The device will remain in this mode as long as the serial data input (SDI) is low. In this default mode, the measured input is external, the GAIN is 1, the digital filter simultaneously rejects 50Hz and 60Hz line frequency noise, and the speed mode is 1x (offset automatically, continuously calibrated).

A simple serial interface grants access to any or all special functions contained within the LTC2480. In order to change the mode of operation, an enable bit (EN) followed by up to 7 bits of data are shifted into the device (see Table 1). The first 3 bits (GS2, GS1, GS0) control the GAIN of the converter from 1 to 256. The 4th bit (IM) is used to select the internal temperature sensor as the conversion input, while the 5th and 6th bits (FA, FB) combine to determine the line frequency rejection mode. The 7th bit (SPD) is used to double the output rate by disabling the offset auto calibration.

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LTC2480

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APPLICATIO S I FOR ATIO

BIT 23

SDO

Hi-Z

SCK

SDI

SLEEP DATA INPUT/OUTPUT

EOC

EN GS2 GS1 GS0 IM FBFA SPD DON’T CARE

Table 1. Selecting Special Modes

Gain

EN GS2 GS1

1 1 1 1 1 1

X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

Any Gain

X X X X

GS0

X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

X X X X

BIT 21

BIT 20 BIT 19 BIT 18

SIGDMY

MSB B16

CONVERSION RESULT

Figure 2. Input/Output Data Timing

Rejection

Mode

IM FA FB SPD Comments

XX X

0 0 0 0 0 0 0

Any

Rejection

Mode

0 0 0 0 0 0 0

0 1

Speed

0 1 0 1 0 1

Keep Previous Mode External Input, Gain = 1, Autocalibration

External Input, Gain = 4, Autocalibration

External Input, Gain = 8, Autocalibration

External Input, Gain = 16, Autocalibration

External Input, Gain = 32, Autocalibration

External Input, Gain = 64, Autocalibration

External Input, Gain = 128, Autocalibration

External Input, Gain = 256, Autocalibration

External Input, Gain = 1, 2x Speed

External Input, Gain = 2, 2x Speed

External Input, Gain = 4, 2x Speed

External Input, Gain = 8, 2x Speed

External Input, Gain = 16, 2x Speed

External Input, Gain = 32, 2x Speed

External Input, Gain = 64, 2x Speed

External Input, Gain = 128, 2x Speed

External Input, Simultaneous 50Hz/60Hz Rejection External Input, 50Hz Rejection

Any

External Input, 60Hz Rejection Reserved, Do Not Use Temperature Input, 50Hz/60Hz Rejection, Gain = 1, Autocalibration

Temperature Input, 50Hz Rejection, Gain = 1, Autocalibration

Temperature Input, 60Hz Rejection, Gain = 1, Autocalibration

Reserved, Do Not Use

2480 TBL1

BIT 4

LSB

BIT 3

BIT 2BIT 22

GS2

CONFIGURATION BITS

BIT 1 BIT 0

GS0GS1

CONVERSION

2480 F02

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LTC2480

Table 2a. The LTC2480 Performance vs GAIN in Normal Speed Mode (VCC = 5V, V

GAIN 1 4 8 16 32 64 128 256 UNIT

Input Span ±2.5 ±0.625 ±0.312 ±0.156 ±78m ±39m ±19.5m ±9.76m V

LSB 38.1 9.54 4.77 2.38 1.19 0.596 0.298 0.149 µV

Noise Free Resolution* 65536 65536 65536 65536 65536 65536 32768 16384 Counts

Gain Error 55555558ppm of FS

Offset Error 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 µV

Table 2b. The LTC2480 Performance vs GAIN in 2x Speed Mode (VCC = 5V, V

GAIN 1248163264128 UNIT

Input Span ±2.5 ±1.25 ±0.625 ±0.312 ±0.156 ±78m ±39m ±19.5m V

LSB 38.1 19.1 9.54 4.77 2.38 1.19 0.596 0.298 µV

Noise Free Resolution* 65536 65536 65536 65536 65536 65536 45875 22937 Counts

Gain Error 55555555ppm of FS

Offset Error 200 200 200 200 200 200 200 200 µV

*The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger.

GAIN (GS2, GS1, GS0)

The input referred gain of the LTC2480 is adjustable from 1 to 256. With a gain of 1, the differential input range is ±V

/2 and the common mode input range is rail-to-rail.

REF

As the GAIN is increased, the differential input range is reduced to ±V

/2 • GAIN but the common mode input

REF

range remains rail-to-rail. As the differential gain is increased, low level voltages are digitized with greater

REF

Rejection Mode (FA, FB)

The LTC2480 includes a high accuracy on-chip oscillator with no required external components. Coupled with a 4th order digital lowpass filter, the LTC2480 rejects line frequency noise. In the default mode, the LTC2480 simultaneously rejects 50Hz and 60Hz by at least 87dB. The LTC2480 can also be configured to selectively reject 50Hz or 60Hz to better than 110dB.

REF

= 5V)

resolution. At a gain of 256, the LTC2480 digitizes an input signal range of ±9.76mV with over 16,000 counts.

Speed Mode (SPD)

Temperature Sensor (IM)

The LTC2480 includes an on-chip temperature sensor. The temperature sensor is selected by setting IM = 1 in the serial input data stream. Conversions are performed directly on the temperature sensor by the converter. While operating in this mode, the device behaves as a temperature to bits converter. The digital reading is proportional to the absolute temperature of the device. This feature allows the converter to linearize temperature sensors or continuously remove temperature effects from external sensors. Several applications leveraging this feature are presented in more detail in the applications section. While operating in this mode, the gain is set to 1 and the speed is set to normal independent of the control bits (GS2, GS1, GS0 and SPD).

The LTC2480 continuously performs offset calibrations. Every conversion cycle, two conversions are automatically performed (default) and the results combined. This result is free from offset and drift. In applications where the offset is not critical, the autocalibration feature can be disabled with the benefit of twice the output rate.

Linearity, full-scale accuracy and full-scale drift are identical for both 2x and 1x speed modes. In both the 1x and 2x speed there is no latency. This enables input steps or multiplexer channel changes to settle in a single conversion cycle easing system overhead and increasing the effective conversion rate.

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APPLICATIO S I FOR ATIO

Output Data Format

The LTC2480 serial output data stream is 24 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 17 bits are the conversion result, MSB first. The remaining 4 bits indicate the configuration state associated with the current conversion result. The third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below –FS) or an overrange condition (the differential input voltage is above +FS).

In applications where the processor generates 32 clock cycles, or to remain compatible with higher resolution converters, the LTC2480’s digital interface will ignore extra clock edges seen during the next conversion period after the 24th and output “1” for the extra clock cycles. Furthermore, CS may be pulled high prior to outputting all 24 bits, aborting the data out transfer and initiating a new conversion.

Bit 23 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete.

Bit 22 (second output bit) is a dummy bit (DMY) and is always LOW.

Bit 21 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW.

Bit 20 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 21 also provides the underrange or overrange indication. If both Bit 21 and Bit 20 are HIGH, the differential input voltage is above +FS. If both Bit 21 and Bit 20 are LOW, the differential input voltage is below –FS.

The function of these bits is summarized in Table 3.

Table 3. LTC2480 Status Bits

BIT 23 BIT 22 BIT 21 BIT 20

INPUT RANGE EOC DMY SIG MSB

VIN ≥ 0.5 • V 0V ≤ VIN < 0.5 • V

–0.5 • V

VIN < – 0.5 • V

REF

≤ VIN < 0V 0001

REF

0011

0010

0000

Bits 20-4 are the 16-bit plus sign conversion result MSB first.

Bits 3-0 are the corresponding configuration bits for the present conversion result. Bits 3-1 are the gain set bits and bit 0 is IM (see Figure 2).

Data is shifted out of the SDO pin under control of the serial clock (SCK) (see Figure 2). Whenever CS is HIGH, SDO remains high impedance and any externally generated SCK clock pulses are ignored by the internal data out shift register.

In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes in real time

Table 4. LTC2480 Output Data Format

DIFFERENTIAL INPUT VOLTAGE BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 … BIT 4

* EOC DMY SIG MSB

VIN* ≥ FS** 0 0110 0 0…0 FS** – 1LSB 0 0101 1 1…1

0.5 • FS** 0 0101 0 0…0

0.5 • FS** – 1LSB 0 0100 1 1…1 0 00100 0 0…0 –1LSB 0 0011 1 1…1 –0.5 • FS** 0 0011 0 0…0 –0.5 • FS** – 1LSB 0 0010 1 1…1 –FS** 0 0010 0 0…0 VIN* < –FS** 0 0001 1 1…1

*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • V

REF

/GAIN.

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LTC2480

from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 23 (EOC) can be captured on the first rising edge of SCK. Bit 22 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 23rd SCK and may be latched on the rising edge of the 24th SCK pulse. On the falling edge of the 24th SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 23) for the next conversion cycle. Table 4 summarizes the output data format.

As long as the voltage on the IN within the –0.3V to (V

and IN– pins is maintained

+ 0.3V) absolute maximum

operating range, a conversion result is generated for any differential input voltage VIN from –FS = –0.5 • V to +FS = 0.5 • V

/GAIN. For differential input voltages

REF

/GAIN

greater than +FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages below –FS, the conversion result is clamped to the value corresponding to –FS – 1LSB.

Conversion Clock

A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a SINC or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz or 60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter system clock. The LTC2480 incorporates a highly accurate on-chip oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators.

Frequency Rejection Selection (FO)

The LTC2480 internal oscillator provides better than 110dB normal mode rejection at the line frequency and all its harmonics (up to the 255th) for 50Hz ±2% or 60Hz ±2%, or better than 87dB normal mode rejection from 48Hz to

62.4Hz. The rejection mode is selected by writing to the on-chip configuration register and the default mode at POR is simultaneous 50Hz/60Hz rejection.

When a fundamental rejection frequency different from 50Hz or 60Hz is required or when the converter must be

–80

–85

–90

–95

–100

–105

–110

–115

–120

–125

NORMAL MODE REJECTION (dB)

–130

–135

–140

–12 –8 –4 0 4 8 12

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DEVIATION FROM NOTCH FREQUENCY f

Figure 3. LTC2480 Normal Mode Rejection When Using an External Oscillator

EOSC

/5120(%)

2480 F03

synchronized with an outside source, the LTC2480 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency f

of the external signal must be at least

EOSC

10kHz to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods t

HEO

and t

LEO

are observed.

While operating with an external conversion clock of a frequency f normal mode rejection in a frequency range of f

, the LTC2480 provides better than 110dB

EOSC

/5120 ± 4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from f

EOSC

/5120 is shown in Figure 3.

Whenever an external clock is not present at the FO pin, the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. The LTC2480 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. If the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. If the change occurs during the data output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid.

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Table 5. LTC2480 State Duration

STATE OPERATING MODE DURATION

CONVERT Internal Oscillator 60Hz Rejection 133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode

67ms, Output Data Rate ≤ 15 Readings/s for 2x Speed Mode

50Hz Rejection 160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode

80ms, Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode

50Hz/60Hz Rejection 147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode

73.6ms, Output Data Rate ≤ 13.6 Readings/s for 2x Speed Mode

External Oscillator FO = External Oscillator 41036/f

with Frequency f

/5120 Rejection) 20556/f

EOSC

SLEEP As Long As CS = HIGH, After a Conversion is Complete

DATA OUTPUT Internal Serial Clock FO = LOW/HIGH As Long As CS = LOW But Not Longer Than 0.62ms

(Internal Oscillator) (24 SCK Cycles)

FO = External Oscillator with As Long As CS = LOW But Not Longer Than 192/f Frequency f

External Serial Clock with As Long As CS = LOW But Not Longer Than 24/f Frequency f

kHz (24 SCK Cycles)

SCK

EOSC

kHz 1x Speed Mode

EOSC

2x Speed Mode

kHz (24 SCK Cycles)

s, Output Data Rate ≤ f

EOSC

s, Output Data Rate ≤ f

EOSC

/41036 Readings/s for

EOSC

/20556 Readings/s for

EOSC

SCK

Table 5 summarizes the duration of each state and the achievable output data rate as a function of FO.

Ease of Use

The

LTC2480

data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy.

The LTC2480 performs offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift.

Power-Up Sequence

The LTC2480 automatically enters an internal reset state when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection.

When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR)

signal with a duration of approximately 4ms. The POR signal clears all internal registers. Following the POR signal, the LTC2480 starts a normal conversion cycle and follows the succession of states described in Figure 1. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval.

On-Chip Temperature Sensor

The LTC2480 contains an on-chip PTAT (proportional to absolute temperature) signal that can be used as a temperature sensor. The internal PTAT has a typical value of 420mV at 27°C and is proportional to the absolute temperature value with a temperature coefficient of 420/(27 + 273) = 1.40mV/°C (SLOPE), as shown in Figure 4. The internal PTAT signal is used in a single-ended mode referenced to device ground internally. The GAIN is automatically set to one (independent of the values of GS0, GS1, GS2) in order to preserve the PTAT property at the ADC output code and avoid an out of range error. The 1x speed mode with automatic offset calibration is automatically selected for the internal PTAT signal measurement as well.

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APPLICATIO S I FOR ATIO

LTC2480

When using the internal temperature sensor, if the output code is normalized to R

SDO

= V

PTAT/VREF

, the temperature

is calculated using the following formula:

•

SDO REF

SLOPE

in Kelvin

and

•

SDO REF

=°

SLOPE

–

in C273

where SLOPE is nominally 1.4mV/°C. Since the PTAT signal can have an initial value variation

which results in errors in SLOPE, to achieve better temperature measurements, a one-time calibration is needed to adjust the SLOPE value. The converter output of the PTAT signal, R0

, is measured at a known temperature

SDO

T0 (in °C) and the SLOPE is calculated as:

SLOPE

•

SDO REF

+00 273

This calibrated SLOPE can be used to calculate the temperature.

If the same V temperature measurement, the actual value of the V

source is used during calibration and

REF

is not needed to measure the temperature as shown in the calculation below:

•

SDO REF

SLOPE

SDO

600

500

(mV)

400

PTAT

300

200

–60

Figure 4. Internal PTAT Signal vs Temperature

–

273

•–

0 273 273

()

VCC = 5V IM = 1

= GND

SLOPE = 1.40mV/°C

30090–30 60

TEMPERATURE (°C)

120

2480 F04

Reference Voltage Range

The LTC2480 external reference voltage range is 0.1V to

. The converter output noise is determined by the

thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. Since the transition noise (600nV) is much less than the quantization noise (V

/217), a decrease in the refer-

REF

ence voltage will increase the converter resolution. A reduced reference voltage will also improve the converter performance when operated with an external conversion clock (external FO signal) at substantially higher output data rates (see the Output Data Rate section). V

REF

must

be ≥1.1V to use the internal temperature sensor.

The negative reference input to the converter is internally tied to GND. GND (Pin 8) should be connected to a ground plane through as short a trace as possible to minimize voltage drop. The LTC2480 has an average operational current of 160µA and for 0.1Ω parasitic resistance, the voltage drop of 16µV causes a gain error of 3.2ppm for V

= 5V.

REF

Input Voltage Range

The analog input is truly differential with an absolute/ common mode range for the IN+ and IN– input pins extending from GND – 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2480 converts the bipolar differential input signal, VIN = IN+ – IN–, from –FS to +FS where FS = 0.5 • V

/GAIN. Outside this range, the

REF

converter indicates the overrange or the underrange condition using distinct output codes. Since the differential input current cancellation does not rely on an on-chip buffer, current cancellation as well as DC performance is maintained rail-to-rail.

nput signals applied to IN+ and IN– pins may extend by 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the IN+ and IN– pins without affecting the performance of the devices. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/Reference Current sections. In addition, series resistors will introduce a

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APPLICATIO S I FOR ATIO

temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if V has a very strong temperature dependency.

SERIAL INTERFACE TIMING MODES

The LTC2480’s 4-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 3- or 4-wire I/O, single cycle or continuous conversion. The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW or FO = HIGH) or an external oscillator connected to the FO pin. Refer to Table 6 for a summary.

External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 5.

The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge.

The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Independent of CS, the device automatically enters the low power sleep state once the conversion is complete.

= 5V. This error

REF

When the device is in the sleep state, its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while CS is LOW. The input data is then shifted in via the SDI pin on the rising edge of SCK (including the first rising edge) and the output data is shifted out of the SDO pin on each falling edge of SCK external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. On the 24th falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is in progress. applications where the processor generates 32 clock cycles, or to remain compatible with higher resolution converters, the LTC2480’s digital interface will ignore extra clock edges seen during the next conversion period after the 24th and outputs “1” for the extra clock cycles.

At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. As described above, CS may be pulled LOW at any time in order to monitor the conversion status.

Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first rising edge and the 24th falling edge of SCK (see Figure 6). On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. If the device has not finished loading the last input bit SPD of SDI by the time CS is pulled HIGH, the SDI information is discarded and the previous configuration is kept. This is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion.

. This enables

Table 6. LTC2480 Interface Timing Modes

CONVERSION DATA CONNECTION

SCK CYCLE OUTPUT and

CONFIGURATION SOURCE CONTROL CONTROL WAVEFORMS

External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 5, 6

External SCK, 3-Wire I/O External SCK SCK Figure 7 Internal SCK, Single Cycle Conversion Internal CS↓ CS↓ Figures 8, 9

Internal SCK, 3-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 10

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APPLICATIO S I FOR ATIO

REFERENCE

0.1V TO V

TEST EOC

(OPTIONAL)

SDO

SCK

(EXTERNAL)

TEST EOC

BIT 23

EOC

2.7V TO 5.5V

1µF

VOLTAGE

ANALOG

INPUT

210

LTC2480

REF

–

SCK

SDO

GND

SDI

INT/EXT CLOCK

4-WIRE SPI INTERFACE

BIT 4BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22

LSB

LTC2480

BIT 0

IMMSBSIG

TEST EOC

Hi-ZHi-ZHi-Z

SDI*

SDO

CONVERSION

DON’T CARE

EOC

SLEEPSLEEP

TEST EOC

EN GS2 GS1 GS0 IM FA FB SPD

DATA OUTPUT CONVERSION

Figure 5. External Serial Clock, Single Cycle Operation

2.7V TO 5.5V

1µF

210

TEST EOC

(OPTIONAL)

Hi-Z

LTC2480

INPUT

REF

–

MSBSIG

REFERENCE

VOLTAGE

0.1V TO V

ANALOG

BIT 23BIT 0

EOC

Hi-Z Hi-ZHi-Z

SCK

SDO

GND

SDI

INT/EXT CLOCK

4-WIRE SPI INTERFACE

DON’T CARE

2480 F05

BIT 8BIT 19 BIT 18 BIT 17 BIT 16 BIT 9BIT 20BIT 21BIT 22

TEST EOC

SCK

(EXTERNAL)

SDI*

DATA

OUTPUT

DON’T CARE DON’T CARE

CONVERSIONSLEEP

SLEEP

EN GS2 GS1 GS0 IM FA FB SPD

DATA OUTPUT

SLEEP

Figure 6. External Serial Clock, Reduced Data Output Length

CONVERSION

2480 F06

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LTC2480

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APPLICATIO S I FOR ATIO

External Serial Clock, 3-Wire I/O

This timing mode utilizes a 3-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 7. CS may be permanently tied to ground, simplifying the user interface or transmission over an isolation barrier.

The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded typically 4ms after V

exceeds approximately 2V. The level

applied to SCK at this time determines if SCK is internal or external. SCK must be driven LOW prior to the end of POR in order to enter the external serial clock timing mode.

Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller indicating the conversion result is ready. EOC = 1 while the conversion is in progress and EOC = 0 once the conversion ends. On the falling edge of EOC, the conversion result is loaded into an internal static shift register. The input data is then shifted in via the SDI pin on the rising edge of SCK (including the first rising edge) and the output data is shifted out of the SDO pin on each falling edge of SCK. EOC can be latched on the first rising edge of SCK. On the 24th falling edge of SCK, SDO goes HIGH (EOC = 1) indicating a new conversion has

begun. In applications where the processor generates 32 clock cycles, or to remain compatible with higher resolution converters, the LTC2480’s digital interface will ignore extra clock edges seen during the next conversion period after the 24th and outputs “1” for the extra clock cycles.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 8.

In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CS. The device will not enter the internal serial clock mode if SCK is driven LOW on the falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven.

The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state.

SDO

SCK

(EXTERNAL)

SDI*

CONVERSION

2.7V TO 5.5V

1µF

210

LTC2480

ANALOG

INPUT

MSBSIG

SDI

REF

SCK

SDO

–

GND

DATA OUTPUT CONVERSION

REFERENCE

VOLTAGE

0.1V TO V

BIT 23

EOC

DON’T CARE DON’T CARE

EN GS2 GS1 GS0 IM FA FB SPD

INT/EXT CLOCK

3-WIRE SPI INTERFACE

BIT 4BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22

LSB

Figure 7. External Serial Clock, CS = 0 Operation

BIT 0

2480 F07

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APPLICATIO S I FOR ATIO

LTC2480

When testing EOC, if the conversion is complete (EOC = 0), the device will exit the low power mode during the EOC test. In order to allow the device to return to the low power sleep state, CS must be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time t after the falling edge of CS (if EOC = 0) or t

EOCtest

after EOC goes LOW (if CS is LOW during the falling edge of EOC). The value of t oscillator. If F frequency f

EOSC

is pulled HIGH before time t

is 12µs if the device is using its internal

EOCtest

is driven by an external oscillator of

, then t

EOCtest

is 3.6/f

EOCtest

in seconds. If CS

EOSC

, the device returns to the sleep state and the conversion result is held in the internal static shift register.

If CS remains LOW longer than t

, the first rising

EOCtest

edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data I/O cycle concludes after the 24th rising edge. The input data is shifted in via the SDI pin on the rising edge of SCK (including the first rising edge) and the output data is shifted out of the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be

used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH and a new conversion starts.

CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first and 24th rising edge of SCK (see Figure 9). On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. If the device has not finished loading the last input bit SPD of SDI by the time CS is pulled HIGH, the SDI information is discarded and the previous configuration is still kept. This is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. If CS is pulled HIGH while the converter is driving SCK LOW, the internal pull-up is not available to restore SCK to a logic HIGH state. This will cause the device to exit the internal serial clock mode on the next falling edge of CS. This can be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CS HIGH when SCK is LOW.

SDO

SCK

(INTERNAL)

SDI*

2.7V TO 5.5V

1µF

210

LTC2480

ANALOG

INPUT

BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22

SDI

REF

DATA OUTPUT CONVERSIONCONVERSION

SCK

SDO

–

GND

REFERENCE

VOLTAGE

0.1V TO V

TEST EOC

Hi-Z Hi-Z Hi-Z Hi-Z

DON’T CARE DON’T CARE

SLEEP

EOCtest

BIT 23

EOC

EN GS2 GS1 GS0 IM FA FB SPD

MSBSIG

INT/EXT CLOCK

4-WIRE

SPI INTERFACE

10k

BIT 4

LSB IM

BIT 0

Figure 8. Internal Serial Clock, Single Cycle Operation

TEST EOC

2480 F08

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LTC2480

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APPLICATIO S I FOR ATIO

Whenever SCK is LOW, the LTC2480’s internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven if the device is in the internal SCK timing mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2480’s internal pull-up remains disabled. Hence, SCK remains LOW. On the next falling edge of CS, the device is switched to the external SCK timing mode. By adding an external 10k pull-up resistor to SCK, this pin goes HIGH once the external driver goes Hi-Z. On the next CS falling edge, the device will remain in the internal SCK timing mode.

A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. Once CS goes HIGH (within the time period defined above as t

), the internal pull-up is

EOCtest

activated. For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a HIGH level before CS goes low again. This is not a concern under normal conditions where CS remains LOW after detecting EOC = 0. This situation is easily overcome by adding an external 10k pull-up resistor to the SCK pin.

Internal Serial Clock, 3-Wire I/O, Continuous Conversion

This timing mode uses a 3-wire interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 10. CS may be permanently tied to ground, simplifying the user interface or transmission over an isolation barrier.

The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 1ms after VCC exceeds 2V. An internal weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected).

During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the low power sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period)

SDO

SCK

(INTERNAL)

SDI*

2.7V TO 5.5V

1µF

210

LTC2480

INPUT

SDI

REF

SCK

SDO

–

GND

BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22

MSBSIG

REFERENCE

VOLTAGE

0.1V TO V

TEST EOC

EOCtest

BIT 0

EOC

Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

DATA

OUTPUT

(OPTIONAL)

TEST EOC

DON’T CARE DON’T CARE

EOCtest

BIT 23

EOC

EN GS2 GS1 GS0 IM FA FB SPD

SLEEPSLEEP

ANALOG

DATA OUTPUT

INT/EXT CLOCK

4-WIRE SPI INTERFACE

10k

BIT 8

Figure 9. Internal Serial Clock, Reduce Data Output Length

CONVERSIONCONVERSIONSLEEP

TEST EOC

2480 F09

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APPLICATIO S I FOR ATIO

SDO

SCK

(INTERNAL)

BIT 23

EOC

2.7V TO 5.5V

1µF

REFERENCE

VOLTAGE

0.1V TO V

ANALOG

INPUT

BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22

210

LTC2480

REF

–

SCK

SDO

GND

SDI

INT/EXT CLOCK

3-WIRE SPI INTERFACE

10k

BIT 4 BIT 0

LSBMSBSIG

LTC2480

SDI*

DON’T CARE DON’T CARE

EN GS2 GS1 GS0 IM FA FB SPD

Figure 10. Internal Serial Clock, CS = 0 Continuous Operation

then immediately begins outputting data. The data input/ output cycle begins on the first rising edge of SCK and ends after the 24th rising edge. The input data is then shifted in via the SDI pin on the rising edge of SCK (including the first rising edge) and the output data is shifted out of the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion.

PRESERVING THE CONVERTER ACCURACY

The LTC2480 is designed to reduce as much as possible the conversion result sensitivity to device decoupling, PCB layout, antialiasing circuits, line frequency perturbations and so on. Nevertheless, in order to preserve the 24-bit accuracy capability of this part, some simple precautions are required.

DATA OUTPUT CONVERSIONCONVERSION

2480 F10

Digital Signal Levels

The LTC2480’s digital interface is easy to use. Its digital inputs (SDI, FO, CS and SCK in External SCK mode of operation) accept standard CMOS logic levels and the internal hysteresis receivers can tolerate edge transition times as slow as 100µs. However, some considerations are re- quired to take advantage of the exceptional accuracy and low supply current of this converter.

The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during the conversion state.

While a digital input signal is in the range 0.5V to (VCC– 0.5V), the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (SDI, FO, CS and SCK in External SCK mode of operation) is within this range, the power supply current may increase even if the signal in question is at a valid logic level. For micropower operation, it is recommended to drive all digital input signals to full CMOS levels [VIL < 0.4V and VOH > (VCC – 0.4V)].

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LTC2480

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APPLICATIO S I FOR ATIO

During the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the pins can severely disturb the analog to digital conversion process. Undershoot and overshoot occur because of the impedance mismatch of the circuit board trace at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to the LTC2480 signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance.

Parallel termination near the LTC2480 pin will eliminate this problem but will increase the driver power dissipation. A series resistor between 27Ω and 56Ω placed near the driver output pin will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology.

An alternate solution is to reduce the edge rate of the control signals. It should be noted that using very slow edges will increase the converter power supply current during the transition time. The differential input architecture reduces the converter’s sensitivity to ground currents.

Particular attention must be given to the connection of the FO signal when the LTC2480 is used with an external conversion clock. This clock is active during the conversion time and the normal mode rejection provided by the internal digital filter is not very high at this frequency. A normal mode signal of this frequency at the converter reference terminals can result in DC gain and INL errors. A normal mode signal of this frequency at the converter input terminals can result in a DC offset error. Such perturbations can occur due to asymmetric capacitive coupling between the FO signal trace and the converter input and/or reference connection traces. An immediate solution is to maintain maximum possible separation between the FO signal trace and the input/reference signals. When the FO signal is parallel terminated near the

. For reference, on a regular FR-4 board,

converter, substantial AC current is flowing in the loop formed by the FO connection trace, the termination and the ground return path. Thus, perturbation signals may be inductively coupled into the converter input and/or reference. In this situation, the user must reduce to a minimum the loop area for the F the differential input and reference connections. Even when F EMI threats which will be minimized by following good layout practices.

Driving the Input and Reference

The input and reference pins of the LTC2480 converter are directly connected to a network of sampling capacitors. Depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transferring small amounts of charge in the process. A simplified equivalent circuit is shown in Figure 11.

For a simple approximation, the source impedance R driving an analog input pin (IN+, IN–, V considered to form, together with RSW and CEQ (see Figure 11), a first order passive network with a time constant τ = (RS + RSW) • CEQ. The converter is able to sample the input signal with better than 1ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant τ. The sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worstcase circumstances, the errors may add.

When using the internal oscillator, the LTC2480’s frontend switched-capacitor network is clocked at 123kHz corresponding to an 8.1µs sampling period. Thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that τ ≤ 8.1µs/14 = 580ns. When an external oscillator of frequency f used, the sampling period is 2.5/f error of less than 1ppm, τ ≤ 0.178/f

Automatic Differential Input Current Cancellation

In applications where the sensor output impedance is low (up to 10kΩ with no external bypass capacitor or up to 500Ω with 0.001µF bypass), complete settling of the input

is not driven, other nearby signals pose similar

signal as well as the loop area for

or GND) can be

REF

EOSC

and, for a settling

EOSC

2480f

APPLICATIO S I FOR ATIO

IIN IIN

I REF

VV V

VD R

VV V

where

AVG AVG

IN CM REF CM

AVG

REF

INCM REFCM

REF EQ

REF T

REF REF CM IN CM

REF EQ

()=()

−

•

()

• − +

•

−

•

−≅

()

–

() ()

.• •

.–

.•

–

•

VININ

IN IN

R M INTERNAL OSCILLATOR Hz MODE

REFCM

INCM

⎛

⎝

⎜

⎞

⎠

⎟

= −

⎛

⎝

⎜

⎞

⎠

⎟

= = Ω

=•

()

+ −

271 60Ω

R 2.98 M INTERNAL OSCILLATOR 50Hz AND 60Hz MODE

R 0.833 10 / f EXTERNAL OSCILLATOR

D IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT

EOSC

WHERE REF– IS INTERNALLY TIED TO GND

occurs. In this case, no errors are introduced and direct digitization of the sensor is possible.

For many applications, the sensor output impedance combined with external bypass capacitors produces RC time constants much greater than the 580ns required for 1ppm accuracy. For example, a 10kΩ bridge driving a 0.1µF bypass capacitor has a time constant an order of magnitude greater than the required maximum. Historically, settling issues were solved using buffers. These buffers led to increased noise, reduced DC performance (Offset/ Drift), limited input/output swing (cannot digitize signals near ground or V power. The LTC2480 uses a proprietary switching algorithm that forces the average differential input current to zero independent of external settling errors. This allows accurate direct digitization of high impedance sensors without the need of buffers. Additional errors resulting from mismatched leakage currents must also be taken into account.

The switching algorithm forces the average input current on the positive input (I current on the negative input (I conversion cycle, the average differential input current (I

IN+

REF

GND

SWITCHING FREQUENCY

= 123kHz INTERNAL OSCILLATOR

= 0.4 • f

–

– I

) is zero. While the differential input current is

–

EXTERNAL OSCILLATOR

EOSC

LEAK

), added system cost and increased

) to be equal to the average input

LEAK

RSW (TYP)

10k

RSW (TYP)

10k

RSW (TYP)

10k

RSW (TYP)

10k

–

). Over the complete

2480 F11

WUUU

zero, the common mode input current (I proportional to the difference between the common mode input voltage (V voltage (V

REFCM

In applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balance bridge type application, both the differential and common mode input current are zero. The accuracy of the converter is unaffected by settling errors. Mismatches in source impedances between IN+ and IN also do not affect the accuracy.

In applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the difference between V common mode of 2.5V and an input common mode of

1.5V, the common mode input current is approximately

0.74µA (in simultaneous 50Hz/60Hz rejection mode). This common mode input current has no effect on the accuracy if the external source impedances tied to IN+ and IN– are matched. Mismatches in these source impedances lead to a fixed offset error but do not affect the linearity or fullscale reading. A 1% mismatch in 1kΩ source resistances leads to a 15ppm shift (74µV) in offset voltage.

12pF (TYP)

Figure 11. LTC2480 Equivalent Analog Input Circuit

) and the common mode reference

INCM

and V

LTC2480

. For a reference

REFCM

+ I

–

)/2 is

2480f

–

LTC2480

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APPLICATIO S I FOR ATIO

SOURCE

INCM

+ 0.5V

– 0.5V

SOURCE

EXT

Figure 12. An RC Network at IN+ and IN

VCC = 5V

= 5V

REF

= 3.75V

–

= 1.25V

= GND

= 25°C

–20

+FS ERROR (ppm)

–40

–60

–80

EXT

10 100 10k

SOURCE

Figure 13. +FS Error vs R

EXT

= 100pF

EXT

= 1nF, 0.1µF, 1µF

(Ω)

SOURCE

= 0pF

at IN+ or IN

PAR

≅20pF

PAR

≅20pF

2480 F13

LTC2480

100k

common mode input current varies proportionally with input voltage. For the case of balanced input impedances, the common mode input current effects are rejected by the large CMRR of the LTC2480 leading to little degradation in

–

2480 F12

accuracy. Mismatches in source impedances lead to gain errors proportional to the difference between the common mode input voltage and the common mode reference voltage. 1% mismatches in 1kΩ source resistances lead to worst-case gain errors on the order of 15ppm or 1LSB

–

(for 1V differences in reference and input common mode voltage). Table 7 summarizes the effects of mismatched source impedance and differences in reference/input common mode voltages.

Table 7. Suggested Input Configuration for LTC2480

BALANCED INPUT UNBALANCED INPUT RESISTANCES RESISTANCES

Constant C V

– V

IN(CM)

REF(CM)

> 1nF at Both C

EXT

> 1nF at Both IN

EXT

IN+ and IN–. Can Take and IN–. Can Take Large Large Source Resistance Source Resistance. with Negligible Error Unbalanced Resistance

Results in an Offset Which Can be Calibrated

Varying C V

– V

IN(CM)

REF(CM)

> 1nF at Both IN

EXT

and IN–. Can Take Large Capacitors and Avoid

Minimize IN+ and IN

Source Resistance with Large Source Impedance

–

Negligible Error (<5k Recommended)

–

VCC = 5V

= 5V

REF

= 1.25V

–

= 3.75V

= GND

= 25°C

–20

–FS ERROR (ppm)

–40

–60

–80

Figure 14. –FS Error vs R

= 1nF, 0.1µF, 1µF

EXT

= 100pF

EXT

10 100 10k

SOURCE

(Ω)

SOURCE

= 0pF

100k

2480 F14

at IN+ or IN

–

In applications where the common mode input voltage varies as a function of input signal level (single-ended input, RTDs, half bridges, current sensors, etc.), the

The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by IN+ and IN–, the expected drift of the dynamic current and offset will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient.

In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift. A 1k source resistance will create a 1µV typical and 10µV maximum offset voltage.

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APPLICATIO S I FOR ATIO

Reference Current

In a similar fashion, the LTC2480 samples the differential reference pins V of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in two distinct situations.

For relatively small values of the external reference capacitors (C

< 1nF), the voltage on the sampling capacitor

REF

settles almost completely and relatively large values for the source impedance result in only small errors. Such values for C

REF

gain performance without significant benefits of reference filtering and the user is advised to avoid them.

Larger values of reference capacitors (C required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance.

In the following discussion, it is assumed the input and reference common mode are the same. Using internal oscillator for 60Hz mode, the typical differential reference resistance is 1MΩ which generates a full-scale (V

/2) gain error of 0.51ppm for each ohm of source

REF

resistance driving the V related difference resistance is 1.1MΩ and the resulting full-scale error is 0.46ppm for each ohm of source resistance driving the V related difference resistance is 1.2MΩ and the resulting full-scale error is 0.42ppm for each ohm of source resistance driving the V external oscillator with a frequency f version clock operation), the typical differential reference resistance is 0.30 • 1012/f resistance driving the V f

ppm gain error. The typical +FS and –FS errors for

EOSC

various combinations of source resistance seen by the V

pin and external capacitance connected to that pin

REF

are shown in Figures 15-18.

and GND transferring small amount

REF

will deteriorate the converter offset and

> 1nF) may be

REF

pin. For 50Hz/60Hz mode, the

REF

pin. For 50Hz mode, the

REF

pin. When FO is driven by an

REF

(external con-

EOSC

Ω and each ohm of source

EOSC

pin will result in 1.67 • 10–6 •

REF

LTC2480

–V

/(V

• REQ) – (0.5 • V

REF

pin current as expressed in Figure 11. When using internal oscillator and 60Hz mode, every 100Ω of reference source resistance translates into about 0.67ppm additional INL error. When using internal oscillator and 50Hz/60Hz mode, every 100Ω of reference source resistance translates into about 0.61ppm additional INL error. When using internal oscillator and 50Hz mode, every 100Ω of reference source resistance translates into about 0.56ppm additional INL error. When FO is driven by an external oscillator with a frequency f

translates into about 2.18 • 10–6 • f

REF

, every 100Ω of source resistance driving

EOSC

tional INL error. Figure 19 shows the typical INL error due to the source resistance driving the V C

values are used. The user is advised to minimize the

REF

source impedance driving the V

In applications where the reference and input common mode voltages are different, extra errors are introduced. For every 1V of the reference and input common mode voltage difference (V

REFCM

each Ohm of reference source resistance introduces an extra (V

REFCM

– V

INCM

)/(V which is 0.074ppm when using internal oscillator and 60Hz mode. When using internal oscillator and 50Hz/60Hz mode, the extra full-scale gain error is 0.067ppm. When using internal oscillator and 50Hz mode, the extra gain error is 0.061ppm. If an external clock is used, the corresponding extra gain error is 0.24 • 10–6 • f

The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by V

and GND, the expected drift of the dynamic

REF

current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications a one-time calibration operation may be sufficient.

• DT)/REQ in the reference

REF

ppm addi-

EOSC

pin when large

REF

pin.

REF

– V

REF

) and a 5V reference,

INCM

• REQ) full-scale gain error,

ppm.

EOSC

In addition to this gain error, the converter INL performance is degraded by the reference source impedance. The INL is caused by the input dependent terms

In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent

2480f

LTC2480

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APPLICATIO S I FOR ATIO

VCC = 5V

= 5V

REF

= 3.75V

–

= 1.25V

= GND

= 25°C

+FS ERROR (ppm)

–10

= 0.01µF

REF

= 0.001µF

REF

= 100pF

REF

= 0pF

REF

100

SOURCE

Figure 15. +FS Error vs R

REF

VCC = 5V

= 5V

REF

= 1.25V

–

= 3.75V

= GND

= 25°C

= 0.01µF

REF

= 0.001µF

= 100pF

REF

= 0pF

100 R

SOURCE

–10

–20

–30

–40

–50

–FS ERROR (ppm)

–60

–70

–80

–90

(Ω)

SOURCE

(Ω)

at V

10k

REF

10k

100k

2480 F15

(Small C

100k

2480 F16

REF

–100

–200

= 1µF, 10µF

REF

–300

VCC = 5V

–FS ERROR (ppm)

–400

–500

)

Figure 18. –FS Error vs R

)

REF

INL (ppm OF V

–10

–2

–4

–6

–8

VCC = 5V V V T C

–0.5

REF

REF IN(CM)

REF

= 5V

= 1.25V

–

= 3.75V = GND = 25°C

200

= 5V

= 25°C

= 10µF

–0.3

= 2.5V

400 R

–0.1

VIN/V

SOURCE

600

(Ω)

SOURCE

0.1

(V)

REF

= 0.01µF

REF

800

at V

R = 1k

R = 500Ω

R = 100Ω

0.3

= 0.1µF

2480 F18

(Large C

REF

2480 F19

1000

0.5

REF

)

Figure 16. –FS Error vs R

500

VCC = 5V V

REF

400

= GND

= 25°C

300

200

+FS ERROR (ppm)

100

Figure 17. +FS Error vs R

= 5V

= 3.75V

–

= 1.25V

200

400

SOURCE

= 1µF, 10µF

REF

600

(Ω)

SOURCE

at V

REF

at V

REF

= 0.1µF

REF

= 0.01µF

800

REF

(Small C

1000

2480 F17

(Large C

REF

)

Figure 19. INL vs Differential Input Voltage and Reference Source Resistance for C

REF

> 1µF

leakage current. This leakage current, nominally 1nA (±10nA max), results in a small gain error. A 100Ω source resistance will create a 0.05µV typical and 0.5µV maxi- mum full-scale error.

Output Data Rate

When using its internal oscillator, the LTC2480 produces up to 7.5 samples per second (sps) with a notch frequency of 60Hz, 6.25sps with a notch frequency of 50Hz and

6.82sps with the 50Hz/60Hz rejection mode. The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When oper-

)

ated with an external conversion clock (FO connected to an

2480f

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APPLICATIO S I FOR ATIO

LTC2480

external oscillator), the LTC2480 output data rate can be increased as desired. The duration of the conversion phase is 41036/f

EOSC

. If f

= 307.2kHz, the converter

EOSC

behaves as if the internal oscillator is used and the notch is set at 60Hz.

An increase in f

over the nominal 307.2kHz will

EOSC

translate into a proportional increase in the maximum output data rate. The increase in output rate is nevertheless accompanied by three potential effects, which must be carefully considered.

First, a change in f

will result in a proportional change

EOSC

in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2480’s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN– pins.

Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (CIN, C

) are used, the

REF

previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of f reference capacitors (CIN, C

. If small external input and/or

EOSC

) are used, the effect of the

REF

external source resistance upon the LTC2480 typical performance can be inferred from Figures 13, 14, 15 and 16 in which the horizontal axis is scaled by 307200/f

EOSC

Third, an increase in the frequency of the external oscillator above 1MHz (a more than 3× increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures 20 to 27. In order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating

= V

IN(CM)

VCC = V

)

REF

OFFSET ERROR (ppm OF V

–10

REF(CM)

= 5V

REF

= 0V

= EXT CLOCK

TA = 85°C

TA = 25°C

20 40 60 80

OUTPUT DATA RATE (READINGS/SEC)

10010030507090

2480 F20

Figure 20. Offset Error vs Output Data Rate and Temperature

3500

= V

IN(CM)

VCC = V

3000

)

REF

2500

2000

1500

1000

+FS ERROR (ppm OF V

500

REF(CM)

= 5V

REF

= EXT CLOCK

TA = 85°C

= 25°C

60 80

OUTPUT DATA RATE (READINGS/SEC)

2480 F21

100

Figure 21. +FS Error vs Output Data Rate and Temperature

–500

)

REF

–1000

–1500

–2000

–2500

–FS ERROR (ppm OF V

= V

IN(CM)

–3000

VCC = V

REF

= EXT CLOCK

–3500

OUTPUT DATA RATE (READINGS/SEC)

TA = 85°C

REF(CM)

= 5V

= 25°C

60 80

2480 F22

100

Figure 22. –FS Error vs Output Data Rate and Temperature

2480f

LTC2480

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APPLICATIO S I FOR ATIO

TA = 85°C

RESOLUTION (BITS)

= V

IN(CM)

VCC = V V F RES = LOG 2 (V

REF(CM)

= 5V

REF

= 0V

= EXT CLOCK

OUTPUT DATA RATE (READINGS/SEC)

Figure 23. Resolution (Noise

REF

/NOISE

= 25°C

)

RMS

60 80

RMS

2480 F23

≤ 1LSB)

vs Output Data Rate and Temperature

/INL

= 25°C

)

MAX

60 80

2480 F24

TA = 85°C

RESOLUTION (BITS)

= V

IN(CM)

VCC = V

REF

= EXT CLOCK

RES = LOG 2 (V

OUTPUT DATA RATE (READINGS/SEC)

REF(CM)

= 5V

REF

100

VCC = 5V, V

RESOLUTION (BITS)

VIN = 0V F

T RES = LOG 2 (V

REF

= V

IN(CM)

REF(CM)

= EXT CLOCK = 25°C

OUTPUT DATA RATE (READINGS/SEC)

Figure 26. Resolution (Noise

= 2.5V

/NOISE

REF

= V

REF

)

RMS

60 80

RMS

= 5V

2480 F26

≤ 1LSB)

100

vs Output Data Rate and Reference Voltage

VCC = 5V, V

= V

IN(CM)

RESOLUTION (BITS)

VIN = 0V

–

= GND

REF

= EXT CLOCK

= 25°C

RES = LOG 2 (V

OUTPUT DATA RATE (READINGS/SEC)

= 2.5V

REF

REF(CM)

REF

VCC = V

/INL

MAX

REF

)

60 80

= 5V

2480 F27

100

Figure 24. Resolution (INL

MAX

≤ 1LSB)

vs Output Data Rate and Temperature

= V

IN(CM)

VIN = 0V F

)

REF

OFFSET ERROR (ppm OF V

–5

–10

REF(CM)

= EXT CLOCK

= 25°C

VCC = V

VCC = 5V, V

OUTPUT DATA RATE (READINGS/SEC)

REF

= 2.5V

60 80

REF

= 5V

Figure 25. Offset Error vs Output Data Rate and Reference Voltage

2480 F25

100

Figure 27. Resolution (INL

≤ 1LSB) vs

MAX

Output Data Rate and Reference Voltage

temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial.

Input Bandwidth

The combined effect of the internal SINC4 digital filter and of the analog and digital autocalibration circuits determines the LTC2480 input bandwidth. When the internal oscillator is used with the notch set at 60Hz, the 3dB input bandwidth is 3.63Hz. When the internal oscillator is used with the notch set at 50Hz, the 3dB input bandwidth is

3.02Hz. If an external conversion clock generator of frequency f bandwidth is 11.8 • 10–6 • f

is connected to the FO pin, the 3dB input

EOSC

2480f

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APPLICATIO S I FOR ATIO

LTC2480

Due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3dB frequency. When the internal oscillator is used, the shape of the LTC2480 input bandwidth is shown in Figure 28. When an external oscillator of frequency f

EOSC

is used, the shape of the LTC2480 input bandwidth can be derived from Figure 28, 60Hz mode curve in which the horizontal axis is scaled by f

The conversion noise (600nV

/307200.

EOSC

typical for V

RMS

REF

= 5V)

can be modeled by a white noise source connected to a noise free converter. The noise spectral density is 47nV√Hz for an infinite bandwidth source and 64nV√Hz for a single

0.5MHz pole source. From these numbers, it is clear that particular attention must be given to the design of external amplification circuits. Such circuits face the simultaneous requirements of very low bandwidth (just a few Hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500kHz) necessary to drive the input switched-capacitor network. A possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer.

When external amplifiers are driving the LTC2480, the ADC input referred system noise calculation can be simplified by Figure 29. The noise of an amplifier driving the LTC2480 input pin can be modeled as a band limited white noise source. Its bandwidth can be approximated by the bandwidth of a single pole lowpass filter with a corner frequency fi. The amplifier noise spectral density is ni. From Figure 29, using fi as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth freqi of the input driving amplifier. This bandwidth includes the band limiting effects of the ADC internal calibration and filtering. The noise of the driving amplifier referred to the converter input and including all these effects can be calculated as N = ni • √freqi. The total system noise (referred to the LTC2480 input) can now be obtained by summing as square root of sum of squares the three ADC input referred noise sources: the LTC2480 internal noise, the noise of the IN+ driving amplifier and the noise of the IN– driving amplifier.

If the FO pin is driven by an external oscillator of frequency f

, Figure 29 can still be used for noise calculation if the

EOSC

–1

–2

–3

–4

–5

INPUT SIGNAL ATTENUATION (dB)

–6

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

Figure 28. Input Signal Bandwidth Using the Internal Oscillator

100

INPUT REFERRED NOISE

EQUIVALENT BANDWIDTH (Hz)

0.1

0.1 1 10 100 1k 10k 100k 1M

Figure 29. Input Referred Noise Equivalent Bandwidth of an Input Connected White Noise Source

x-axis is scaled by f ratio f

/307200, the Figure 29 plot accuracy begins to

EOSC

50Hz MODE 60Hz MODE

60Hz MODE

50Hz MODE

INPUT NOISE SOURCE SINGLE POLE

EQUIVALENT BANDWIDTH (Hz)

/307200. For large values of the

EOSC

50Hz AND 60Hz MODE

2480 F28

2480 F29

decrease, but at the same time the LTC2480 noise floor rises and the noise contribution of the driving amplifiers lose significance.

Normal Mode Rejection and Antialiasing

One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2480 significantly simplifies antialiasing filter requirements. Additionally, the input current cancellation feature of the LTC2480 allows external lowpass filtering without degrading the DC performance of the device.

2480f

LTC2480

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APPLICATIO S I FOR ATIO

The SINC4 digital filter provides greater than 120dB normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS). The LTC2480’s autocalibration circuits further simplify the antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. Independent of the operating mode, fS = 256 • fN = 2048

• f

OUTMAX

where fN is the notch frequency and f

OUTMAX

is the maximum output data rate. In the internal oscillator mode with a 50Hz notch setting, fS =

12800Hz, with 50Hz/60Hz rejection, fS = 13960Hz and with a 60Hz notch setting f f

EOSC

= 15360Hz. In the external oscillator mode, fS =

/20. The performance of the normal mode rejection

is shown in Figures 30 and 31.

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

INPUT NORMAL MODE REJECTION (dB)

–110

–120

S2fS3fS4fS5fS6fS7fS8fS9fS

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

10fS11fS12f

2480 F30

In 1x speed mode, the regions of low rejection occurring at integer multiples of f

have a very narrow bandwidth.

Magnified details of the normal mode rejection curves are shown in Figure 32 (rejection near DC) and Figure 33 (rejection at fS = 256fN) where fN represents the notch frequency. These curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the fN value.

The user can expect to achieve this level of performance using the internal oscillator as it is demonstrated by Figures 34, 35 and 36. Typical measured values of the normal mode rejection of the LTC2480 operating with an internal oscillator and a 60Hz notch setting are shown in Figure 34

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

INPUT NORMAL MODE REJECTION (dB)

–110

–120

2fS3fS4fS5fS6fS7fS8fS9fS10f

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2480 F31

Figure 30. Input Normal Mode Rejection, Internal Oscillator and 50Hz Notch Mode

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

INPUT NORMAL MODE REJECTION (dB)

–110

–120

fN0 2fN3fN4fN5fN6fN7fN8f

INPUT SIGNAL FREQUENCY (Hz)

fN = f

EOSC/5120

2480 F32

Figure 31. Input Normal Mode Rejection, Internal Oscillator and 60Hz Notch Mode or External Oscillator

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

INPUT NORMAL MODE REJECTION (dB)

–110

–120

250f

252fN254fN256fN258fN260fN262f

INPUT SIGNAL FREQUENCY (Hz)

2480 F33

Figure 32. Input Normal Mode Rejection at DC Figure 33. Input Normal Mode Rejection at fS = 256f

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APPLICATIO S I FOR ATIO

LTC2480

–20

–40

–60

–80

NORMAL MODE REJECTION (dB)

–100

–120

15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

MEASURED DATA CALCULATED DATA

INPUT FREQUENCY (Hz)

VCC = 5V V

= 5V

REF

IN(CM)

IN(P-P)

= 25°C

= 2.5V

= 5V

2480 F34

Figure 34. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (60Hz Notch)

–20

–40

–60

–80

NORMAL MODE REJECTION (dB)

–100

–120

12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz)

MEASURED DATA CALCULATED DATA

VCC = 5V V

= 5V

REF

IN(CM)

IN(P-P)

= 25°C

= 2.5V = 5V

2480 F35

Figure 35. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (50Hz Notch)

–20

–40

–60

–80

NORMAL MODE REJECTION (dB)

–100

–120

20 40 60 80 100 120 140 160 180 200 220

MEASURED DATA CALCULATED DATA

INPUT FREQUENCY (Hz)

VCC = 5V V

= 5V

REF

IN(CM)

IN(P-P)

= 25°C

= 2.5V

= 5V

2483 F36

Figure 36. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (50Hz/60Hz Mode)

superimposed over the theoretical calculated curve. Similarly, the measured normal mode rejection of the LTC2480 for the 50Hz rejection mode and 50Hz/60Hz rejection mode are shown in Figures 35 and 36.

As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front of the LTC2480. If passive RC components are placed in front of the LTC2480, the input dynamic current should be considered (see Input Current section). In this case, the differential input current cancellation feature of the LTC2480 allows external RC networks without significant degradation in DC performance.

Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2480 third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale. In many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and the LTC2480 is eminently suited for such tasks. When the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. With a reference voltage V

= 5V, the LTC2480 has a full-scale differen-

REF

tial input range of 5V peak-to-peak. Figures 37 and 38 show measurement results for the LTC2480 normal mode rejection ratio with a 7.5V peak-to-peak (150% of full scale) input signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5V peakto-peak (full scale) input signal. In Figure 37, the LTC2480 uses the internal oscillator with the notch set at 60Hz (F

= LOW) and in Figure 38 it uses the internal oscillator with the notch set at 50Hz. It is clear that the LTC2480 rejection performance is maintained with no compromises in this extreme situation. When operating with large input signal levels, the user must observe that such signals do not violate the device absolute maximum ratings.

Using the 2x speed mode of the LTC2480, the device bypasses the digital offset calibration operation to double the output data rate. The superior normal mode rejection is maintained as shown in Figures 30 and 31. However, the magnified details near DC and fS = 256fN are different, see Figures 39 and 40. In 2x speed mode, the bandwidth is

11.4Hz for the 50Hz rejection mode, 13.6Hz for the 60Hz rejection mode and 12.4Hz for the 50Hz/60Hz rejection

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LTC2480

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APPLICATIO S I FOR ATIO

–20

–40

= 5V

IN(P-P)

= 7.5V

IN(P-P)

(150% OF FULL SCALE)

VCC = 5V V

= 5V

REF

INCM

= 25°C

= 2.5V

–20

–40

= 5V

IN(P-P)

= 7.5V

IN(P-P)

(150% OF FULL SCALE)

VCC = 5V V

= 5V

REF

IN(CM)

= 25°C

= 2.5V

–60

–80

NORMAL MODE REJECTION (dB)

–100

–120

15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

INPUT FREQUENCY (Hz)

Figure 37. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch)

–20

–40

–60

–80

INPUT NORMAL REJECTION (dB)

–100

–120

N2fN3fN4fN5fN6fN7fN8fN

INPUT SIGNAL FREQUENCY (fN)

2480 F39

2480 F37

–60

–80

NORMAL MODE REJECTION (dB)

–100

–120

12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz)

Figure 38. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch)

–20

–40

–60

–80

INPUT NORMAL REJECTION (dB)

–100

–120

250248 252 254 256 258 260 262 264

INPUT SIGNAL FREQUENCY (fN)

2480 F48

2480 F38

Figure 39. Input Normal Mode Rejection 2x Speed Mode

–20

–40

–60

–80

NORMAL MODE REJECTION (dB)

–100

–120

25 75

MEASURED DATA CALCULATED DATA

125 225

100

INPUT FREQUENCY (Hz)

150

VCC = 5V V

= 5V

REF

INCM

IN(P-P)

= GND

= 25°C

175

= 2.5V

= 5V

200

2480 F41

Figure 41. Input Normal Mode Rejection vs Input Frequency, 2x Speed Mode and 50Hz/60Hz Mode

mode. Typical measured values of the normal mode rejection of the LTC2480 operating with the internal oscillator and 2x speed mode is shown in Figure 41.

Figure 40. Input Normal Mode Rejection 2x Speed Mode

–70

–80

–90

–100

–110

–120

NORMAL MODE REJECTION (dB)

–130

–140

50 52

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

NO AVERAGE

56 60 62

54 58

WITH RUNNING AVERAGE

2480 F42

Figure 42. Input Normal Mode Rejection 2x Speed Mode

When the LTC2480 is configured in 2x speed mode, by performing a running average, a SINC1 notch is combined with the SINC4 digital filter, yielding the normal mode

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APPLICATIO S I FOR ATIO

LTC2480

rejection identical as that for the 1x speed mode. The averaging operation still keeps the output rate with the following algorithm:

Result 1 = average (sample 0, sample 1)

Result 2 = average (sample 1, sample 2)

……

Result n = average (sample n – 1, sample n)

The main advantage of the running average is that it achieves simultaneous 50Hz/60Hz rejection at twice the effective output rate, as shown in Figure 42. The raw output data provides a better than 70dB rejection over 48Hz to 62.4Hz, which covers both 50Hz ±2% and 60Hz ±2%. With running average on, the rejection is better than 87dB for both 50Hz ±2% and 60Hz ±2%.

Complete Thermocouple Measurement System with Cold Junction Compensation

The LTC2480 is ideal for direct digitization of thermocouples and other low voltage output sensors. The input has a typical offset error of 500nV (2.5µV max) offset drift of 10nV/°C and a noise level of 600nV

. The input span may be

RMS

optimized for various sensors by setting the gain of the PGA. Using an external 5V reference with a PGA gain of 64 gives a ±78mV input range—perfect for thermocouples.

Figure 44 (last page of this data sheet) is a complete type K thermocouple meter. The only signal conditioning is a simple surge protection network. In any thermocouple

meter, the cold junction temperature sensor must be at the same temperature as the junction between the thermocouple materials and the copper printed circuit board traces. The tiny LTC2480 can be tucked neatly underneath an Omega MPJ-K-F thermocouple socket ensuring close thermal coupling.

The LTC2480’s 1.4mV/°C PTAT circuit measures the cold junction temperature. Once the thermocouple voltage and cold junction temperature are known, there are many ways of calculating the thermocouple temperature including a straight-line approximation, lookup tables or a polynomial curve fit. Calibration is performed by applying an accurate 500mV to the ADC input derived from an LT®1236 reference and measuring the local temperature with an accurate thermometer as shown in Figure 43. In calibration mode, the up and down buttons are used to adjust the local temperature reading until it matches an accurate thermometer. Both the voltage and temperature calibration are easily automated.

The complete microcontroller code for this application is available on the LTC2480 product webpage at:

http://www.linear.com

It can be used as a template for may different instruments and it illustrates how to generate calibration coefficients for the onboard temperature sensor. Extensive comments detail the operation of the program. The read_LTC2480() function controls the operation of the LTC2480 and is listed below for reference.

NC1M4V0

ISOTHERMAL

LT1236

IN OUT

TRIM

GND

R7 8k

R8 1k

TYPE K

THERMOCOUPLE

JACK

(OMEGA MPJ-K-F)

26.3C

REF

LTC2480

GND

–

1µF

SCK

SDO

SDI

118

2480 F43

0.1µF

Figure 43. Calibration Setup

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LTC2480

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APPLICATIO S I FOR ATIO

/*** read_LTC2480() ************************************************************ This is the function that actually does all the work of talking to the LTC2480. The spi_read() function performs an 8 bit bidirectional transfer on the SPI bus. Data changes state on falling clock edges and is valid on rising edges, as determined by the setup_spi() line in the initialize() function.

A good starting point when porting to other processors is to write your own spi_write function. Note that each processor has its own way of configuring the SPI port, and different compilers may or may not have built-in functions for the SPI port. Also, since the state of the LTC2480’s SDO line indicates when a conversion is complete you need to be able to read the state of this line through the processor’s serial data input. Most processors will let you read this pin as if it were a general purpose I/O line, but there may be some that don’t.

When in doubt, you can always write a “bit bang” function for troubleshooting purposes.

The “fourbytes” structure allows byte access to the 32 bit return value:

struct fourbytes // Define structure of four consecutive bytes { // To allow byte access to a 32 bit int or float. int8 te0; // int8 te1; // The make32() function in this compiler will int8 te2; // also work, but a union of 4 bytes and a 32 bit int int8 te3; // is probably more portable. };

Also note that the lower 4 bits are the configuration word from the previous conversion. The 4 LSBs are cleared so that they don’t affect any subsequent mathematical operations. While you can do a right shift by 4, there is no point if you are going to convert to floating point numbers - just adjust your scaling constants appropriately. *******************************************************************************/ signed int32 read_LTC2480(char config) { union // adc_code.bits32 all 32 bits { // adc_code.by.te0 byte 0 signed int32 bits32; // adc_code.by.te1 byte 1 struct fourbytes by; // adc_code.by.te2 byte 2 } adc_code; // adc_code.by.te3 byte 3

output_low(CS); // Enable LTC2480 SPI interface while(input(PIN_C4)) {} // Wait for end of conversion. The longest // you will ever wait is one whole conversion period

// Now is the time to switch any multiplexers because the conversion is finished // and you have the whole data output time for things to settle.

adc_code.by.te3 = 0; // Set upper byte to zero. adc_code.by.te2 = spi_read(config); // Read first byte, send config byte adc_code.by.te1 = spi_read(0); // Read 2nd byte, send speed bit adc_code.by.te0 = spi_read(0); // Read 3rd byte. ‘0’ argument is necessary // to act as SPI master!! (compiler // and processor specific.) output_high(CS); // Disable LTC2480 SPI interface

// Clear configuration bits and subtract offset. This results in // a 2’s complement 32 bit integer with the LTC2480’s MSB in the 2^20 position adc_code.by.te0 = adc_code.by.te0 & 0xF0; adc_code.bits32 = adc_code.bits32 - 0x00200000;

return adc_code.bits32; } // End of read_LTC2480()

2480f

PACKAGE DESCRIPTIO

LTC2480

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698)

0.675 ±0.05

3.50 ±0.05

1.65 ±0.05 (2 SIDES)2.15 ±0.05

PACKAGE OUTLINE

0.25 ± 0.05

2.38 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

PIN 1

TOP MARK

(SEE NOTE 5)

0.200 REF

0.50 BSC

(2 SIDES)

3.00 ±0.10 (4 SIDES)

0.75 ±0.05

0.00 – 0.05

1.65 ± 0.10 (2 SIDES)

R = 0.115

TYP

2.38 ±0.10 (2 SIDES)

BOTTOM VIEW—EXPOSED PAD

0.38 ± 0.10

106

0.25 ± 0.05

0.50 BSC

(DD10) DFN 0403

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

2480f

LTC2480

TYPICAL APPLICATIO

ISOTHERMAL

R2 2k

TYPE K

THERMOCOUPLE

JACK

(OMEGA MPJ-K-F)

CONTRAST

REF

LTC2480

–

GND

2 × 16 CHARACTER

LCD DISPLAY

(OPTREX DMC162488

OR SIMILAR)

GND D0

D1 D2 D3

GND

118

SCK

SDO

SDI

D7 D6 D5 D4 EN

CALIBRATE

C8 1µF

6 9 7 1 10

0.1µF

2 1

10k

PIC16F73

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

RA5

RA4

RA3

RA2

RA1

RA0

OSC1

OSC2

MCLR

V V

2480 F44

6MHz

10k

0.1µF

BAT54

DOWN UP

Figure 44. Complete Type K Thermocouple Meter

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PART NUMBER DESCRIPTION COMMENTS

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with Differential Inputs

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Noise, 2ppm INL

RMS

Noise, 4ppm INL,

RMS

Simultaneous 50Hz/60Hz Rejection (LTC2411-1)

LTC2413 24-Bit, No Latency ∆Σ ADC with Differential Inputs Simultaneous 50Hz/60Hz Rejection, 800nV LTC2415/ 24-Bit, No Latency ∆Σ ADCs with 15Hz Output Rate Pin Compatible with the LTC2410

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LT/TP 0405 500 • PRINTED IN THE USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

P-P

RMS

Noise

2480f

Datasheet LTC2480 Datasheet (LINEAR TECHNOLOGY)

Specifications and Main Features

Frequently Asked Questions

User Manual