Datasheet LTC2430, LTC2431 Datasheet (LINEAR TECHNOLOGY)

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Page 1

LTC2430/LTC2431

FEATURES

■

Low Supply Current (200µA in Conversion Mode and 4µA in Autosleep Mode)

■

Differential Input and Differential Reference with GND to VCC Common Mode Range

■

3ppm INL, No Missing Codes

■

10ppm Full-Scale Error and 1ppm Offset

■

0.56ppm Noise, 20.8 ENOBs

■

No Latency: Digital Filter Settles in a Single Cycle. Each Conversion Is Accurate, Even After an Input Step

■

Single Supply 2.7V to 5.5V Operation

■

Internal Oscillator—No External Components Required

■

110dB Min, 50Hz/60Hz Notch Filter

■

Pin Compatible with 24-Bit LTC2410/LTC2411

APPLICATIO S

■

Direct Sensor Digitizer

■

Weight Scales

■

Direct Temperature Measurement

■

Gas Analyzers

■

Strain Gauge Transducers

■

Instrumentation

■

Data Acquisition

■

Industrial Process Control

■

DVMs and Meters

20-Bit No Latency ∆Σ

ADCs

with Differential Input and

Differential Reference

DESCRIPTIO

The LTC®2430/LTC2431 are 2.7V to 5.5V micropower 20-bit differential ∆Σ analog-to-digital converters with an integrated oscillator, 3ppm INL and 0.56ppm RMS noise. They use delta-sigma technology and provide single cycle settling time for multiplexed applications. Through a

single pin, the better than 110dB differential mode rejection at 50Hz or 60Hz ±2%, or they can be driven by an external oscillator for a user-defined rejection frequency. The internal oscillator requires no external frequency setting components.

The converters accept any external differential reference voltage from 0.1V to VCC for flexible ratiometric and remote sensing measurement configurations. The fullscale differential input range is from –0.5V The reference common mode voltage, V input common mode voltage, V dently set anywhere within GND to VCC. The DC common mode input rejection is better than 120dB.

The LTC 3-wire digital interface that is compatible with SPI and MICROWIRETM protocols.

, LTC and LT are registered trademarks of Linear Technology Corporation.

No Latency ∆Σ is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.

LTC2430/LTC2431

2430/LTC2431

can be configured for

to 0.5V

REF

, and the

REFCM

, may be indepen-

INCM

communicate through a flexible

REF

TYPICAL APPLICATIO S

+ 0.25V) TO 20V

OUT

3V TO 5V

4.7µF

0.1µF

ANALOG INPUT RANGE

TO 0.5V

–0.5V

REF

LT1790

LTC2431

REF

SCK

–

REF

SDO

–

GND

24301 TA01

0.1µF

= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION

3-WIRE SPI INTERFACE

Total Unadjusted Error

(VCC = 5V, V

VCC = 5V

= 5V

REF

= V

= GND

–1.5–2

= 2.5V

INCM

–0.5–1

INPUT VOLTAGE (V)

INCM

)

REF

1 0

–1

TUE (ppm OF V

–2 –3 –4 –5

–2.5

REF

0.5 1 2

= 5V)

85°C25°C

–45°C

1.5

24301 G01

2.5

24301f

Page 2

LTC2430/LTC2431

1 2 3 4 5

REF

–

10 9 8 7 6

SCK SDO CS GND

TOP VIEW

MS PACKAGE

10-LEAD PLASTIC MSOP

WWWU

ABSOLUTE AXI U RATI GS

(Notes 1, 2)

Supply Voltage (VCC) to GND.......................–0.3V to 7V

Analog Input Pins Voltage

to GND......................................... –0.3V to (VCC + 0.3V)

Reference Input Pins Voltage

to GND......................................... –0.3V to (VCC + 0.3V)

Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)

PACKAGE/ORDER I FOR ATIO

TOP VIEW

GND

REF

–

REF

–

GND

GN PACKAGE

16-LEAD PLASTIC SSOP

= 125°C, θJA = 110°C/W

JMAX

GND

SCK

SDO

GND

ORDER PART NUMBER

LTC2430CGN LTC2430IGN

GN PART MARKING

2430 2430I

Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)

Operating Temperature Range

LTC2430C/LTC2431C ..............................0°C to 70°C

LTC2430I/LTC2431I ........................... – 40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

ORDER PART NUMBER

LTC2431CMS LTC2431IMS

MS PART MARKING

= 125°C, θJA = 120°C/W

JMAX

LTXD LTXE

ELECTRICAL CHARACTERISTICS

Consult LTC Marketing for parts specified with wider operating temperature ranges.

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 0.1V ≤ V Integral Nonlinearity 4.5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, V

5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, V REF+ = 2.5V, REF– = GND, V

Offset Error 2.5V ≤ REF+ ≤ VCC, REF– = GND, ● 520 µV

GND ≤ IN

Offset Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, 50 nV/°C

GND ≤ IN+ = IN– ≤ V

Positive Full-Scale Error 2.5V ≤ REF+ ≤ VCC, REF– = GND, ● 10 20 ppm of V

IN+ = 0.75REF+, IN– = 0.25 • REF

Positive Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, 0.1 ppm of V

IN+ = 0.75REF+, IN– = 0.25 • REF

Negative Full-Scale Error 2.5V ≤ REF+ ≤ VCC, REF– = GND, ● 10 20 ppm of V

IN+ = 0.25 • REF+, IN– = 0.75 • REF

Negative Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, 0.1 ppm of V

Total Unadjusted Error 4.5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, V

5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, V REF+ = 2.5V, REF– = GND, V

Output Noise 5V ≤ VCC ≤ 5.5V, REF+ = 5V, V

GND ≤ IN– = IN+ ≤ 5V, (Note 13)

≤ VCC, –0.5 • V

REF

= IN– ≤ VCC (Note 14)

≤ VIN ≤ 0.5 • V

REF

= 1.25V (Note 6) 10 ppm of V

INCM

= 0.25 • REF+, IN– = 0.75 • REF

= 1.25V 15 ppm of V

INCM

REF

(Note 5) ● 20 Bits

REF

= 1.25V (Note 6) 2 ppm of V

INCM

= 2.5V (Note 6) ● 3 20 ppm of V

INCM

REF

= 1.25V 3 ppm of V

INCM

= 2.5V 6 ppm of V

INCM

REF

– = GND, 2.8 µV

REF REF REF

REF

/°C

REF

/°C

REF REF REF

RMS

24301f

Page 3

LTC2430/LTC2431

CO VERTER CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Common Mode Rejection DC 2.5V ≤ REF+ ≤ VCC, REF– = GND, ● 110 120 dB

GND ≤ IN

Input Common Mode Rejection 2.5V ≤ REF+ ≤ VCC, REF– = GND, ● 140 dB 60Hz ±2% GND ≤ IN

Input Common Mode Rejection 2.5V ≤ REF+ ≤ VCC, REF– = GND, ● 140 dB 50Hz ±2% GND ≤ IN

Input Normal Mode Rejection (Notes 5, 7) ● 110 140 dB 60Hz ±2%

Input Normal Mode Rejection (Notes 5, 8) ● 110 140 dB 50Hz ±2%

Reference Common Mode 2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V, ● 130 140 dB Rejection DC V

Power Supply Rejection, DC REF+ = 2.5V, REF– = GND, IN– = IN+ = GND 110 dB Power Supply Rejection, 60Hz ±2% REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7) 120 dB Power Supply Rejection, 50Hz ±2% REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 8) 120 dB

–

= IN+ ≤ 5V (Note 5)

–

= IN+ ≤ 5V, (Notes 5, 7)

–

= IN+ ≤ 5V, (Notes 5, 8)

= 2.5V, IN– = IN+ = GND (Note 5)

REF

The ● denotes specifications which apply over the full operating

A ALOG I PUT A D REFERE CE

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

–

IN V

REF

–

REF V

REF

CS (IN+)IN CS (IN–)IN CS (REF+)REF CS (REF–)REF I I I I

(IN+)IN+ DC Leakage Current CS = VCC, IN+ = GND ● –10 1 10 nA

DC_LEAK

(IN–)IN– DC Leakage Current CS = VCC, IN– = V

DC_LEAK

(REF+)REF+ DC Leakage Current CS = VCC, REF+ = V

DC_LEAK

(REF–)REF– DC Leakage Current CS = VCC, REF– = GND ● –10 1 10 nA

DC_LEAK

Absolute/Common Mode IN+ Voltage ● GND – 0.3V VCC + 0.3V V Absolute/Common Mode IN– Voltage ● GND – 0.3V VCC + 0.3V V Input Differential Voltage Range ● –V

(IN

– IN–) Absolute/Common Mode REF+ Voltage ● 0.1 V Absolute/Common Mode REF– Voltage ● GND VCC – 0.1V V Reference Differential Voltage Range ● 0.1 V

– REF–)

(REF

Sampling Capacitance 1.5 pF

–

Sampling Capacitance 1.5 pF

–

Sampling Capacitance 1.5 pF

● –10 1 10 nA

/2 V

REF

/2 V

REF

24301f

Page 4

LTC2430/LTC2431

DIGITAL I PUTS A D DIGITAL OUTPUTS

operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

High Level Input Voltage 2.7V ≤ VCC ≤ 5.5V ● 2.5 V CS, F

Low Level Input Voltage 4.5V ≤ VCC ≤ 5.5V ● 0.8 V CS, F

High Level Input Voltage 2.7V ≤ VCC ≤ 5.5V (Note 9) ● 2.5 V SCK 2.7V ≤ V

Low Level Input Voltage 4.5V ≤ VCC ≤ 5.5V (Note 9) ● 0.8 V SCK 2.7V ≤ V

Digital Input Current 0V ≤ VIN ≤ V CS, F

Digital Input Current 0V ≤ VIN ≤ VCC (Note 9) ● –10 10 µA SCK

Digital Input Capacitance 10 pF CS, F

Digital Input Capacitance (Note 9) 10 pF SCK

High Level Output Voltage IO = –800µA ● VCC – 0.5V V SDO

Low Level Output Voltage IO = 1.6mA ● 0.4 V SDO

High Level Output Voltage IO = –800µA (Note 10) ● VCC – 0.5V V SCK

Low Level Output Voltage IO = 1.6mA (Note 10) ● 0.4 V SCK

Hi-Z Output Leakage ● –10 10 µA SDO

2.7V ≤ VCC ≤ 3.3V 2.0 V

2.7V ≤ VCC ≤ 5.5V 0.6 V

≤ 3.3V (Note 9) 2.0 V

≤ 5.5V (Note 9) 0.6 V

The ● denotes specifications which apply over the full

● –10 10 µA

POWER REQUIRE E TS

otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage ● 2.7 5.5 V Supply Current

Conversion Mode CS = 0V (Note 12) Sleep Mode CS = V

Sleep Mode CS = V

The ● denotes specifications which apply over the full operating temperature range,

● 200 300 µA

(Note 12) ● 410 µA

, 2.7V ≤ VCC ≤ 3.3V 2 µA

(Note 12)

24301f

Page 5

LTC2430/LTC2431

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

EOSC

HEO

LEO

CONV

ISCK

ESCK

LESCK

HESCK

DOUT_ISCK

DOUT_ESCK

KQMAX

KQMIN

External Oscillator Frequency Range ● 5 2000 kHz External Oscillator High Period ● 0.25 200 µs External Oscillator Low Period ● 0.25 200 µs Conversion Time FO = 0V ● 130.86 133.53 136.20 ms

Internal SCK Frequency Internal Oscillator (Note 10) 19.2 kHz

Internal SCK Duty Cycle (Note 10) ● 45 55 % External SCK Frequency Range (Note 9) ● 2000 kHz External SCK Low Period (Note 9) ● 250 ns External SCK High Period (Note 9) ● 250 ns Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12) ● 1.22 1.25 1.28 ms

External SCK 24-Bit Data Output Time (Note 9) ● 24/f CS ↓ to SDO Low Z ● 0 200 ns CS ↑ to SDO High Z ● 0 200 ns CS ↓ to SCK ↓ (Note 10) ● 0 200 ns CS ↓ to SCK ↑ (Note 9) ● 50 ns SCK ↓ to SDO Valid ● 220 ns SDO Hold After SCK ↓ (Note 5) ● 15 ns SCK Set-Up Before CS ↓ ● 50 ns SCK Hold After CS ↓ ● 50 ns

The ● denotes specifications which apply over the full operating temperature

= V

External Oscillator (Note 11)

External Oscillator (Notes 10, 11) f

External Oscillator (Notes 10, 11)

● 157.03 160.23 163.44 ms

● 20510/f

● 192/f

(in kHz) ms

EOSC

/8 kHz

EOSC

(in kHz) ms

EOSC

(in kHz) ms

ESCK

Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired.

Note 2: All voltage values are with respect to GND. Note 3: V

REF

= IN+ – IN–, V

Note 4: F source with f

= 2.7V to 5.5V unless otherwise specified.

= REF+ – REF–, V

INCM

pin tied to GND or to VCC or to external conversion clock

= 153600Hz unless otherwise specified.

EOSC

= (REF+ + REF–)/2;

REFCM

= (IN+ + IN–)/2.

Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from

a straight line passing through the actual endpoints of the transfer curve. The deviation is calculated as the measured code minus the expected value.

Note 7: FO = 0V (internal oscillator) or f

= 153600Hz ±2%

EOSC

(external oscillator). Note 8: F

= VCC (internal oscillator) or f

= 128000Hz ±2%

EOSC

(external oscillator).

Note 9: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is f

and is expressed in kHz.

ESCK

Note 10: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance C

Note 11: The external oscillator is connected to the F oscillator frequency, f

, is expressed in kHz.

EOSC

= 20pF.

LOAD

pin. The external

Note 12: The converter uses the internal oscillator. F

= 0V or FO = VCC.

Note 13: The output noise includes the contribution of the internal calibration operations.

Note 14: Guaranteed by design and test correlation.

24301f

Page 6

LTC2430/LTC2431

TYPICAL PERFOR A CE CHARACTERISTICS

Total Unadjusted Error (VCC = 5V, V

VCC = 5V

= 5V

REF

= V

INCM

= GND

–1.5–2

INCM

INPUT VOLTAGE (V)

)

REF

1 0

–1

TUE (ppm OF V

–2 –3 –4 –5

–2.5

Integral Nonlinearity (VCC = 5V, V

5 4 3

)

REF

1 0

–1

INL (ppm OF V

–2

VCC = 5V

–3

= 5V

REF

= V

INCM

–4

= GND

–5

–2.5

= 2.5V

INCM

–1.5–2

INPUT VOLTAGE (V)

REF

= 2.5V

–0.5–1

REF

25°C

–45°C

85°C

–0.5–1

= 5V)

0.5 1 2

= 5V)

0.5 1 2

85°C25°C

–45°C

1.5

24301 G01

24301 G04

2.5

Total Unadjusted Error (VCC = 5V, V

VCC = 5V

REF

INCM

= GND

)

REF

1 0

–1

TUE (ppm OF V

–2 –3 –4 –5

–1.25

= 2.5V

REF

= V

= 1.25V

INCM

–0.75–1

–0.25–0.5

INPUT VOLTAGE (V)

Integral Nonlinearity (VCC = 5V, V

VCC = 5V

= 2.5V

REF

INCM

= GND

)

REF

1 0

–1

INL (ppm OF V

–2 –3 –4 –5

–1 0.25 0.5 1

–1.25

REF

= V

= 1.25V

INCM

–0.75

–0.25–0.5

INPUT VOLTAGE (V)

= 2.5V)

–45°C

85°C

0.25 0.5 1

= 2.5V)

85°C

–45°C

25°C

0.75

24301 G02

24301 G05

1.25

Total Unadjusted Error (VCC = 2.7V, V

VCC = 2.7V

= 2.5V

REF

)

REF

–5

TUE (ppm OF V

–10

–15

–20

–1.25

V F

INCM

= V

= GND

–0.75

= 1.25V

INCM

–0.25–0.5

INPUT VOLTAGE (V)

Integral Nonlinearity (VCC = 2.7V, V

VCC = 2.7V

= 2.5V

REF

= V

INCM

= GND

)

REF

–5

INL (ppm OF V

–10

–15

–20

–1.25

= 1.25V

INCM

–0.75

–0.25–0.5

INPUT VOLTAGE (V)

= 2.5V)

REF

25°C

0.25 1.250.5–1 0 1

= 2.5V)

REF

25°C

0.25 1.250.5–1 0 1

–45°C

85°C

0.75

24301 G03

–45°C

85°C

0.75

24301 G06

Noise Histogram (Output Rate =

7.5Hz, VCC = 5V, V

10,000 CONSECUTIVE READINGS

= 5V

REF

= 0V

= 2.5V

INCM

= GND

= 25°C

NUMBER OF READINGS (%)

–1.5 –0.5 0.5 2.51–2 –1 0 2

–2.5

OUTPUT CODE (ppm OF V

REF

= 5V)

GAUSSIAN DISTRIBUTION m = –0.25ppm σ = 0.550ppm

1.5 )

REF

24301 G07

Noise Histogram (Output Rate =

7.5Hz, VCC = 2.7V, V

10,000 CONSECUTIVE

READINGS V

= 2.7V

= 2.5V

REF

= 0V

= 2.5V

INCM

= GND

= 25°C

8 6

NUMBER OF READINGS (%)

4 2 0

–2–3

–4

OUTPUT CODE (ppm OF V

0–1

REF

23 5

= 2.5V)

GAUSSIAN DISTRIBUTION m = –1.07ppm σ = 1.06ppm

)

REF

24301 G08

RMS Noise vs Input Differential Voltage

1.0 VCC = 5V

0.9

= 5V

REF

= 2.5V

INCM

0.8

)

= GND

REF

= 25°C

0.7

0.6

0.5

0.4

0.3

RMS NOISE (ppm OF V

0.2

0.1

–1.5–2

–2.5

–0.5–1

INPUT DIFFERENTIAL VOLTAGE (V)

0.5 1 2

1.5

2.5

24301 G10

24301f

Page 7

VCC (V)

2.7 3.1

2.4

RMS NOISE (µV)

2.8

3.4

3.5

4.3

4.7

24301 G13

2.6

3.2

3.0

3.9

5.1

5.5

REF+ = 2.5V REF

–

= GND

= 0V

INCM

= GND

= 25°C

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2430/LTC2431

RMS Noise vs V

3.4

3.2

3.0

2.8

RMS NOISE (µV)

2.6

2.4 –1 0

RMS Noise vs V

3.4 VCC = 5V

–

REF V

= 0V

3.2 V

INCM

= GND

= 25°C

3.0

2.8

RMS NOISE (µV)

2.6

2.4

= GND

INCM

VCC = 5V

REF

= 5V

–

REF

= GND

= 0V

= GND

INCM

= GND

= 25°C

INCM

(V)

24301 G11

REF

(V)

REF

24301 G14

RMS Noise vs Temperature (TA)

3.4 VCC = 5V

= 5V

REF

= 0V

3.2

3.0

2.8

RMS NOISE (µV)

2.6

2.4

1.0

0.8

)

0.6

REF

0.4

0.2

–0.2 –0.4 –0.6

OFFSET ERROR (ppm OF V

–0.8

–1.0

= GND

INCM

= GND

–50

–25

TEMPERATURE (°C)

Offset Error vs V

VCC = 5V

= 5V

REF

–

REF

= GND

= 0V

= GND

= 25°C

–1

02550

INCM

(V)

INCM

75 100

24301 G12

24301 G15

RMS Noise vs V

Offset Error vs Temperature

1.0

0.8

)

0.6

REF

0.4

0.2 0

–0.2 –0.4

VCC = 5V

=5V

REF

–0.6

OFFSET ERROR (ppm OF V

–0.8 –1.0

–45

V V F

IN INCM

= 0V

= GND

–30 0

–15

TEMPERATURE (°C)

30 90

24301 G16

1.0

0.8

)

0.6

REF

0.4

0.2

–0.2 –0.4 –0.6

OFFSET ERROR (ppm OF V

–0.8 –1.0

Offset Error vs V

REF+ = V

REF– = GND

= 0V

= GND

INCM

= GND

= 25°C

3.1

3.5

2.7

3.9 VCC (V)

4.3

4.7

5.1

24301 G17

5.5

Offset Error vs V

5 4

)

REF

2 1 0

–1

VCC = 5V

–

–2

= GND

REF

= 0V

–3

OFFSET ERROR (ppm OF V

= GND

INCM

= GND

–4

= 25°C

–5

REF

(V)

REF

24301 G18

Full-Scale Error vs Temperature

)

REF

VCC = 5V

= 5V

REF

= GND

INCM

–10

FULL-SCALE ERROR (ppm OF V

–20

–45

–30 –15 0 15

+FS ERROR

= 2.5V

–FS ERROR

30 45 60 75 90

TEMPERATURE (°C)

24301 G19

24301f

Page 8

LTC2430/LTC2431

TEMPERATURE (°C)

–45

SLEEP MODE CURRENT (µA)

–15

30 90

24301 G27

–30 0

VCC = 5.5V

VCC = 2.7V

VCC = 5V

VCC = 3V

FO = GND CS = V

SCK = NC SDO = NC

TYPICAL PERFOR A CE CHARACTERISTICS

Full-Scale Error vs V

)

REF

+FS ERROR

–5

–FS ERROR

–10

FULL-SCALE ERROR (ppm OF V

–15

–20

123 53.50.5 1.5 2.5 4.5

REF

PSRR vs Frequency at V

VCC = 4.1V

REF+ = 2.5V

–20

–

= GND

REF

= GND

–

–40

= GND

= 25°C

–60

–80

REJECTION (dB)

–100

–120

–140

10 100

FREQUENCY AT VCC (Hz)

REF

VCC = 5V

–

= GND

REF

= GND

= 0.5V

INCM

TA = 25°C

(V)

10k 1M

1k 100k

REF

24301 G20

24301 G23

Full-Scale Error vs V

5 4

)

REF

+FS ERROR

2 1 0

–1

–2

–3

FULL-SCALE ERROR (ppm OF V

–4 –5

–FS ERROR

3.1 3.9 5.1 5.5

2.7

3.5 4.3 4.7 VCC (V)

PSRR vs Frequency at V

VCC = 4.1VDC ±0.7V

REF

15170

= 2.5V

–

= GND

REF

= GND

–

= GND

= 25°C

15220 15270 15370

FREQUENCY AT VCC (Hz)

–20

–40

–60

–80

REJECTION (dB)

–100

–120

–140

REF

REF F

= GND

INCM

TA = 25°C

15320

= 2.5V

–

= GND

= 0.5V

REF

24301 G21

24301 G24

PSRR vs Frequency at V

VCC = 4.1VDC ±1.4V

= 2.5V

REF

–20

–

= GND

REF

= GND

–

–40

= GND

= 25°C

–60

–80

REJECTION (dB)

–100

–120

–140

FREQUENCY AT VCC (Hz)

100

140

120 160

Conversion Current vs Temperature

240

230

220

210

FO = GND

200

CS = GND SCK = NC

190

SDO = NC

180

CONVERSION CURRENT (µA)

170

160

–45

VCC = 5.5V

VCC = 5V

VCC = 3V

VCC = 2.7V

–15 15 45–30 9003060

TEMPERATURE (°C)

180

220200

24301 G22

24301 G25

1000

900

800

700

600

500

400

SUPPLY CURRENT (µA)

300

200

100

Conversion Current vs Output Data Rate

= V

REF

IN+ = GND

–

= GND

IN SCK = NC SDO = NC SDI = GND CS = GND

= EXT OSC

= 25°C

10 20 30 40 50 100

OUTPUT DATA RATE (READINGS/SEC)

VCC = 5V

VCC = 3V

60 70 80 90

Sleep Mode Current vs Temperature

24301 G26

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LTC2430/LTC2431

PI FU CTIO S

GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these pins to a ground plane through a low impedance connection. All seven pins must be connected to ground for proper operation.

VCC (Pin 2): Positive Supply Voltage. Bypass to GND with a 10µF tantalum capacitor in parallel with 0.1µF ceramic capacitor as close to the part as possible.

REF+ (Pin 3), REF– (Pin 4): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, is maintained more positive than the reference negative input, REF–, by at least 0.1V.

IN+ (Pin 5), IN– (Pin 6): Differential Analog Input. The voltage on these pins can have any value between GND – 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ – IN–) extends from – 0.5 • (V the converter produces unique overrange and underrange output codes.

CS (Pin 11): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion.

REF

(LTC2430)

) to 0.5 • (V

REF

). Outside this input range

SDO (Pin 12): Three-State Digital Output. During the Data Output period, this pin is used as serial data output. When the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW.

SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as digital input for the external serial interface clock during the Data Output period. A weak internal pullup is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS.

FO (Pin 14): Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion time. When the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. When the FO pin is connected to GND (FO = OV), the converter uses its internal oscillator and the digital filter first null is located at 60Hz. When F is driven by an external clock signal with a frequency f the converter uses this signal as its system clock and the digital filter first null is located at a frequency f

EOSC

/2560.

(LTC2431) VCC (Pin 1): Positive Supply Voltage. Bypass to GND

(Pin␣ 6) with a 10µF tantalum capacitor in parallel with

0.1µF ceramic capacitor as close to the part as possible. REF+ (Pin 2), REF– (Pin 3): Differential Reference Input.

The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, is maintained more positive than the reference negative input, REF–, by at least 0.1V.

IN+ (Pin 4), IN– (Pin 5): Differential Analog Input. The voltage on these pins can have any value between GND – 0.3V and VCC + 0.3V. Within these limits, the converter bipolar input range (VIN = IN+ – IN–) extends

from –0.5 • (V range, the converter produces unique overrange and underrange output codes.

GND (Pin 6): Ground. Connect this pin to a ground plane through a low impedance connection.

CS (Pin 7): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion.

) to 0.5 • (V

REF

). Outside this input

REF

24301f

Page 10

LTC2430/LTC2431

PI FU CTIO S

(LTC2431)

SDO (Pin 8): Three-State Digital Output. During the Data

Output period, this pin is used as the serial data output. When the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW.

SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as the digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as the digital input for the external serial interface clock during the Data Output period. A weak internal pull-up is automatically activated in Internal Serial

FU CTIO AL BLOCK DIAGRA

Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS.

FO (Pin 10): Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion time. When the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. When the FO pin is connected to GND (FO = OV), the converter uses its internal oscillator and the digital filter first null is located at 60Hz. When F is driven by an external clock signal with a frequency f

EOSC

, the converter uses this signal as its system clock and the digital filter first null is located at a frequency f

INTERNAL

OSCILLATOR

EOSC

/2560.

GND

REF REF

–

+ –

TEST CIRCUITS

SDO

DAC

1.69k

Hi-Z TO V

VOL TO V

VOH TO Hi-Z

AUTOCALIBRATION

AND CONTROL

∫∫∫

∑

ADC

DECIMATING FIR

SERIAL

INTERFACE

(INT/EXT)

SDO

SCK

2431 FD

Figure 1

1.69k

SDO

= 20pF

LOAD

2431 TA03

Hi-Z TO V VOH TO V VOL TO Hi-Z

LOAD

2431 TA04

= 20pF

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LTC2430/LTC2431

CONVERTER OPERATION

Converter Operation Cycle

The LTC2430/LTC2431 are low power, delta-sigma analogto-digital converters with an easy-to-use 3-wire serial interface (see Figure 1). Their operation is made up of three states. The converters’ operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 2). The 3-wire interface consists of serial data output (SDO), serial clock (SCK) and chip select (CS).

Initially, the LTC2430/LTC2431 perform a conversion. Once the conversion is complete, the device enters the sleep state. The part remains in the sleep state as long as CS is HIGH. While in this sleep state, power consumption is reduced by nearly two orders of magnitude. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state.

Once CS is pulled LOW, the device exits the low power mode and enters the data output state. If CS is pulled HIGH before the first rising edge of SCK, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. If CS remains LOW after the first rising edge of SCK, the device begins outputting the conversion result. Taking CS high at this point will terminate the data output state and start a new conversion. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the

falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3). The data output state is concluded once 24 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats.

Through timing control of the CS and SCK pins, the LTC2430/LTC2431 offer several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section.

Conversion Clock

A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a Sinc or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz or 60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter system clock. The LTC2430/LTC2431 incorporate a highly accurate on-chip oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2430/ LTC2431 achieve a minimum of 110dB rejection at the line frequency (50Hz or 60Hz ±2%).

Ease of Use

CONVERT

SLEEP

FALSE

CS = LOW

AND

SCK

TRUE

DATA OUTPUT

Figure 2. LTC2430/LTC2431 State Transition Diagram

2431 F02

The

LTC2430/LTC2431

data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog inputs is easy.

The LTC2430/LTC2431 perform offset and full-scale calibrations in every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift.

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Power-Up Sequence

The LTC2430/LTC2431 automatically enter an internal reset state when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.)

When the VCC voltage rises above this critical threshold, the LTC2430 or LTC2431 creates an internal power-onreset (POR) signal with a duration of approximately 1ms. The POR signal clears all internal registers. Following the POR signal, the converter starts a normal conversion cycle and follows the succession of states described above. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval.

Reference Voltage Range

The LTC2430/LTC2431 accept a differential external reference voltage. The absolute/common mode voltage specification for the REF+ and REF– pins covers the entire range from GND to VCC. For correct converter operation, the REF+ pin must always be more positive than the REF– pin.

The LTC2430/LTC2431 can accept a differential reference voltage from 0.1V to VCC. The converter (LTC2430 or LTC2431) output noise is determined by the thermal noise of the front-end circuits, and, as such, its value in microvolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter’s effective resolution. On the other hand, a reduced reference voltage will improve the converter’s overall INL performance. A reduced reference voltage will also improve the converter performance when operated with an external conversion clock (external FO signal) at substantially higher output data rates.

Input Voltage Range

The analog input is truly differential with an absolute/common mode range for the IN+ and IN– input pins extending from GND – 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due

to input leakage current increase rapidly. Within these limits, the LTC2430 or LTC2431 converts the bipolar differential input signal, VIN = IN+ – IN–, from –FS = – 0.5 • V to +FS = 0.5 • V range the converter indicates the overrange or the underrange condition using distinct output codes.

Input signals applied to IN+ and IN– pins may extend by 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the IN+ and IN– pins without affecting the performance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. In addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if V This error has a very strong temperature dependency.

Output Data Format

The LTC2430/LTC2431 serial output data stream is 24 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 21 bits are the conversion result, MSB first. The third and fourth bits together are also used to indicate an underrange condition (the differential input voltage is below – FS) or an overrange condition (the differential input voltage is above +FS).

Bit 23 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete.

Bit 22 (second output bit) is a dummy bit (DMY) and is always LOW.

Bit 21 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW.

Bit 20 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 21 also provides the underrange or overrange indication. If both Bit 21 and Bit 20 are HIGH, the differential input voltage is

where V

REF

= REF+ – REF–. Outside this

REF

= 5V.

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LTC2430/LTC2431

above +FS. If both Bit 21 and Bit 20 are LOW, the differential input voltage is below –FS.

The function of these bits is summarized in Table 1.

Table 1. LTC2430/LTC2431 Status Bits

Bit 23 Bit 22 Bit 21 Bit 20

Input Range EOC DMY SIG MSB

VIN ≥ 0.5 • V 0V ≤ VIN < 0.5 • V –0.5 • V VIN < –0.5 • V

REF

≤ VIN < 0V 0 0 0 1

REF

0011 0010

0000

Bits 20-0 are the 21-bit conversion result MSB first. Bit 0 is the least significant bit (LSB). Data is shifted out of the SDO pin under control of the serial

clock (SCK), see Figure 3. Whenever CS is HIGH, SDO remains high impedance and any externally generated SCK clock pulses are ignored by the internal data out shift register.

In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 23 (EOC) can be captured on the first rising edge of SCK. Bit 22 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 23rd SCK and may be latched on the rising edge of the 24th SCK pulse. On the falling edge of the 24th SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 22) for the next conversion cycle. Table 2 summarizes the output data format.

As long as the voltage on the IN+ and IN– pins is maintained within the –0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any differential input voltage VIN from –FS = –0.5 • V +FS = 0.5 • V

. For differential input voltages greater than

REF

BIT 0

LSB

2431 F03

SDO

SCK

SLEEP

Hi-Z

BIT 23

EOC

1234524

MSBSIG“0”

DATA OUTPUT CONVERSION

BIT 19BIT 20BIT 21BIT 22

Figure 3. Output Data Timing

Table 2. LTC2430/LTC2431 Output Data Format

Differential Input Voltage Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 … Bit 0 V

* EOC DMY SIG MSB LSB

VIN* ≥ 0.5 • V

0.5 • V

REF

0.25 • V

REF

0.25 • V

REF

0 00100 0 0…0 –1LSB 0 0011 1 1…1 –0.25 • V –0.25 • V –0.5 • V VIN* < –0.5 • V *The differential input voltage VIN = IN+ – IN–.

**The differential reference voltage V

** 00110 0 0…0

REF

** – 1LSB 00101 1 1…1

** 0 0101 0 0…0 ** – 1LSB 00100 1 1…1

** 0 0011 0 0…0

REF

** – 1LSB 00010 1 1…1

REF

** 00010 0 0…0

REF

** 00001 1 1…1

REF

= REF+ – REF–.

REF

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APPLICATIO S I FOR ATIO

+FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages below –FS, the conversion result is clamped to the value corresponding to –FS – 1LSB.

Frequency Rejection Selection (FO)

The LTC2430/LTC2431 internal oscillator provides better than 110dB normal mode rejection at the line frequency and all its harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz rejection, FO should be connected to GND while for 50Hz rejection the FO pin should be connected to VCC.

The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level. A selection change during the sleep or data output states will not disturb the converter operation. If the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected.

When a fundamental rejection frequency different from 50Hz or 60Hz is required or when the converter must be synchronized with an outside source, the LTC2430 or LTC2431 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency f

of the external signal must

EOSC

be at least 5kHz to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods t and t

are observed.

LEO

HEO

While operating with an external conversion clock of a frequency f

, the LTC2430 or LTC2431 provides better

EOSC

than 110dB normal mode rejection in a frequency range f

/2560 ±4% and its harmonics. The normal mode

EOSC

rejection as a function of the input frequency deviation from f

/2560 is shown in Figure 4.

EOSC

Whenever an external clock is not present at the FO pin, the converter (LTC2430 or LTC2431) automatically activates its internal oscillator and enters the Internal Conversion Clock mode. Its operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. If the change occurs during the conversion state, the result of the conversion in

–80 –85 –90

–95 –100 –105 –110 –115 –120 –125

NORMAL MODE REJECTION (dB)

–130 –135 –140

–12–8–404812

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DEVIATION FROM NOTCH FREQUENCY f

Figure 4. LTC2430/LTC2431 Normal Mode Rejection When Using an External Oscillator of Frequency f

EOSC

/2560(%)

2431 F04

EOSC

progress may be outside specifications but the following conversions will not be affected. If the change occurs during the data output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid.

Table 3 summarizes the duration of each state and the achievable output data rate as a function of FO.

SERIAL INTERFACE PINS

The LTC2430/LTC2431 transmit the conversion results and receives the start of conversion command through a synchronous 3-wire interface. During the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result.

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock.

In the Internal SCK mode of operation, the SCK pin is an output and the converter (LTC2430 or LTC2431) creates its own serial clock by dividing the internal conversion clock by 8. In the External SCK mode of operation, the SCK pin is used as input. The internal or external SCK mode is selected on power-up and then reselected every time a HIGH-to-LOW transition is detected at the CS pin. If SCK

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Table 3. LTC2430/LTC2431 State Duration

State Operating Mode Duration

CONVERT Internal Oscillator FO = LOW 133ms, Output Data Rate ≤ 7.5 Readings/s

(60Hz Rejection) FO = HIGH 160ms, Output Data Rate ≤ 6.2 Readings/s

(50Hz Rejection)

External Oscillator FO = External Oscillator 20510/f

with Frequency f (f

/2560 Rejection)

EOSC

SLEEP As Long As CS = HIGH DATA OUTPUT Internal Serial Clock FO = LOW/HIGH As Long As CS = LOW But Not Longer Than 1.25ms

(Internal Oscillator) (24 SCK cycles) FO = External Oscillator with As Long As CS = LOW But Not Longer Than 192/f

Frequency f

External Serial Clock with As Long As CS = LOW But Not Longer Than 24/f Frequency f

kHz (24 SCK cycles)

SCK

EOSC

kHz

EOSC

kHz (24 SCK cycles)

s, Output Data Rate ≤ f

EOSC

/20510 Readings/s

EOSC

SCK

is HIGH or floating at power-up or during this transition, the converter enters the internal SCK mode. If SCK is LOW at power-up or during this transition, the converter enters the external SCK mode.

Serial Data Output (SDO)

The serial data output pin, SDO, provides the result of the last conversion as a serial bit stream (MSB first) during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states.

When CS is HIGH, the SDO driver is switched to a high impedance state. This allows sharing the serial interface with other devices. If CS is LOW during the convert or sleep state, SDO will output EOC. If CS is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW.

Chip Select Input (CS)

The active LOW chip select, CS, is used to test the conversion status and to enable the data output transfer as described in the previous sections.

new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i.e., after the first rising edge of SCK occurs with CS␣ =␣ LOW).

Finally, CS can be used to control the free-running modes of operation, see Serial Interface Timing Modes section. Grounding CS will force the ADC to continuously convert at the maximum output rate selected by FO.

SERIAL INTERFACE TIMING MODES

The LTC2430/LTC2431’s 3-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 2- or 3-wire I/O, single cycle conversion. The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW or F

= HIGH) or an external oscillator connected to the FO pin. Refer to Table␣ 4 for a summary.

External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible)

In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The converter (LTC2430 or LTC2431) will abort any serial data transfer in progress and start a

This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 5.

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Table 4. LTC2430/LTC2431 Interface Timing Modes

Conversion Data Connection

SCK Cycle Output and

Configuration Source Control Control Waveforms

External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 5, 6 External SCK, 2-Wire I/O External SCK SCK Figure 7 Internal SCK, Single Cycle Conversion Internal CS ↓ CS ↓ Figures 8, 9 Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 10

2.7V TO 5.5V

1µF

LTC2430/ LTC2431

REF REF

IN IN GND

–

SDO

SCK

(EXTERNAL)

TEST EOC

CONVERSION

TEST EOC

SLEEP SLEEP

TEST EOC

REFERENCE

VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

TO 0.5V

–0.5V

REF

BIT 23

EOC

Figure 5. External Serial Clock, Single Cycle Operation

The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge.

The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin. EOC␣ =␣ 1 while a conversion is in progress and EOC = 0 if the conversion is over. With CS HIGH, the device automatically enters the low power sleep state once the conversion is complete.

= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION

3-WIRE

SPI INTERFACE

BIT 0BIT 19 BIT 18BIT 20BIT 21BIT 22

LSBMSBSIG

DATA OUTPUT CONVERSION

TEST EOC

Hi-ZHi-ZHi-Z

2431 F05

SCK

SDO

enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. On the 24th falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is in progress.

At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. As described above, CS may be pulled LOW at any time in order to monitor the conversion status.

When CS is low, the device enters the data output mode. The result is held in the internal static shift register until the first SCK rising edge is seen while CS is LOW. Data is shifted out the SDO pin on each falling edge of SCK. This

Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first rising edge and the 24th falling edge of SCK, see Figure 6. On the rising edge of CS,

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LTC2430/LTC2431

SDO

SCK

(EXTERNAL)

SLEEP

DATA

OUTPUT

EOC

TEST EOC

CONVERSION

SLEEP

Hi-Z

TEST EOC

(OPTIONAL)

2.7V TO 5.5V

1µF

REFERENCE

VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

TO 0.5V

–0.5V

REF

BIT 23BIT 0

EOC

Hi-Z Hi-ZHi-Z

SLEEP

REF REF

IN IN GND

LTC2430/

LTC2431

–

SCK

SDO

DATA OUTPUT

= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION

3-WIRE SPI INTERFACE

MSBSIG

Figure 6. External Serial Clock, Reduced Data Output Length

BIT 8BIT 19 BIT 9BIT 20BIT 21BIT 22

TEST EOC

CONVERSION

2431 F06

the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion.

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 7. CS may be permanently tied to ground, simplifying the user interface or isolation barrier.

The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 1ms after VCC exceeds 2V. The level applied to SCK at this time determines if SCK is internal or external. SCK must be driven LOW prior to the end of POR in order to enter the external serial clock timing mode.

Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller indicating the conversion result is ready. EOC = 1 while the conversion is in progress and

EOC␣ =␣ 0 once the conversion ends. On the falling edge of EOC, the conversion result is loaded into an internal static shift register. Data is shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising edge of SCK. EOC can be latched on the first rising edge of SCK. On the 24th falling edge of SCK, SDO goes HIGH (EOC␣ =␣ 1) indicating a new conversion has begun.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 8.

In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CS. The device will not enter the internal serial clock mode if SCK is driven LOW on the falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven.

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APPLICATIO S I FOR ATIO

ANALOG INPUT RANGE

–0.5V

REFERENCE

VOLTAGE

0.1V TO V

TO 0.5V

REF

2.7V TO 5.5V

1µF

REF

LTC2430/

LTC2431

REF

–

REF

–

IN GND

SCK

SDO

= 50Hz REJECTION

= EXTERNAL OSCILLATOR = 60Hz REJECTION

2-WIRE I/O

SDO

SCK

(EXTERNAL)

CONVERSION

BIT 23

EOC

MSBSIG

DATA OUTPUT CONVERSION

BIT 19 BIT 18BIT 20BIT 21BIT 22

Figure 7. External Serial Clock, CS = 0 Operation

2.7V TO 5.5V

1µF

ANALOG INPUT RANGE

–0.5V

REF

EOCtest

REFERENCE

VOLTAGE

0.1V TO V

TO 0.5V

REF

REF REF

IN IN GND

LTC2430/

LTC2431

–

SCK

SDO

= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION

3-WIRE SPI INTERFACE

BIT 0

LSB

2431 F07

10k

SDO

SCK

(INTERNAL)

TEST EOC

Hi-Z Hi-Z Hi-Z Hi-Z

TEST EOC

(OPTIONAL)

SLEEP

BIT 23

EOC

MSBSIG

DATA OUTPUT CONVERSIONCONVERSION

BIT 19 BIT 18BIT 20BIT 21BIT 22

BIT 0

LSB

TEST EOC

2431 F08

Figure 8. Internal Serial Clock, Single Cycle Operation

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LTC2430/LTC2431

The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state.

When testing EOC, if the conversion is complete (EOC = 0), the device will exit the sleep state and enter the data output state if CS remains LOW. In order to allow the device to return to the low power sleep state, CS must be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time t (if EOC = 0) or t

after EOC goes LOW (if CS is LOW

EOCtest

during the falling edge of EOC). The value of t

after the falling edge of CS

EOCtest

is 23µs

if the device is using its internal oscillator (FO = logic LOW or HIGH). If FO is driven by an external oscillator of frequency f HIGH before time t

EOSC

, then t

EOCtest

is 3.6/f

. If CS is pulled

EOSC

, the device returns to the sleep state. The conversion result is held in the internal static shift register.

If CS remains LOW longer than t

, the first rising

EOCtest

edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins on this first rising edge of SCK and concludes after the 24th rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH and a new conversion starts.

Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first and 24th rising edge of SCK, see Figure 9. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. If CS is pulled HIGH while the converter is driving SCK LOW, the

SDO

SCK

(INTERNAL)

SLEEP

2.7V TO 5.5V

1µF

REFERENCE

VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

–0.5V

TO 0.5V

REF

EOCtest

BIT 0

EOC

Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

DATA

OUTPUT

TEST EOC

CONVERSION

SLEEP

TEST EOC

(OPTIONAL)

SLEEP

EOCtest

BIT 23

EOC

REF

REF REF

IN IN GND

LTC2430/

LTC2431

–

SCK

SDO

DATA OUTPUT

MSBSIG

= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION

3-WIRE SPI INTERFACE

BIT 19 BIT 18BIT 20BIT 21BIT 22

BIT 8

10k

TEST EOC

CONVERSION

2431 F09

Figure 9. Internal Serial Clock, Reduced Data Output Length

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APPLICATIO S I FOR ATIO

internal pull-up is not available to restore SCK to a logic HIGH state. This will cause the device to exit the internal serial clock mode on the next falling edge of CS. This can be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CS HIGH when SCK is LOW.

Whenever SCK is LOW, the

LTC2430/LTC2431

’s internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven if the device is in the internal SCK timing mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the

LTC2430/LTC2431

’s internal pull-up remains disabled. Hence, SCK remains LOW. On the next falling edge of CS, the device is switched to the external SCK timing mode. By adding an external 10k pull-up resistor to SCK, this pin goes HIGH once the external driver goes Hi-Z. On the next CS falling edge, the device will remain in the internal SCK timing mode.

A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. Once CS goes HIGH (within the time period defined above as t

), the internal pull-up is

EOCtest

activated. For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a

HIGH level before CS goes low again. This is not a concern under normal conditions where CS remains LOW after detecting EOC = 0. This situation is easily overcome by adding an external 10k pull-up resistor to the SCK pin.

Internal Serial Clock, 2-Wire I/O, Continuous Conversion

This timing mode uses a 2-wire, all output (SCK and SDO) interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 10. CS may be permanently tied to ground, simplifying the user interface or isolation barrier.

The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 1ms after VCC exceeds 2V. An internal weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected).

During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the

SDO

SCK

(INTERNAL)

2.7V TO 5.5V

1µF

REFERENCE

VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

TO 0.5V

–0.5V

REF

BIT 23

EOC

REF

REF REF

IN IN GND

MSBSIG

LTC2430/

LTC2431

–

DATA OUTPUT CONVERSIONCONVERSION

SCK

SDO

BIT 19 BIT 18BIT 20BIT 21BIT 22

Figure 10. Internal Serial Clock, CS = 0 Continuous Operation

= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION

2-WIRE I/O

BIT 0

LSB

2431 F10

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LTC2430/LTC2431

low power sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and ends after the 24th rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion.

PRESERVING THE CONVERTER ACCURACY

The LTC2430/LTC2431 are designed to reduce as much as possible the conversion result sensitivity to device decoupling, PCB layout, antialiasing circuits, line frequency perturbations and so on. Nevertheless, in order to preserve the extreme accuracy capability of this part, some simple precautions are desirable.

Digital Signal Levels

The LTC2430/LTC2431’s digital interface is easy to use. The digital inputs (FO, CS and SCK in External SCK mode of operation) accept standard TTL/CMOS logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100µs. However, some considerations are required to take advantage of the exceptional accuracy and low supply current of this converter.

During the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the LTC2431 conversion process. Undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to LTC2430/LTC2431 signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance.

Parallel termination near the LTC2430/LTC2431 pin will eliminate this problem but will increase the driver power dissipation. A series resistor between 27Ω and 56Ω placed near the driver or near the LTC2431 pin will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology.

An alternate solution is to reduce the edge rate of the control signals. It should be noted that using very slow edges will increase the converter power supply current during the transition time. The differential input and reference architecture reduce substantially the converter’s sensitivity to ground currents.

pins may severely disturb the analog to digital

. For reference, on a regular FR-4 board,

LTC2430/

The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during the conversion state.

While a digital input signal is in the range 0.5V to (VCC␣ –␣ 0.5V), the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (FO, CS and SCK in External SCK mode of operation) is within this range, the

LTC2430/LTC2431 crease even if the signal in question is at a valid logic level. For micropower operation, it is recommended to drive all digital input signals to full CMOS levels [VIL < 0.4V and VOH > (VCC – 0.4V)].

power supply current may in-

Particular attention must be given to the connection of the FO signal when the converter (LTC2430 or LTC2431) is used with an external conversion clock. This clock is active during the conversion time and the normal mode rejection provided by the internal digital filter is not very high at this frequency. A normal mode signal of this frequency at the converter reference terminals may result into DC gain and INL errors. A normal mode signal of this frequency at the converter input terminals may result into a DC offset error. Such perturbations may occur due to asymmetric capacitive coupling between the FO signal trace and the converter input and/or reference connection traces. An immediate solution is to maintain maximum possible separation

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APPLICATIO S I FOR ATIO

between the FO signal trace and the input/reference signals. When the FO signal is parallel terminated near the converter, substantial AC current is flowing in the loop formed by the FO connection trace, the termination and the ground return path. Thus, perturbation signals may be inductively coupled into the converter input and/or reference. In this situation, the user must reduce to a minimum the loop area for the FO signal as well as the loop area for the differential input and reference connections.

Driving the Input and Reference

The input and reference pins of the converter (LTC2430 or LTC2431) are directly connected to a network of sampling capacitors. Depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transfering small amounts of charge in the process. A simplified equivalent circuit is shown in Figure 11.

For a simple approximation, the source impedance R

driving an analog input pin (IN+, IN–, REF+ or REF–) can be considered to form, together with RSW and CEQ (see Figure␣ 11), a first order passive network with a time constant τ = (RS + RSW) • CEQ. The converter is able to

sample the input signal with better than 1ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant τ. The sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worstcase circumstances, the errors may add.

When using the internal oscillator (FO = LOW or HIGH), the LTC2430/LTC2431’s front-end switched-capacitor network is clocked at 76800Hz corresponding to a 13µs sampling period. Thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that τ ≤ 13µs/14 = 920ns. When an external oscillator of frequency f and, for a settling error of less than 1ppm, τ ≤ 0.14/f

is used, the sampling period is 2/f

EOSC

Input Current

If complete settling occurs on the input, conversion results will be unaffected by the dynamic input current. An incomplete settling of the input signal sampling process may result in gain and offset errors, but it will not degrade the INL performance of the converter. Figure 11 shows the mathematical expressions for the average bias currents flowing through the IN+ and IN– pins as a result of the

REF

IIN+

VIN+

IIN–

VIN–

–

REF

–

REF

SWITCHING FREQUENCY

= 76800Hz INTERNAL OSCILLATOR (FO = LOW OR HIGH)

= 0.5 • f

LEAK

EXTERNAL OSCILLATOR

EOSC

LEAK

RSW (TYP)

20k

RSW (TYP)

20k

RSW (TYP)

20k

RSW (TYP)

20k

2431 F11

Figure 11. LTC2430/LTC2431 Equivalent Analog Input Circuit

6pF (TYP)

VV V

+−

IN INCM REFCM

IIN

()

AVG

−

IIN

()

AVG

IREF

()

AVG

−

I REF

()

WHERE

=−

V REF REF

REF

REFCM

=−

VININ

INCM

43 2 60

R M INTERNAL OSCILLATOR HzNotch F LOW

EQ O

52 0 50

R M INTERNAL OSCILLATOR Hz Notch F HIGH

EQ O

=•

666 10

R f EXTERNAL OSCILLATOR

EQ EOSC

()

•

VV V

−+ −

IN INCM REFCM

AVG

+−



REF REF

 

+−



IN IN

 

Ω

•

VV V

•− +

REF INCM REFCM

VV V

−• − +

REF INCM REFCM

+−









− 



•

−

REF EQ

•

() ()

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APPLICATIO S I FOR ATIO

LTC2430/LTC2431

sampling charge transfers when integrated over a substantial time period (longer than 64 internal clock cycles).

The effect of this input dynamic current can be analyzed using the test circuit of Figure 12. The C

capacitor

PAR

includes the LTC2430/LTC2431 pin capacitance (5pF typical) plus the capacitance of the test fixture used to obtain the results shown in Figures 13 and 14. A careful implementation can bring the total input capacitance (CIN + C

) closer to 5pF thus achieving better performance

PAR

than the one predicted by Figures 13 and 14. For simplicity, two distinct situations can be considered.

or relatively small values of input capacitance (CIN <

0.01µF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CIN will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them. Nevertheless, when small values of CIN are unavoidably present as parasitics of input multiplexers, wires, connectors or sensors, the LTC2430 or LTC2431 can maintain its exceptional accuracy while operating with relative large values of source resistance as shown in Figures 13 and 14. These measured results may be slightly different from the first order approximation suggested earlier because they include the effect of the actual second order input network together with the nonlinear settling process of the input amplifiers. For small CIN values, the settling on IN+ and IN– occurs almost independently and there is little benefit in trying to match the source impedance for the two pins.

Larger values of input capacitors (CIN > 0.01µF) may be required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. When FO = LOW (internal oscillator and 60Hz notch), the typical differential input resistance is 21.6MΩ which will generate a gain error of approximately 0.023ppm for each ohm of source resistance driving IN+ or IN–. When FO = HIGH (internal oscillator and 50Hz notch), the typical differential input resistance is 26MΩ which will generate a gain error of approximately 0.019ppm for each ohm of source resistance driving IN+ or IN–. When FO is driven by

an external oscillator with a frequency f

EOSC

(external conversion clock operation), the typical differential input resistance is 3.3 • 1012/f

Ω and each ohm of source

EOSC

resistance driving IN+ or IN– will result in 0.15 • 10–6 • f

ppm gain error. The effect of the source resistance on

EOSC

the two input pins is additive with respect to this gain error.

SOURCE

+ 0.5V

INCM

– 0.5V

SOURCE

Figure 12. An RC Network at IN+ and IN

VCC = 5V

= 5V

REF

–

+FS ERROR (ppm)

–10

= GND

REF

= 3.75V

–

= 1.25V

= GND

= 25°C

1 10 100 1k 10k 100k

IN =

Figure 13. +FS Error vs R

–10

–20

VCC = 5V V

REF

–30

–FS ERROR (ppm)

REF

= 1.25V

–

= 3.75V

–40

= GND

= 25°C

–50

IN =

= 5V

–

= GND

10 100 1k 10k

Figure 14. –FS Error vs R

IN =

0.001µF

100pF

SOURCE

0.01µF

0.001µF

100pF

IN =

SOURCE

0pF

PAR

≅20pF

PAR

≅20pF

0.01µF

IN =

(Ω)

at IN+ or IN– (Small CIN)

0pF

IN =

(Ω)

at IN+ or IN– (Small CIN)

2431 F13

2431 F14

LTC2430/

100k

LTC2431

–

2431 F12

–

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APPLICATIO S I FOR ATIO

The typical +FS and –FS errors as a function of the sum of the source resistance seen by IN+ and IN– for large values of CIN are shown in Figure 15.

In addition to this gain error, an offset error term may also appear. The offset error is proportional with the mismatch between the source impedance driving the two input pins IN+ and IN– and with the difference between the input and reference common mode voltages. While the input drive circuit nonzero source impedance combined with the converter average input current will not degrade the INL performance, indirect distortion may result from the modulation of the offset error by the common mode component of the input signal. Thus, when using large CIN capacitor values, it is advisable to carefully match the source impedance seen by the IN+ and IN– pins. When FO = LOW

VCC = 5V

= 5V

REF

–

= GND

REF

= 3.75V

–

= 1.25V

= GND

= 25°C

+FS ERROR (ppm)

200

100

Figure 15a. +FS Error vs R

–5

CIN = 1µF, 10µF

–10

VCC = 5V

= 5V

REF

–FS ERROR (ppm)

–15

–20

REF

100

–

= GND

= 1.25V

–

= 3.75V

= GND = 25°C

200

Figure 15b. –FS Error vs R

300

400 R

CIN = 1µF, 10µF

500

600

(Ω)

SOURCE

at IN+ or IN– (Large CIN)

SOURCE

CIN = 0.01µF

500

600

(Ω)

SOURCE

at IN+ or IN– (Large CIN)

SOURCE

CIN = 0.1µF

CIN = 0.01µF

800

700

CIN = 0.1µF

800

700

900

2431 F15a

2431 F15b

1000

(internal oscillator and 60Hz notch), every 1Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of

0.023ppm. When FO = HIGH (internal oscillator and 50Hz notch), every 1Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.019ppm. When FO is driven by an external oscillator with a frequency f

EOSC

every 1Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.15 • 10–6 • f

ppm. Figure 16

EOSC

shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the IN+ and IN– pins when large CIN values are used.

If possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. This configuration eliminates the offset error caused by mismatched source impedances.

The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 1%. Such

C D

E F

OFFSET ERROR (ppm)

–20

–40

0.5

A: ∆RIN = +1k B: ∆R C: ∆R D: ∆R

Figure 16. Offset Error vs Common Mode Voltage (V

= VIN+ = VIN–) and Input Source Resistance Imbalance

(∆R

INCM

= R

SOURCEIN

IN IN

– R

= +500Ω = +200Ω = 0Ω

VCC = 5V V

REF

FO = GND R

SOURCEIN

= 10µF

= 25°C

1.5

SOURCEIN

= 5V

–

= GND

–

= V

INCM

–

= 500Ω

2.5

(V)

INCM

–

) for Large CIN Values (CIN ≥ 1µF)

3.5

E: ∆RIN = –200Ω F: ∆R

= –500Ω

= –1k

G: ∆R

4.5

2431 F16

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LTC2430/LTC2431

a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by IN+ and IN–, the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient.

In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift. A 100Ω source resistance will create a 0.1µV typical and 1µV maximum offset voltage.

Reference Current

In a similar fashion, the LTC2430 or LTC2431 samples the differential reference pins REF+ and REF– transfering small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in the same two distinct situations.

For relatively small values of the external reference capacitors (C

< 0.01µF), the voltage on the sampling capacitor

REF

settles almost completely and relatively large values for the source impedance result in only small errors. Such values for C

will deteriorate the converter offset and

REF

gain performance without significant benefits of reference filtering and the user is advised to avoid them.

(external conversion clock operation), the typical differential reference resistance is 2.4 • 1012/f

Ω and each

EOSC

ohm of source resistance drving REF+ or REF– will result in 0.206 • 10–6 • f

ppm gain error. The effect of the

EOSC

source resistance on the two reference pins is additive with respect to this gain error. The typical FS errors for various combinations of source resistance seen by the REF+ and REF– pins and external capacitance C

REF

connected to these pins are shown in Figures 17 and 18. Typical – FS errors are similar to +FS errors with opposite polarity.

In addition to this gain error, the converter INL performance is degraded by the reference source impedance. When FO = LOW (internal oscillator and 60Hz notch), every 100Ω of source resistance driving REF+ or REF– translates

0pF

–10

–20

VCC = 5V V

–30

+FS ERROR (ppm)

V V V

–40

F T

–50

REF =

= 5V

REF

–

= GND

REF

= 3.75V

–

= 1.25V

= GND

= 25°C

10 100 1k 10k

Figure 17a. +FS Error vs R

0.01µF

0.001µF

100pF

SOURCE

REF =

100k

(Ω)

2431 F17a

at REF+ or REF– (Small CIN)

Larger values of reference capacitors (C

> 0.01µF)

REF

may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. When FO = LOW (internal oscillator and 60Hz notch), the typical differential reference resistance is 15.6MΩ which will generate a gain error of approximately 0.032ppm for each ohm of source resistance driving REF+ or REF–. When F

= HIGH (internal oscillator and 50Hz notch), the typical differential reference resistance is 18.7MΩ which will generate a gain error of approximately 0.027ppm for each ohm of source resistance driving REF+ or REF–. When F is driven by an external oscillator with a frequency f

EOSC

VCC = 5V

= 5V

REF

–

= GND

REF

= 1.25V

= GND

= 25°C

–FS ERROR (ppm)

–10

–

= 3.75V

REF =

10 100 1k 10k

Figure 17b. –FS Error vs R

0.01µF

REF =

0.001µF

100pF

0pF

REF =

(Ω)

SOURCE

at REF+ or REF– (Small CIN)

SOURCE

2431 F17b

100k

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–10

–20

= 1µF, 10µF

REF

–30

VCC = 5V

= 5V

REF

–40

+FS ERROR (ppm)

–50

–60

–

= GND

REF

= 3.75V

–

= 1.25V

= GND

= 25°C

200 400 600 800

Figure 18a. +FS Error vs R

VCC = 5V

= 5V

REF

–

–FS ERROR (ppm)

= GND

REF

= 1.25V

–

= 3.75V

= GND

= 25°C

200 400 600 800

Figure 18b. –FS Error vs R

SOURCE

= 0.01µF

REF

= 0.1µF

REF

(Ω)

10001000 300 500 700 900

2431 F18a

at REF+ or REF– (Large C

= 1µF, 10µF

REF

= 0.1µF

REF

= 0.01µF

REF

(Ω)

10001000 300 500 700 900

2431 F18b

at REF+ or REF– (Large C

REF

)

into about 0.11ppm additional INL error. When FO = HIGH (internal oscillator and 50Hz notch), every 100Ω of source resistance driving REF+ or REF– translates into about

0.092ppm additional INL error. When FO is driven by an external oscillator with a frequency f

, every 100Ω of

EOSC

source resistance driving REF+ or REF– translates into about 0.73 • 10–6 • f

ppm additional INL error. Fig-

EOSC

ure␣ 19 shows the typical INL error due to the source resistance driving the REF+ or REF– pins when large C

REF

values are used. The effect of the source resistance on the two reference pins is additive with respect to this INL error. In general, matching of source impedance for the REF

15 12

)

REF

3 0

–3

INL (ppm OF V

–6

–9 –12 –15

–0.5

= 5V

REF

–

REF

INCM

–0.3–0.4

= 5V = GND

= 0.5(V

–0.1–0.2

INDIF/VREFDIF

= GND

= 10µF

REF

= 25°C

–

+ V

) = 2.5V

SOURCE =

10k

SOURCE =

0.1 0.2 0.4

0.3

0.5

2431 F19

Figure 19. INL vs Differential Input Voltage (VIN = IN+ – IN–) and Reference Source Resistance (R for Large C

Values (C

REF

≥ 1µF)

at REF+ and REF–)

SOURCE

and REF– pins does not help the gain or the INL error. The user is thus advised to minimize the combined source impedance driving the REF+ and REF– pins rather than to try to match it.

The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typical better than 1%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by REF

and REF–, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient.

In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA max), results in a small gain error. A 100Ω source resistance will create a 0.05µV typical and 0.5µV maxi- mum full-scale error.

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LTC2430/LTC2431

Output Data Rate

When using the internal oscillator, the LTC2430/LTC2431 can produce up to 7.5 readings per second with a notch frequency of 60Hz (FO = LOW) and 6.25 readings per second with a notch frequency of 50Hz (FO = HIGH). The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (FO connected to an external oscillator), the LTC2430/LTC2431 output data rate can be increased as desired. The duration of the conversion phase is 20510/f

EOSC

. If f

= 153600Hz, the

EOSC

converter behaves as if the internal oscillator is used and the notch is set at 60Hz. There is no significant difference in the LTC2430/LTC2431 performance between these two operation modes.

An increase in f

over the nominal 153600Hz will

EOSC

translate into a proportional increase in the maximum output data rate. This substantial advantage is nevertheless accompanied by three potential effects, which must be carefully considered.

First, a change in f

will result in a proportional change

EOSC

in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2430/LTC2431’s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN– pins.

Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (CIN, C

) are used, the

REF

previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of f or reference capacitors (CIN, C

. If small external input and/

EOSC

) are used, the effect of

REF

the external source resistance upon the LTC2430/LTC2431 typical performance can be inferred from Figures 13, 14

and 17 in which the horizontal axis is scaled by 153600/f

EOSC

Third, an increase in the frequency of the external oscillator above 1.6MHz (a more than 10× increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures␣ 20 to

27. In order to obtain the highest possible level of accuracy from this converter at output data rates above 50 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. The accuracy is also sensitive to the clock signal levels and edge rate as discussed in the section Digital Signal Levels. In certain circumstances, a reduction of the differential reference voltage may be beneficial.

Input Bandwidth

The combined effect of the internal sinc4 digital filter and of the analog and digital autocalibration circuits determines the LTC2430/LTC2431 input bandwidth. When the internal oscillator is used, the 3dB input bandwidth of the LTC2430/LTC2431 is 3.63Hz for 60Hz notch frequency (FO = LOW) and 3.02Hz for 50Hz notch frequency (FO = HIGH). If an external conversion clock generator of frequency f bandwidth is 2.36 • 10–5 • f

is connected to the FO pin, the 3dB input

EOSC

Due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3dB frequency. When the internal oscillator is used, the shape of the LTC2430/LTC2431 input bandwidth is shown in Figure␣ 28. When an external oscillator of frequency f

is used, the shape of the LTC2430/LTC2431 input

EOSC

bandwidth can be derived from Figure␣ 28, FO = LOW curve of the LTC2411 in which the horizontal axis is scaled by f

/153600.

EOSC

The conversion noise (2.8µV

typical for V

RMS

= 5V) can

REF

be modeled as a white noise source connected to a noise free converter. The noise spectral density is 67nV/√Hz for

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= V

INCM

)

REF

7 6 5 4 3 2

OFFSET ERROR (ppm OF V

1 0

REFCM

VCC = V V F

= 5V

REF

= 0V

= EXT OSC

TA = 85°C

TA = 25°C

10 90

OUTPUT DATA RATE (READINGS/SEC)

100

2431 F20

Figure 20. Offset Error vs Output Data Rate and Temperature

= V

INCM

REFCM

VCC = V

)

REF

–FS ERROR (ppm OF V

–5

= 5V

REF

= EXT OSC

TA = 25°C

TA = 85°C

OUTPUT DATA RATE (READINGS/SEC)

60 80

2431 F22

100

)

REF

–5

–10

–15

–20

+FS ERROR (ppm OF V

= V

INCM

–25

VCC = V

REF

= EXT OSC

–30

OUTPUT DATA RATE (READINGS/SEC)

REFCM

= 5V

TA = 25°C

TA = 85°C

60 80

2431 F21

100

Figure 21. +FS Error vs Output Data Rate and Temperature

= V

REF

= GND

REFCM

= 5V

TA = 25°C

TA = 85°C

/NOISE

REF

)

RMS

60 80

2431 F23

100

INCM

VCC = V

RESOLUTION (BITS)

= 0V

= EXT OSC

–

REF RES = LOG

OUTPUT DATA RATE (READINGS/SEC)

Figure 22. –FS Error vs Output Data Rate and Temperature

RESOLUTION (BITS)

INCM

VCC = V

= EXT OSC

REF RES = LOG

OUTPUT DATA RATE (READINGS/SEC)

Figure 24. Resolution (INL

= V

–

= GND

TA = 85°C

REFCM

= 5V

REF

2(VREF

TA = 25°C

/INL

)

MAX

60 80

RMS

100

2430 F24

≤ 1LSB)

vs Output Data Rate and Temperature

Figure 23. Resolution (Noise

RMS

≤ 1LSB)

vs Output Data Rate and Temperature

= V

INCM

)

REF

2 1

0 –1 –2 –3

OFFSET ERROR (ppm OF V

–4 –5

REFCM

VIN = 0V

–

REF

= GND

= EXT OSC

= 25°C

200 100

OUTPUT DATA RATE (READINGS/SEC)

VCC = V

REF

VCC = 2.7V

REF

= 5V

= 2.5V

2431 F25

Figure 25. Offset Error vs Output Data Rate and V

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LTC2430/LTC2431

VCC = V

VCC = 2.7V

REF

/NOISE

REF

= 2.5V

RMS

60 80

= V

INCM

RESOLUTION (BITS)

REFCM

VIN = 0V F

= EXT OSC

–

= GND

REF

= 25°C

RES = LOG

OUTPUT DATA RATE (READINGS/SEC)

2(VREF

Figure 26. Resolution (Noise vs Output Data Rate and V

–1

–2

–3

–4

–5

INPUT SIGNAL ATTENUATION (dB)

FO = HIGH FO = LOW

)

= 5V

RMS

100

2430 F26

≤ 1LSB)

INCM

RESOLUTION (BITS)

VIN = 0V

= EXT OSC

REF

= 25°C

RES = LOG

OUTPUT DATA RATE (READINGS/SEC)

= V

–

= GND

REFCM

2(VREF

VCC = V

/INL

Figure 27. Resolution (INL vs Output Data Rate and V

1000

100

INPUT REFERRED NOISE

EQUIVALENT BANDWIDTH (Hz)

FO = LOW

FO = HIGH

= 5V

REF

VCC = 2.7V

= 2.5V

REF

)

MAX

60 80

MAX

100

2430 F27

≤ 1LSB)

–6

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2431 F28

Figure 28. Input Signal Bandwidth Using the Internal Oscillator

an infinite bandwidth source and 216nV/√Hz for a single

0.5MHz pole source. From these numbers, it is clear that particular attention must be given to the design of external amplification circuits. Such circuits face the simultaneous requirements of very low bandwidth (just a few Hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500kHz) necessary to drive the input switched-capacitor network. A possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer.

When external amplifiers are driving the LTC2430/ LTC2431, the ADC input referred system noise calculation can be simplified by Figure 29. The noise of an amplifier driving the LTC2430/LTC2431 input pin can be modeled as a band-limited white noise source. Its bandwidth can be

0.1

0.1 1

10 100 1k 10k 100k 1M

INPUT NOISE SOURCE SINGLE POLE

EQUIVALENT BANDWIDTH (Hz)

2431 G29

Figure 29. Input Referred Noise Equivalent Bandwidth of an Input Connected White Noise Source

approximated by the bandwidth of a single pole lowpass filter with a corner frequency fi. The amplifier noise spectral density is ni. From Figure␣ 29, using fi as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth freqi of the input driving amplifier. This bandwidth includes the band limiting effects of the ADC internal calibration and filtering. The noise of the driving amplifier referred to the converter input and including all these effects can be calculated as N␣ = ni • √freqi. The total system noise (referred to the LTC2430/LTC2431 input) can now be obtained by summing as square root of sum of squares the three ADC input referred noise sources: the LTC2430/ LTC2431 internal noise (2.8µV), the noise of the IN

driving amplifier and the noise of the IN– driving amplifier.

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If the FO pin is driven by an external oscillator of frequency f

, Figure 29 can still be used for noise calculation if the

EOSC

x-axis is scaled by f ratio f

/153600, the Figure 29 plot accuracy begins to

EOSC

/153600. For large values of the

EOSC

decrease, but in the same time the LTC2430/LTC2431 noise floor rises and the noise contribution of the driving amplifiers lose significance.

Normal Mode Rejection and Antialiasing

One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2430/LTC2431 significantly simplifies antialiasing filter requirements.

The sinc4 digital filter provides greater than 120dB normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS). The LTC2430/LTC2431’s autocalibration circuits further simplify the antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. Independent of the operating mode, fS = 256 • fN = 2048

• f

OUTMAX

where fN is the notch frequency and f

OUTMAX

is the maximum output data rate. In the internal oscillator mode, fS = 12,800Hz with a 50Hz notch setting and fS = 15,360Hz with a 60Hz notch setting. In the external oscillator mode, fS = f

EOSC

/10.

The combined normal mode rejection performance is shown in Figure␣ 30 for the internal oscillator with 50Hz notch setting (FO = HIGH) and in Figure␣ 31 for the internal

oscillator with FO = LOW and for the external oscillator mode. The regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth. Magnified details of the normal mode rejection curves are shown in Figure␣ 32 (rejection near DC) and Figure␣ 33 (rejection at fS = 256fN) where fN represents the notch frequency. These curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the fN value.

The user can expect to achieve in practice this level of performance using the internal oscillator as it is demonstrated by Figures 34 to 36. Typical measured values of the normal mode rejection of the LTC2430/LTC2431 operating with an internal oscillator and a 60Hz notch setting are shown in Figure 34 superimposed over the theoretical calculated curve. Similarly, typical measured values of the normal mode rejection of the LTC2430/LTC2431 operating with an internal oscillator and a 50Hz notch setting are shown in Figure 35 superimposed over the theoretical calculated curve.

As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front of the LTC2430/LTC2431. If passive RC components are placed in front of the LTC2430/LTC2431, the input dynamic current should be considered (see Input Current section). In cases where large effective RC time constants are used, an external buffer amplifier may be required to minimize the effects of dynamic input current.

FO = HIGH

–10 –20 –30 –40 –50 –60 –70 –80 –90

–100

INPUT NORMAL MODE REJECTION (dB)

–110 –120

S2fS3fS4fS5fS6fS7fS8fS9fS

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

10fS11fS12f

2431 F30

Figure 30. Input Normal Mode Rejection, Internal Oscillator and 50Hz Notch

0 –10 –20 –30 –40 –50 –60 –70 –80 –90

–100

INPUT NORMAL MODE REJECTION (dB)

–110 –120

2fS3fS4fS5fS6fS7fS8fS9fS10f

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

FO = LOW OR

= EXTERNAL OSCILLATOR,

= 10 • f

EOSC

2431 F31

Figure 31. Input Normal Mode Rejection, Internal Oscillator and FO = LOW or External Oscillator

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LTC2430/LTC2431

0 –10 –20 –30 –40 –50 –60 –70 –80 –90

–100

INPUT NORMAL MODE REJECTION (dB)

–110 –120

fN0 2fN3fN4fN5fN6fN7fN8f

INPUT SIGNAL FREQUENCY (Hz)

Figure 32. Input Normal Mode Rejection

–20

–40

–60

–80

MEASURED DATA CALCULATED DATA

2431 F32

VCC = 5V V V V F T

REF INCM IN(P-P)

= GND

= 25°C

= 5V

= 2.5V

= 5V

0 –10 –20 –30 –40 –50 –60 –70 –80 –90

–100

INPUT NORMAL MODE REJECTION (dB)

–110 –120

250f

252fN254fN256fN258fN260fN262f

INPUT SIGNAL FREQUENCY (Hz)

Figure 33. Input Normal Mode Rejection

–20

–40

–60

–80

MEASURED DATA CALCULATED DATA

2431 F33

VCC = 5V V

= 5V

REF

INCM

IN(P-P)

= 5V

= 25°C

= 2.5V

= 5V

NORMAL MODE REJECTION (dB)

–100

–120

0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240

INPUT FREQUENCY (Hz)

2431 F34

NORMAL MODE REJECTION (dB)

–100

–120

0 25 50 75 100 125 150 175

INPUT FREQUENCY (Hz)

2431 F35

Figure 34. Input Normal Mode Rejection vs Input Frequency Figure 35. Input Normal Mode Rejection vs Input Frequency

Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2430/LTC2431 third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale. In many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and LTC2430/LTC2431 are eminently suited for such tasks. When the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. With a reference voltage V

␣ =␣ 5V, the

REF

LTC2430/LTC2431 have a full-scale differential input range of 5V peak-to-peak. Figures 36 and 37 show measurement results for the LTC2430/LTC2431 normal mode rejection ratio with a 7.5V peak-to-peak (150% of full scale) input signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5V peakto-peak (full scale) input signal. It is clear that the LTC2430/ LTC2431 rejection performance is maintained with no compromises in this extreme situation. When operating with large input signal levels, the user must observe that such signals do not violate the device absolute maximum ratings.

200

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–20

–40

–60

–80

–100

NORMAL MODE REJECTION (dB)

–120

0 15 30 45 60 75 90 105 120 135 150 165 180 195 210

= 5V

IN(P-P)

= 7.5V

IN(P-P)

(150% OF FULL SCALE)

INPUT FREQUENCY (Hz)

VCC = 5V V

= 5V

REF

INCM

= GND

= 25°C

= 2.5V

225 240

2431 F36

Figure 36. Measured Input Normal Mode Rejection vs Input Frequency

BRIDGE APPLICATIONS

Typical strain gauge based bridges deliver only 2mV/Volt of excitation. As the maximum reference voltage of the LTC2430/LTC2431 is 5V, remote sensing of applied excitation without additional circuitry requires that excitation be limited to 5V. This gives only 10mV full scale, which can be resolved to 1 part in 3500 without averaging. For many solid state sensors, this is comparable to the sensor. Averaging 128 samples however reduces the noise level by a factor of eight, bringing the resolving power to 1 part in 40000, comparable to better weighing systems. Hysteresis and creep effects in the load cells are typically much greater than this. Most applications that require strain measurements to this level of accuracy are measuring slowly changing phenomena, hence the time required to average a large number of readings is usually not an issue. For those systems that require accurate measurement of a small incremental change on a significant tare weight, the lack of history effects in the LTC2400 family is of great benefit.

For those applications that cannot be fulfilled by the LTC2430/LTC2431 alone, compensating for error in external amplification can be done effectively due to the “no latency” feature of the LTC2430/LTC2431. No latency operation allows samples of the amplifier offset and gain to be interleaved with weighing measurements. The use of correlated double sampling allows suppression of 1/f noise, offset and thermocouple effects within the bridge. Correlated double sampling involves alternating

–20

–40

–60

–80

NORMAL MODE REJECTION (dB)

–100

–120

25 50 75 100 125 150 175 200

= 5V

IN(P-P)

= 7.5V

IN(P-P)

(150% OF FULL SCALE)

INPUT FREQUENCY (Hz)

VCC = 5V V

= 5V

REF

INCM

= 5V

= 25°C

= 2.5V

2431 F37

Figure 37. Measured Input Normal Mode Rejection vs Input Frequency

the polarity of excitation and dealing with the reversal of input polarity mathematically. Alternatively, bridge excitation can be increased to as much as ±10V, if one of several precision attenuation techniques is used to produce a precision divide operation on the reference signal. Another option is the use of a reference within the 5V input range of the LTC2430/LTC2431 and developing excitation via fixed gain, or LTC1043 based voltage multiplication, along with remote feedback in the excitation amplifiers, as shown in Figures 43 and 45.

Figure 38 shows an example of a simple bridge connection. Note that it is suitable for any bridge application

LT1019

350Ω

BRIDGE

R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS

0.1µF10µF 0.1µF

REF

SDO

–

REF

SCK

LTC2430/

LTC2431

–

GND

Figure 38. Simple Bridge Connection

2431 F38

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LTC2430/LTC2431

where measurement speed is not of the utmost importance. For many applications where large vessels are weighed, the average weight over an extended period of time is of concern and short term weight is not readily determined due to movement of contents, or mechanical resonance. Often, large weighing applications involve load cells located at each load bearing point, the output of which can be summed passively prior to the signal processing circuitry, actively with amplification prior to the ADC, or can be digitized via multiple ADC channels and summed mathematically. The mathematical summation of the output of multiple LTC2430/LTC2431’s provide the benefit of a root square reduction in noise. The low power consumption of the LTC2430/LTC2431 make it attractive for multidrop communication schemes where the ADC is located within the load-cell housing.

A direct connection to a load cell is perhaps best incorporated into the load-cell body, as minimizing the distance to the sensor largely eliminates the need for protection devices, RFI suppression and wiring. The LTC2430/ LTC2431 exhibit extremely low temperature dependent drift. As a result, exposure to external ambient temperature ranges does not compromise performance. The incorporation of any amplification considerably complicates

thermal stability, as input offset voltages and currents, temperature coefficient of gain settling resistors all become factors.

The circuit in Figure 39 shows an example of a simple amplification scheme. This example produces a differential output with a common mode voltage of 2.5V, as determined by the bridge. The use of a true three amplifier instrumentation amplifier is not necessary, as the LTC2430/ LTC2431 have common mode rejection far beyond that of most amplifiers. The LTC1051 is a dual autozero amplifier that can be used to produce a gain of 10 before its input referred noise dominates the LTC2430/LTC2431 noise. This example shows a gain of 34, that is determined by a feedback network built using a resistor array containing eight individual resistors. The resistors are organized to optimize temperature tracking in the presence of thermal gradients. The second LTC1051 buffers the low noise input stage from the transient load steps produced during conversion.

The gain stability and accuracy of this approach is very good, due to a statistical improvement in resistor matching due to individual error contribution being reduced. A gain of 34 may seem low, when compared to common

350Ω

BRIDGE

U1A

–

RN1

RN1 = 5k × 8 RESISTOR ARRAY U1A, U1B, U2A, U2B = 1/2 LTC1051

611

–

U1B

0.1µF

710

512

0.1µF

–

U2A

–

U2B

Figure 39. Using Autozero Amplifiers to Reduce Input Referred Noise

REF REF

LTC2430/ LTC2431

–

GND

REF

0.1µF

SDO

SCK

2431 F39

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practice in earlier generations of load-cell interfaces, however the accuracy of the LTC2430/LTC2431 changes the rationale. Achieving high gain accuracy and linearity at higher gains may prove difficult, while providing little benefit in terms of noise reduction.

At a gain of 100, the gain error that could result from typical open-loop gain of 160dB is –1ppm, however, worst-case is at the minimum gain of 116dB, giving a gain error of –158ppm. Worst-case gain error at a gain of 34, is –54ppm. The use of the LTC1051A reduces the worstcase gain error to –33ppm. The advantage of gain higher than 34, then becomes dubious, as the input referred noise sees little improvement and gain accuracy is potentially compromised.

Note that this 4-amplifier topology has advantages over the typical integrated 3-amplifier instrumentation amplifier in that it does not have the high noise level common in the output stage that usually dominates when an instrumentation amplifier is used at low gain. If this amplifier is used at a gain of 10, the gain error is only 10ppm and input referred noise is reduced to 0.28µV

. The buffer stages

RMS

can also be configured to provide gain of up to 50 with high gain stability and linearity.

Figure 40 shows an example of a single amplifier used to produce single-ended gain. This topology is best used in

applications where the gain setting resistor can be made to match the temperature coefficient of the strain gauges. If the bridge is composed of precision resistors, with only one or two variable elements, the reference arm of the bridge can be made to act in conjunction with the feedback resistor to determine the gain. If the feedback resistor is incorporated into the design of the load cell, using resistors which match the temperature coefficient of the loadcell elements, good results can be achieved without the need for resistors with a high degree of absolute accuracy. The common mode voltage in this case, is again a function of the bridge output. Differential gain as used with a 350Ω bridge is:

Common mode gain is half the differential gain. The maximum differential signal that can be used is 1/4 V as opposed to 1/2 V

in the 2-amplifier topology above.

REF

Remote Half Bridge Interface

As opposed to full bridge applications, typical half bridge applications must contend with nonlinearity in the bridge output, as signal swing is often much greater. Applications include RTD’s, thermistors and other resistive elements that undergo significant changes over their span. For

350Ω

BRIDGE

0.1µV

LTC1050

–

1µF

4.99k

= 9.95 =

Figure 40. Bridge Amplification Using a Single Amplifier

R1 + R2

R1 + 175Ω

46.4k

175Ω

1µF

20k

10µF

REF REF

–

LTC2430/

LTC2431

–

GND

0.1µF

2431 F40

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APPLICATIO S I FOR ATIO

LTC2430/LTC2431

single variable element bridges, the nonlinearity of the half bridge output can be eliminated completely; if the reference arm of the bridge is used as the reference to the ADC, as shown in Figure 41. The LTC2430/LTC2431 can accept inputs up to 1/2 V

. Hence, the reference resistor R1

REF

must be at least 2× the highest value of the variable resistor.

In the case of 100Ω platinum RTD’s, this would suggest a value of 800Ω for R1. Such a low value for R1 is not advisable due to self-heating effects. A value of 25.5k is shown for R1, reducing self-heating effects to acceptable levels for most sensors.

The basic circuit shown in Figure 41 shows connections for a full 4-wire connection to the sensor, which may be

2.7V TO 5.5V

REF

–

LTC2430/

LTC2431

–

GND

2431 F41

25.5k

0.1%

PLATINUM

100Ω

RTD

located remotely. The differential input connections will reject induced or coupled 60Hz interference, however, the reference inputs do not have the same rejection. If 60Hz or other noise is present on the RTD, a low pass filter is recommended as shown in Figure 42. Note that you cannot place a large capacitor directly at the junction of R1 and R2, as it will store charge from the sampling process. A better approach is to produce a low pass filter decoupled from the input lines with a high value resistor (R3).

The use of a third resistor in the half bridge, between the variable and fixed elements gives essentially the same result as the two resistor version, but has a few benefits. If, for example, a 25k reference resistor is used to set the excitation current with a 100Ω RTD, the negative reference input is sampling the same external node as the positive input, but may result in errors if used with a long cable. For short cable applications, the errors may be acceptably low. If instead the single 25k resistor is replaced with a 10k 5% and a 10k 0.1% reference resistor, the noise level introduced at the reference, at least at higher frequencies, will be reduced. A filter can be introduced into the network, in the form of one or more capacitors, or ferrite beads, as long as the sampling pulses are not translated into an error. The reference voltage is also reduced, but this is not undesirable, as it will decrease the value of the LSB, although, not the input referred noise level.

Figure 41. Remote Half Bridge Interface

10k

0.1%

10k, 5%

100Ω

RTD

PLATINUM

Figure 42. Remote Half Bridge Sensing with Noise Supression on Reference

R3 10k 5%

1µF

LTC1050

–

560Ω

10k

REF REF

LTC2430/ LTC2431

–

GND

2431 F42

24301f

Page 36

LTC2430/LTC2431

WUUU

APPLICATIO S I FOR ATIO

The circuit shown in Figure 42 shows a more rigorous example of Figure 41, with increased noise suppression and more protection for remote applications.

Figure 43 shows an example of gain in the excitation circuit and remote feedback from the bridge. The LTC1043s provide voltage multiplication, providing ±10V from a 5V reference with only 1ppm error. The amplifiers are used at unity-gain and, hence, introduce a very little error due to gain error or due to offset voltages. A 1µV/°C offset voltage

15V15V

200Ω

10V 5V

350Ω

BRIDGE

2N3904

33Ω

10V

2N3906

–15V

–10V

33Ω

20Ω

LTC1150

–15V

15V

LTC1150

–15V

1µF

–

0.1µF

drift translates into 0.05ppm/°C gain error. Simpler alternatives, with the amplifiers providing gain using resistor arrays for feedback, can produce results that are similar to bridge sensing schemes via attenuators. Note that the amplifiers must have high open-loop gain or gain error will be a source of error. The fact that input offset voltage has relatively little effect on overall error may lead one to use low performance amplifiers for this application. Note that the gain of a device such as an LF156, (25V/mV over

15V

U1 LTC1043

U2 LTC1043

47µF 0.1µF

10µF

0.1µF

LT1236-5

LTC2430/

LTC2431

REF

–

REF

–

GND

10V

0.1µF

1µF

FILM

–10V

200Ω

U2 LTC1043

–10V

*FLYING CAPACITORS ARE

1µF FILM (MKP OR EQUIVALENT)

SEE LTC1043 DATA SHEET FOR DETAILS ON UNUSED HALF OF U1

2431 F43

Figure 43. LTC1043 Provides Precise 4× Reference for Excitation Voltages

24301f

Page 37

WUUU

APPLICATIO S I FOR ATIO

LTC2430/LTC2431

temperature) will produce a worst-case error of –180ppm at a noise gain of 3, such as would be encountered in an inverting gain of 2, to produce –10V from a 5V reference.

The error associated with the 10V excitation would be –80ppm. Hence, overall reference error could be as high as 130ppm, the average of the two.

Figure 45 shows a similar scheme to provide excitation using resistor arrays to produce precise gain. The circuit is configured to provide 10V and –5V excitation to the bridge, producing a common mode voltage at the input to the LTC2430/LTC2431 of 2.5V, maximizing the AC input range for applications where induced 60Hz could reach amplitudes up to 2V

RMS

The circuits in Figures 43 and 45 could be used where multiple bridge circuits are involved and bridge output can be multiplexed onto a single LTC2430/LTC2431, via an inexpensive multiplexer such as the 74HC4052.

Figure 44 shows the use of an LTC2430/LTC2431 with a differential multiplexer. This is an inexpensive multiplexer that will contribute some error due to leakage if used directly with the output from the bridge, or if resistors are inserted as a protection mechanism from overvoltage. Although the bridge output may be within the input range

of the A/D and multiplexer in normal operation, some thought should be given to fault conditions that could result in full excitation voltage at the inputs to the multiplexer or ADC. The use of amplification prior to the multiplexer will largely eliminate errors associated with channel leakage developing error voltages in the source impedance.

Complete 20-Bit Data Acquistion System in 0.1 Inch

The LTC2430/LTC2431 provide 20-bit accuracy while consuming a maximum of 300µA. The MS package of the LTC2431 makes it especially attractive in applications where very limited space is available. A complete 20-bit data acquisition system in 0.1 inch2 is shown in Figure 46 where the LTC2431 is powered by the LT1790 reference family in an S6 package. A supply voltage from 0.25V above the LT1790 output level to 20V enables the LT1790 to source up to 1mA and ensure the solid performance of the LT2431.

The 3V, 3.3V, 4.096V and 5V versions of the LT1790 can power the LTC2430/LTC2431 directly. Lower voltage versions will require a separate VCC supply of 2.7V to 5.5V for the LTC2430/LTC2431.

12 14 15 11

1 5

TO OTHER

DEVICES

Figure 44. Use a Differential Mulitplexer to Expand Channel Capability

2 4

74HC4052

47µF

13 3

REF

–

REF

LTC2430/

LTC2431

–

GND

2431 F44

A0 A1

24301f

Page 38

LTC2430/LTC2431

WUUU

APPLICATIO S I FOR ATIO

350Ω BRIDGE

TWO ELEMENTS

VARYING

2N3904

22Ω

10V

33Ω

×2

Q2, Q3

2N3906

×2

15V

–15V

–5V

20Ω

RN1

10k

RN1

10k

20Ω

0.1µF

1/2

LT1112

15V

1/2

LT1112

–15V

RN1

10k

–

LT1236-5

C3 47µF

LTC2430/

LTC2431

REF

–

REF

–

RN1 10k

RN1 IS CADDOCK T914 10K-010-02

2431 F45

GND

0.1µF

Figure 45. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier

24301f

Page 39

PACKAGE DESCRIPTIO

LTC2430/LTC2431

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.045 ±.005

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.007 – .0098

(0.178 – 0.249)

.016 – .050

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

(0.406 – 1.270)

(MILLIMETERS)

INCHES

.150 – .165

.0250 TYP.0165 ±.0015

.015

(0.38 ± 0.10)

0° – 8° TYP

± .004

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661)

0.889

± 0.127

(.035 ± .005)

.229 – .244

(5.817 – 6.198)

× 45°

.008 – .012

(0.203 – 0.305)

MS Package

.053 – .068

(1.351 – 1.727)

.189 – .196*

(4.801 – 4.978)

12 11 10

678

.0250

(0.635)

BSC

(0.229)

.150 – .157** (3.810 – 3.988)

.004 – .0098

(0.102 – 0.249)

GN16 (SSOP) 0502

.009

REF

5.23

(.206)

MIN

0.305 ± 0.038

(.0120 ± .0015)

TYP

RECOMMENDED SOLDER PAD LAYOUT

0.254

(.010)

GAUGE PLANE

0.18

(.007)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

3.2 – 3.45

(.126 – .136)

DETAIL “A”

0.50

(.0197)

BSC

° – 6° TYP

0.53 ± 0.01

(.021 ± .006)

SEATING

PLANE

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

4.90 ± 0.15

(1.93 ± .006)

0.17 – 0.27

(.007 – .011)

TYP

1.10

(.043)

MAX

0.50

(.0197)

BSC

0.497 ± 0.076

(.0196 ± .003)

3.00 ± 0.102

(.118 ± .004)

NOTE 4

0.86

(.034)

REF

0.13 ± 0.076

(.005 ± .003)

MSOP (MS) 0802

8910

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REF

24301f

Page 40

LTC2430/LTC2431

TYPICAL APPLICATIO

SUPPLY VOLTAGE RANGE:

+ 0.25V) TO 20V

OUT

Relative Size of Components

Figure 46. Complete 20-Bit Data Acquisition System in 0.1 inch

LT1790

4.7µF

0.1µF

ANALOG INPUT RANGE

TO 0.5V

–0.5V

REF

THE LT1790 IS AVAILABLE WITH 1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V AND 5V OUTPUTS

THE LTC2431 MAY BE POWERED BY THE LT1790 3V, 3.3V, 4.096V AND 5V VERSIONS

OUT

REF

LT1790

REF REF

IN IN GND

LTC2431

–

SCK

SDO

24301 TA05

0.1µF

= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION

3-WIRE SPI INTERFACE

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT®1019 Precision Bandgap Reference, 2.5V, 5V 3ppm/°C Drift, 0.05% Max Initial Accuracy LT1025 Micropower Thermocouple Cold Junction Compensator 80µA Supply Current, 0.5°C Initial Accuracy LTC1050 Precision Chopper Stabilized Op Amp No External Components 5µV Offset, 1.6µV LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max Initial Accuracy, 5ppm/°C Drift LT1460 Micropower Series Reference 0.075% Max Initial Accuracy, 10ppm/°C Max Drift LT1790 Micropower SOT23 Low Dropout Reference Family 0.05% Max Initial Accuracy, 10ppm/°C Max Drift LTC2400 24-Bit, No Latency ∆Σ ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency ∆Σ ADC 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2410 24-Bit, Fully Differential, No Latency ∆Σ ADC 0.16ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2411 24-Bit, Fully Differential, No Latency ∆Σ ADC in MS10 0.29ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2413 24-Bit, Fully Differential, No Latency ∆Σ ADC Simultaneous 50Hz and 60Hz Rejection, 800nV LTC2414/LTC2418 8-/16-Channel 24-Bit Differential, No Latency ∆Σ ADC 0.2ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error LTC2415 24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate Pin Compatible with the LTC2410 LTC2420 20-Bit, No Latency ∆Σ ADC in SO-8 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 LTC2421/LTC2422 1-/2-Channel, 20-Bit, No Latency ∆Σ ADC in MSOP-10 1.2ppm Noise, Low Power 2.7V to 5.5V Supply, 200µA LTC2424/LTC2428 4-/8-Channel, 20-Bit, No Latency ∆Σ ADC 1.2ppm Noise, Pin Compatible with LTC2404/LTC2408 LTC2440 24-Bit, High Speed, Low Noise ∆Σ ADC 200nV

Noise, 4000Hz Output Rate

RMS

P-P

Noise

RMS

Noise

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

24301f

LT/TP 0303 2K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2002