Datasheet LTC2402, LTC2401 Datasheet (Linear Technology)

1-/2-Channel 24-Bit µPower

Final Electrical Specifications

No Latency ∆Σ

LTC2401/LTC2402

TM

ADC in MSOP-10

FEATURES

■

24-Bit ADC in Tiny MSOP-10 Package

■

1- or 2-Channel Inputs

■

Automatic Channel Selection (Ping-Pong) (LTC2402)

■

Zero Scale and Full Scale Set for Reference
and Ground Sensing

■

4ppm INL, No Missing Codes

■

4ppm Full-Scale Error

■

0.5ppm Offset

■

0.6ppm Noise

■

Internal Oscillator—No External Components Required

■

110dB Min, 50Hz/60Hz Notch Filter

■

Single Conversion Settling Time for
Multiplexed Applications

■

Reference Input Voltage: 0.1V to V

■

Live Zero—Extended Input Range Accommodates

CC

12.5% Overrange and Underrange

■

Single Supply 2.7V to 5.5V Operation

■

Low Supply Current (200µA) and Auto Shutdown

U

APPLICATIO S

■

Weight Scales

■

Direct Temperature Measurement

■

Gas Analyzers

■

Strain-Gage Transducers

■

Instrumentation

■

Data Acquisition

■

Industrial Process Control

U

January 2000

DESCRIPTIO

The LTC®2401/LTC2402 are 1- and 2-channel 2.7V to

5.5V micropower 24-bit analog-to-digital converters with
an integrated oscillator, 4ppm INL and 0.6ppm RMS
noise. These ultrasmall devices use delta-sigma technol­ogy and a new digital filter architecture that settles in a
single cycle. This eliminates the latency found in conven­tional ∆Σ converters and simplifies multiplexed applica­tions.

Through a single pin, the LTC2401/LTC2402 can be
configured for better than 110dB rejection at 50Hz or
60Hz ±2%, or can be driven by an external oscillator for
a user defined rejection frequency in the range 1Hz to
120Hz. The internal oscillator requires no external fre­quency setting components.

These converters accept an external reference voltage
from 0.1V to VCC. With an extended input conversion
range of –12.5% V
ZS

), the LTC2401/LTC2402 smoothly resolve the off-

SET

set and overrange problems of preceding sensors or
signal conditioning circuits.

The LTC2401/LTC2402 communicate through a 2- or
3-wire digital interface that is compatible with SPI and
MICROWIRETM protocols.

, LTC and LT are registered trademarks of Linear Technology Corporation.

No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.

to 112.5% V

REF

REF

(V

REF

= FS

SET

–

TYPICAL APPLICATIO

2.7V TO 5.5V

1µF

REFERENCE VOLTAGE

ZS

+ 0.1V TO V

SET

INPUT RANGE

TO 1.12V

–0.12V

REF

(V

= FS

REF

SET

0V TO FS

ANALOG

– ZS

SET

REF

SET

– 100mV

CC

)

U

V

CC

110

V

2

FS

3

CH1 SDO

4

CH0

5

ZS

F

CC

O

LTC2402

SET

SET

9

SCK

8

7

CS

6

GND

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION

3-WIRE
SPI INTERFACE

24012 TA01

Pseudo Differential Bridge Digitizer

2.7V TO 5.5V

1

V

CC

LTC2402

2

FS

SET

4

CH0

3

CH1

5

ZS

SET

GND

9

SCK

8

CS

F

O

7

10

3-WIRE
SPI INTERFACE

INTERNAL OSCILLATOR
60Hz REJECTION

SDO

6

24012TA02

1

LTC2401/LTC2402

1
2
3
4
5

V

CC

FS

SET

CH1
CH0

ZS

SET

10
9
8
7
6

F

O

SCK
SDO
CS
GND

TOP VIEW

MS10 PACKAGE

10-LEAD PLASTIC MSOP

WW

W

ABSOLUTE MAXIMUM RATINGS

U

(Notes 1, 2)

Supply Voltage (VCC) to GND.......................–0.3V to 7V

Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V)

Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V)

Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)

Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)

UUW

PACKAGE/ORDER INFORMATION

TOP VIEW

10

1

V

CC

FS

2

SET

V

3

IN

NC

4

ZS

5

SET

MS10 PACKAGE

10-LEAD PLASTIC MSOP

T

= 125°C, θJA = 130°C/W

JMAX

F

O

SCK

9

SDO

8

CS

7

GND

6

Consult factory for Military grade parts.

ORDER PART NUMBER

LTC2401CMS
LTC2401IMS

MS10 PART MARKING

LTMB
LTMC

Operating Temperature Range

LTC2401/LTC2402C ................................ 0°C to 70°C

LTC2401/LTC2402I ............................ –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

ORDER PART NUMBER

LTC2402CMS
LTC2402IMS

MS10 PART MARKING

T

= 125°C, θJA = 130°C/W

JMAX

LTMD

LTME

U

CONVERTER CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution ● 24 Bits
No Missing Codes Resolution 0.1V ≤ FS
Integral Nonlinearity FS

FS

SET
SET

Offset Error 2.5V ≤ FS
Offset Error Drift 2.5V ≤ FS
Full-Scale Error 2.5V ≤ FS
Full-Scale Error Drift 2.5V ≤ FS
Total Unadjusted Error FS

FS

SET
SET

Output Noise VIN = 0V (Note 13) 3 µV
Normal Mode Rejection 60Hz ±2% (Note 7) ● 110 130 dB
Normal Mode Rejection 50Hz ±2% (Note 8) ● 110 130 dB
Power Supply Rejection, DC FS
Power Supply Rejection, 60Hz ±2% FS
Power Supply Rejection, 50Hz ±2% FS

SET

SET

SET

≤ VCC, ZS

SET

= 2.5V, ZS
= 5V, ZS

≤ VCC, ZS

SET

≤ VCC, ZS

SET

≤ VCC, ZS

SET

≤ VCC, ZS

SET

SET

= 2.5V, ZS
= 5V, ZS

SET

= 2.5V, ZS
= 2.5V, ZS
= 2.5V, ZS

SET

= 0V (Note 6) ● 4 15 ppm of V

SET

= 0V 10 ppm of V

SET

SET

SET

The ● denotes specifications which apply over the full operating

= FS

REF

= 0V (Note 5) ● 24 Bits

SET

= 0V (Note 6) ● 2 10 ppm of V

= 0V ● 0.5 2 ppm of V

SET

= 0V 0.01 ppm of V

SET

= 0V ● 4 10 ppm of V

SET

= 0V 0.04 ppm of V

SET

= 0V 5 ppm of V

= 0V, VIN = 0V 100 dB
= 0V, VIN = 0V, (Note 7) 110 dB
= 0V, VIN = 0V, (Note 8) 110 dB

SET

– ZS

. (Notes 3, 4)

SET

REF

REF

REF
REF

REF

/°C

REF

/°C

REF
REF

RMS

2

LTC2401/LTC2402

UU

U

A ALOG I PUT A D REFERE CE

temperature range, otherwise specifications are at TA = 25°C. V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

FS

SET

ZS

SET

C

S(IN)

C

S(REF)

I

IN(LEAK)

I

REF(LEAK)

Input Voltage Range (Note 14) ● –0.125 • V
Full-Scale Set Range ● 0.1 + ZS
Zero-Scale Set Range ● 0FS
Input Sampling Capacitance 10 pF
Reference Sampling Capacitance 15 pF
Input Leakage Current CS = V
Reference Leakage Current V

U

CC

= 2.5V, CS = V

REF

The ● denotes specifications which apply over the full operating

REF

= FS

CC

SET

– ZS

. (Note 3)

SET

REF

SET

● –10 1 10 nA

● –12 1 12 nA

1.125 • V
V

CC

– 0.1 V

SET

REF

V
V

UU

DIGITAL I PUTS A D DIGITAL OUTPUTS

operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

V

IH

V

IL

I

IN

I

IN

C

IN

C

IN

V

OH

V

OL

V

OH

V

OL

I

OZ

High Level Input Voltage 2.7V ≤ VCC ≤ 5.5V ● 2.5 V
CS, F

O

Low Level Input Voltage 4.5V ≤ VCC ≤ 5.5V ● 0.8 V
CS, F

O

High Level Input Voltage 2.7V ≤ VCC ≤ 5.5V (Note 9) ● 2.5 V
SCK 2.7V ≤ V

Low Level Input Voltage 4.5V ≤ VCC ≤ 5.5V (Note 9) ● 0.8 V
SCK 2.7V ≤ V

Digital Input Current 0V ≤ VIN ≤ V
CS, F

O

Digital Input Current 0V ≤ VIN ≤ VCC (Note 9) ● –10 10 µA
SCK

Digital Input Capacitance 10 pF
CS, F

O

Digital Input Capacitance (Note 9) 10 pF
SCK

High Level Output Voltage IO = –800µA ● VCC – 0.5 V
SDO

Low Level Output Voltage IO = 1.6mA ● 0.4 V
SDO

High Level Output Voltage IO = –800µA (Note 10) ● VCC – 0.5 V
SCK

Low Level Output Voltage IO = 1.6mA (Note 10) ● 0.4 V
SCK

High-Z Output Leakage ● –10 10 µA
SDO

2.7V ≤ VCC ≤ 3.3V 2.0 V

2.7V ≤ VCC ≤ 5.5V 0.6 V

The ● denotes specifications which apply over the full

≤ 3.3V (Note 9) 2.0 V

CC

≤ 5.5V (Note 9) 0.6 V

CC

CC

● –10 10 µA

WU

POWER REQUIRE E TS

The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

CC

I

CC

Supply Voltage ● 2.7 5.5 V
Supply Current

Conversion Mode CS = 0V (Note 12)
Sleep Mode CS = V

(Note 12) ● 20 30 µA

CC

● 200 300 µA

3

LTC2401/LTC2402

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

EOSC

t

HEO

t

LEO

t

CONV

f

ISCK

D

ISCK

f

ESCK

t

LESCK

t

HESCK

t

DOUT_ISCK

t

DOUT_ESCK

t

1

t2 CS ↑ to SDO High Z ● 0 150 ns
t3 CS ↓ to SCK ↓ (Note 10) ● 0 150 ns
t4 CS ↓ to SCK ↑ (Note 9) ● 50 ns
t

KQMAX

t

KQMIN

t

5

t

6

External Oscillator Frequency Range ● 2.56 307.2 kHz
External Oscillator High Period ● 0.5 390 µs
External Oscillator Low Period ● 0.5 390 µs
Conversion Time FO = 0V ● 130.66 133.33 136 ms

Internal SCK Frequency Internal Oscillator (Note 10) 19.2 kHz

Internal SCK Duty Cycle (Note 10) 45 55 %
External SCK Frequency Range (Note 9) ● 2000 kHz
External SCK Low Period (Note 9) ● 250 ns
External SCK High Period (Note 9) ● 250 ns
Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 10, 12) ● 1.64 1.67 1.70 ms

External SCK 32-Bit Data Output Time (Note 9) ● 32/f
CS ↓ to SDO Low Z ● 0 150 ns

SCK ↓ to SDO Valid ● 200 ns
SDO Hold After SCK ↓ (Note 5) ● 15 ns
SCK Set-Up Before CS ↓ ● 50 ns
SCK Hold After CS ↓ ● 50 ns

The ● denotes specifications which apply over the full operating temperature

= V

F

O

CC

External Oscillator (Note 11)

External Oscillator (Notes 10, 11) f

External Oscillator (Notes 10, 11)

● 156.80 160 163.20 ms

● 20480/f

● 256/f

(in kHz) ms

EOSC

/8 kHz

EOSC

(in kHz) ms

EOSC

(in kHz) ms

ESCK

Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.

Note 2: All voltage values are with respect to GND.
Note 3: V

= 2.7 to 5.5V unless otherwise specified. Input source

CC

resistance = 0Ω.
Note 4: Internal Conversion Clock source with the F

to GND or to V
f

= 153600Hz unless otherwise specified.

EOSC

or to external conversion clock source with

CC

pin tied

O

Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from

a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.

Note 7: FO = 0V (internal oscillator) or f

= 153600Hz ±2%

EOSC

(external oscillator).
Note 8: F

= VCC (internal oscillator) or f

O

= 128000Hz ±2%

EOSC

(external oscillator).

Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is f

and is expressed in kHz.

ESCK

Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation, the
SCK pin has a total equivalent load capacitance C

LOAD

= 20pF.

Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, f

, is expressed in kHz.

EOSC

Note 12: The converter uses the internal oscillator.

= 0V or FO = VCC.

F

O

Note 13: The output noise includes the contribution of the internal
calibration operations.

Note 14: For reference voltage values V
of –0.125 • V

to 1.125 • V

REF

is limited by the absolute maximum

REF

rating of the Analog Input Voltage pin (Pin 3). For 2.5V < V

0.267V + 0.89 • V
For 0.267V + 0.89 • V
to V

+ 0.3V.

CC

, the input voltage range is –0.3V to 1.125 • V

CC

< V

CC

≤ VCC, the input voltage range is –0.3V

REF

> 2.5V, the extended input

REF

REF

≤

.

REF

4

LTC2401/LTC2402

U

UU

PIN FUNCTIONS

VCC (Pin 1): Positive Supply Voltage. Bypass to GND
(Pin␣ 4) with a 10µF tantalum capacitor in parallel with

0.1µF ceramic capacitor as close to the part as possible.

FS

(Pin 2): Full-Scale Set Input. This pin defines the

SET

full-scale input value. When VIN = FS
full scale (FFFFFH). The total reference voltage is
FS

– ZS

SET

CH0, CH1 (Pins 4, 3): Analog Input Channels. The input
voltage range is –0.125 • V
V

> 2.5V, the input voltage range may be limited by the

REF

absolute maximum rating of – 0.3V to VCC + 0.3V. Conver­sions are performed alternately between CH0
and CH1 for the LTC2402. Pin 4 is a No Connect (NC) on
the LTC2401.

ZS

(Pin 5): Zero-Scale Set Input. This pin defines the

SET

zero-scale input value. When VIN = ZS
outputs zero scale (00000H).

GND (Pin 6): Ground. Shared pin for analog ground,
digital ground, reference ground and signal ground. Should
be connected directly to a ground plane through a mini­mum length trace or it should be the single-point-ground
in a single-point grounding system.

CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW on CS wakes up the ADC. A
LOW-to-HIGH transition on this pin disables the SDO
digital output. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.

SET

.

REF

, the ADC outputs

SET

to 1.125 • V

, the ADC

SET

REF

. For

SDO (Pin 8): Three-State Digital Output. During the data
output period, this pin is used for serial data output. When
the chip select CS is HIGH (CS = VCC), the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin can be used as a conversion status out­put. The conversion status can be observed by pulling CS
LOW.

SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the data output
period. In the External Serial Clock Operation mode, SCK
is used as digital input for the external serial interface. An
internal pull-up current source is automatically activated
in Internal Serial Clock Operation mode. The Serial Clock
mode is determined by the level applied to SCK at power
up and the falling edge of CS.

FO (Pin 10): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter’s
first null is located at 50Hz. When the FO pin is connected
to GND (FO = 0V), the converter uses its internal oscillator
and the digital filter’s first null is located at 60Hz. When F
is driven by an external clock signal with a frequency f
the converter uses this signal as its clock and the digital
filter first null is located at a frequency f

EOSC

/2560.

EOSC

O

,

5

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

Output Data Format

The LTC2401/LTC2402 serial output data stream is 32 bits
long. The first 4 bits represent status information indicat­ing the sign, selected channel, input range and conversion
state. The next 24 bits are the conversion result, MSB first.
The remaining 4 bits are sub LSBs beyond the 24-bit level
that may be included in averaging or discarded without
loss of resolution.

Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.

Bit 30 (second output bit) is LOW if the last conversion
was performed on CH0 and HIGH for CH1.

Bit 29 (third output bit) is the conversion result sign indi­cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW. The sign bit changes state during the zero
code.

Bit 28 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0␣ ≤␣VIN ≤ V
normal input range, VIN > V

, this bit is LOW. If the input is outside the

REF

or VIN < 0, this bit is HIGH.

REF

The function of these bits is summarized in Table 1.

Table 1. LTC2401/LTC2402 Status Bits

Bit 31 Bit 30 Bit 29 Bit 28

Input Range EOC CH0/CH1 SIG EXR

VIN > V

REF

0 < VIN ≤ V
VIN = 0+/0
VIN < 0 0 0/1 0 1

REF

–

0 0/1 1 1
0 0/1 1 0
0 0/1 1/0 0

Bit 27 (fifth output bit) is the most significant bit (MSB).
Bits 27-4 are the 24-bit conversion result MSB first.
Bit 4 is the least significant bit (LSB).
Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may

be included in averaging or discarded without loss of
resolution.

Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 1. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.

In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro­controller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first

6

CS

BIT 31

SDO

Hi-Z

SCK

SLEEP DATA OUTPUT CONVERSION

EOC

1 2 3 4 5 272832

BIT 28BIT 29BIT 30

MSBEXTSIGCH0/CH1

Figure 1. Output Data Timing

LSB

BIT 0BIT 27 BIT 4

24

24012 F01

WUUU

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.

As long as the voltage on the VIN pin is maintained within
the –0.3V to (VCC + 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from –0.125 • V
greater than 1.125 • V
to the value corresponding to 1.125 • V
voltages below –0.125 • V
clamped to the value corresponding to –0.125 • V

to 1.125 • V

REF

, the conversion result is clamped

REF

For input voltages

REF.

. For input

REF

, the conversion result is

REF

REF

.

Single Ended Half-Bridge Digitizer
with Reference and Ground Sensing

Sensors convert real world phenomena (temperature,
pressure, gas levels, etc.) into a voltage. Typically, this
voltage is generated by passing an excitation current

through the sensor. The wires connecting the sensor to the
ADC form parasitic resistors RP1 and RP2. The excitation
current also flows through parasitic resistors RP1 and RP2,
as shown in Figure 2. The voltage drop across these
parasitic resistors leads to systematic offset and full-scale
errors.

In order to eliminate the errors associated with these
parasitic resistors, the LTC2401/LTC2402 include a full­scale set input (FS
(ZS

). As shown in Figure 3, the FS

SET

) and a zero-scale set input

SET

pin acts as a zero

SET

input full-scale sense input. Errors due to parasitic resis­tance RP1 in series with the half-bridge sensor are

+

R

V

FULL-SCALE ERROR

P1

–

I

EXCITATION

Figure 2. Errors Due to Excitation Currents

SENSOR SENSOR OUTPUT

R

P2

+
–

+

V

OFFSET ERROR

–

24012 F02

Table 2. LTC2401/LTC2402 Output Data Format

Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 … Bit 4 Bit 3-0

Input Voltage EOC CH SELECT SIG EXR MSB LSB SUB LSBs*

VIN > 9/8 • V
9/8 • V
V

REF

V

REF

3/4V
3/4V
1/2V
1/2V
1/4V
1/4V
0+/0
–1LSB 0 CH0/CH1 0111 1 11...1 X
–1/8 • V
VIN < –1/8 • V
*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.

**The sign bit changes state during the 0 code.

REF

REF

+ 1LSB 0 CH0/CH1 1100 0 00...0 X

+ 1LSB 0 CH0/CH1 1011 0 00...0 X

REF

REF

+ 1LSB 0 CH0/CH1 1010 0 00...0 X

REF

REF

+ 1LSB 0 CH0/CH1 1001 0 00...0 X

REF

REF
–

REF

REF

0 CH0/CH1 1100 0 11...1 X
0 CH0/CH1 1100 0 11...1 X

0 CH0/CH1 1011 1 11...1 X

0 CH0/CH1 1010 1 11...1 X

0 CH0/CH1 1001 1 11...1 X

0 CH0/CH1 1000 1 11...1 X
0 CH0/CH1 1/0** 0 0 0 0 0 0 ... 0 X

0 CH0/CH1 0111 1 00...0 X
0 CH0/CH1 0111 1 00...0 X

7

LTC2401/LTC2402

00000

H

12.5%
EXTENDED
RANGE

ADC DATA OUT

FFFFF

H

ZS

SET

FS

SET

V

IN

24012 F04

12.5%
EXTENDED
RANGE

WUUU

APPLICATIO S I FOR ATIO

removed by the FS
scale output of the ADC (data out = FFFFFF
at VIN = VB = FS

SET

due to RP2 are removed by the ground sense input ZS
The absolute zero output of the ADC (data out = 000000
occurs at VIN = VA = ZS

input to the ADC. The absolute full-

SET

) will occur

HEX

, see Figure 4. Similarly, the offset errors

.

SET

)

HEX

. Parasitic resistors RP3 to R

SET

P5

have negligible errors due to the 1nA (typ) leakage current
at pins FS

SET

, ZS

and VIN. The wide dynamic input

SET

range (–300mV to 5.3V) and low noise (0.6ppm RMS)
enable the LTC2401 or the LTC2402 to directly digitize the
output of the bridge sensor.

1

V

CC

LTC2401

2

FS

SET

9

V

IN

ZS

GND

SET

SCK

SDO

CS

8

3-WIRE
SPI INTERFACE

7

10

F

O

24012 F03

3

5

6

I

EXCITATION

R

IDC = 0

P1

V

B

R

P3

IDC = 0

R

P4

IDC = 0

V

A

R

R

P5

P2

The LTC2402 is ideal for applications requiring continu­ous monitoring of two input sensors. As shown in
Figure 5, the LTC2402 can monitor both a thermocouple
temperature probe and a cold junction temperature sen­sor. Absolute temperature measurements can be
performed with a variety of thermocouples using digital
cold junction compensation.

The selection between CH0 and CH1 is automatic. Initially,
after power-up, a conversion is performed on CH0. For
each subsequent conversion, the input channel selection

8

Figure 3. Half-Bridge Digitizer with
Zero-Scale and Full-Scale Sense

12k

THERMISTOR

100Ω

Figure 4. Transfer Curve with Zero-Scale and Full-Scale Set

2.7V TO 5.5V

COLD JUNCTION

LTC2402

110

V

CC

2

FS

3

CH1 SDO

4

CH0

5

ZS

SET

SET

SCK

CS

GND

F

O

9

8

7

6

–+

ISOLATION

THERMOCOUPLE

BARRIER

Figure 5. Isolated Temperature Measurement

PROCESSOR

24012 F05

WUUU

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

is alternated. Embedded within the serial data output is a
status bit indicating which channel corresponds to the
conversion result. If the conversion was performed on
CH0, this bit (Bit 30) is LOW and is HIGH if the conversion
was performed on CH1 (see Figure 6).

There are no extra control or status pins required to
perform the alternating 2-channel measurements. The
LTC2402 only requires two digital signals (SCK and SDO).
This simplification is ideal for isolated temperature mea­surements or systems where minimal control signals are
available.

Pseudo Differential Applications

Generally, designers choose fully differential topologies
for several reasons. First, the interface to a 4- or 6-wire
bridge is simple (it is a differential output). Second, they
require good rejection of line frequency noise. Third, they

typically look at a small differential signal sitting on a
large common mode voltage; they need accurate
measurements of the differential signal independent of
the common mode input voltage. Many applications
currently using fully differential analog-to-digital con­verters for any of the above reasons may migrate to a
pseudo differential conversion using the LTC2402.

Direct Connection to a Full Bridge

The LTC2402 interfaces directly to a 4- or 6-wire bridge, as
shown in Figure 7. Like the LTC2401, the LTC2402 in­cludes a FS

and a ZS

SET

for sensing the excitation

SET

voltage directly across the bridge. This eliminates errors
due to excitation currents flowing through parasitic resis­tors. The LTC2402 also includes two single ended input
channels which can tie directly to the differential output of
the bridge. The two conversion results may be digitally
subtracted yielding the differential result.

SCK

SDO

EOC

CH1

• • • • • •

CH1 DATA OUT

EOC

CH0

CH0 DATA OUT

Figure 6. Embedded Selected Channel Indicator

I

EXCITATION

IDC = 0

350Ω 350Ω

350Ω 350Ω

IDC = 0

5V

1

V

CC

2

FS

SET

LTC2402

3

CH1

4

CH0

5

ZS

SET

GND

SCK

SDO

9

8

3-WIRE
SPI INTERFACE

7

CS

10

F

O

24012 F07

24012 F06

Figure 7. Pseudo Differential Strain Guage Application

9

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

The LTC2402’s single ended rejection of line frequencies
(±2%) and harmonics is better than 110dB. Since the
device performs two independent single ended conver­sions each with >110dB rejection, the overall common
mode and differential rejection is much better than the
80dB rejection typically found in other differential input
delta-sigma converters.

In addition to excellent rejection of line frequency noise,
the LTC2402 also exhibits excellent single ended noise
rejection over a wide range of frequencies due to its 4

th

order sinc filter. Each single ended conversion indepen­dently rejects high frequency noise (> 60Hz). Care must be
taken to insure noise at frequencies below 15Hz and at
multiples of the ADC sample rate (15,600Hz) are not
present. For this application, it is recommended the
LTC2402 is placed in close proximity to the bridge sensor
in order to reduce the noise injected into the ADC input. By
performing three successive conversions (CH0-CH1-CH0),
the drift and low frequency noise can be measured and
compensated for digitally.

The absolute accuracy (less than 10 ppm total error) of the
LTC2402 enables extremely accurate measurement of
small signals sitting on large voltages. Each of the two
pseudo differential measurements performed by the
LTC2402 is absolutely accurate independent of the com­mon mode voltage output from the bridge. The pseudo
differential result obtained from digitally subtracting the
two single ended conversion results is accurate to within

the noise level of the device (3µV

) divided by square

RMS

root of 2, independent of the common mode input voltage.
Typically, a bridge sensor outputs 2mV/V full scale. With

a 5V excitation, this translates to a full-scale output of
10mV. Divided by the RMS noise of 4.2µV(= 3µV • 1.414),
this circuit yields 2,300 counts with no averaging or
amplification. If more counts are required, several conver­sions may be averaged (the number of effective counts is
increased by a factor of square root of 2 for each doubling
of averages).

An RTD Temperature Digitizer

RTDs used in remote temperature measurements often
have long lead lengths between the ADC and RTD sensor.
These long lead lengths lead to voltage drops due to
excitation current in the interconnect to the RTD. This
voltage drop can be measured and digitally removed using
the LTC2402 (see Figure 8).

The excitation current (typically 200µA) flows from the
ADC through a long lead length to the remote temperature
sensor (RTD). This current is applied to the RTD, whose
resistance changes as a function of temperature (100Ω to
400Ω for 0°C to 800°C). The same excitation current flows
back to the ADC ground and generates another voltage
drop across the return leads. In order to get an accurate
measurement of the temperature, these voltage drops
must be measured and removed from the conversion
result. Assuming the resistance is approximately the same

10

5V

1

V

CC

2

FS

SET

I

+

P

t

V

RTD

100Ω

Figure 8. RTD Remote Temperature Measurement

I

–

EXCITATION

EXCITATION

IDC = 0

= 200µA

R1

= 200µA

R2

LTC2402

SET

GND

SCK

SDO

CS

F

O

4

CH0

3

CH1

5

ZS

9

8

7

10

3-WIRE
SPI INTERFACE

24012 F08

WUUU

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

for the forward and return paths (R1 = R2), the auxiliary
channel on the LTC2402 can measure this drop. These
errors are then removed with simple digital correction.

The result of the first conversion on CH0 corresponds to
an input voltage of V
second conversion (CH1) is –R1 • I

RTD

+ R1 • I

EXCITATION.

EXCITATION.

The result of the

Note, the
LTC2402’s input range is not limited to the supply rails, it
has underrange capabilities. The device’s input range is
–300mV to V

+ 300mV. Adding the two conversion

REF

results together, the voltage drop across the RTD’s leads
are cancelled and the final result is V

RTD

.

An Isolated, 24-Bit Data Acquisition System

The LTC1535 is useful for signal isolation. Figure 9 shows
a fully isolated, 24-bit differential input A/D converter
implemented with the LTC1535 and LTC2402. Power on
the isolated side is regulated by an LT1761-5.0 low noise,
low dropout micropower regulator. Its output is suitable
for driving bridge circuits and for ratiometric applications.

During power-up, the LTC2402 becomes active at VCC =

2.3V, while the isolated side of the LTC1535 must wait for
V

to reach its undervoltage lockout threshold of 4.2V.

CC2

Below 4.2V, the LTC1535’s driver outputs Y and Z are in a
high impedance state, allowing the 1kΩ pull-down to
define the logic state at SCK. When the LTC2402 first
becomes active, it samples SCK; a logic “0” provided by
the 1kΩ pull-down invokes the external serial clock mode.
In this mode, the LTC2402 is controlled by a single clock
line from the nonisolated side of the barrier, through the
LTC1535’s driver output Y. The entire power-up sequence,
from the time power is applied to V

until the LT1761’s

CC1

output has reached 5V, is approximately 1ms.
Data returns to the nonisolated side through the LTC1535’s

receiver at RO. An internal divider on receiver input B sets
a logic threshold of approximately 3.4V at input A, facili­tating communications with the LTC2402’s SDO output
without the need for any external components.

“SDO”

“SCK”

LOGIC 5V

1/2 BAT54C

+

10µF
16V
TANT

T1

1/2 BAT54C

ST1

V

+

CC1

ISOLATION

1

ST2

G1

BARRIER

LTC1535

G2

T1 = COILTRONICS CTX02-14659
OR SIEMENS B78304-A1477-A3

RO
RE
DE
DI

10µF

10V

1

TANT

1µF

V

CC2

= LOGIC COMMON

1

= FLOATING COMMON

2

A
B
Y

Z

LT1761-5

IN OUT

SHDN BYP

GND

2

+

10µF
10V
TAN T

2

1k

21 2

2

10µF

F

O

SCK
SDO
CS
GND

+

LTC2402

FS

ZS

V

SET

CH1
CH0

SET

10µF
10V
TAN T

CC

10µF

CERAMIC

2

24012 F09

Figure 9. Complete, Isolated 24-Bit Data Acquisition System

11

LTC2401/LTC2402

(

UU

W

PACKAGE I FOR ATIO

0.007

(0.18)

0.021 ± 0.006
(0.53 ± 0.015)

* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006"

Dimensions in inches (millimeters) unless otherwise noted.

MS10 Package

10-Lead Plastic MSOP

(LTC DWG # 05-08-1661)

0.118 ± 0.004*

0° – 6° TYP

(3.00 ± 0.102)

0.193 ± 0.006
(4.90 ± 0.15)

SEATING

PLANE

0.040 ± 0.006
(1.02 ± 0.15)

0.009

(0.228)

REF

8910

7

6

0.118 ± 0.004**

45

12

3

0.0197
(0.50)

BSC

0.152mm) PER SIDE

(3.00 ± 0.102)

0.034 ± 0.004
(0.86 ± 0.102)

0.006 ± 0.004

(0.15 ± 0.102)

MSOP (MS10) 1098

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1019 Precision Bandgap Reference, 2.5V, 5V 3ppm/°C Drift, 0.05% Max
LT1025 Micropower Thermocouple Cold Junction Compensator 80µA Supply Current, 0.5°C Initial Accuracy
LTC1043 Dual Precision Instrumentation Switched Capacitor Precise Charge, Balanced Switching, Low Power

Building Block

LTC1050 Precision Chopper Stabilized Op Amp No External Components 5µV Offset, 1.6µV
LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max, 5ppm/°C Drift
LTC1391 8-Channel Multiplexer Low RON: 45Ω, Low Charge Injection Serial Interface
LT1460 Micropower Series Reference 0.075% Max, 10ppm/°C Max Drift, 2.5V, 5V and 10V Versions,

MSOP, PDIP, SO-8, SOT-23 and TO-92 Packages

LT1461-2.5 Precision Micropower Voltage Reference 50µA Supply Current, 3ppm/°C Drift
LTC2400 24-Bit, No Latency ∆Σ ADC in SO-8 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency ∆Σ ADC 4ppm INL, 10ppm Total Unadjusted Error, 200µA

24012i LT/TP 0100 4K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2000

12

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear-tech.com

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