Datasheet LTC2401, LTC2402 Datasheet (LINEAR TECHNOLOGY)

Download

Page 1

No Latency ∆Σ

FEATURES

■

24-Bit ADCs in Tiny MSOP-10 Packages

■

4ppm INL, No Missing Codes

■

4ppm Full-Scale Error

■

0.5ppm Offset

■

0.6ppm Noise

■

Single Conversion Settling Time for Multiplexed Applications

■

1- or 2-Channel Inputs

■

Automatic Channel Selection (Ping-Pong) (LTC2402)

■

Zero Scale and Full Scale Set for Reference and Ground Sensing

■

Internal Oscillator—No External Components Required

■

110dB Min, 50Hz/60Hz Notch Filter

■

Reference Input Voltage: 0.1V to V

■

Live Zero—Extended Input Range Accommodates

12.5% Overrange and Underrange

■

Single Supply 2.7V to 5.5V Operation

■

Low Supply Current (200µA) and Auto Shutdown

APPLICATIO S

LTC2401/LTC2402

1-/2-Channel 24-Bit µPower

ADCs in MSOP-10

DESCRIPTIO

The LTC®2401/LTC2402 are 1- and 2-channel 2.7V to 5.5V micropower 24-bit analog-to-digital converters with an integrated oscillator, 4ppm INL and 0.6ppm RMS noise. These ultrasmall devices use delta-sigma technology and a new digital filter architecture that settles in a single cycle. This eliminates the latency found in conventional ∆Σ converters and simplifies multiplexed applications.

Through a single pin, the LTC2401/LTC2402 can be configured for better than 110dB rejection at 50Hz or 60Hz ±2%, or can be driven by an external oscillator for a user defined rejection frequency in the range 1Hz to 120Hz. The internal oscillator requires no external frequency setting components.

These converters accept an external reference voltage from 0.1V to VCC. With an extended input conversion range of –12.5% V ZS

), the LTC2401/LTC2402 smoothly resolve the off-

SET

set and overrange problems of preceding sensors or signal conditioning circuits.

to 112.5% V

REF

= FS

SET

–

■

Weight Scales

■

Direct Temperature Measurement

■

Gas Analyzers

■

Strain Gauge Transducers

■

Instrumentation

■

Data Acquisition

■

Industrial Process Control

TYPICAL APPLICATIO

2.7V TO 5.5V

1µF

110

REFERENCE VOLTAGE

+ 0.1V TO V

SET

ANALOG INPUT RANGE

– 0.12V

SET

+ 0.12V

– ZS

SET

REF

SET

– 100mV

REF

SET

FS = FS

0V TO FS

)

CH1 SDO

CH0

LTC2402

SET

SCK

GND

The LTC2401/LTC2402 communicate through a 2- or 3-wire digital interface that is compatible with SPI and MICROWIRETM protocols.

, LTC and LT are registered trademarks of Linear Technology Corporation.

No Latency ∆Σ is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.

Pseudo Differential Bridge Digitizer

SCK

SDO

2.7V TO 5.5V

3-WIRE SPI INTERFACE

INTERNAL OSCILLATOR 60Hz REJECTION

24012TA02

= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION

3-WIRE SPI INTERFACE

24012 TA01

LTC2402

SET

CH0

CH1

SET

GND

Page 2

LTC2401/LTC2402

1 2 3 4 5

SET

CH1 CH0

SET

10 9 8 7 6

SCK SDO CS GND

TOP VIEW

MS10 PACKAGE

10-LEAD PLASTIC MSOP

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

Supply Voltage (VCC) to GND.......................– 0.3V to 7V

Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V)

Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V)

Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)

Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)

UUW

PACKAGE/ORDER INFORMATION

TOP VIEW

SET

MS10 PACKAGE

10-LEAD PLASTIC MSOP

= 125°C, θJA = 130°C/W

JMAX

SCK

SDO

GND

Consult factory for Military grade parts.

ORDER PART NUMBER

LTC2401CMS LTC2401IMS

MS10 PART MARKING

LTMB LTMC

Operating Temperature Range

LTC2401/LTC2402C ................................ 0°C to 70°C

LTC2401/LTC2402I ............................ –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

ORDER PART NUMBER

LTC2402CMS LTC2402IMS

MS10 PART MARKING

= 125°C, θJA = 130°C/W

JMAX

LTMD

LTME

CONVERTER CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution ● 24 Bits No Missing Codes Resolution 0.1V ≤ FS Integral Nonlinearity FS

SET SET

Offset Error 2.5V ≤ FS Offset Error Drift 2.5V ≤ FS Full-Scale Error 2.5V ≤ FS Full-Scale Error Drift 2.5V ≤ FS Total Unadjusted Error FS

SET SET

Output Noise VIN = 0V (Note 13) 3 µV Normal Mode Rejection 60Hz ±2% (Note 7) ● 110 130 dB Normal Mode Rejection 50Hz ±2% (Note 8) ● 110 130 dB Power Supply Rejection, DC FS Power Supply Rejection, 60Hz ±2% FS Power Supply Rejection, 50Hz ±2% FS

SET

≤ VCC, ZS

SET

= 2.5V, ZS = 5V, ZS

≤ VCC, ZS

SET

≤ VCC, ZS

SET

≤ VCC, ZS

SET

≤ VCC, ZS

SET

= 2.5V, ZS = 5V, ZS

SET

= 2.5V, ZS = 2.5V, ZS = 2.5V, ZS

SET

= 0V (Note 6) ● 4 15 ppm of V

SET

= 0V 10 ppm of V

SET

The ● denotes specifications which apply over the full operating

= FS

REF

= 0V (Note 5) ● 24 Bits

SET

= 0V (Note 6) ● 2 10 ppm of V

= 0V ● 0.5 2 ppm of V

SET

= 0V 0.01 ppm of V

SET

= 0V ● 4 10 ppm of V

SET

= 0V 0.04 ppm of V

SET

= 0V 5 ppm of V

= 0V, VIN = 0V 100 dB = 0V, VIN = 0V, (Notes 7, 15) 110 dB = 0V, VIN = 0V, (Notes 8, 15) 110 dB

SET

– ZS

. (Notes 3, 4)

SET

REF

REF REF

REF

/°C

REF

/°C

REF REF

RMS

Page 3

LTC2401/LTC2402

A ALOG I PUT A D REFERE CE

temperature range, otherwise specifications are at TA = 25°C. V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SET

S(IN)

S(REF)

IN(LEAK)

REF(LEAK)

Input Voltage Range (Note 14) ● ZS Full-Scale Set Range ● 0.1 + ZS Zero-Scale Set Range ● 0FS Input Sampling Capacitance 10 pF Reference Sampling Capacitance 15 pF Input Leakage Current CS = V Reference Leakage Current V

= 2.5V, CS = V

REF

The ● denotes specifications which apply over the full operating

REF

= FS

SET

– ZS

. (Note 3)

SET

– 0.12V

SET

● –10 1 10 nA

● –12 1 12 nA

REF

SET

+ 0.12V

SET

– 0.1 V

REF

V V

DIGITAL I PUTS A D DIGITAL OUTPUTS

operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

High Level Input Voltage 2.7V ≤ VCC ≤ 5.5V ● 2.5 V CS, F

Low Level Input Voltage 4.5V ≤ VCC ≤ 5.5V ● 0.8 V CS, F

High Level Input Voltage 2.7V ≤ VCC ≤ 5.5V (Note 9) ● 2.5 V SCK 2.7V ≤ V

Low Level Input Voltage 4.5V ≤ VCC ≤ 5.5V (Note 9) ● 0.8 V SCK 2.7V ≤ V

Digital Input Current 0V ≤ VIN ≤ V CS, F

Digital Input Current 0V ≤ VIN ≤ VCC (Note 9) ● –10 10 µA SCK

Digital Input Capacitance 10 pF CS, F

Digital Input Capacitance (Note 9) 10 pF SCK

High Level Output Voltage IO = –800µA ● VCC – 0.5 V SDO

Low Level Output Voltage IO = 1.6mA ● 0.4 V SDO

High Level Output Voltage IO = –800µA (Note 10) ● VCC – 0.5 V SCK

Low Level Output Voltage IO = 1.6mA (Note 10) ● 0.4 V SCK

High-Z Output Leakage ● –10 10 µA SDO

2.7V ≤ VCC ≤ 3.3V 2.0 V

2.7V ≤ VCC ≤ 5.5V 0.6 V

The ● denotes specifications which apply over the full

≤ 3.3V (Note 9) 2.0 V

≤ 5.5V (Note 9) 0.6 V

● –10 10 µA

POWER REQUIRE E TS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage ● 2.7 5.5 V Supply Current

Conversion Mode CS = 0V (Note 12) Sleep Mode CS = V

(Note 12) ● 20 30 µA

● 200 300 µA

Page 4

LTC2401/LTC2402

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

EOSC

HEO

LEO

CONV

ISCK

ESCK

LESCK

HESCK

DOUT_ISCK

DOUT_ESCK

KQMAX

KQMIN

External Oscillator Frequency Range ● 2.56 307.2 kHz External Oscillator High Period ● 0.5 390 µs External Oscillator Low Period ● 0.5 390 µs Conversion Time FO = 0V ● 130.86 133.53 136.20 ms

Internal SCK Frequency Internal Oscillator (Note 10) 19.2 kHz

Internal SCK Duty Cycle (Note 10) 45 55 % External SCK Frequency Range (Note 9) ● 2000 kHz External SCK Low Period (Note 9) ● 250 ns External SCK High Period (Note 9) ● 250 ns Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 10, 12) ● 1.64 1.67 1.70 ms

External SCK 32-Bit Data Output Time (Note 9) ● 32/f CS ↓ to SDO Low Z ● 0 150 ns CS ↑ to SDO High Z ● 0 150 ns CS ↓ to SCK ↓ (Note 10) ● 0 150 ns CS ↓ to SCK ↑ (Note 9) ● 50 ns SCK ↓ to SDO Valid ● 200 ns SDO Hold After SCK ↓ (Note 5) ● 15 ns SCK Set-Up Before CS ↓ ● 50 ns SCK Hold After CS ↓ ● 50 ns

The ● denotes specifications which apply over the full operating temperature

= V

External Oscillator (Note 11)

External Oscillator (Notes 10, 11) f

External Oscillator (Notes 10, 11)

● 157.03 160.23 163.44 ms

● 20510/f

● 256/f

(in kHz) ms

EOSC

/8 kHz

EOSC

(in kHz) ms

EOSC

(in kHz) ms

ESCK

Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired.

Note 2: All voltage values are with respect to GND. Note 3: V

= 2.7 to 5.5V unless otherwise specified. Input source

resistance = 0Ω. Note 4: Internal Conversion Clock source with the F

to GND or to V f

= 153600Hz unless otherwise specified.

EOSC

or to external conversion clock source with

pin tied

Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from

a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.

Note 7: FO = 0V (internal oscillator) or f

= 153600Hz ±2%

EOSC

(external oscillator). Note 8: F

= VCC (internal oscillator) or f

= 128000Hz ±2%

EOSC

(external oscillator).

Note 9: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is f

and is expressed in kHz.

ESCK

Note 10: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation, the SCK pin has a total equivalent load capacitance C

LOAD

= 20pF.

Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, f

, is expressed in kHz.

EOSC

Note 12: The converter uses the internal oscillator.

= 0V or FO = VCC.

Note 13: The output noise includes the contribution of the internal calibration operations.

= FS

– ZS

Note 14: V

REF

SET

to –0.3V and the maximum to V Note 15: VCC (DC) = 4.1V, VCC (AC) = 2.8V

. The minimum input voltage is limited

SET

+ 0.3V.

P-P

Page 5

INPUT VOLTAGE (V)

–0.3

–10

ERROR (ppm)

–5

–0.25 –0.2 –0.15 –0.1

24012 G03

–0.05 0

TA = 25°C

TA = –45°C

TA = –55°C

TA = 90°C

= 125°C

VCC = 3V V

REF

= 2.5V

TYPICAL PERFOR A CE CHARACTERISTICS

Total Unadjusted Error (3V Supply)

VCC = 3V

= 2.5V

REF

= –55°C, –45°C, 25°C, 90°C

INL (3V Supply)

VCC = 3V

= 2.5V

REF

LTC2401/LTC2402

Negative Extended Input Range Total Unadjusted Error (3V Supply)

ERROR (ppm)

–5

125°C

–10

0.5

INPUT VOLTAGE (V)

1.0

1.5

Positive Extended Input Range Total Unadjusted Error (3V Supply)

VCC = 3V

= 2.5V

REF

= –55°C, –45°C, 25°C, 90°C, 125°C

ERROR (ppm)

–5

–10

2.5

2.55 2.6 2.65 2.7 INPUT VOLTAGE (V)

2.0

24012 G01

2.75 2.8

24012 G04

2.5

ERROR (ppm)

–5

–10

= –55°C, –45°C, 25°C, 90°C

0.5

1.0

INPUT VOLTAGE (V)

1.5

125°C

2.0

Total Unadjusted Error (5V Supply)

VCC = 5V

= 5V

REF

= –55°C, –45°C, 25°C, 90°C, 125°C

ERROR (ppm)

–5

–10

INPUT VOLTAGE (V)

3.02.5

24012 G02

INL (5V Supply)

VCC = 5V

= 5V

REF

= –55°C, –45°C, 25°C, 90°C, 125°C

ERROR (ppm)

–5

24012 G05

–10

0.5

2.5

1.5 INPUT VOLTAGE (V)

3.5

4.5

24012 G06

Negative Extended Input Range Total Unadjusted Error (5V Supply)

ERROR (ppm)

–5

V V

–10

–0.3

TA = 90°C

TA = 25°C

TA = –45°C

TA = –55°C

= 5V

REF

–0.25 –0.2 –0.15 –0.1

INPUT VOLTAGE (V)

= 125°C

–0.05 0

24012 G07

Positive Extended Input Range Total Unadjusted Error (5V Supply)

VCC = 5V

= 5V

REF

ERROR (ppm)

–5

–10

5.0

TA = 90°C

= 125°C

5.05 5.1 5.15 5.2 INPUT VOLTAGE (V)

TA = –55°C

TA = –45°C

TA = 25°C

5.25 5.3

24012 G08

Offset Error vs Reference Voltage

OFFSET ERROR (ppm)

REFERENCE VOLTAGE (V)

VCC = 5V

= 25°C

24012 G09

Page 6

LTC2401/LTC2402

TYPICAL PERFOR A CE CHARACTERISTICS

RMS Noise vs Reference Voltage Offset Error vs V

20 18 16

)

REF

14 12 10

RMS NOISE (ppm OF V

4 2 0

REFERENCE VOLTAGE (V)

VCC = 5V T

= 25°C

24012 G10

5.0 V

= 2.5V

REF

= 25°C

2.5

OFFSET ERROR (ppm)

–2.5

–5.0

2.7

3.2 3.7 4.2 4.7 V

5.2

24012 G11

RMS Noise vs V

5.0 V

= 2.5V

REF

= 25°C

2.5

RMS NOISE (ppm)

3.2 3.7 4.2 4.7

2.7

Noise Histogram RMS Noise vs Code Out Offset Error vs Temperature

350

VCC = 5V

= 5V

REF

300

= 0V

250

200

150

100

NUMBER OF READINGS

1.00 VCC = 5V

= 5V

REF

= –0.3V TO 5.3V

= 25°C

0.75

0.50

RMS NOISE (ppm)

0.25

5.0 VCC = 5V

= 5V

REF

= 0V

2.5

OFFSET ERROR (ppm)

–2.5

5.2

24012 G12

–1 0 1 3

–2

OUTPUT CODE (ppm)

Full-Scale Error vs Temperature

5.0 VCC = 5V

= 5V

REF

= 5V

2.5

–2.5

FULL-SCALE ERROR (ppm)

–5.0

–55

–30 –5 20 45

TEMPERATURE (°C)

24012 G13

70 95 120

24012 G16

–0.3

2.5

CODE OUT (HEX)

5.3

24012 G14

–5.0

–55

–30 –5 20 45

TEMPERATURE (°C)

Full-Scale Error vs Reference Voltage Full-Scale Error vs V

FULL-SCALE ERROR (ppm)

1234

REFERENCE VOLTAGE (V)

VCC = 5V

= V

24012 G17

REF

= 2.5V

REF

= 2.5V

= 25°C

FULL-SCALE ERROR (ppm)

2.7

3.2 3.7 4.2 4.7

70 95 120

24012 G15

5.2

24012 G18

Page 7

FREQUENCY AT VCC (Hz)

–120

REJECTION (dB)

–105

–90

–75

–60

100 10k

24012 G21

VCC = 4.1V V

= 0V

= 25°C

= 0

FREQUENCY AT VIN (Hz)

–120

REJECTION (dB)

–100

–80

–60

–40

–20

50 100 150 200

24012 G24

250

VCC = 5V V

REF

= 5V

= 2.5V

= 0

INPUT FREQUENCY

–60

–40

24012 G27

–80

–100

fS/2 f

–120

–140

–20

REJECTION (dB)

TYPICAL PERFOR A CE CHARACTERISTICS

Conversion Current vs Temperature

230

220

210

200

190

180

SUPPLY CURRENT (µA)

170

160

150

–30 –5 45

–55

VCC = 5.5V

VCC = 4.1V

VCC = 2.7V

TEMPERATURE (°C)

70 95 120

24012 G19

Sleep Current vs Temperature

SUPPLY CURRENT (µA)

–30 –5 20 45

–55

VCC = 2.7V

VCC = 5V

TEMPERATURE (°C)

70 95 120

24012 G20

LTC2401/LTC2402

Rejection vs Frequency at V

–40

VCC = 4.1V

= 0V

= 25°C

= 0

–60

–80

REJECTION (dB)

–100

–120

FREQUENCY AT VCC (Hz)

100

150

Rejection vs Frequency at V

–60

–70

–80

–90

–100

–110

REJECTION (dB)

–120

–130

–140

–12–8–404812

INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)

200

250

24012 G22

24012 G25

Rejection vs Frequency at V

–60

VCC = 4.1V

= 0V

= 25°C

= 0

–75

–90

REJECTION (dB)

–105

–120

15200

15250 15300 15350 15400

FREQUENCY AT VCC (Hz)

Rejection vs Frequency at V

VCC = 5V

= 5V

REF

–20

= 2.5V

= 0

–40

–60

REJECTION (dB)

–80

–100

–120

SAMPLE RATE = 15.36kHz ±2%

15100

15200 15300 15400 15500

FREQUENCY AT VIN (Hz)

15450 15500

24012 G23

24012 G26

Rejection vs Frequency at V

Page 8

LTC2401/LTC2402

TYPICAL PERFOR A CE CHARACTERISTICS

INL vs Output Rate

VCC = 5V

= 5V

REF

= EXTERNAL

INL (BITS)

TA = 90°C

TA = 25°C

OUTPUT RATE (Hz)

TA = –55°C

24012 G28

100

UUU

PIN FUNCTIONS

VCC (Pin 1): Positive Supply Voltage. Bypass to GND (Pin␣ 6) with a 10µF tantalum capacitor in parallel with

0.1µF ceramic capacitor as close to the part as possible.

Resolution vs Output Rate

RESOLUTION (BITS)

VCC = 5V

= 5V

REF

= EXTERNAL

TA = 90°C

TA = 25°C

OUTPUT RATE (Hz)

TA = –55°C

100

24012 G29

be connected directly to a ground plane through a minimum length trace or it should be the single-point-ground in a single-point grounding system.

(Pin 2): Full-Scale Set Input. This pin defines the

SET

full-scale input value. When VIN = FS

, the ADC outputs

SET

full scale (FFFFFH). The total reference voltage is FS

SET

– ZS

SET

CH0, CH1 (Pins 4, 3): Analog Input Channels. The input voltage range is –0.125 • V V

> 2.5V, the input voltage range may be limited by the

REF

to 1.125 • V

REF

. For

absolute maximum rating of – 0.3V to VCC + 0.3V. Conversions are performed alternately between CH0 and CH1 for the LTC2402. Pin 4 is a No Connect (NC) on the LTC2401.

(Pin 5): Zero-Scale Set Input. This pin defines the

SET

zero-scale input value. When VIN = ZS

, the ADC

SET

outputs zero scale (00000H). GND (Pin 6): Ground. Shared pin for analog ground,

digital ground, reference ground and signal ground. Should

CS (Pin 7): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW on CS wakes up the ADC. A LOW-to-HIGH transition on this pin disables the SDO digital output. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion.

SDO (Pin 8): Three-State Digital Output. During the data output period, this pin is used for serial data output. When the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin can be used as a conversion status output. The conversion status can be observed by pulling CS LOW.

Page 9

LTC2401/LTC2402

3.4k

SDO

24012 TC02

Hi-Z TO V

VOH TO V

VOL TO Hi-Z

LOAD

= 20pF

PIN FUNCTIONS

SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the data output period. In the External Serial Clock Operation mode, SCK is used as digital input for the external serial interface. An internal pull-up current source is automatically activated in Internal Serial Clock Operation mode. The Serial Clock mode is determined by the level applied to SCK at power up and the falling edge of CS.

FUNCTIONAL BLOCK DIAGRA

GND

FO (Pin 10): Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion time. When the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter’s first null is located at 50Hz. When the FO pin is connected to GND (FO = 0V), the converter uses its internal oscillator and the digital filter’s first null is located at 60Hz. When F is driven by an external clock signal with a frequency f

EOSC

, the converter uses this signal as its clock and the digital filter first null is located at a frequency f

OSCILLATOR

AUTOCALIBRATION

AND CONTROL

EOSC

INTERNAL

/2560.

(INT/EXT)

REF

TEST CIRCUITS

SDO

DAC

3.4k

Hi-Z TO V

VOL TO V

VOH TO Hi-Z

LOAD

∫∫∫

= 20pF

24012 TC01

∑

ADC

DECIMATING FIR

SERIAL

INTERFACE

SDO

SCK

24012 FD

Page 10

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

Converter Operation Cycle

The LTC2401/LTC2402 are low power, delta-sigma analog-to-digital converters with an easy to use 3-wire serial interface. Their operation is simple and made up of three states. The converter operating cycle begins with the conversion, followed by a low power sleep state and concluded with the data output (see Figure 1). The 3-wire interface consists of serial data output (SDO), a serial clock (SCK) and a chip select (CS).

Initially, the LTC2401/LTC2402 perform a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced by an order of magnitude. The part remains in the sleep state as long as CS is logic HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state.

Once CS is pulled low, the device begins outputting the conversion result. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK, see Figure 3. The data output state is concluded once 32 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion cycle and the cycle repeats.

CONVERT

SLEEP

CS AND

SCK

DATA OUTPUT

24012 F01

Figure 1. LTC2401/LTC2402 State Transition Diagram

Through timing control of the CS and SCK pins, the LTC2401/LTC2402 offer several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section.

Conversion Clock

A major advantage delta-sigma converters offer over conventional type converters is an on-chip digital filter (commonly known as Sinc or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz or 60Hz plus their harmonics. In order to reject these frequencies in excess of 110dB, a highly accurate conversion clock is required. The LTC2401/LTC2402 incorporate an on-chip highly accurate oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2401/ LTC2402 reject line frequencies (50Hz or 60Hz ±2%) a minimum of 110dB.

Ease of Use

The LTC2401/LTC2402 data output has no latency, filter settling or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing an analog input voltage is easy.

The LTC2401/LTC2402 perform offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift.

Power-Up Sequence

The LTC2401/LTC2402 automatically enter an internal reset state when the power supply voltage VCC drops below approximately 2.2V. This feature guarantees the

Page 11

WUUU

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

integrity of the conversion result and of the serial interface mode selection which is performed at the initial power-up. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.)

When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with duration of approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2401/LTC2402 start a normal conversion cycle and follows the normal succession of states described above. The first conversion result following POR is accurate within the specifications of the device.

Reference Voltage Range

The LTC2401/LTC2402 can accept a reference voltage (V

REF

= FS

SET

– ZS

)

from 0V to VCC. The converter

SET

output noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter’s effective resolution. On the other hand, a reduced reference voltage will improve the overall converter INL performance. The recommended range for the LTC2401/LTC2402 voltage reference is 100mV to VCC.

Input Voltage Range

The converter is able to accommodate system level offset and gain errors as well as system level overrange situations due to its extended input range, see Figure 2. The LTC2401/LTC2402 convert input signals within the extended input range of –0.125 • V (V

= FS

REF

For large values of V

SET

– ZS

SET

REF

= FS

SET

REF

– ZS

to 1.125 • V

this range

SET

REF

is limited by the absolute maximum voltage range of –0.3V to (VCC + 0.3V). Beyond this range, the input ESD protection devices begin to turn on and the errors due to the input leakage current increase rapidly.

Input signals applied to VIN may extend below ground by –300mV and above VCC by 300mV. In order to limit any fault current, a resistor of up to 5k may be added in series with the VIN pin without affecting the performance of the device. In the physical layout, it is important to maintain

VCC + 0.3V

+ 0.12V

SET

REF

SET

NORMAL

INPUT

RANGE

SET

– 0.12V

REF

–0.3V

Figure 2. LTC2401/LTC2402 Input Range

= FS

REF

SET

– ZS

EXTENDED

INPUT

RANGE

)

SET

ABSOLUTE

MAXIMUM

INPUT

RANGE

24012 F02

the parasitic capacitance of the connection between this series resistance and the VIN pin as low as possible; therefore, the resistor should be located as close as practical to the VIN pin. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Analog Input/Reference Current section. In addition, a series resistor will introduce a temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if V

= 5V. This error

REF

has a very strong temperature dependency.

Output Data Format

The LTC2401/LTC2402 serial output data stream is 32 bits long. The first 4 bits represent status information indicating the sign, selected channel, input range and conversion state. The next 24 bits are the conversion result, MSB first. The remaining 4 bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.

Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete.

Bit 30 (second output bit) for the LTC2402, this bit is LOW if the last conversion was performed on CH0 and HIGH for CH1. This bit is always low for the LTC2401.

Page 12

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW. The sign bit changes state during the zero code.

Bit 28 (forth output bit) is the extended input range (EXR) indicator. If the input is within the normal input range 0␣ ≤␣VIN ≤ V normal input range, VIN > V

, this bit is LOW. If the input is outside the

REF

or VIN < 0, this bit is HIGH.

REF

The function of these bits is summarized in Table 1.

Table 1. LTC2401/LTC2402 Status Bits

Bit 31 Bit 30 Bit 29 Bit 28

Input Range EOC CH0/CH1 SIG EXR

VIN > V

REF

0 < VIN ≤ V VIN = 0+/0 VIN < 0 0 0/1 0 1

REF

–

0 0/1 1 1 0 0/1 1 0 0 0/1 1/0 0

Bit 27 (fifth output bit) is the most significant bit (MSB). Bits 27-4 are the 24-bit conversion result MSB first. Bit 4 is the least significant bit (LSB). Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may

be included in averaging or discarded without loss of resolution.

Data is shifted out of the SDO pin under control of the serial clock (SCK), see Figure 3. Whenever CS is HIGH, SDO remains high impedance and any SCK clock pulses are ignored by the internal data out shift register.

In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes real time from

HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 31 (EOC) can be captured on the first rising edge of SCK. Bit 30 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 31st SCK and may be latched on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating a new conversion cycle has been initiated. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format.

As long as the voltage on the VIN pin is maintained within the –0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any input value from –0.125 • V greater than 1.125 • V to the value corresponding to 1.125 • V voltages below –0.125 • V clamped to the value corresponding to –0.125 • V

to 1.125 • V

REF

, the conversion result is clamped

REF

For input voltages

REF.

. For input

REF

, the conversion result is

REF

Frequency Rejection Selection (FO Pin Connection)

The LTC2401/LTC2402 internal oscillator provides better than 110dB normal mode rejection at the line frequency and all its harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz rejection, FO (Pin 10) should be connected to GND (Pin 6) while for 50Hz rejection the FO pin should be connected to V

(Pin␣ 1).

The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level. A selection change during the sleep or data output states will not

SDO

SCK

BIT 31

EOC

Hi-Z

1 2 3 4 5 272832

SLEEP DATA OUTPUT CONVERSION

BIT 28BIT 29BIT 30

MSBEXTSIGCH0/CH1

Figure 3. Output Data Timing

LSB

BIT 0BIT 27 BIT 4

24012 F03

Page 13

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

Table 2. LTC2401/LTC2402 Output Data Format

Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 … Bit 4 Bit 3-0

Input Voltage EOC CH SELECT SIG EXR MSB LSB SUB LSBs*

VIN > 9/8 • V 9/8 • V V

REF

3/4V 3/4V 1/2V 1/2V 1/4V 1/4V 0+/0 –1LSB 0 CH0/CH1 0111 1 11...1 X –1/8 • V VIN < –1/8 • V *The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.

**The sign bit changes state during the 0 code.

REF

+ 1LSB 0 CH0/CH1 1100 0 00...0 X

+ 1LSB 0 CH0/CH1 1011 0 00...0 X

REF

+ 1LSB 0 CH0/CH1 1010 0 00...0 X

REF

+ 1LSB 0 CH0/CH1 1001 0 00...0 X

REF

–

REF

0 CH0/CH1 1100 0 11...1 X 0 CH0/CH1 1100 0 11...1 X

0 CH0/CH1 1011 1 11...1 X

0 CH0/CH1 1010 1 11...1 X

0 CH0/CH1 1001 1 11...1 X

0 CH0/CH1 1000 1 11...1 X 0 CH0/CH1 1/0** 0 0 0 0 0 0 ... 0 X

0 CH0/CH1 0111 1 00...0 X 0 CH0/CH1 0111 1 00...0 X

disturb the converter operation. If the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected.

When a fundamental rejection frequency different from 50Hz or 60Hz is required or when the converter must be synchronized with an outside source, the LTC2401/ LTC2402 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency f

of the external signal must

EOSC

be at least 2560Hz (1Hz notch frequency) to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods t

HEO

and t

are observed.

LEO

While operating with an external conversion clock of a frequency f

, the LTC2401/LTC2402 provide better

EOSC

than 110dB normal mode rejection in a frequency range f

/2560 ±4% and its harmonics. The normal mode

EOSC

rejection as a function of the input frequency deviation from f

/2560 is shown in Figure 4.

EOSC

Whenever an external clock is not present at the FO pin, the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. The LTC2401/ LTC2402 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an

–60

–70

–80

–90

–100

–110

REJECTION (dB)

–120

–130

–140

–12 –8 –4 0 4 8 12

INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)

24012 F04

Figure 4. LTC2401/LTC2402 Normal Mode Rejection When Using an External Oscillator of Frequency f

EOSC

Page 14

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

external serial clock. If the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. If the change occurs during the data output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid.

Table 3 summarizes the duration of each state as a function of FO.

SERIAL INTERFACE

The LTC2401/LTC2402 transmit the conversion results and receives the start of conversion command through a synchronous 3-wire interface. During the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result.

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 9) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock.

input. The internal or external SCK mode is selected on power-up and then reselected every time a HIGH-to-LOW transition is detected at the CS pin. If SCK is HIGH or floating at power-up or during this transition, the converter enters the internal SCK mode. If SCK is LOW at power-up or during this transition, the converter enters the external SCK mode.

Serial Data Output (SDO)

The serial data output pin, SDO (Pin 8), drives the serial data during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states.

When CS (Pin 7) is HIGH, the SDO driver is switched to a high impedance state. This allows sharing the serial interface with other devices. If CS is LOW during the convert or sleep state, SDO will output EOC. If CS is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW. The device remains in the sleep state until the first rising edge of SCK occurs while CS = 0.

Chip Select Input (CS)

In the Internal SCK mode of operation, the SCK pin is an output and the LTC2401/LTC2402 create their own serial clock by dividing the internal conversion clock by 8. In the

The active LOW chip select, CS (Pin 7), is used to test the conversion status and to enable the data output transfer as described in the previous sections.

External SCK mode of operation, the SCK pin is used as

Table 3. LTC2401/LTC2402 State Duration

State Operating Mode Duration

CONVERT Internal Oscillator FO = LOW 133ms

(60Hz Rejection) FO = HIGH 160ms

(50Hz Rejection)

External Oscillator FO = External Oscillator 20510/f

with Frequency f (f

/2560 Rejection)

EOSC

SLEEP As Long As CS = HIGH Until CS = 0 and SCK DATA OUTPUT Internal Serial Clock FO = LOW/HIGH As Long As CS = LOW But Not Longer Than 1.67ms

(Internal Oscillator) (32 SCK cycles) FO = External Oscillator with As Long As CS = LOW But Not Longer Than 256/f

Frequency f

External Serial Clock with As Long As CS = LOW But Not Longer Than 32/f Frequency f

kHz (32 SCK cycles)

SCK

EOSC

kHz

EOSC

kHz (32 SCK cycles)

EOSC

SCK

Page 15

WUUU

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2401/LTC2402 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i.e., after the first rising edge of SCK occurs with CS = 0).

Finally, CS can be used to control the free-running modes of operation, see Serial Interface Timing Modes section. Grounding CS will force the ADC to continuously convert at the maximum output rate selected by FO. Tying a capacitor to CS will reduce the output rate and power dissipation by a factor proportional to the capacitor’s value, see Figures 12 to 14.

SERIAL INTERFACE TIMING MODES

The LTC2401/LTC2402’s 3-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 2- or 3-wire I/O, single cycle conversion and autostart. The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW or FO = HIGH) or an external oscillator connected to the FO pin. Refer to Table 4 for a summary.

External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 5.

The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge.

The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Independent of CS, the device automatically enters the low power sleep state once the conversion is complete.

When the device is in the sleep state (EOC = 0), its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while CS is LOW. Data is shifted out the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. On the 32nd falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is in progress.

At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. As described above, CS may be pulled LOW at any time in order to monitor the conversion status.

Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first rising edge and the 32nd falling edge of SCK, see Figure 6. On the rising edge

Table 4. LTC2401/LTC2402 Interface Timing Modes

Conversion Data Connection

SCK Cycle Output and

Configuration Source Control Control Waveforms

External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 5, 6 External SCK, 2-Wire I/O External SCK SCK Figure 7 Internal SCK, Single Cycle Conversion Internal CS ↓ CS ↓ Figures 8, 9 Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 10 Internal SCK, Autostart Conversion Internal C

EXT

Internal Figure 11

Page 16

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

SDO

SCK

(EXTERNAL)

CONVERSION

2.7V TO 5.5V

1µF

110

SET

REF

)

CH1 SDO

REFERENCE VOLTAGE

+ 0.1V TO V

SET

ANALOG INPUT RANGE

– 0.12V

SET

REF

+ 0.12V

SET

= FS

– ZS

REF

SET

– 100mV

0V TO FS

TEST EOCTEST EOC

SLEEP DATA OUTPUT CONVERSION

BIT 31

EOC

LTC2402

SET

CH0

SET

SCK

GND

MSB SUB LSBEXRCH0/CH1

= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION

3-WIRE SERIAL I/O

BIT 4BIT 27 BIT 26BIT 28BIT 29BIT 30

LSB

BIT 0

Figure 5. External Serial Clock, Single Cycle Operation

TEST EOC

Hi-ZHi-ZHi-Z

24012 F05

SDO

SCK

(EXTERNAL)

2.7V TO 5.5V

1µF

110

SET

REF

)

CH1 SDO

CH0

REFERENCE VOLTAGE

+ 0.1V TO V

SET

ANALOG INPUT RANGE

– 0.12V

SET

REF

+ 0.12V

SET

= FS

– ZS

REF

SET

0V TO FS

TEST EOC TEST EOC

EOC

Hi-Z

CONVERSIONSLEEP SLEEP

DATA OUTPUT

– 100mV

SET

BIT 31BIT 0

EOC

Hi-Z Hi-ZHi-Z

LTC2402

SET

SCK

GND

3-WIRE SERIAL I/O

DATA OUTPUT

= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION

MSBEXRSIGCH0/CH1

BIT 8BIT 27 BIT 9BIT 28BIT 29BIT 30

TEST EOC

CONVERSION

24012 F06

Figure 6. External Serial Clock, Reduced Data Output Length

Page 17

WUUU

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion.

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 7. CS may be permanently tied to ground (Pin 6), simplifying the user interface or isolation barrier.

The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 0.5ms after VCC exceeds 2.2V. The level applied to SCK at this time determines if SCK is internal or external. SCK must be driven LOW prior to the end of POR in order to enter the external serial clock timing mode.

Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller indicating the conversion result is ready. EOC = 1 while the conversion is in

progress and EOC = 0 once the conversion enters the low power sleep state. On the falling edge of EOC, the conversion result is loaded into an internal static shift register. The device remains in the sleep state until the first rising edge of SCK. Data is shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising edge of SCK. EOC can be latched on the first rising edge of SCK. On the 32nd falling edge of SCK, SDO goes HIGH (EOC = 1) indicating a new conversion has begun.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 8.

In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CS. The device will not enter the internal serial clock mode if SCK is driven LOW on the falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven.

SDO

SCK

(EXTERNAL)

CONVERSION

2.7V TO 5.5V

1µF

110

SET

REF

)

CH1 SDO

CH0

REFERENCE VOLTAGE

+ 0.1V TO V

SET

ANALOG INPUT RANGE

– 0.12V

SET

REF

+ 0.12V

SET

= FS

– ZS

REF

SET

– 100mV

0V TO FS

BIT 31

EOC

SLEEP DATA OUTPUT CONVERSION

LTC2402

SET

SCK

GND

MSBEXRSIGCH0/CH1

= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION

2-WIRE SERIAL I/O

BIT 4BIT 27 BIT 26BIT 28BIT 29BIT 30

LSB

BIT 0

Figure 7. External Serial Clock, CS = 0 Operation

24012 F07

Page 18

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

REFERENCE VOLTAGE

ANALOG INPUT RANGE

SET

= FS

REF

0V TO FS

EOCtest

+ 0.1V TO V

SET

– 0.12V

+ 0.12V

SET

REF

– ZS

– 100mV

2.7V TO 5.5V

1µF

110

LTC2402

SCK

SET

CH1 SDO

CH0

SET

GND

SET

REF

)

= INTERNAL OSC/50Hz REJECTION

= EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION

10k

SDO

SCK

(INTERNAL)

TEST EOC

Hi-Z Hi-Z Hi-Z Hi-Z

BIT 31

EOC

SLEEP DATA OUTPUT CONVERSIONCONVERSION

Figure 8. Internal Serial Clock, Single Cycle Operation

The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state.

When testing EOC, if the conversion is complete (EOC = 0), the device will exit the sleep state and enter the data output state if CS remains LOW. In order to prevent the device from exiting the low power sleep state, CS must be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time t (if EOC = 0) or t

after EOC goes LOW (if CS is LOW

EOCtest

during the falling edge of EOC). The value of t

after the falling edge of CS

EOCtest

is 23µs

if the device is using its internal oscillator (F0 = logic LOW or HIGH). If FO is driven by an external oscillator of frequency f HIGH before time t

EOSC

, then t

EOCtest

is 3.6/f

. If CS is pulled

EOSC

, the device remains in the sleep state. The conversion result is held in the internal static shift register.

BIT 27 BIT 26BIT 28BIT 29BIT 30

MSBEXRSIGCH0/CH1

If CS remains LOW longer than t

BIT 4

LSB

EOCtest

BIT 0

, the first rising

TEST EOC

2400 F08

edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins on this first rising edge of SCK and concludes after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH, and a new conversion starts.

Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first and 32nd rising edge of SCK, see Figure 9. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. If CS is pulled HIGH while the converter is driving SCK LOW, the

Page 19

WUUU

APPLICATIO S I FOR ATIO

REFERENCE VOLTAGE

SET

ANALOG INPUT RANGE

SET

= FS

REF

0V TO FS

EOCtest

+ 0.1V TO V

– 0.12V

+ 0.12V

SET

– ZS

SET

2.7V TO 5.5V

1µF

REF

)

SET

– 100mV

110

CH1 SDO

CH0

LTC2402

SET

SCK

GND

LTC2401/LTC2402

= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION

10k

SDO

SCK

(INTERNAL)

BIT 0

EOC

Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

DATA OUTPUT

TEST EOCTEST EOC

SLEEP DATA OUTPUT

BIT 31

EOC

CH0/CH1

Figure 9. Internal Serial Clock, Reduced Data Output Length

internal pull-up is not available to restore SCK to a logic HIGH state. This will cause the device to exit the internal serial clock mode on the next falling edge of CS. This can be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CS HIGH when SCK is LOW.

Whenever SCK is LOW, the LTC2401/LTC2402’s internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven if the device is in the internal SCK timing mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2401/LTC2402’s internal pullup remains disabled. Hence, SCK remains LOW. On the next falling edge of CS, the device is switched to the external SCK timing mode. By adding an external 10k pullup resistor to SCK, this pin goes HIGH once the external driver goes Hi-Z. On the next CS falling edge, the device will remain in the internal SCK timing mode.

CONVERSIONCONVERSIONSLEEP

TEST EOC

24012 F09

BIT 27 BIT 26BIT 28BIT 29BIT 30

MSBEXRSIG

BIT 8

A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. Once CS goes HIGH (within the time period defined above as t

), the internal pull-up is activated.

EOCtest

For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a HIGH level before CS goes low again. This is not a concern under normal conditions where CS remains LOW after detecting EOC = 0. This situation is easily overcome by adding an external 10k pull-up resistor to the SCK pin.

Internal Serial Clock, 2-Wire I/O, Continuous Conversion

This timing mode uses a 2-wire, all output (SCK and SDO) interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 10. CS may be permanently tied to ground (Pin 6), simplifying the user interface or isolation barrier.

Page 20

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

REFERENCE VOLTAGE

SET

ANALOG INPUT RANGE

– 0.12V

SET

= FS

REF

0V TO FS

1µF

+ 0.1V TO V

REF

+ 0.12V

– ZS

SET

– 100mV

SET

2.7V TO 5.5V

110

REF

)

CH1 SDO

CH0

LTC2402

SET

SCK

GND

= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION

10k

SDO

SCK

(INTERNAL)

BIT 31

EOC

CH0/CH1

SLEEP

MSBEXRSIG

Figure 10. Internal Serial Clock, Continuous Operation

The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 0.5ms after VCC exceeds 2.2V. An internal weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected).

During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the low power sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and ends after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd

BIT 4 BIT 0BIT 27 BIT 26BIT 28BIT 29BIT 30

LSB

DATA OUTPUT CONVERSIONCONVERSION

24012 F10

rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion.

Internal Serial Clock, Autostart Conversion

This timing mode is identical to the internal serial clock, 2-wire I/O described above with one additional feature. Instead of grounding CS, an external timing capacitor is tied to CS.

While the conversion is in progress, the CS pin is held HIGH by an internal weak pull-up. Once the conversion is complete, the device enters the low power sleep state and an internal 25nA current source begins discharging the capacitor tied to CS, see Figure 11. The time the converter spends in the sleep state is determined by the value of the external timing capacitor, see Figures 12 and 13. Once the voltage at CS falls below an internal threshold (≈1.4V), the device automatically begins outputting data. The data output cycle begins on the first rising edge of SCK and ends on the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be

Page 21

WUUU

APPLICATIO S I FOR ATIO

REFERENCE VOLTAGE

+ 0.1V TO V

SET

ANALOG INPUT RANGE

– 0.12V

SET

= FS

REF

SET

0V TO FS

GND

REF

+ 0.12V

– ZS

– 100mV

SET

2.7V TO 5.5V

1µF

REF

)

SET

110

CH1 SDO

CH0

LTC2402

SET

SCK

GND

= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION

EXT

LTC2401/LTC2402

10k

SDO

SCK

(INTERNAL)

(SEC)

SAMPLE

SLEEP

Figure 11. Internal Serial Clock, Autostart Operation

VCC = 5V

= 3V

10 100 100000

CAPACITANCE ON CS (pF)

1000 10000

24012 F12

BIT 31

EOC

CH0/CH1

BIT 29BIT 30

SIG

DATA OUTPUT CONVERSIONCONVERSION

SAMPLE RATE (Hz)

10 100 10000

BIT 0

VCC = 5V

1000

CAPACITANCE ON CS (pF)

Hi-ZHi-Z

24012 F11

= 3V

100000

24012 F13

Figure 12. CS Capacitance vs t

SAMPLE

Figure 13. CS Capacitance vs Output Rate

Page 22

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

used to shift the conversion result into external circuitry. After the 32nd rising edge, CS is pulled HIGH and a new conversion is immediately started. This is useful in applications requiring periodic monitoring and ultralow power. Figure 14 shows the average supply current as a function of capacitance on CS.

It should be noticed that the external capacitor discharge current is kept very small in order to decrease the converter power dissipation in the sleep state. In the autostart mode the analog voltage on the CS pin cannot be observed without disturbing the converter operation using a regular oscilloscope probe. When using this configuration, it is important to minimize the external leakage current at the CS pin by using a low leakage external capacitor and properly cleaning the PCB surface.

The internal serial clock mode is selected every time the voltage on the CS pin crosses an internal threshold voltage. An internal weak pull-up at the SCK pin is active while CS is discharging; therefore, the internal serial clock timing mode is automatically selected if SCK is floating. It is important to ensure there are no external drivers pulling SCK LOW while CS is discharging.

300

250

)

RMS

200

150

100

SUPPLY CURRENT (µA

Figure 14. CS Capacitance vs Supply Current

VCC = 5V

VCC = 3V

10 100 1000 10000

CAPACITANCE ON CS (pF)

100000

24012 F14

as 100µs. However, some considerations are required to take advantage of exceptional accuracy and low supply current.

The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during the conversion state.

In order to preserve the LTC2401/LTC2402’s accuracy, it is very important to minimize the ground path impedance which may appear in series with the input and/or reference signal and to reduce the current which may flow through this path. The GND pin should be connected to a low resistance ground plane through a minimum length trace. The use of multiple via holes is recommended to further reduce the connection resistance.

In an alternative configuration, the GND pin of the converter can be the single-point-ground in a single point grounding system. The input signal ground, the reference signal ground, the digital drivers ground (usually the digital ground) and the power supply ground (the analog ground) should be connected in a star configuration with the common point located as close to the GND pin as possible.

The power supply current during the conversion state should be kept to a minimum. This is achieved by restricting the number of digital signal transitions occurring during this period.

While a digital input signal is in the range 0.5V to (VCC␣ –␣ 0.5V), the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (FO, CS and SCK in External SCK mode of operation) is within this range, the LTC2401/LTC2402 power supply current may increase even if the signal in question is at a valid logic level. For micropower operation and in order to minimize the potential errors due to additional ground pin current, it is recommended to drive all digital input signals to full CMOS levels [VIL < 0.4V and VOH > (VCC – 0.4V)].

DIGITAL SIGNAL LEVELS

The LTC2401/LTC2402’s digital interface is easy to use. Its digital inputs (FO, CS and SCK in External SCK mode of operation) accept standard TTL/CMOS logic levels and the internal hysteresis receivers can tolerate edge rates as slow

Severe ground pin current disturbances can also occur due to the undershoot of fast digital input signals. Undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to LTC2401/LTC2402. For

Page 23

WUUU

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

reference, on a regular FR-4 board, signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance.

Parallel termination near the LTC2401/LTC2402 pin will eliminate this problem but will increase the driver power dissipation. A series resistor between 27Ω and 56Ω placed near the driver or near the LTC2401/LTC2402 pin will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology.

Driving the Input and Reference

The analog input and reference of the typical delta-sigma analog-to-digital converter are applied to a switched capacitor network. This network consists of capacitors switching between the analog input (VIN), ZS and FS at both VIN and V

(Pin 2). The result is small current spikes seen

SET

. A simplified input equivalent circuit

REF

(Pin 5)

SET

is shown in Figure 15.

LTC2401/LTC2402’s internal switched capacitor network is clocked at 153,600Hz corresponding to a 6.5µs sam- pling period. Fourteen time constants are required each time a capacitor is switched in order to achieve 1ppm settling accuracy.

Therefore, the equivalent time constant at VIN and V

REF

should be less than 6.5µs/14 = 460ns in order to achieve 1ppm accuracy.

Input Current (VIN)

If complete settling occurs on the input, conversion results will be uneffected by the dynamic input current. If the settling is incomplete, it does not degrade the linearity performance of the device. It simply results in an offset/ full-scale shift, see Figure 16. To simplify the analysis of input dynamic current, two separate cases are assumed: large capacitance at VIN (CIN > 0.01µF) and small capaci- tance at VIN (CIN < 0.01µF).

TUE

The key to understanding the effects of this dynamic input current is based on a simple first order RC time constant model. Using the internal oscillator, the

REF(LEAK)

SET

CH0/CH1

SET

REF(LEAK)

IN(LEAK)

SWITCHING FREQUENCY f = 153.6kHz FOR INTERNAL OSCILLATOR (f

FOR EXTERNAL OSCILLATORS

f = f

EOSC

Figure 15. LTC2401/LTC2402 Equivalent Analog Input Circuit

AVERAGE INPUT CURRENT:

= 0.25(VIN – 0.5 • V

2.5pF (TYP)

24012 F15

= LOGIC LOW OR HIGH)

REF

)fC

SET

24012 F16

Figure 16. Offset/Full-Scale Shift

If the total capacitance at VIN (see Figure 17) is small (<0.01µF), relatively large external source resistances (up to 20k for 20pF parasitic capacitance) can be tolerated without any offset/full-scale error. Figures 18 and 19 show a family of offset and full-scale error curves for various small valued input capacitors (CIN < 0.01µF) as a function of input source resistance.

For large input capacitor values (CIN > 0.01µF), the input spikes are averaged by the capacitor into a DC current. The gain shift becomes a linear function of input source

Page 24

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

SOURCE

INTPUT

SIGNAL

SOURCE

Figure 17. An RC Network at V

VCC = 5V

= 5V

REF

= 0V

= 25°C

OFFSET ERROR (ppm)

–10

CIN = 0.01µF

CIN = 1000pF

CIN = NO CAP

10 100 1k 10k

SOURCE

Figure 18. Offset vs R

OFFSET ERROR (ppm)

VCC = 5V V

REF

= 25°C

CIN = 22µF C C C C C

= 5V

= 0V

200

= 10µF

= 1µF

= 0.1µF

= 0.01µF

= 0.001µF

400 R

SOURCE

(Ω)

600

(Ω)

C ≅20pF

SOURCE

PAR

CIN = 100pF

24012 F18

(Small C)

800

24012 F19

LTC2401/

LTC2402

100k

1000

24012 F17

(Ω)

VCC = 5V

= 5V

REF

= 5V

= 25°C

800

24012 F20

SOURCE

10k

24012 F21

SOURCE

1000

(Large C)

100k

(Small C)

–10

–20

–30

–40

–50

FULL-SCALE ERROR (ppm)

–60

–70

–80

CIN = 22µF C

200 600

= 10µF = 1µF = 0.1µF = 0.01µF = 0.001µF

400

SOURCE

Figure 20. Full-Scale Error vs R

VCC = 5V

= 5V

REF

= 5V

= 25°C

–10

FULL-SCALE (ppm)

–30

–50

CIN = 0.01µF

CIN = 1000pF

CIN = 100pF

100 R

SOURCE

CIN = NO CAP

(Ω)

Figure 21. Full-Scale Error vs R

In addition to the input current spikes, the input ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA max), results in a fixed offset shift of 10µV for a 10k source resistance.

Figure 19. Offset vs R

SOURCE

(Large C)

resistance independent of input capacitance, see Figures 20 and 21. The equivalent input impedance is 6.25MΩ. This results in ±400µA of input dynamic current at the extreme values of VIN (VIN = 0V and VIN = V V

= 5V). This corresponds to a 0.8ppm shift in offset

REF

, when

and full-scale readings for every 10Ω of input source resistance.

The effect of input leakage current is evident for CIN = 0 in Figures 18 and 21. A leakage current of 3nA results in a 150µV (30ppm) error for a 50k source resistance. As R

SOURCE

gets larger, the switched capacitor input current

begins to dominate.

Reference Current (V

REF

)

Similar to the analog input, the reference input has a dynamic input current. This current has negligible effect

Page 25

WUUU

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

on the offset. However, the reference current at VIN = V

REF

is similar to the input current at full-scale. For large values of reference capacitance (C

> 0.01µF), the full-scale

VREF

error shift is 0.08ppm/Ω of external reference resistance independent of the capacitance at V the capacitance tied to V

is small (C

REF

, see Figure 22. If

REF

< 0.01µF), an

VREF

input resistance of up to 20k (20pF parasitic capacitance at V

) may be tolerated, see Figure 23.

REF

Unlike the analog input, the integral nonlinearity of the device can be degraded with excessive external RC time constants tied to the reference input. If the capacitance

160

VCC = 5V V

= 5V

REF

= 5V

= 25°C

120

= 0.1µF

CIN = 1µF

FULL-SCALE ERROR (ppm)

CIN = 10µF

= 0.01µF

at node V

is small (C

REF

< 0.01µF), the reference input

VREF

can tolerate large external resistances without reduction in INL, see Figure 24. If the external capacitance is large (C

0.04ppm/Ω independent of capacitance at V

> 0.01µF), the linearity will be degraded by

VREF

REF

, see

Figure 25. In addition to the dynamic reference current, the V

REF

ESD

protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA max), results in a fixed full-scale shift of 10µV for a 10k source resistance.

= 5V

REF

= 25°C

= 1000pF

= 0.01µF

INL ERROR (ppm)

= 100pF

= 20pF

200

RESISTANCE AT V

400

600

REF

(Ω)

Figure 22. Full-Scale Error vs R

VCC = 5V

= 5V

REF

= 5V

= 25°C

= 10µF

CIN = 1000pF

–25

FULL-SCALE ERROR (ppm)

–50

100

1k 10k

RESISTANCE AT V

CIN = 100pF

(Ω)

REF

Figure 23. Full-Scale Error vs R

800

24012 F22

(Large C)

VREF

CIN = 20pF

24012 F23

(Small C)

VFEF

1000

100k

100

1k 10k

RESISTANCE AT V

Figure 24. INL Error vs R

VCC = 5V

= 5V

REF

= 25°C

INL ERROR (ppm)

200

RESISTANCE AT V

VREF

= 0.1µF

VREF

= 0.01µF

400

Figure 25. INL Error vs R

VREF

= 1µF

600

REF

(Ω)

VREF

(Ω)

VREF

100k

24012 F24

(Small C)

= 10µF

800

1000

24012 F25

(Large C)

Page 26

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

ANTIALIASING

One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2401/LTC2402 significantly simplify antialiasing filter requirements.

The digital filter provides very high rejection except at integer multiples of the modulator sampling frequency (fS), see Figure 26. The modulator sampling frequency is 256 • FO, where FO is the notch frequency (typically 50Hz or 60Hz). The bandwidth of signals not rejected by the digital filter is narrow (≈0.2%) compared to the bandwidth of the frequencies rejected.

As a result of the oversampling ratio (256) and the digital filter, minimal (if any) antialias filtering is required in front of the LTC2401/LTC2402. If passive RC components are placed in front of the LTC2401/LTC2402, the input dynamic current should be considered (see Input Current section). In cases where large effective RC time constants are used, an external buffer amplifier may be required to minimize the effects of input dynamic current.

The modulator contained within the LTC2401/LTC2402 can handle large-signal level perturbations without saturating. Signal levels up to 40% of V

do not saturate the

REF

analog modulator. These signals are limited by the input ESD protection to 300mV below ground and 300mV above VCC.

Single Ended Half-Bridge Digitizer with Reference and Ground Sensing

Sensors convert real world phenomena (temperature, pressure, gas levels, etc.) into a voltage. Typically, this voltage is generated by passing an excitation current through the sensor. The wires connecting the sensor to the ADC form parasitic resistors RP1 and RP2. The excitation current also flows through parasitic resistors RP1 and RP2, as shown in Figure 27. The voltage drop across these parasitic resistors leads to systematic offset and full-scale errors.

In order to eliminate the errors associated with these parasitic resistors, the LTC2401/LTC2402 include a fullscale set input (FS (ZS

). As shown in Figure 28, the FS

SET

) and a zero-scale set input

SET

pin acts as a zero

SET

current full-scale sense input. Errors due to parasitic resistance RP1 in series with the half-bridge sensor are removed by the FS scale output of the ADC (data out = FFFFFF

EXCITATION

Figure 27. Errors Due to Excitation Currents

input to the ADC. The absolute full-

SET

) will occur

HEX

FULL-SCALE ERROR

–

OFFSET ERROR

–

+ –

24012 F27

SENSOR SENSOR OUTPUT

–20

–40

–60

–80

REJECTION (dB)

–100

–120

–140

fS/2 f

INPUT FREQUENCY

Figure 26. Sinc4 Filter Rejection

24012 F26

IDC = 0

EXCITATION

IDC = 0

LTC2401

SET

GND

SCK

3-WIRE SPI INTERFACE

24012 F03

SDO

Figure 28. Half-Bridge Digitizer with Zero-Scale and Full-Scale Sense

Page 27

WUUU

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

at VIN = VB = FS

, see Figure 29. Similarly, the offset

SET

errors due to RP2 are removed by the ground sense input ZS

. The absolute zero output of the ADC (data out =

SET

000000

) occurs at VIN = VA = ZS

HEX

. Parasitic resistors

SET

RP3 to RP5 have negligible errors due to the 1nA (typ) leakage current at pins FS

SET

, ZS

and VIN. The wide

SET

dynamic input range (–300mV to 5.3V) and low noise (0.6ppm RMS) enable the LTC2401 or the LTC2402 to directly digitize the output of the bridge sensor.

The LTC2402 is ideal for applications requiring continuous monitoring of two input sensors. As shown in Figure 30, the LTC2402 can monitor both a thermocouple

FFFFF

temperature probe and a cold junction temperature sensor. Absolute temperature measurements can be performed with a variety of thermocouples using digital cold junction compensation.

The selection between CH0 and CH1 is automatic. Initially, after power-up, a conversion is performed on CH0. For each subsequent conversion, the input channel selection is alternated. Embedded within the serial data output is a status bit indicating which channel corresponds to the conversion result. If the conversion was performed on CH0, this bit (Bit 30) is LOW and is HIGH if the conversion was performed on CH1 (see Figure 31).

12.5% EXTENDED RANGE

ADC DATA OUT

00000

SET

12.5% UNDER RANGE

Figure 29. Transfer Curve with Zero-Scale and Full-Scale Set

2.7V TO 5.5V

12k

COLD JUNCTION

THERMISTOR

100Ω

LTC2402

110

CH1 SDO

CH0

SET

SCK

GND

–+

ISOLATION

THERMOCOUPLE

BARRIER

24012 F29

PROCESSOR

24012 F30

Figure 30. Isolated Temperature Measurement

Page 28

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

SCK

SDO

EOC

CH1

• • • • • •

CH1 DATA OUT

EOC

CH0

CH0 DATA OUT

Figure 31. Embedded Selected Channel Indicator

EXCITATION

IDC = 0

350Ω 350Ω

IDC = 0

SET

LTC2402

CH1

CH0

SET

GND

SCK

SDO

3-WIRE SPI INTERFACE

24012 F32

24012 F31

Figure 32. Pseudo Differential Strain Guage Application

There are no extra control or status pins required to perform the alternating 2-channel measurements. The LTC2402 only requires two digital signals (SCK and SDO). This simplification is ideal for isolated temperature measurements or systems where minimal control signals are available.

Pseudo Differential Applications

Generally, designers choose fully differential topologies for several reasons. First, the interface to a 4- or 6-wire bridge is simple (it is a differential output). Second, they require good rejection of line frequency noise. Third, they typically look at a small differential signal sitting on a large common mode voltage; they need accurate measurements of the differential signal independent of

the common mode input voltage. Many applications currently using fully differential analog-to-digital converters for any of the above reasons may migrate to a pseudo differential conversion using the LTC2402.

Direct Connection to a Full Bridge

The LTC2402 interfaces directly to a 4- or 6-wire bridge, as shown in Figure 32. The LTC2402 includes a FS ZS

for sensing the excitation voltage directly across the

SET

and a

bridge. This eliminates errors due to excitation currents flowing through parasitic resistors. The LTC2402 also includes two single ended input channels which can tie directly to the differential output of the bridge. The two conversion results may be digitally subtracted yielding the differential result.

Page 29

WUUU

APPLICATIO S I FOR ATIO

LTC2401/LTC2402

The LTC2402’s single ended rejection of line frequencies (±2%) and harmonics is better than 110dB. Since the device performs two independent single ended conversions each with >110dB rejection, the overall common mode and differential rejection is much better than the 80dB rejection typically found in other differential input delta-sigma converters.

In addition to excellent rejection of line frequency noise, the LTC2402 also exhibits excellent single ended noise rejection over a wide range of frequencies due to its 4

order sinc filter. Each single ended conversion independently rejects high frequency noise (> 60Hz). Care must be taken to insure noise at frequencies below 15Hz and at multiples of the ADC sample rate (15,360Hz) are not present. For this application, it is recommended the LTC2402 is placed in close proximity to the bridge sensor in order to reduce the noise injected into the ADC input. By performing three successive conversions (CH0-CH1-CH0), the drift and low frequency noise can be measured and compensated for digitally.

The absolute accuracy (less than 10 ppm total error) of the LTC2402 enables extremely accurate measurement of small signals sitting on large voltages. Each of the two pseudo differential measurements performed by the LTC2402 is absolutely accurate independent of the common mode voltage output from the bridge. The pseudo differential result obtained from digitally subtracting the two single ended conversion results is accurate to within

the noise level of the device (3µV

) times the square

RMS

root of 2, independent of the common mode input voltage. Typically, a bridge sensor outputs 2mV/V full scale. With

a 5V excitation, this translates to a full-scale output of 10mV. Divided by the RMS noise of 4.2µV(= 3µV • 1.414), this circuit yields 2,300 counts with no averaging or amplification. If more counts are required, several conversions may be averaged (the number of effective counts is increased by a factor of square root of 2 for each doubling of averages).

An RTD Temperature Digitizer

RTDs used in remote temperature measurements often have long lead lengths between the ADC and RTD sensor. These long lead lengths lead to voltage drops due to excitation current in the interconnect to the RTD. This voltage drop can be measured and digitally removed using the LTC2402 (see Figure 33).

The excitation current (typically 200µA) flows from the ADC through a long lead length to the remote temperature sensor (RTD). This current is applied to the RTD, whose resistance changes as a function of temperature (100Ω to 400Ω for 0°C to 800°C). The same excitation current flows back to the ADC ground and generates another voltage drop across the return leads. In order to get an accurate measurement of the temperature, these voltage drops must be measured and removed from the conversion result. Assuming the resistance is approximately the same

100Ω

SET

RTD

–

Figure 33. RTD Remote Temperature Measurement

EXCITATION

IDC = 0

= 200µA

25Ω

1000pF

5k25Ω

0.1µF

LTC2402

CH0

CH1

SET

GND

SCK

SDO

3-WIRE SPI INTERFACE

24012 F33

Page 30

LTC2401/LTC2402

WUUU

APPLICATIO S I FOR ATIO

for the forward and return paths (R1 = R2), the auxiliary channel on the LTC2402 can measure this drop. These errors are then removed with simple digital correction.

The result of the first conversion on CH0 corresponds to an input voltage of V second conversion (CH1) is –R1 • I

RTD

+ R1 • I

EXCITATION.

The result of the

Note, the LTC2402’s input range is not limited to the supply rails, it has underrange capabilities. The device’s input range is –300mV to V

+ 300mV. Adding the two conversion

REF

results together, the voltage drop across the RTD’s leads are cancelled and the final result is V

RTD

An Isolated, 24-Bit Data Acquisition System

The LTC1535 is useful for signal isolation. Figure 34 shows a fully isolated, 24-bit differential input A/D converter implemented with the LTC1535 and LTC2402. Power on the isolated side is regulated by an LT1761-5.0 low noise, low dropout micropower regulator. Its output is suitable for driving bridge circuits and for ratiometric applications.

During power-up, the LTC2402 becomes active at VCC =

2.3V, while the isolated side of the LTC1535 must wait for V

to reach its undervoltage lockout threshold of 4.2V.

CC2

Below 4.2V, the LTC1535’s driver outputs Y and Z are in a high impedance state, allowing the 1kΩ pull-down to define the logic state at SCK. When the LTC2402 first becomes active, it samples SCK; a logic “0” provided by the 1kΩ pull-down invokes the external serial clock mode. In this mode, the LTC2402 is controlled by a single clock line from the nonisolated side of the barrier, through the LTC1535’s driver output Y. The entire power-up sequence, from the time power is applied to V

until the LT1761’s

CC1

output has reached 5V, is approximately 1ms. Data returns to the nonisolated side through the LTC1535’s

receiver at RO. An internal divider on receiver input B sets a logic threshold of approximately 3.4V at input A, facilitating communications with the LTC2402’s SDO output without the need for any external components.

“SDO”

“SCK”

LOGIC 5V

1/2 BAT54C

10µF 16V TANT

1/2 BAT54C

ST2

ST1

RO RE DE DI

CC1

10µF

10V

TANT

LTC1535

ISOLATION

BARRIER

T1 = COILTRONICS CTX02-14659 OR SIEMENS B78304-A1477-A3

1µF

CC2

= LOGIC COMMON

= FLOATING COMMON

A B Y Z

LT1761-5

IN OUT

SHDN BYP

GND

10µF 10V TAN T

21 2

10µF

SCK SDO CS GND

LTC2402

SET

CH1 CH0

SET

10µF 10V TANT

10µF

CERAMIC

24012 F09

Figure 34. Complete, Isolated 24-Bit Data Acquisition System

Page 31

LTC2401/LTC2402

PACKAGE I FOR ATIO

0.007 (0.18)

0.021 (0.53 ± 0.015)

* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

Dimensions in inches (millimeters) unless otherwise noted.

MS10 Package

10-Lead Plastic MSOP

(LTC DWG # 05-08-1661)

0.118 ± 0.004*

± 0.006

° – 6° TYP

(3.00 ± 0.102)

0.193 ± 0.006 (4.90 ± 0.15)

SEATING

PLANE

0.040

± 0.006

(1.02 ± 0.15)

0.009

(0.228)

REF

0.0197 (0.50)

BSC

8910

0.118 ± 0.004** (3.00 ± 0.102)

0.034 ± 0.004

(0.86 ± 0.102)

0.006 ± 0.004

(0.15 ± 0.102)

MSOP (MS10) 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Page 32

LTC2401/LTC2402

TYPICAL APPLICATIO

Figure 35 shows the block diagram of a demo circuit (contact LTC for a demonstration) of a multichannel isolated temperature measurement system. This circuit decodes an address to select which LTC2402 receives a 32-bit burst of SCK signal. All devices independently

SD0

(ADDRESS

OR COUNTER)

HC138SCK

HC138

HC595

ADDRESS

LATCH

SEE FIGURE 34 FOR THE COMPLETE CIRCUIT

convert either the thermal couple output or the thermistor cold juntion output. After each conversion, the devices enter their sleep state and wait for the SCK signal before clocking out data and beginning the next conversion.

SDO

SCK

SDO

SCK

SDO

SCK

LTC2402

SET

LTC2402

SET

LTC2402

SET

CH1 CH0

SET

2500V

CH1 CH0

SET

CH1 CH0

–

24012 F35

LTC1535

Figure 35. Mulitchannel Isolated Temperature Measurement System

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1019 Precision Bandgap Reference, 2.5V, 5V 3ppm/°C Drift, 0.05% Max LTC1050 Precision Chopper Stabilized Op Amp No External Components 5µV Offset, 1.6µV LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max, 5ppm/°C Drift LTC1391 8-Channel Multiplexer Low RON: 45Ω, Low Charge Injection Serial Interface LT1460 Micropower Series Reference 0.075% Max, 10ppm/°C Max Drift, 2.5V, 5V and 10V Versions LT1461-2.5 Precision Micropower Voltage Reference 50µA Supply Current, 3ppm/°C Drift LTC1535 Isolated RS485 Transceiver 2500V

RMS

Isolation

LTC2400 24-Bit, No Latency ∆Σ ADC in SO-8 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency ∆Σ ADC 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2410 24-Bit, Fully Differential, No Latency ∆Σ ADC in SSOP-16 0.16ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2411 24-Bit, Fully Differential, No Latency ∆Σ ADC in MS10 0.29ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2413 24-Bit, No Latency ∆Σ ADC Simultaneous 50Hz and 60Hz Rejection, 0.16ppm Noise LTC2420 20-Bit, No Latency ∆Σ ADC in SO-8 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 LTC2424/LTC2428 4-/8-Channel, 20-Bit, No Latency ∆Σ ADC 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408

24012f LT/LCG 1000 4K • PRINTED IN USA

 LINEAR TE CHNO LOG Y C O RP O R ATION 2000

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear-tech.com

P-P

Noise