Page 1
查询LTC2291供应商
FEATURES
■
Integrated Dual 12-Bit ADCs
■
Sample Rate: 65Msps/40Msps/25Msps
■
Single 3V Supply (2.7V to 3.4V)
■
Low Power: 400mW/235mW/150mW
■
71dB SNR up to 70MHz Input
■
85dB SFDR up to 70MHz Input
■
110dB Channel Isolation at 100MHz
■
Multiplexed or Separate Data Bus
■
Flexible Input: 1V
■
575MHz Full Power Bandwidth S/H
■
Clock Duty Cycle Stabilizer
■
Shutdown and Nap Modes
■
Pin Compatible Family
P-P
to 2V
P-P
Range
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)
10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)
■
64-Pin (9mm × 9mm) QFN Package
U
APPLICATIO S
■
Wireless and Wired Broadband Communication
■
Imaging Systems
■
Spectral Analysis
■
Portable Instrumentation
LTC2293/LTC2292/LTC2291
Dual 12-Bit, 65/40/25Msps
Low Power 3V ADCs
U
DESCRIPTIO
The LTC®2293/LTC2292/LTC2291 are 12-bit 65Msps/
40Msps/25Msps, low power dual 3V A/D converters designed for digitizing high frequency, wide dynamic range
signals. The LTC2293/LTC2292/LTC2291 are perfect for
demanding imaging and communications applications
with AC performance that includes 71dB SNR and 85dB
SFDR for signals well beyond the Nyquist frequency.
DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSB
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.3V
logic. An optional multiplexer allows both channels to
share a digital output bus.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
RMS
.
TYPICAL APPLICATIO
ANALOG
INPUT A
CLK A
CLK B
ANALOG
INPUT B
+
INPUT
S/H
–
CLOCK/DUTY CYCLE
CONTROL
CLOCK/DUTY CYCLE
CONTROL
+
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
12-BIT
PIPELINED
ADC CORE
U
OUTPUT
DRIVERS
OUTPUT
DRIVERS
229321 TA01
OV
D11A
•
•
•
D0A
OGND
MUX
OV
D11B
•
•
•
D0B
OGND
DD
LTC2293: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
72
71
70
SNR (dBFS)
69
DD
68
0
100
50
INPUT FREQUENCY (MHz)
150
200
229321 TA02
229321f
1
Page 2
LTC2293/LTC2292/LTC2291
WW
W
U
ABSOLUTE AXI U RATI GS
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (V
Digital Input Voltage .................... –0.3V to (V
Digital Output Voltage ................– 0.3V to (OV
Power Dissipation............................................ 1500mW
Operating Temperature Range
LTC2293C, LTC2292C, LTC2291C........... 0°C to 70°C
LTC2293I, LTC2292I, LTC2291I .......... –40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
+ 0.3V)
DD
+ 0.3V)
DD
+ 0.3V)
DD
UUW
PACKAGE/ORDER I FOR ATIO
TOP VIEW
DD
64 GND
63 VDD62 SENSEA
61 VCMA
60 MODE
59 SHDNA
58 OEA
57 OFA
56 DA11
55 DA10
54 DA9
53 DA8
52 DA7
51 DA6
50 OGND
49 OV
A
1
INA+
–
A
2
INA
REFHA 3
REFHA 4
REFLA 5
REFLA 6
V
7
DD
CLKA
8
CLKB 9
V
10
DD
REFLB 11
REFLB 12
REFHB 13
REFHB 14
–
A
15
INB
+
A
16
INB
17
19
18
DD
V
GND
SENSEB
64-LEAD (9mm × 9mm) PLASTIC QFN
EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB
T
65
20
NC 24
OEB 23
MUX 21
VCMB
SHDNB 22
UP PACKAGE
= 125°C, θJA = 20°C/W
JMAX
NC 25
DB0 26
DB1 27
DB2 28
ORDER PART
NUMBER
DB3 29
48 DA5
47 DA4
46 DA3
45 DA2
44 DA1
43 DA0
42 NC
41 NC
40 OFB
39 DB11
38 DB10
37 DB9
36 DB8
35 DB7
34 DB6
33 DB5
32
DD
DB4 30
OV
OGND 31
QFN PART*
MARKING
LTC2293CUP
LTC2293IUP
LTC2292CUP
LTC2293UP
LTC2292UP
LTC2291UP
LTC2292IUP
LTC2291CUP
LTC2291IUP
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
U
CO VERTER CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Resolution ● 12 12 12 Bits
(No Missing Codes)
Integral Linearity Error Differential Analog Input (Note 5) ● –1.4 ±0.3 1.4 – 1.4 ±0.3 1.4 –1.3 ±0.3 1.3 LSB
Differential Differential Analog Input ● – 0.8 ±0.15 0.8 –0.7 ±0.15 0.7 –0.7 ±0.15 0.7 LSB
Linearity Error
Offset Error (Note 6) ● –12 ±212–12±212–12±212 mV
Gain Error External Reference ● –2.5 ±0.5 2.5 –2.5 ±0.5 2.5 – 2.5 ±0.5 2.5 %FS
Offset Drift ±10 ±10 ±10 µV/°C
Full-Scale Drift Internal Reference ±30 ±30 ±30 ppm/°C
External Reference ±15 ±15 ±15 ppm/°C
Gain Matching External Reference ±0.3 ±0.3 ±0.3 %FS
Offset Matching ±2 ±2 ±2mV
Transition Noise SENSE = 1V 0.25 0.25 0.25 LSB
The ● denotes the specifications which apply over the full operating
LTC2293 LTC2292 LTC2291
RMS
229321f
2
Page 3
LTC2293/LTC2292/LTC2291
UU
A ALOG I PUT
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
V
IN,CM
I
IN
I
SENSE
I
MODE
t
AP
t
JITTER
CMRR Analog Input Common Mode Rejection Ratio 80 dB
U
Analog Input Range (A
Analog Input Common Mode Differential Input (Note 7) ● 1 1.5 1.9 V
Analog Input Leakage Current 0V < A
SENSEA, SENSEB Input Leakage 0V < SENSEA, SENSEB < 1V ● –3 3 µA
MODE Input Leakage Current 0V < MODE < V
Sample-and-Hold Acquisition Delay Time 0 ns
Sample-and-Hold Acquisition Delay Time Jitter 0.2 ps
Full Power Bandwidth Figure 8 Test Circuit 575 MHz
W
DY A IC ACCURACY
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 5MHz Input 71.3 71.4 71.4 dB
SFDR 5MHz Input 90 90 90 dB
SFDR 5MHz Input 90 90 90 dB
S/(N+D) 5MHz Input 71.3 71.4 71.4 dB
I
MD
Spurious Free
Dynamic Range
2nd or 3rd
Harmonic
Spurious Free
Dynamic Range
4th Harmonic
or Higher
Signal-to-Noise
Plus Distortion
Ratio
Intermodulation
Distortion
Crosstalk fIN = Nyquist –110 –110 –110 dB
The ● denotes the specifications which apply over the full operating temperature range, otherwise
+
–
–A
IN
) 2.7V < V
IN
< 3.4V (Note 7) ● 1V to 2V V
DD
+
–
, A
< V
IN
IN
DD
DD
● –1 1 µA
● –3 3 µA
RMS
The ● denotes the specifications which apply over the full operating temperature range,
LTC2293 LTC2292 LTC2291
12.5MHz Input ● 70.1 71.2 dB
20MHz Input ● 69.6 71.3 dB
30MHz Input ● 69.6 71.3 dB
70MHz Input 71.3 71.1 70.9 dB
140MHz Input 71 70.7 70.6 dB
12.5MHz Input ● 75 90 dB
20MHz Input ● 74 90 dB
30MHz Input ● 74 90 dB
70MHz Input 85 85 85 dB
140MHz Input 80 80 80 dB
12.5MHz Input ● 80 90 dB
20MHz Input ● 79 90 dB
30MHz Input ● 78 90 dB
70MHz Input 90 90 90 dB
140MHz Input 90 90 90 dB
12.5MHz Input ● 69.8 71.2 dB
20MHz Input ● 69.4 71.2 dB
30MHz Input ● 69.4 71.2 dB
70MHz Input 71.1 70.9 70.8 dB
140MHz Input 69.9 69.9 69.8 dB
fIN = Nyquist, 90 90 90 dB
Nyquist + 1MHz
229321f
3
Page 4
LTC2293/LTC2292/LTC2291
UU U
I TER AL REFERE CE CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage I
VCM Output Tempco ±30 ppm/°C
VCM Line Regulation 2.7V < VDD < 3.3V 3 mV/V
VCM Output Resistance –1mA < I
= 0 1.475 1.500 1.525 V
OUT
(Note 4)
< 1mA 4 Ω
OUT
UU
DIGITAL I PUTS A D DIGITAL OUTPUTS
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LOGIC INPUTS (CLK, OE, SHDN, MUX)
V
IH
V
IL
I
IN
C
IN
LOGIC OUTPUTS
OVDD = 3V
C
OZ
I
SOURCE
I
SINK
V
OH
V
OL
OV
= 2.5V
DD
V
OH
V
OL
OVDD = 1.8V
V
OH
V
OL
High Level Input Voltage VDD = 3V ● 2V
Low Level Input Voltage VDD = 3V ● 0.8 V
Input Current VIN = 0V to V
Input Capacitance (Note 7) 3 pF
Hi-Z Output Capacitance OE = High (Note 7) 3 pF
Output Source Current V
Output Sink Current V
High Level Output Voltage IO = –10µA 2.995 V
Low Level Output Voltage IO = 10µA 0.005 V
High Level Output Voltage IO = –200µA 2.49 V
Low Level Output Voltage IO = 1.6mA 0.09 V
High Level Output Voltage IO = –200µA 1.79 V
Low Level Output Voltage IO = 1.6mA 0.09 V
= 0V 50 mA
OUT
= 3V 50 mA
OUT
= –200µA ● 2.7 2.99 V
I
O
= 1.6mA ● 0.09 0.4 V
I
O
The ● denotes the specifications which apply over the
DD
● –10 10 µA
4
229321f
Page 5
LTC2293/LTC2292/LTC2291
WU
POWER REQUIRE E TS
range, otherwise specifications are at T
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
V
OV
IV
P
P
P
DD
DD
DD
DISS
SHDN
NAP
Analog Supply (Note 9) ● 2.7 3 3.4 2.7 3 3.4 2.7 3 3.4 V
Voltage
Output Supply (Note 9) ● 0.5 3 3.6 0.5 3 3.6 0.5 3 3.6 V
Voltage
Supply Current Both ADCs at f
Power Dissipation Both ADCs at f
Shutdown Power SHDN = H, 2 2 2 mW
(Each Channel) OE = H, No CLK
Nap Mode Power SHDN = H, 15 15 15 mW
(Each Channel) OE = L, No CLK
= 25°C. (Note 8)
A
The ● denotes the specifications which apply over the full operating temperature
LTC2293 LTC2292 LTC2291
S(MAX)
S(MAX)
● 133 150 78 95 50 60 mA
● 400 450 235 285 150 180 mW
UW
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
f
s
t
L
t
H
t
AP
t
D
t
MD
Pipeline 6 6 6 Cycles
Latency
Sampling Frequency (Note 9) ● 165140125MHz
CLK Low Time Duty Cycle Stabilizer Off ● 7.3 7.7 500 11.8 12.5 500 18.9 20 500 ns
Duty Cycle Stabilizer On
(Note 7)
CLK High Time Duty Cycle Stabilizer Off ● 7.3 7.7 500 11.8 12.5 500 18.9 20 500 ns
Duty Cycle Stabilizer On
(Note 7)
Sample-and-Hold 0 0 0 ns
Aperture Delay
CLK to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 1.4 2.7 5.4 1.4 2.7 5.4 ns
MUX to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 1.4 2.7 5.4 1.4 2.7 5.4 ns
Data Access Time CL = 5pF (Note 7) ● 4.3 10 4.3 10 4.3 10 ns
After OE↓
BUS Relinquish Time (Note 7) ● 3.3 8.5 3.3 8.5 3.3 8.5 ns
The ● denotes the specifications which apply over the full operating temperature
LTC2293 LTC2292 LTC2291
● 5 7.7 500 5 12.5 500 5 20 500 ns
● 5 7.7 500 5 12.5 500 5 20 500 ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
Note 4: VDD = 3V, f
25MHz (LTC2291), input range = 2V
otherwise noted.
= 65MHz (LTC2293), 40MHz (LTC2292), or
SAMPLE
with differential drive, unless
P-P
without latchup.
DD
DD
, they
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: V
25MHz (LTC2291), input range = 1V
current and power dissipation are the sum total for both channels with
both channels active.
Note 9: Recommended operating conditions.
= 3V, f
DD
= 65MHz (LTC2293), 40MHz (LTC2292), or
SAMPLE
with differential drive. The supply
P-P
229321f
5
Page 6
LTC2293/LTC2292/LTC2291
CODE
0 30721024 2048 4096
DNL ERROR (LSB)
229321 G03
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2293/LTC2292/LTC2291:
Crosstalk vs Input Frequency
–100
–105
–110
–115
CROSSTALK (dB)
–120
–125
–130
0
20 40 60 80
INPUT FREQUENCY (MHz)
LTC2293: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
65Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
510152025
FREQUENCY (MHz)
LTC2293: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
65Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
6
510152025
FREQUENCY (MHz)
229321 G01
30
229321 G04
30
229321 G07
100
LTC2293: Typical INL,
2V Range, 65Msps
1.00
0.75
0.50
0.25
0
–0.25
INL ERROR (LSB)
–0.50
–0.75
–1.00
0 30721024 2048 4096
CODE
LTC2293: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
65Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
510152025
FREQUENCY (MHz)
LTC2293: 8192 Point 2-Tone FFT,
fIN = 28.2MHz and 26.8MHz, –1dB,
2V Range 65Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
510152025
FREQUENCY (MHz)
229321 G02
30
229321 G05
30
229321 G08
LTC2293: Typical DNL,
2V Range, 65Msps
LTC2293: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
65Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
510152025
FREQUENCY (MHz)
LTC2293: Grounded Input
Histogram, 65Msps
70000
60000
50000
40000
COUNT
30000
20000
10000
2123
0
2042
61496
2043
CODE
30
229321 G06
1910
2044
229321 G09
229321f
Page 7
LTC2293/LTC2292/LTC2291
SAMPLE RATE (Msps)
0
SNR AND SFDR (dBFS)
110
100
90
80
70
60
80
229321 G12
20
40
60
100
SNR
SFDR
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2293: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
72
71
LTC2293: SFDR vs Input Frequency,
–1dB, 2V Range, 65Msps
100
95
90
LTC2293: SNR and SFDR vs
Sample Rate, 2V Range,
f
= 5MHz, –1dB
IN
70
SNR (dBFS)
69
68
0
50
INPUT FREQUENCY (MHz)
100
LTC2293: SNR and SFDR vs
Clock Duty Cycle, 65Msps
100
SFDR: DCS ON
95
90
85
80
75
SNR AND SFDR (dBFS)
70
65
30
SFDR: DCS OFF
SNR: DCS ON
SNR: DCS OFF
35 45 55 65
40 50 70
CLOCK DUTY CYCLE (%)
LTC2293: I
5MHz Sine Wave Input, –1dB
155
150
60
VDD
200
229321 G10
229321 G13
vs Sample Rate,
85
80
SFDR (dBFS)
75
70
65
50 100 200
0
INPUT FREQUENCY (MHz)
LTC2293: SNR vs Input Level,
fIN = 30MHz, 2V Range, 65Msps
80
70
60
50
40
30
SNR (dBc AND dBFS)
20
10
0
–60 –50
dBFS
dBc
– 40 –20–30
INPUT LEVEL (dBFS)
150
229321 G11
LTC2293: SFDR vs Input Level,
fIN = 30MHz, 2V Range, 65Msps
120
110
100
90
80
70
60
50
SFDR (dBc AND dBFS)
40
30
–10
0
229321 G14
LTC2293: I
20
–60 –50 – 40 –20–30
vs Sample Rate,
OVDD
5MHz Sine Wave Input, –1dB,
O
= 1.8V
VDD
12
dBFS
dBc
INPUT LEVEL (dBFS)
90dBc SFDR
REFERENCE LINE
–10
229321 G15
0
(mA)
OVDD
I
10
8
6
4
2
0
0
10 30
20
SAMPLE RATE (Msps)
70
40
60
50
80
229321 G17
229321f
7
145
135
(mA)
125
2V RANGE
VDD
I
115
105
95
0
10 30
20
SAMPLE RATE (Msps)
1V RANGE
70
40
60
50
80
229321 G16
Page 8
LTC2293/LTC2292/LTC2291
FREQUENCY (MHz)
0
AMPLITUDE (dB)
229321 G20
5101520
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2292: Typical INL,
2V Range, 40Msps
1.00
0.75
0.50
0.25
0
–0.25
INL ERROR (LSB)
–0.50
–0.75
–1.00
0
1024 2048 4096
3072
CODE
229321 G18
LTC2292: Typical DNL,
2V Range, 40Msps
1.00
0.75
0.50
0.25
0
–0.25
DNL ERROR (LSB)
–0.50
–0.75
–1.00
0
1024 2048 4096
3072
CODE
LTC2292: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
40Msps
229321 G19
AMPLITUDE (dB)
AMPLITUDE (dB)
8
–100
–110
–120
LTC2292: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
40Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5101520
FREQUENCY (MHz)
LTC2292: 8192 Point 2-Tone FFT,
fIN = 21.6MHz and 23.6MHz,
–1dB, 2V Range, 40Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
5101520
FREQUENCY (MHz)
229321 G21
229321 G24
LTC2292: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
40Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
5101520
FREQUENCY (MHz)
LTC2292: Grounded Input
Histogram, 40Msps
70000
60000
50000
40000
COUNT
30000
20000
10000
1424
0
2050
61538
2051 2052
CODE
2558
229321 G22
229321 G25
LTC2292: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
40Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
5101520
FREQUENCY (MHz)
LTC2292: SNR vs Input Frequency,
–1dB, 2V Range, 40Msps
72
71
70
SNR (dBFS)
69
68
0
50
INPUT FREQUENCY (MHz)
100
150
229321 G23
200
229321 G26
229321f
Page 9
LTC2293/LTC2292/LTC2291
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2292: SNR and SFDR vs
LTC2292: SFDR vs Input Frequency,
–1dB, 2V Range, 40Msps
100
95
90
85
80
SFDR (dBFS)
75
70
65
50 100 200
0
INPUT FREQUENCY (MHz)
LTC2292: SFDR vs Input Level,
fIN = 5MHz, 2V Range, 40Msps
120
110
100
90
80
70
60
50
SNR (dBc AND dBFS)
40
30
20
dBFS
dBc
90dBc SFDR
REFERENCE LINE
–60 –50 – 40 –20–30
INPUT LEVEL (dBFS)
LTC2291: Typical INL,
2V Range, 25Msps
1.00
0.75
0.50
0.25
0
–0.25
INL ERROR (LSB)
–0.50
–0.75
–1.00
0
1024 2048 4096
CODE
3072
150
229321 G27
–10
229321 G30
229321 G33
0
Sample Rate, 2V Range,
fIN = 5MHz, –1dB
110
100
90
80
SNR AND SFDR (dBFS)
70
60
0
LTC2292: I
SFDR
SNR
4020 60
SAMPLE RATE (Msps)
vs Sample Rate,
VDD
5MHz Sine Wave Input, –1dB
100
90
(mA)
VDD
I
80
70
60
0
2V RANGE
10
20
SAMPLE RATE (Msps)
LTC2291: Typical DNL,
2V Range, 25Msps
1.00
0.75
0.50
0.25
0
–0.25
DNL ERROR (LSB)
–0.50
–0.75
–1.00
0
1024 2048 4096
CODE
1V RANGE
30
40
3072
229321 G28
229321 G31
229321 G34
LTC2292: SNR vs Input Level,
fIN = 5MHz, 2V Range, 40Msps
80
70
60
50
40
30
SNR (dBc AND dBFS)
20
10
80
0
–60 –50
LTC2292: I
dBFS
dBc
– 40 –20–30
INPUT LEVEL (dBFS)
vs Sample Rate,
OVDD
–10
229321 G29
0
5MHz Sine Wave Input, –1dB,
O
= 1.8V
VDD
8
6
(mA)
4
OVDD
I
2
50
0
10
0
SAMPLE RATE (Msps)
30
40
20
50
229321 G32
LTC2291: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
25Msps
0
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
0
24 6810
FREQUENCY (MHz)
12
229321 G35
229321f
9
Page 10
LTC2293/LTC2292/LTC2291
FREQUENCY (MHz)
0
AMPLITUDE (dB)
229321 G38
24 6810
12
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
TYPICAL PERFOR A CE CHARACTERISTICS
AMPLITUDE (dB)
–100
–110
–120
AMPLITUDE (dB)
SFDR (dBFS)
10
LTC2291: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
25Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
24 6810
FREQUENCY (MHz)
LTC2291: 8192 Point 2-Tone FFT,
fIN = 10.9MHz and 13.8MHz,
–1dB, 2V Range, 25Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
246810
FREQUENCY (MHz)
LTC2291: SFDR vs Input
Frequency, –1dB, 2V Range,
25Msps
100
95
90
85
80
75
70
65
50 100 200
0
INPUT FREQUENCY (MHz)
150
12
229321 G36
12
229321 G39
229321 G42
UW
–10
–20
–30
–40
–50
–60
–70
AMPLITUDE (dB)
–80
–90
–100
–110
–120
70000
60000
50000
40000
COUNT
30000
20000
10000
110
100
SNR AND SFDR (dBFS)
LTC2291: 8192 Point FFT,
= 70MHz, –1dB, 2V Range,
f
IN
25Msps
0
0
24 6810
FREQUENCY (MHz)
LTC2291: Grounded Input
Histogram, 25Msps
61758
2155
0
2048 2049
CODE
LTC2291: SNR and SFDR vs
Sample Rate, 2V Range,
fIN = 5MHz, –1dB
SFDR
90
80
70
60
10
0
SNR
30
20
SAMPLE RATE (Msps)
12
229321 G37
1607
2050
229321 G40
40 50
229321 G43
LTC2291: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
25Msps
LTC2291: SNR vs Input Frequency,
–1dB, 2V Range, 25Msps
72
71
70
SNR (dBFS)
69
68
0
50
INPUT FREQUENCY (MHz)
100
150
LTC2291: SNR vs Input Level,
fIN = 5MHz, 2V Range, 25Msps
80
70
60
50
40
30
SNR (dBc AND dBFS)
20
10
0
–60 –50
dBFS
dBc
– 40 –20–30
INPUT LEVEL (dBFS)
229321 G41
–10
229321 G44
200
0
229321f
Page 11
LTC2293/LTC2292/LTC2291
0
10
20
515
25
30
35
SAMPLE RATE (Msps)
I
OVDD
(mA)
229321 G47
6
4
2
0
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2291: SFDR vs Input Level,
f
= 5MHz, 2V Range, 25Msps
IN
120
110
100
90
80
70
60
50
SFDR (dBc AND dBFS)
40
30
20
–60 –50 – 40 –20–30
dBFS
dBc
90dBc SFDR
REFERENCE LINE
INPUT LEVEL (dBFS)
–10
229321 G45
LTC2291: I
5MHz Sine Wave Input, –1dB
70
60
(mA)
50
VDD
I
40
0
30
0
515
vs Sample Rate,
VDD
2V RANGE
1V RANGE
10
SAMPLE RATE (Msps)
20
25
30
229321 G46
LTC2291: I
vs Sample Rate,
OVDD
5MHz Sine Wave Input, –1dB,
O
= 1.8V
VDD
35
U
UU
PI FU CTIO S
+
A
(Pin 1): Channel A Positive Differential Analog
INA
Input.
–
A
(Pin 2): Channel A Negative Differential Analog
INA
Input.
REFHA (Pins 3, 4): Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
REFLA (Pins 5, 6): Channel A Low Reference. Short
together and bypass to Pins 3, 4 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1µF ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 13, 14 with an additional 2.2µF ceramic chip ca-
pacitor and to ground with a 1µF ceramic chip capacitor.
REFHB (Pins 13, 14): Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1µF ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 11, 12 with an additional 2.2µF ceramic chip ca-
pacitor and to ground with a 1µF ceramic chip capacitor.
–
A
(Pin 15): Channel B Negative Differential Analog
INB
Input.
+
A
(Pin 16): Channel B Positive Differential Analog
INB
Input.
GND (Pins 17, 64): ADC Power Ground.
SENSEB (Pin 19): Channel B Reference Programming Pin.
Connecting SENSEB to V
selects the internal reference
CMB
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of ±V
V
CMB
SENSEB
(Pin 20): Channel B 1.5V Output and Input Common
. ±1V is the largest valid input range.
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to V
CMA
.
229321f
11
Page 12
LTC2293/LTC2292/LTC2291
U
UU
PI FU CTIO S
MUX (Pin 21): Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA13, OFA; Channel B
comes out on DB0-DB13, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0DB13, OFB; Channel B comes out on DA0-DA13, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together.
SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to VDD results in normal operation with the outputs at high impedance. Connecting
SHDNB to VDD and OEB to GND results in nap mode with
the outputs at high impedance. Connecting SHDNB to V
and OEB to VDD results in sleep mode with the outputs at
high impedance.
OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.
NC (Pins 24, 25, 41, 42): Do Not Connect These Pins.
DB0 – DB11 (Pins 26 to 30, 33 to 39): Channel B Digital
Outputs. DB11 is the MSB.
OGND (Pins 31, 50): Output Driver Ground.
OVDD (Pins 32, 49): Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1µF ceramic chip capacitor.
OFB (Pin 40): Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.
DA0 – DA11 (Pins 43 to 48, 51 to 56): Channel A Digital
Outputs. DA11 is the MSB.
OFA (Pin 57): Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.
DD
SHDNA (Pin 59): Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting
SHDNA to V
the outputs at high impedance. Connecting SHDNA to V
and OEA to VDD results in sleep mode with the outputs at
high impedance.
MODE (Pin 60): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects straight binary output format and turns the clock duty cycle stabilizer
off. 1/3 VDD selects straight binary output format and turns
the clock duty cycle stabilizer on. 2/3 VDD selects 2’s
complement output format and turns the clock duty cycle
stabilizer on. VDD selects 2’s complement output format
and turns the clock duty cycle stabilizer off.
V
(Pin 61): Channel A 1.5V Output and Input Common
CMA
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to V
SENSEA (Pin 62): Channel A Reference Programming Pin.
Connecting SENSEA to V
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of ±V
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
and OEA to GND results in nap mode with
DD
.
CMB
selects the internal reference
CMA
. ±1V is the largest valid input range.
SENSEA
DD
OEA (Pin 58): Channel A Output Enable Pin. Refer to
SHDNA pin function.
12
229321f
Page 13
LTC2293/LTC2292/LTC2291
UU
W
FUNCTIONAL BLOCK DIAGRA
+
A
IN
A
V
2.2µF
SENSE
INPUT
S/H
–
IN
CM
1.5V
REFERENCE
RANGE
SELECT
FIRST PIPELINED
ADC STAGE
REF
BUF
SECOND PIPELINED
ADC STAGE
DIFF
REF
AMP
THIRD PIPELINED
ADC STAGE
INTERNAL CLOCK SIGNALSREFH REFL
FOURTH PIPELINED
CLOCK/DUTY
CYCLE
CONTROL
ADC STAGE
CONTROL
LOGIC
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
SHIFT REGISTER
AND CORRECTION
OUTPUT
DRIVERS
OV
DD
OF
D11
•
•
•
D0
REFH
1µF1µF
0.1µF
2.2µF
REFL
CLK
SHDN
OEMODE
Figure 1. Functional Block Diagram (Only One Channel is Shown)
OGND
229321 F01
229321f
13
Page 14
LTC2293/LTC2292/LTC2291
WUW
TI I G DIAGRA S
Dual Digital Output Bus Timing
(Only One Channel is Shown)
t
AP
ANALOG
INPUT
CLK
D0-D11, OF
ANALOG
INPUT A
ANALOG
INPUT B
N
t
H
t
D
N – 6
N + 1
t
L
Multiplexed Digital Output Bus Timing
t
APA
A
t
APB
B
A + 1
B + 1
N + 2
N – 5 N – 4 N – 3 N – 2
A + 2
B + 2
N + 3
N + 4
N + 5
N – 1
229321 TD01
A + 4
A + 3
B + 4
B + 3
CLKA = CLKB = MUX
D0A-D11A, OFA
D0B-D11B, OFB
t
H
A – 6
B – 6
t
L
B – 6
t
D
A – 6
A – 5
B – 5
B – 5
A – 5
A – 4
B – 4
t
MD
B – 4
A – 4
A – 3
B – 3
B – 3
A – 3
A – 2
B – 2
229321 TD02
14
229321f
Page 15
WUUU
APPLICATIO S I FOR ATIO
LTC2293/LTC2292/LTC2291
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when CLK reaches midsupply to the instant
that the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
THD = 20Log √(V22 + V32 + V42 + . . . Vn2)/V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNR
Crosstalk
Crosstalk is the coupling from one channel (being driven
by a full-scale signal) onto the other channel (being driven
by a –1dBFS signal).
CONVERTER OPERATION
As shown in Figure 1, the LTC2293/LTC2292/LTC2291 are
dual CMOS pipelined multistep converters. The converters have six pipelined ADC stages; a sampled analog input
will result in a digitized value six cycles later (see the
Timing Diagram section). For optimal AC performance
the analog inputs should be driven differentially. For cost
= –20log (2π) • fIN • t
JITTER
JITTER
229321f
15
Page 16
LTC2293/LTC2292/LTC2291
U
WUU
APPLICATIO S I FOR ATIO
sensitive applications, the analog inputs can be driven
single-ended with slightly worse harmonic distortion. The
CLK input is single-ended. The LTC2293/LTC2292/
LTC2291 have two phases of operation, determined by the
state of the CLK input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2293/
LTC2292/LTC2291 CMOS differential sample-and-hold.
The analog inputs are connected to the sampling capacitors (C
SAMPLE
shown attached to each input (C
) through NMOS transistors. The capacitors
PARASITIC
) are the summa-
tion of all other capacitance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when CLK is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As CLK transitions from
high to low, the inputs are reconnected to the sampling
16
LTC2293/LTC2292/LTC2291
15Ω
+
A
IN
15Ω
–
A
IN
CLK
V
DD
C
PARASITIC
V
DD
Figure 2. Equivalent Input Circuit
1pF
C
PARASITIC
1pF
V
DD
C
SAMPLE
4pF
C
SAMPLE
4pF
229321 F02
229321f
Page 17
WUUU
APPLICATIO S I FOR ATIO
LTC2293/LTC2292/LTC2291
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, A
should be driven with the input signal and A
–
should be
IN
IN
+
connected to 1.5V or VCM.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The VCM output pin may
be used to provide the common mode bias level. VCM can
be tied directly to the center tap of a transformer to set the
DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2293/LTC2292/LTC2291
can be influenced by the input drive circuitry, particularly
the second and third harmonics. Source impedance and
reactance can influence SFDR. At the falling edge of CLK,
the sample-and-hold circuit will connect the 4pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when CLK rises, holding the
sampled input on the sampling capacitor. Ideally the input
circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F
ENCODE
); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2293/LTC2292/LTC2291 being
driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM,
setting the ADC input signal at its optimum DC level.
Terminating on the transformer secondary is desirable, as
this provides a common mode path for charging glitches
caused by the sample and hold. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedance seen by the ADC does not exceed 100Ω
for each ADC input. A disadvantage of using a transformer
is the loss of low frequency response. Most small RF
transformers have poor performance at frequencies below 1MHz.
V
CM
2.2µF
0.1µFT1
ANALOG
INPUT
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
25Ω
25Ω
25Ω
0.1µF
25Ω
12pF
+
A
IN
LTC2293
LTC2292
LTC2291
–
A
IN
229321 F03
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input
frequencies.
229321f
17
Page 18
LTC2293/LTC2292/LTC2291
WUUU
APPLICATIO S I FOR ATIO
V
CM
2.2µF
A
12pF
A
+
IN
LTC2293
LTC2292
LTC2291
–
IN
229321 F04
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
+
+
CM
–
–
25Ω
25Ω
Figure 4. Differential Drive with an Amplifier
Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
V
CM
2.2µF
12pF
+
A
IN
LTC2293
LTC2292
LTC2291
–
A
IN
229321 F05
ANALOG
INPUT
1k
0.1µF
1k
25Ω
25Ω
0.1µF
Figure 5. Single-Ended Drive
V
CM
2.2µF
ANALOG
INPUT
0.1µF
T1
0.1µF
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
25Ω
25Ω
12Ω
12Ω
0.1µF
8pF
A
IN
A
IN
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 70MHz and 170MHz
V
CM
2.2µF
ANALOG
INPUT
0.1µF
T1
0.1µF
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
25Ω
25Ω
0.1µF
A
IN
A
IN
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 170MHz and 300MHz
+
–
+
–
LTC2293
LTC2292
LTC2291
229321 F06
LTC2293
LTC2292
LTC2291
229321 F07
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
For input frequencies above 70MHz, the input circuits of
Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux
coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In
Figure 8, the series inductors are impedance matching
elements that maximize the ADC bandwidth.
18
ANALOG
0.1µF
INPUT
T1
0.1µF
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
25Ω
25Ω
6.8nH
0.1µF
6.8nH
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 300MHz
V
2.2µF
A
A
CM
IN
IN
+
LTC2293
LTC2292
LTC2291
–
229321 F08
229321f
Page 19
WUUU
APPLICATIO S I FOR ATIO
LTC2293/LTC2292/LTC2291
Reference Operation
Figure 9 shows the LTC2293/LTC2292/LTC2291 reference circuitry consisting of a 1.5V bandgap reference, a
difference amplifier and switching and control circuit. The
internal voltage reference can be configured for two pin
selectable input ranges of 2V (±1V differential) or 1V
(±0.5V differential). Tying the SENSE pin to VDD selects
the 2V range; tying the SENSE pin to V
selects the 1V
CM
range.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.5V reference output, V
. This provides a high
CM
frequency low impedance path to ground for internal and
external circuitry.
LTC2293/LTC2292/LTC2291
4Ω
V
TIE TO V
TIE TO V
CM
RANGE = 2 • V
0.5V < V
1.5V
FOR 2V RANGE;
DD
FOR 1V RANGE;
SENSE
SENSE
1µF
CM
2.2µF
SENSE
FOR
< 1V
REFH
RANGE
DETECT
AND
CONTROL
1.5V BANDGAP
REFERENCE
1V
INTERNAL ADC
HIGH REFERENCE
0.5V
BUFFER
The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9. Each
ADC channel has an independent reference with its own
bypass capacitors. The two channels can be used with the
same or different input ranges.
Other voltage ranges between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
For the best channel matching, connect an external reference
to SENSEA and SENSEB.
1.5V
12k
0.75V
12k
Figure 10. 1.5V Range ADC
V
2.2µF
SENSE
1µF
CM
LTC2293
LTC2292
LTC2291
229321 F10
Input Range
2.2µF
1µF
0.1µF
REFL
DIFF AMP
INTERNAL ADC
LOW REFERENCE
Figure 9. Equivalent Reference Circuit
229321 F09
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 3.8dB. See the Typical Performance Characteristics section.
Driving the Clock Input
The CLK inputs can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with
a low jitter squaring circuit before the CLK pin (Figure 11).
229321f
19
Page 20
LTC2293/LTC2292/LTC2291
WUUU
APPLICATIO S I FOR ATIO
CLEAN
FERRITE
BEAD
0.1µF
CLK
SUPPLY
LTC2293
LTC2292
LTC2291
229321 F11
4.7µF
1k
1k
NC7SVU04
SINUSOIDAL
CLOCK
INPUT
Figure 11. Sinusoidal Single-Ended CLK Drive
0.1µF
50Ω
The noise performance of the LTC2293/LTC2292/LTC2291
can depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
result in additional aperture jitter that will be RMS summed
with the inherent ADC aperture jitter.
In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The
input clock duty cycle can vary from 40% to 60% and the
clock duty cycle stabilizer will maintain a constant 50%
internal duty cycle. If the clock is turned off for a long
period of time, the duty cycle stabilizer circuit will require
a hundred clock cycles for the PLL to lock onto the input
clock. To use the clock duty cycle stabilizer, the MODE pin
should be connected to 1/3VDD or 2/3VDD using external
resistors. The MODE pin controls both Channel A and
Channel B—the duty cycle stabilizer is either on or off for
both channels.
The lower limit of the LTC2293/LTC2292/LTC2291 sample
rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on
storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified
minimum operating frequency for the LTC2293/LTC2292/
LTC2291 is 1Msps.
It is recommended that CLKA and CLKB are shorted
together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKA and CLKB can be driven
by two different signals. If this delay exceeds 1ns, the
performance of the part may degrade. CLKA and CLKB
should not be driven by asynchronous signals.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2293/LTC2292/
LTC2291 is 65Msps (LTC2293), 40Msps (LTC2292), and
25Msps (LTC2291). For the ADC to operate properly, the
CLK signal should have a 50% (±5%) duty cycle. Each half
cycle must have at least 7.3ns (LTC2293), 11.8ns
(LTC2292), and 18.9ns (LTC2291) for the ADC internal
circuitry to have enough settling time for proper operation.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 12 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital
outputs of the LTC2293/LTC2292/LTC2291 should drive a
minimal capacitive load to avoid possible interaction
20
229321f
Page 21
LTC2293/LTC2292/LTC2291
U
WUU
APPLICATIO S I FOR ATIO
LTC2293/LTC2292/LTC2291
V
DD
DATA
PREDRIVER
FROM
LATCH
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
LOGIC
OE
Figure 12. Digital Output Buffer
OV
DD
0.5V
TO V
0.1µF
TYPICAL
DATA
OUTPUT
DD
V
DD
OV
DD
43Ω
OGND
229321 F12
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2293/LTC2292/LTC2291
parallel digital output can be selected for offset binary or
2’s complement format. Note that MODE controls both
Channel A and Channel B. Connecting MODE to GND or
1/3VDD selects straight binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 1 shows the logic
states for the MODE pin.
Table 1. MODE Pin Function
Clock Duty
MODE Pin Output Format Cycle Stabilizer
0 Straight Binary Off
1/3V
2/3V
V
DD
DD
DD
Straight Binary On
2’s Complement On
2’s Complement Off
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example, if the converter is driving a DSP powered by a 1.8V
supply, then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data access and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long
periods of inactivity. Channels A and B have independent
output enable pins (OEA, OEB).
229321f
21
Page 22
LTC2293/LTC2292/LTC2291
U
WUU
APPLICATIO S I FOR ATIO
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to V
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to V
to GND results in nap mode, which typically dissipates
30mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Channels A and B have independent SHDN pins (SHDNA,
SHDNB). Channel A is controlled by SHDNA and OEA, and
Channel B is controlled by SHDNB and OEB. The nap, sleep
and output enable modes of the two channels are completely
independent, so it is possible to have one channel operating while the other channel is in nap or sleep mode.
Digital Output Multiplexer
The digital outputs of the LTC2293/LTC2292/LTC2291 can
be multiplexed onto a single data bus. The MUX pin is a
digital input that swaps the two data busses. If MUX is High,
Channel A comes out on DA0-DA11, OFA; Channel B comes
out on DB0-DB11, OFB. If MUX is Low, the output busses
are swapped and Channel A comes out on DB0-DB11, OFB;
Channel B comes out on DA0-DA11, OFA. To multiplex both
channels onto a single output bus, connect MUX, CLKA and
CLKB together (see the Timing Diagram for the multiplexed
mode). The multiplexed data is available on either data
bus—the unused data bus can be disabled with its OE pin.
DD
DD
and OE
Grounding and Bypassing
The LTC2293/LTC2292/LTC2291 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC.
High quality ceramic bypass capacitors should be used at
the V
tors must be located as close to the pins as possible. Of
particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be placed as close
to the device as possible (1.5mm or less). A size 0402
ceramic capacitor is recommended. The large 2.2µF ca-
pacitor between REFH and REFL can be somewhat further
away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as
possible.
The LTC2293/LTC2292/LTC2291 differential inputs should
run parallel and close to each other. The input traces
should be as short as possible to minimize capacitance
and to minimize noise pickup.
Heat Transfer
Most of the heat generated by the LTC2293/LTC2292/
LTC2291 is transferred from the die through the bottomside exposed pad and package leads onto the printed
circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large
grounded pad on the PC board. It is critical that all ground
pins are connected to a ground plane of sufficient area.
, OVDD, VCM, REFH, and REFL pins. Bypass capaci-
DD
22
229321f
Page 23
LTC2293/LTC2292/LTC2291
C21
0.1µF
C27
0.1µF
V
DD
V
DD
V
DD
V
DD
V
DD
V
CC
V
CMB
C20
2.2µF
C18 1µF
C23 1µF
C34
0.1µF
C31
12pF
C17
0.1µF
C14
0.1µF
C25
0.1µF
C30
18pF
L2
47nH
R28
24
Ω
C32
18pF
C28
2.2µF
C35
0.1µF
C24
0.1µF
C36
4.7µF
E3
V
DD
3V
E5
PWR
GND
V
DD
V
CC
V
CC
228876 AI01
C1
0.1µF
R16
33Ω
R1
1k
R2
1k
R3
1k
R10
1k
R14
49.9Ω
R20
24.9Ω
R18
24.9Ω
R24
24.9Ω
R17
OPT
R22
24.9Ω
R23
51
T2
ETC1-1T
C29
0.1µF
C33
0.1µF
J3
CLOCK
INPUT
U6
NC7SVU04
U4
NC7SV86P5X
U7
NC7SV86P5X
U3
NC7SVU04
C13
0.1µF
C15
0.1µF
C12
4.7µF
6.3V
L1
BEAD
V
DD
C19
0.1µF
C11
0.1µF
C4
0.1µF
C2
2.2µF
C10
2.2µF
C9 1µF
C13 1µF
R15
1k
J4
ANALOG
INPUT B
V
CC
1
2
3
4
••
5
V
CMB
C8
0.1µF
C6
12pF
C44
0.1µF
R6
24.9Ω
R5
24.9Ω
R9
24.9Ω
R4
OPT
R7
24.9Ω
R8
51
T1
ETC1-1T
C3
0.1µF
C7
0.1µF
J2
ANALOG
INPUT A
1
2
3
5
••
4
V
CMA
V
CMA
12
V
DD
V
DD
34
2/3V
DD
56
1/3V
DD
78
GND
JP1 MODE
C16 0.1µF
25
23
27
29
31
33
35
37
39
21
19
15
17
13
9
7
1
3
5
2
4
11
26
24
30
28
34
32
38
40
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
40
3201S-40G1
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
36
22
20
16
18
14
10
8
6
12
R13
10k
R11
10k
R12
10k
R30
15
Ω
R
N1D
33Ω
R
N1C
33Ω
R
N1B
33Ω
R
N1A
33Ω
R
N2D
33Ω
R
N2C
33Ω
R
N2B
33Ω
R
N2A
33Ω
R
N3D
33Ω
R
N3C
33Ω
R
N3B
33Ω
R
N3A
33Ω
R
N4D
33Ω
R
N4C
33Ω
R
N4B
33Ω
C39
1µF
C38
0.01µF
V
CC
V
DD
BYP
GND
ADJ
OUT
SHDN
GND
IN
1
2
3
4
8
U8
LT1763
7
6
5
GND
R26
100k
R25
105k
C37
10µF
6.3V
E4
GND
C40
0.1µF
C41
0.1µF
A
INA
+
A
INA
–
REFHA
REFHA
REFLA
REFLA
V
DD
CLKA
CLKB
V
DD
REFLB
REFLB
REFHB
REFHB
A
INB
–
A
INB
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DA5
DA4
DA3
DA2
DA1
DA0
NC
NC
OFB
DB11
DB10
DB9
DB8
DB7
DB6
DB5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
GND
V
DD
SENSEA
VCMA
MODE
SHDNA
OEA
OFA
DA11
DA10
DA9
DA8
DA7
DA6
OGND
OV
DD
GND
V
DD
SENSEB
VCMB
MUX
SHDNB
OEB
NC
NC
DB0
DB1
DB2
DB3
DB4
OGND
OV
DD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
E2
EXT
REF B
12
V
DD
34
V
CM
V
DD
V
CMB
56
EXT REF
JP3 SENSE
E1
EXT
REF A
12
V
DD
34
V
CM
V
DD
56
EXT REF
JP2 SENSE A
C5
0.1µF
C26
0.1µF
V
CC
B3
B2
B4
B5
B6
B7
OE
B1
B0
A3
A1
A0
18
17
16
15
14
13
12
11
19
2
20
V
CC
74VCX245BQX
V
CC
3
4
5
6
7
8
9
1
10
A2
A7
T/R
GND
A5
A4
A6
B3
B2
B4
B5
B6
B7
OE
B1
B0
A3
A1
A0
18
17
16
15
14
13
12
11
19
2
20
V
CC
74VCX245BQX
V
CC
3
4
5
6
7
8
9
1
10
A2
A7
T/R
GND
A5
A4
A6
A0
A1
A2
A3
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
R29
51
Ω
L4
47nH
C43
8.2pF
L3
47nH
C42
8.2pF
U5
24LC025
V
CC
R31
TBD
R27
TBD
V
CC
U10
NC7SV86P5X
R32
22Ω
U1
LTC2293
U
WUU
APPLICATIO S I FOR ATIO
229321f
23
Page 24
LTC2293/LTC2292/LTC2291
U
WUU
APPLICATIO S I FOR ATIO
Silkscreen Top
Top Side
24
229321f
Page 25
LTC2293/LTC2292/LTC2291
U
WUU
APPLICATIO S I FOR ATIO
Inner Layer 2 GND
Inner Layer 3 Power
229321f
25
Page 26
LTC2293/LTC2292/LTC2291
U
WUU
APPLICATIO S I FOR ATIO
Bottom Side
26
229321f
Page 27
PACKAGE DESCRIPTIO
LTC2293/LTC2292/LTC2291
U
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705)
0.70 ±0.05
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
9 .00 ± 0.10
(4 SIDES)
PIN 1 TOP MARK
(SEE NOTE 5)
7.15 ±0.05
(4 SIDES)
8.10 ±0.05 9.50 ±0.05
PACKAGE OUTLINE
0.75 ± 0.05
7.15 ± 0.10
(4-SIDES)
R = 0.115
TYP
PIN 1
CHAMFER
6463
0.40 ± 0.10
1
2
0.200 REF
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
0.25 ± 0.05
0.50 BSC
(UP64) QFN 1003
229321f
27
Page 28
LTC2293/LTC2292/LTC2291
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1403A/LTC1403 14-Bit/12-Bit 2.8Msps Serial ADC 3V, 14mW, Differential Input, MSOP Package
LTC1407A/LTC1407 14-Bit/12-Bit 3Msps, Simultaneous Sampling Serial ADC 3V, 14mW, 2-Ch. Differential Input, MSOP Package
LTC1749 12-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 87dB SFDR
LTC1750 14-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR
LTC2225 12-Bit, 10Msps ADC 60mW, 71dB SNR, 5mm × 5mm QFN
LTC2226 12-Bit, 25Msps ADC 75mW, 71dB SNR, 5mm × 5mm QFN
LTC2227 12-Bit, 40Msps ADC 125mW, 71dB SNR, 5mm × 5mm QFN
LTC2228 12-Bit, 65Msps ADC 205mW, 71dB SNR, 5mm × 5mm QFN
LTC2229 12-Bit, 80Msps ADC 211mW, 70.6dB SNR, 5mm × 5mm QFN
LTC2236 10-Bit, 25Msps ADC 75mW, 61dB SNR, 5mm × 5mm QFN
LTC2237 10-Bit, 40Msps ADC 125mW, 61dB SNR, 5mm × 5mm QFN
LTC2238 10-Bit, 65Msps ADC 205mW, 61dB SNR, 5mm × 5mm QFN
LTC2239 10-Bit, 80Msps ADC 211mW, 61dB SNR, 5mm × 5mm QFN
LTC2245 14-Bit, 10Msps ADC 60mW, 74.4dB SNR, 5mm × 5mm QFN
LTC2246 14-Bit, 25Msps ADC 75mW, 74dB SNR, 5mm × 5mm QFN
LTC2247 14-Bit, 40Msps ADC 125mW, 74dB SNR, 5mm × 5mm QFN
LTC2248 14-Bit, 65Msps ADC 205mW, 74dB SNR, 5mm × 5mm QFN
LTC2249 14-Bit, 80Msps ADC 222mW, 73dB SNR, 5mm × 5mm QFN
LTC2286 Dual 10-Bit, 25Msps ADC 150mW, 61dB SNR, 9mm × 9mm QFN
LTC2287 Dual 10-Bit, 40Msps ADC 235mW, 61dB SNR, 9mm × 9mm QFN
LTC2288 Dual 10-Bit, 65Msps ADC 400mW, 61dB SNR, 9mm × 9mm QFN
LTC2289 Dual 10-Bit, 80Msps ADC 445mW, 61dB SNR, 9mm × 9mm QFN
LTC2290 Dual 12-Bit, 10Msps ADC 120mW, 71dB SNR, 9mm × 9mm QFN
LTC2294 Dual 12-Bit, 80Msps ADC 445mW, 70.6dB SNR, 9mm × 9mm QFN
LTC2295 Dual 14-Bit, 10Msps ADC 120mW, 74.4dB SNR, 9mm × 9mm QFN
LTC2296 Dual 14-Bit, 25Msps ADC 150mW, 74dB SNR, 9mm × 9mm QFN
LTC2297 Dual 14-Bit, 40Msps ADC 235mW, 74dB SNR, 9mm × 9mm QFN
LTC2298 Dual 14-Bit, 65Msps ADC 400mW, 74dB SNR, 9mm × 9mm QFN
LTC2299 Dual 14-Bit, 80Msps ADC 445mW, 73dB SNR, 9mm × 9mm QFN
LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514 Ultralow Distortion IF Amplifier/ADC Driver 450MHz 1dB BW, 47dB OIP3, Digital Gain
with Digitally Controlled Gain Control 10.5dB to 33dB in 1.5dB/Step
LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator 20dBm IIP3, Integrated LO Quadrature Generator
LT5516 0.8GHz to 1.5GHz Direct Conversion Quadrature Demodulator 21.5dBm IIP3, Integrated LO Quadrature Generator
LT5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator 21dBm IIP3, Integrated LO Quadrature Generator
LT5522 600MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB,
50Ω Single Ended RF and LO Ports
28
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
229321f
LT/TP 1204 1K • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2004
Loading...