Datasheet LTC2249 Datasheet (LINEAR TECHNOLOGY)

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Page 1

FEATURES

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Sample Rate: 80Msps

■

Single 3V Supply (2.7V to 3.4V)

■

Low Power: 222mW

■

73dB SNR at 70MHz Input

■

90dB SFDR at 70MHz Input

■

No Missing Codes

■

Flexible Input: 1V

■

575MHz Full Power Bandwidth S/H

■

Clock Duty Cycle Stabilizer

■

Shutdown and Nap Modes

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Pin Compatible Family

P-P

to 2V

P-P

Range

125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit) 105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit) 80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit) 65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit) 40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit) 25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit) 10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)

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32-Pin (5mm × 5mm) QFN Package

APPLICATIO S

LTC2249

14-Bit, 80Msps

Low Power 3V ADC

DESCRIPTIO

The LTC®2249 is a 14-bit 80Msps, low power 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2249 is perfect for demanding imaging and communications applications with AC performance that includes 73dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency.

DC specs include ±1LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSB

A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic.

A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

RMS

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Wireless and Wired Broadband Communication

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Imaging Systems

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Ultrasound

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Spectral Analysis

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Portable Instrumentation

TYPICAL APPLICATIO

REFH

REFL

ANALOG

INPUT

FLEXIBLE

REFERENCE

INPUT

S/H

–

CLOCK/DUTY

CYCLE

CONTROL

CLK

14-BIT PIPELINED ADC CORE

CORRECTION

LOGIC

OUTPUT

DRIVERS

2229 TA01

D13

•

OGND

SNR vs Input Frequency,

–1dB, 2V Range

SNR (dBFS)

INPUT FREQUENCY (MHz)

100

150

200

2249 G09

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LTC2249

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ABSOLUTE AXI U RATI GS

OVDD = VDD (Notes 1, 2)

Supply Voltage (VDD) ................................................. 4V

Digital Output Ground Voltage (OGND) ....... –0.3V to 1V

Analog Input Voltage (Note 3) ..... –0.3V to (V

Digital Input Voltage .................... –0.3V to (V

Digital Output Voltage ................– 0.3V to (OV

Power Dissipation............................................ 1500mW

Operating Temperature Range

LTC2249C ............................................... 0°C to 70°C

LTC2249I............................................. –40°C to 85°C

Storage Temperature Range ..................–65°C to 125°C

+ 0.3V)

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

VDDVCMSENSE

32 31 30 29 28 27 26 25

1AIN

–

AIN

REFH

REFL

GND

9 10 11 12

CLK

32-LEAD (5mm × 5mm) PLASTIC QFN

JMAX

EXPOSED PAD IS GND (PIN 33)

MUST BE SOLDERED TO PCB

ORDER PART NUMBER

LTC2249CUH LTC2249IUH

MODEOFD13

13 14 15 16

OED0D1D2D3

SHDN

UH PACKAGE

= 125°C, θJA = 34°C/W

QFN PART MARKING*

D12

D11

2249

D10

OGND

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

CO VERTER CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. (Note 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 14 Bits

Integral Linearity Error Differential Analog Input (Note 5) ● –4 ±1 4 LSB

Differential Linearity Error Differential Analog Input ● –1 ±0.5 1 LSB

Offset Error (Note 6) ● –12 ±212 mV

Gain Error External Reference ● –2.5 ±0.5 2.5 %FS

Offset Drift ±10 µV/°C

Full-Scale Drift Internal Reference ±30 ppm/°C

Transition Noise SENSE = 1V 1.2 LSB

The ● denotes the specifications which apply over the full operating

External Reference ±5 ppm/°C

RMS

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LTC2249

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A ALOG I PUT

specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IN,CM

SENSE

MODE

JITTER

CMRR Analog Input Common Mode Rejection Ratio 80 dB

Analog Input Range (A

Analog Input Common Mode (A

Analog Input Leakage Current 0V < A

SENSE Input Leakage 0V < SENSE < 1V ● –3 3 µA

MODE Pin Leakage ● –3 3 µA

Sample-and-Hold Acquisition Delay Time 0 ns

Sample-and-Hold Acquisition Delay Time Jitter 0.2 ps

DY A IC ACCURACY

otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SNR Signal-to-Noise Ratio 5MHz Input 73 dB

SFDR Spurious Free Dynamic Range 5MHz Input 90 dB

2nd or 3rd Harmonic

SFDR Spurious Free Dynamic Range 5MHz Input 95 dB

4th Harmonic or Higher

S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 72.9 dB

Intermodulation Distortion f

Full Power Bandwidth Figure 8 Test Circuit 575 MHz

The ● denotes the specifications which apply over the full operating temperature range, otherwise

= 25°C. (Note 4)

–

– A

) 2.7V < V

–

+ A

)/2 Differential Input (Note 7) ● 1 1.5 1.9 V

Single Ended Input (Note 7)

< 3.4V (Note 7) ● ±0.5 to ±1V

● 0.5 1.5 2 V

–

, A

< V

● –1 1 µA

The ● denotes the specifications which apply over the full operating temperature range,

40MHz Input ● 70.8 73 dB

70MHz Input 73 dB

140MHz Input 72.6 dB

40MHz Input

70MHz Input 90 dB

140MHz Input 85 dB

40MHz Input

70MHz Input 95 dB

140MHz Input 90 dB

40MHz Input ● 70.2 72.8 dB

70MHz Input 72.8 dB

140MHz Input 72.1 dB

= 28.2MHz, f

IN1

= 26.8MHz 90 dB

IN2

● 75 90 dB

● 81 95 dB

RMS

UU U

I TER AL REFERE CE CHARACTERISTICS

(Note 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage I

VCM Output Tempco ±25 ppm/°C

VCM Line Regulation 2.7V < VDD < 3.4V 3 mV/V

VCM Output Resistance –1mA < I

OUT

= 0 1.475 1.500 1.525 V

< 1mA 4 Ω

OUT

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LTC2249

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DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

LOGIC INPUTS (CLK, OE, SHDN)

LOGIC OUTPUTS

OVDD = 3V

SOURCE

SINK

= 2.5V

OVDD = 1.8V

High Level Input Voltage VDD = 3V ● 2V

Low Level Input Voltage VDD = 3V ● 0.8 V

Input Current VIN = 0V to V

Input Capacitance (Note 7) 3 pF

Hi-Z Output Capacitance OE = High (Note 7) 3 pF

Output Source Current V

Output Sink Current V

High Level Output Voltage IO = –10µA 2.995 V

Low Level Output Voltage IO = 10µA 0.005 V

High Level Output Voltage IO = –200µA 2.49 V

Low Level Output Voltage IO = 1.6mA 0.09 V

High Level Output Voltage IO = –200µA 1.79 V

Low Level Output Voltage IO = 1.6mA 0.09 V

= 25°C. (Note 4)

= 0V 50 mA

OUT

= 3V 50 mA

OUT

= –200µA ● 2.7 2.99 V

= 1.6mA ● 0.09 0.4 V

The ● denotes the specifications which apply over the

● –10 10 µA

POWER REQUIRE E TS

range, otherwise specifications are at TA = 25°C. (Note 8)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DISS

SHDN

NAP

Analog Supply Voltage (Note 9) ● 2.7 3 3.4 V

Output Supply Voltage (Note 9) ● 0.5 3 3.6 V

Supply Current ● 74 86 mA

Power Dissipation ● 222 258 mW

Shutdown Power SHDN = H, OE = H, No CLK 2 mW

Nap Mode Power SHDN = H, OE = L, No CLK 15 mW

The ● denotes the specifications which apply over the full operating temperature

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LTC2249

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TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Pipeline 5 Cycles Latency

Sampling Frequency (Note 9) ● 1 80 MHz

CLK Low Time Duty Cycle Stabilizer Off ● 5.9 6.25 500 ns

CLK High Time Duty Cycle Stabilizer Off ● 5.9 6.25 500 ns

Sample-and-Hold Aperture Delay 0ns

CLK to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 ns Data Access Time After OE↓ CL = 5pF (Note 7) ● 4.3 10 ns

BUS Relinquish Time (Note 7) ● 3.3 8.5 ns

The ● denotes the specifications which apply over the full operating temperature

Duty Cycle Stabilizer On (Note 7)

● 5 6.25 500 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V

, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above V

Note 4: VDD = 3V, f

= 80MHz, input range = 2V

SAMPLE

without latchup.

with differential

P-P

Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.

Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111.

Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, f

differential drive. Note 9: Recommended operating conditions.

drive, unless otherwise noted.

TYPICAL PERFOR A CE CHARACTERISTICS

Typical INL, 2V Range

2.0

1.5

1.0

0.5

–0.5

INL ERROR (LSB)

–1.0

–1.5

–2.0

4096

8192

CODE

12288

16384

2249 G01

Typical DNL, 2V Range

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

4096

8192

CODE

12288

16384

2249 G02

= 80MHz, input range = 1V

SAMPLE

8192 Point FFT, fIN = 5MHz, –1dB, 2V Range

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

with

P-P

FREQUENCY (MHz)

2510

2249 G03

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LTC2249

CLOCK DUTY CYCLE (%)

SNR AND SFDR (dBFS)

2249 G12

40 50

35 65

45 55 70

SFDR: DCS ON

SNR: DCS ON

SNR: DCS OFF

SFDR: DCS OFF

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TYPICAL PERFOR A CE CHARACTERISTICS

8192 Point FFT, fIN = 30MHz, –1dB, 2V Range

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

FREQUENCY (MHz)

8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, –1dB, 2V Range

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

FREQUENCY (MHz)

8192 Point FFT, fIN = 70MHz, –1dB, 2V Range

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

2510

2249 G04

–120

FREQUENCY (MHz)

2510

2249 G05

8192 Point FFT, fIN = 140MHz, –1dB, 2V Range

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

FREQUENCY (MHz)

2510

2249 G06

SNR vs Input Frequency,

Grounded Input Histogram

50000

35969

43161

CODE

25292

6150

1987

178

2249 G08

45000

40000

35000

30000

25000

COUNT

20000

15000

10000

5000

2510

2249 G07

8201

12558

5194

552

8203 8205 8207 8209

–1dB, 2V Range

SNR (dBFS)

INPUT FREQUENCY (MHz)

100

150

200

2249 G09

SFDR vs Input Frequency, –1dB, 2V Range

100

SFDR (dBFS)

50 100 200

INPUT FREQUENCY (MHz)

150

2249 G10

SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB

100

SNR AND SFDR (dBFS)

10 20 30

40 50

SAMPLE RATE (Msps)

SFDR

SNR

60 70 90 100

SNR and SFDR vs Clock Duty Cycle

110

2249 G11

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TYPICAL PERFOR A CE CHARACTERISTICS

LTC2249

SNR vs Input Level, fIN = 70MHz, 2V Range

SNR (dBc AND dBFS)

VDD

dBFS

dBc

–40 –30

–50–60–70

INPUT LEVEL (dBFS)

vs Sample Rate,

5MHz Sine Wave Input, –1dB

(mA)

VDD

2V RANGE

1V RANGE

–20

–10

2249 G13

SFDR vs Input Level, fIN = 70MHz, 2V Range

120

110

100

SFDR (dBc AND dBFS)

–80

OVDD

Wave Input, –1dB, O

(mA)

OVDD

dBFS

dBc

100dBc SFDR

REFERENCE LINE

–60

–40

INPUT LEVEL (dBFS)

–20

2249 G14

vs Sample Rate, 5MHz Sine

= 1.8V

VDD

SAMPLE RATE (Msps)

60 80

2249 G15

100

SAMPLE RATE (Msps)

60 80

2249 G16

100

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LTC2249

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PI FU CTIO S

AIN+ (Pin 1): Positive Differential Analog Input.

- (Pin 2): Negative Differential Analog Input.

REFH (Pins 3, 4): ADC High Reference. Short together and

bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor.

REFL (Pins 5, 6): ADC Low Reference. Short together and bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor.

(Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF

ceramic chip capacitors.

GND (Pin 8): ADC Power Ground.

CLK (Pin 9): Clock Input. The input sample starts on the

positive edge.

SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to V results in sleep mode with the outputs at high impedance.

OE (Pin 11): Output Enable Pin. Refer to SHDN pin function.

D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): Digital Outputs. D13 is the MSB.

OGND (Pin 20): Output Driver Ground.

OVDD (Pin 21): Positive Supply for the Output Drivers.

Bypass to ground with 0.1µF ceramic chip capacitor.

OF (Pin 28): Over/Under Flow Output. High when an over or under flow has occurred.

MODE (Pin 29): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.

SENSE (Pin 30): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±V

VCM (Pin 31): 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor.

GND (Exposed Pad) (Pin 33): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.

. ±1V is the largest valid input range.

SENSE

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LTC2249

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FUNCTIONAL BLOCK DIAGRA

2.2µF

SENSE

INPUT

S/H

–

1.5V

REFERENCE

RANGE SELECT

FIRST PIPELINED

ADC STAGE

REF BUF

SECOND PIPELINED

ADC STAGE

DIFF REF AMP

REFH

0.1µF

2.2µF

THIRD PIPELINED

ADC STAGE

INTERNAL CLOCK SIGNALSREFH REFL

REFL

FOURTH PIPELINED

CLOCK/DUTY

CYCLE

CONTROL

CLK

ADC STAGE

MODE

CONTROL

LOGIC

SHDN

FIFTH PIPELINED

ADC STAGE

SIXTH PIPELINED

ADC STAGE

SHIFT REGISTER

AND CORRECTION

OUTPUT DRIVERS

OGND

2249 F01

D13

•

1µF1µF

Figure 1. Functional Block Diagram

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LTC2249

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TI I G DIAGRA

ANALOG

INPUT

CLK

D0-D13, OF

N – 5 N

N + 1

N + 2

N + 3

N – 4 N – 3 N – 2 N – 1

N + 4

N + 5

2249 TD01

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APPLICATIO S I FOR ATIO

LTC2249

DYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.

Signal-to-Noise Ratio

The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:

THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1)

where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.

If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product.

Spurious Free Dynamic Range (SFDR)

Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal.

Input Bandwidth

The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.

Aperture Delay Time

The time from when CLK reaches mid-supply to the instant that the input signal is held by the sample and hold circuit.

Aperture Delay Jitter

The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be:

SNR

= –20log (2π • fIN • t

JITTER

)

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LTC2249

15Ω

PARASITIC

1pF

PARASITIC

1pF

SAMPLE

4pF

SAMPLE

4pF

LTC2249

–

CLK

2249 F02

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APPLICATIO S I FOR ATIO

CONVERTER OPERATION

As shown in Figure 1, the LTC2249 is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2249 has two phases of operation, determined by the state of the CLK input pin.

Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2249 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (C

SAMPLE

) through NMOS transistors. The capacitors shown attached to each input (C

PARASITIC

) are the summation of all other capaci-

tance associated with each input.

During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will

When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered

be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.

by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation.

Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer.

Figure 2. Equivalent Input Circuit

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APPLICATIO S I FOR ATIO

Single-Ended Input

For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, A should be driven with the input signal and A connected to 1.5V or V

–

should be

Common Mode Bias

For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin (Pin

31) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor.

Input Drive Impedance

As with all high performance, high speed ADCs, the dynamic performance of the LTC2249 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sampleand-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2F

ENCODE

); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling.

For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC2249 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz.

Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies.

2.2µF

12pF

2.2µF

12pF

LTC2249

–

2249 F03

LTC2249

–

2249 F04

ANALOG

INPUT

0.1µFT1 1:1

T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

25Ω

0.1µF

25Ω

Figure 3. Single-Ended to Differential Conversion Using a Transformer

HIGH SPEED

ANALOG

INPUT

DIFFERENTIAL

AMPLIFIER

–

25Ω

–

25Ω

Figure 4. Differential Drive with an Amplifier

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APPLICATIO S I FOR ATIO

Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required.

The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input.

For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In

0.1µF

ANALOG

INPUT

Figure 5. Single-Ended Drive

2.2µF

25Ω

0.1µF

12pF

LTC2249

–

2249 F05

Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth.

Reference Operation

Figure 9 shows the LTC2249 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to V pin to V

selects the 1V range.

ANALOG

INPUT

Figure 8. Recommended Front End Circuit for Input Frequencies Above 300MHz

selects the 2V range; tying the SENSE

0.1µF

25Ω

0.1µF

T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE

25Ω

6.8nH

2.2µF

LTC2249

–

2249 F08

2.2µF

8pF

LTC2249

–

2249 F06

ANALOG

INPUT

0.1µF

T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

25Ω

12Ω

0.1µF

12Ω

Figure 6. Recommended Front End Circuit for Input Frequencies Between 70MHz and 170MHz

2.2µF

LTC2249

–

2249 F07

ANALOG

INPUT

0.1µF

T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

25Ω

0.1µF

Figure 7. Recommended Front End Circuit for Input Frequencies Between 170MHz and 300MHz

TIE TO V

RANGE = 2 • V

LTC2249

4Ω

2.2µF

SENSE

REFH

0.1µF

REFL

RANGE

DETECT

AND

CONTROL

1.5V

FOR 2V RANGE;

FOR 1V RANGE;

SENSE

0.5V < V

SENSE

1µF

2.2µF

1µF

FOR

< 1V

Figure 9. Equivalent Reference Circuit

1.5V BANDGAP REFERENCE

INTERNAL ADC HIGH REFERENCE

DIFF AMP

INTERNAL ADC LOW REFERENCE

0.5V

BUFFER

2249 F09

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APPLICATIO S I FOR ATIO

LTC2249

The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry.

The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9.

Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor.

Input Range

The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 5.7dB.

Driving the Clock Input

The CLK input can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low-jitter squaring circuit before the CLK pin (see Figure 11).

The noise performance of the LTC2249 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter.

In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source.

1.5V

12k

0.75V

12k

Figure 10. 1.5V Range ADC

2.2µF

SENSE

1µF

LTC2249

2249 F10

CLEAN

FERRITE

BEAD

0.1µF

CLK

SUPPLY

LTC2249

4.7µF

NC7SVU04

SINUSOIDAL

CLOCK

INPUT

Figure 11. Sinusoidal Single-Ended CLK Drive

0.1µF

50Ω

2249 F11

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LTC2249

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APPLICATIO S I FOR ATIO

Figures 12 and 13 show alternatives for converting a differential clock to the single-ended CLK input. The use of a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact.

The transformer in the example may be terminated with the appropriate termination for the signaling in use. The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10Ω to 20Ω ohm series resistor to act as both a low pass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for reflections.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2249 is 80Msps. For the ADC to operate properly, the CLK signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 5.9ns for the ADC internal circuitry to have enough settling time for proper operation.

An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3V

or 2/3VDD using external resistors.

The lower limit of the LTC2249 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2249 is 1Msps.

CLEAN

FERRITE

BEAD

0.1µF

CLK

SUPPLY

LTC2249

4.7µF

100Ω

IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR

2249 F12

ETC1-1T

5pF-30pF

DIFFERENTIAL

CLOCK

INPUT

Figure 13. LVDS or PECL CLK Drive Using a TransformerFigure 12. CLK Drive Using an LVDS or PECL to CMOS Converter

0.1µF

CLK

FERRITE

BEAD

LTC2249

2249 F13

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APPLICATIO S I FOR ATIO

LTC2249

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit.

Table 1. Output Codes vs Input Voltage

A (2V Range) OF (Offset Binary) (2’s Complement)

>+1.000000V 1 11 1111 1111 1111 01 1111 1111 1111

+0.999878V 0 11 1111 1111 1111 01 1111 1111 1111 +0.999756V 0 11 1111 1111 1110 01 1111 1111 1110

+0.000122V 0 10 0000 0000 0001 00 0000 0000 0001

0.000000V 0 10 0000 0000 0000 00 0000 0000 0000 –0.000122V 0 01 1111 1111 1111 11 1111 1111 1111 –0.000244V 0 01 1111 1111 1110 11 1111 1111 1110

–0.999878V 0 00 0000 0000 0001 10 0000 0000 0001 –1.000000V 0 00 0000 0000 0000 10 0000 0000 0000

<–1.000000V 1 00 0000 0000 0000 10 0000 0000 0000

–

– A

D13 – D0 D13 – D0

Digital Output Buffers

Figure 14 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors.

LTC2249

DATA

FROM

LATCH

PREDRIVER

LOGIC

43Ω

OGND

0.5V TO 3.6V

0.1µF

TYPICAL DATA OUTPUT

As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2249 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF.

Lower OVDD voltages will also help reduce interference from the digital outputs.

Data Format

Using the MODE pin, the LTC2249 parallel digital output can be selected for offset binary or 2’s complement format. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3V

or 2/3VDD logic values. Table 2 shows the logic states for the MODE pin.

Table 2. MODE Pin Function

Clock Duty

MODE Pin Output Format Cycle Stablizer

0 Offset Binary Off

1/3V

2/3V

Offset Binary On

2’s Complement On

2’s Complement Off

Overflow Bit

When OF outputs a logic high the converter is either overranged or underranged.

2249 F12

Figure 14. Digital Output Buffer

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APPLICATIO S I FOR ATIO

Output Driver Power

Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply.

OVDD can be powered with any voltage from 500mV up to

3.6V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD.

Output Enable

The outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity.

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to V results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dissipates 15mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap modes, all digital outputs are disabled and enter the Hi-Z state.

Grounding and Bypassing

The LTC2249 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance is the 0.1µF capacitor between REFH and REFL. This capacitor should be placed as close to the device as possible (1.5mm or less). A size 0402 ceramic capacitor is recommended. The large 2.2µF ca- pacitor between REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible.

The LTC2249 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup.

Heat Transfer

Most of the heat generated by the LTC2249 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area.

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APPLICATIO S I FOR ATIO

LTC2249

Clock Sources for Undersampling

Undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz.

In cases where absolute clock frequency accuracy is relatively unimportant and only a single ADC is required, a 3V canned oscillator from vendors such as Saronix or Vectron can be placed close to the ADC and simply connected directly to the ADC. If there is any distance to the ADC, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. You must not allow the clock to overshoot the supplies or performance will suffer. Do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise.

The lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a filter close to the ADC may be beneficial. This filter should be close to the ADC to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the ADC. If you are sensitive to close-in phase noise, the power supply for oscillators and any buffers

must be very stable, or propagation delay variation with supply will translate into phase noise. Even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. If your clock is also used to drive digital devices such as an FPGA, you should locate the oscillator, and any clock fan-out devices close to the ADC, and give the routing to the ADC precedence. The clock signals to the FPGA should have series termination at the driver to prevent high frequency noise from the FPGA disturbing the substrate of the clock fan-out device. If you use an FPGA as a programmable divider, you must re-time the signal using the original oscillator, and the retiming flip-flop as well as the oscillator should be close to the ADC, and powered with a very quiet supply.

For cases where there are multiple ADCs, or where the clock source originates some distance away, differential clock distribution is advisable. This is advisable both from the perspective of EMI, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer PCBs. The differential pairs must be close together and distanced from other signals. The differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart.

2249fa

Page 20

LTC2249

0.1µF C11

0.1µF

GND

JP2

2.2µF

1µF

0.1µF

8.2pF

GND

JP1

SHDN

C15

2.2µF

C16

0.1µF

C18

0.1µF

C25

4.7µF

PWR

GND

2249 TA02

C17 0.1µF

C20

0.1µF

C19

0.1µF

C14

0.1µF

R10

33Ω

EXT REF

R14

R15

R16

49.9Ω

24.9Ω

12.4Ω

OPT

24.9Ω

50Ω

ETC1-1-13

0.1µF

CLOCK

INPUT

NC7SVU04

C13

0.1µF

C10

0.1µF

4.7µF

6.3V

BEAD

C12

0.1µF

ANALOG

INPUT

–

REFH

REFL

CLK

SHDN

SENSE

MODE

GND

LTC2249

D12

D11

GND

D13

OGND

D10

OE1

OE2

LE1

LE2

GND

O11

O10

GND

74VCX16373MTD

N1C

33Ω

GND

O12

O13

O14

O15

3201S-40G1

SDA

24LC025

SCL

••

2/3V

1/3V

GND

JP4 MODE

EXT REF

JP3 SENSE

N1B

33Ω

N1A

33Ω

N2D

33Ω

N2C

33Ω

N2B

33Ω

N2A

33Ω

N3D

33Ω

N3C

33Ω

N3B

33Ω

N3A

33Ω

N4D

33Ω

N4B

33Ω

N4A

33Ω

R13

10k

R11

10k

R12

10k

N4C

33Ω

N1D

33Ω

C28

1µF

C27

0.01µF

NC7SV86P5X

BYP

GND

ADJ

OUT

SHDN

GND

LT1763

GND

R18

100k

R17

105k

C26

10µF

6.3V

GND

C21

0.1µF

C22

0.1µF

C23

0.1µF

C24

0.1µF

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APPLICATIO S I FOR ATIO

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APPLICATIO S I FOR ATIO

LTC2249

Silkscreen Top

Topside

Inner Layer 2 GND

2249fa

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APPLICATIO S I FOR ATIO

Inner Layer 3 Power

Bottomside

Silkscreen Bottom

2249fa

Page 23

PACKAGE DESCRIPTIO

www.BDTIC.com/LINEAR

5.50 ±0.05

4.10 ±0.05

3.45 ±0.05 (4 SIDES)

RECOMMENDED SOLDER PAD LAYOUT

5.00 ± 0.10 (4 SIDES)

PIN 1 TOP MARK (NOTE 6)

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693)

0.70 ±0.05

PACKAGE OUTLINE

0.25 ± 0.05

0.50 BSC

0.75 ± 0.05

0.00 – 0.05

LTC2249

BOTTOM VIEW—EXPOSED PAD

R = 0.115

TYP

0.23 TYP

(4 SIDES)

0.40 ± 0.10

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

3.45 ± 0.10 (4-SIDES)

(UH) QFN 0603

0.200 REF

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

0.25 ± 0.05

0.50 BSC

2249fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Page 24

LTC2249

www.BDTIC.com/LINEAR

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LTC2246 14-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 74.5dB SNR, 90dB SFDR, 32-Pin QFN

LTC2247 14-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN

LTC2248 14-Bit, 65Msps, 3V ADC, Lowest Power 205mW, 74.3dB SNR, 90dB SFDR, 32-Pin QFN

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Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

2249fa

LT 0106 REV A • PRINTED IN USA

Datasheet LTC2249 Datasheet (LINEAR TECHNOLOGY)

Specifications and Main Features

Frequently Asked Questions

User Manual